THC63LVD824 - THine Electronics, Inc.

THC63LVD824 Rev.1.03

THine

THC63LVD824

Single(135MHz)/Dual(170MHz) Link LVDS Receiver for XGA/SXGA/SXGA+/UXGA

General Description

The TH C63LVD82 4 receiver is designed to support

Single Link transmission between Host and Flat Panel

Display up to SXGA+ resolutions and Dual Link trans-

mission between Host and Flat Panel Display up to

UXGA resolution s. The THC63LVD824 co nverts the

LVDS data streams back into 48bits o f CMOS/TTL data

with falling edge or rising edge clock for convenient

with a variety of LCD panel controllers.

In Single Link, data transmit clock frequency of

135MHz, 48bits of RGB data are transmitted at an

effective rate of 945Mbps per LVDS channel. Using a

135MHz clock, the data throughput is 472Mbytes per

second.

In Dual Link, data transmit clock frequency of 85MHz,

48bits of RGB data are transmitted at an effective rate

of 595Mbps per LVDS channel. Using a 85MHz clock,

the data throughput is 595Mbytes per second.

Features

•Wide dot clock range: 25-170MHz suited for VGA,

SVGA, XGA, SXGA, SXGA+ and UXGA

•PLL requires No external components

•Supports Single Link up to 135MHz dot clock for

SXGA+

•Supports Dual Link up to 170MHz dot clock for

UXGA

•50% output clock duty cycle

•TTL clock edge programmable

•TTL output driverbility selectable for lower EMI

•Power down mode

•Low power single 3.3V CMOS design

•100pin TQFP

•THC63LVDF 84A compatible

•THC63LVD814 pin compatible

Block Diagram

SERIAL TO PARALLEL

PLL

SERIAL TO PARALLEL

PLL

28

DEMUX

RA1 +/-

RB1 +/-

RC1 +/-

RD1 +/-

RCLK1 +/-

RA2 +/-

RB2 +/-

RC2 +/-

RD2 +/-

R/F

/PDWN

(25 to 135MHz)

RCLK2 +/-

(25 to 85MHz)

1st Link

8

RED1

GREEN1

BLUE1

HSYNC

VSYNC

DE

RED2

GREEN2

BLUE2

RECEIVER CLOCK OUT

(25 to 85MHz)

1st DATA

2nd DATA

CMOS/TTL OUTPUT

2nd Link

LVDS INPUT

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THC63L VD824 Rev.1.03

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Pin Out

LVDS GND

RA1-

RA1+

RB1-

RB1+

LVDS VCC

RC1-

RC1+

RCLK1-

RCLK1+

RD1-

RD1+

LVDS GND

RA2-

RA2+

RB2-

RB2+

LVDS VCC

RC2-

RC2+

RCLK2-

RCLK2+

RD2-

RD2+

LVDS GND

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

R15

GND

VCC

R14

R13

R12

R11

R10

GND

VCC

CLKOUT

B27

B26

B25

B24

B23

GND

VCC

B22

B21

B20

G27

GND

VCC

G26

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

PLL GND

PLL VCC

GND

/PDWN

MODE0

MODE1

GND

R/F

DRVSEL

R20

R21

R22

R23

R24

VCC

GND

R25

R26

R27

G20

G21

G22

G23

G24

G25

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

DE

VSYNC

HSYNC

B17

B16

GND

VCC

B15

B14

B13

B12

B11

B10

G17

G16

G15

G14

G13

GND

VCC

G12

G11

G10

R17

R16

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

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THC63L VD824 Rev.1.03

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Pin Description

Pin Name Pin # Type Description

RA1+, RA1- 78, 77 LVDS IN

The 1st Link. The 1st pixel input data when Dual Link.

RB1+, RB1- 80, 79 LVDS IN

RC1+, RC1- 83, 82 LVDS IN

RD1+, RD1- 87, 86 LVDS IN

RCLK1+, RCLK1- 85, 84 LVDS IN LVDS Clock Input for 1st Link.

RA2+, RA2- 90, 89 LVDS IN

The 2nd Link. These pins are disabled when Single Link.

RB2+, RB2- 92, 91 LVDS IN

RC2+, RC2- 95, 94 LVDS IN

RD2+, RD2- 99, 98 LVDS IN

RCLK2+, RCLK2- 97, 96 LVDS IN LVDS Clock Input for 2nd Link.

R17 ~ R10 52, 51, 50, 47,

46, 45, 44, 43 OUT

The 1st Pixel Data Outputs.G17 ~ G10 62, 61, 60, 59,

58, 55, 54, 53 OUT

B17 ~ B10 72, 71, 68, 67,

66, 65, 64, 63 OUT

R27 ~ R20 19, 18, 17, 14,

13, 12, 11, 10 OUT

The 2nd Pixel Data Outputs.G27 ~ G20 29, 26, 25, 24,

23, 22, 21, 20 OUT

B27 ~ B20 39, 38, 37, 36,

35, 32, 31, 30 OUT

DE 75 OUT Data Enable Output.

VSYNC 74 OUT Vsync Output.

HSYNC 73 OUT Hsync Output.

CLKOUT 40 OUT Clock Output.

DRVSEL 9 IN Output Driverbility Select.

H: High power, L: Low power.

R/F 8 IN Output Clock Triggering Edge Select.

H: Rising edge, L: Falling edge.

MODE1, MODE0 6, 5 IN

/PDWN 4 IN H: Normal operation,

L: Power down (all outputs are pulled to ground)

VCC 15, 27, 33, 41,

48, 56, 69 Power Power Supply Pins for TTL outputs and digital circuitry.

GND 3, 7, 16, 28, 34,

42, 49, 57, 70 Ground Ground Pins for TTL outputs and digital circuitry.

LVDS VCC 81,93 Power Power Supply Pins for LVDS inputs.

LVDS GND 76, 88, 100 Ground Ground Pins for LVDS inputs.

Pix e l Da t a Mo de .

MODE1 MODE0 Mode

LL Dual Link

L H Single Link

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Absolute Maximum Ratings 1

Electrical Characteristics

CMOS/TTL DC Specifications VCC = 3.0V ~ 3.6V, Ta = -10 ~ +70

LVDS Receiver DC Specifications VCC = 3.0V ~ 3.6V, Ta = -10 ~ +70

PLL VCC 2 Power Power Supply Pin for PLL circuitry.

PLL GND 1 Ground Ground Pin for PLL circuitry.

Supply Voltage (VCC)-0.3V ~ +4.0V

CMOS/TTL Input Voltage -0.3V ~ (VCC + 0.3V)

CMOS/TTL Output Voltage -0.3V ~ (VCC + 0.3V)

LVDS R eceiver Input Voltage -0.3V ~ (VCC + 0.3V)

Output Current -30mA ~ 30 mA

Junction Temperature +125

Storage Temperature Range -55 ~ +125

Lead Temperature (Soldering, 10sec) +230

Maximum Power Dissipation @+25 1.0W

1. “Absolute Maximum Ratings” are those valued beyond which the safety of the device can not be guaranteed. They

are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics”

specify conditions for device operation.

Symbol Parameter Conditions Min. Typ. Max. Units

VIH High Level Input Voltage 2.0 VCC V

VIL Low Level Input Voltage GND 0.8 V

VOH High Level Output Voltage IOH= -2mA, -4mA (data)

IOH= -4mA, -8mA (clock) 2.4 V

VOL Low Level Output Voltage IOH= -2mA, -4mA (data)

IOH= -4mA, -8mA (clock) 0.4 V

IINC Input Current µA

Symbol Parameter Conditions Min. Typ. Max. Units

VTH Differential Input High Threshold VOC= 1.2V 100 mV

VTL Differential Input Low Threshold VOC= 1.2V -100 mV

IINL Input Current VIN= 2.4V / 0V

VCC= 3.6V µA

Pin Name Pin # Type Description

°C

°C°C

°C

°C°C

0V VIN VCC

≤≤ 10±

°C°C

20±

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THC63L VD824 Rev.1.03

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Supply Current VCC = 3.0V ~ 3.6V, Ta = -10 ~ +70

(*) VESA is a trademark of the Video Electronic s Standards Associ ation.

Symbol Parameter Condition(*) Typ. Max. Units

IRCCG

Receiver Supply

Current

(256 Gray Scale Pattern)

VESA SXGA (60Hz),

fCLKOUT = 54MHz

MODE<1:0>=LH

CL=8pF,

Vcc=3.3V 57 66 mA

VESA UXGA (60Hz),

fCLKOUT = 81MHz

MODE<1:0>=LL

CL=8pF,

Vcc=3.3V 85 97 mA

IRCCW

Receiver Supply

Current

(Double Checker Pattern)

VESA SXGA (60Hz),

fCLKOUT = 54MHz

MODE<1:0>=LH

CL=8pF,

Vcc=3.3V 87 99 mA

VESA UXGA (60Hz),

fCLKOUT = 81MHz

MODE<1:0>=LL

CL=8pF,

Vcc=3.3V 148 173 mA

IRCCS Receiver Power Down

Supply Current /PDWN = L 10 µA

°C°C

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THC63L VD824 Rev.1.03

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256 Gray Scale Pattern

Double Checker Pattern

CLKOUT

Rx0/Gx0/Bx0

Rx1/Gx1/Bx1

Rx2/Gx2/Bx2

Rx3/Gx3/Bx3

Rx4/Gx4/Bx4

Rx5/Gx5/Bx5

Rx6/Gx6/Bx6

Rx7/Gx7/Bx7

x=1,2

DE

CLKOUT

R1n/G1n/B1n

R2n/G2n/B2n

n=0~7

DE

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Switching Characteristics VCC = 3.0V ~ 3.6V, Ta = -10 ~ +70

Symbol Parameter Min. Typ. Max. Units

tRCP CLKOUT Period Dual-in / Dual-out 11.76 tRCIP 40.0 ns

Single-in / Dual-out 14.8 2tRCIP 80.0 ns

tRCH CLKOUT High Time ns

tRCL CKLOUT Low Time ns

tRS TTL Data Setup to CLKOUT 0.3tRCP ns

tRH TTL Data Hold from CKLOUT 0.3tRCP ns

tTLH TTL Low to High Transition Ti me 3.0 5.0 ns

tTHL TTL High to Low Transition Time 3.0 5.0 ns

tRIP1 Input Data Position0 (tRCIP = 7.4ns) -0.25 0.0 +0.25 ns

tRIP0 Input Data Position1 (tRCIP = 7.4ns) ns

tRIP6 Input Data Position2 (tRCIP = 7.4ns) ns

tRIP5 Input Data Position3 (tRCIP = 7.4ns) ns

tRIP4 Input Data Position4 (tRCIP = 7.4ns) ns

tRIP3 Input Data Position5 (tRCIP = 7.4ns) ns

tRIP2 Input Data Position6 (tRCIP = 7.4ns) ns

tRPLL Phase Lock Loop Set 10.0 ms

tRCIP CLKIN Period 7.4 40.0 ns

tCK12 Skew Time between RCLK1 and

RCLK2 ns

°C°C

tRCP

2

-----------

tRCP

2

-----------

tRCIP

7

-------------0.25–tRCIP

7

-------------tRCIP

7

-------------0.25+

2tRCIP

7

-------------0.25–2

tRCIP

7

-------------2

tRCIP

7

-------------0.25+

3tRCIP

7

-------------0.25–3

tRCIP

7

-------------3

tRCIP

7

-------------0.25+

4tRCIP

7

-------------0.25–4

tRCIP

7

-------------4

tRCIP

7

-------------0.25+

5tRCIP

7

-------------0.25–5

tRCIP

7

-------------5

tRCIP

7

-------------0.25+

6tRCIP

7

-------------0.25–6

tRCIP

7

-------------6

tRCIP

7

-------------0.25+

0.3tRCIP

±

AC Timing Diagrams

TTL Outputs

8pF

TTL Output

TTL Output Load

20%

80%

20%

80%

tTLH tTHL

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THC63L VD824 Rev.1.03

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AC Timing Diagrams

TTL Outputs

2.0V 2.0V 2.0V

0.8V 0.8V

R/F = L

R/F = H

2.0V 2.0V

0.8V 0.8V

tRCP tRS

tRH

tRCH tRCL

CLKOUT

Rxn

Gxn

Bxn

x = 1,2

n = 0~ 7

Phase Lock Loop Set Time

VCC 3.0V

2.0V

tRPLL

RCLKx+/-

/PDWN

CLKOUT

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THC63L VD824 Rev.1.03

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Pixel Map Table for Single/Dual Link

TFT Panel Data

LSB 24Bit 18Bit

824 TTL Output Pin

1st Pixel Data

R10 -

MSB

R11

R12

R13

R14

R15

R16

R17

-

R10

R11

R12

R13

R14

R15

LSB

MSB

G11

G12

G13

G14

G15

G16

G17

-

G10

G11

G12

G13

G14

G15

G10 -

LSB

MSB

B11

B12

B13

B14

B15

B16

B17

-

B10

B11

B12

B13

B14

B15

B10 -

R10

R11

R12

R13

R14

R15

R16

R17

G11

G12

G13

G14

G15

G16

G17

G10

B11

B12

B13

B14

B15

B16

B17

B10

TFT Panel D ata

LSB 24Bit 18Bit

824 TTL Output Pi n

2nd Pixel Data

R20 -

MSB

R21

R22

R23

R24

R25

R26

R27

-

R20

R21

R22

R23

R24

R25

LSB

MSB

G21

G22

G23

G24

G25

G26

G27

-

G20

G21

G22

G23

G24

G25

G20 -

LSB

MSB

B21

B22

B23

B24

B25

B26

B27

-

B20

B21

B22

B23

B24

B25

B20 -

R20

R21

R22

R23

R24

R25

R26

R27

G21

G22

G23

G24

G25

G26

G27

G20

B21

B22

B23

B24

B25

B26

B27

B20

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THC63L VD824 Rev.1.03

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TFT Pa nel

(1400 x 1050)

#1 #2 #1400#1399

HSYNC

DE

CLKOUT

R1x/G1x/B1x

R2x/G2x/B2x

#1

#2

#3

#4

#5

#6 #8

#1399

#1400

#1397

#1398

1395

1396

#7

n = 0~7

824 TTL Data Output Timing for Single/Dual Link

Example : SXGA+(1400 x 1050)

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Vdiff = 0V

Ryx+/-

AC Timing D i agrams

LVDS Inputs

Ryx6 Ryx5 Ryx4 Ryx3 Ryx2 Ryx1 Ryx0 Ryx6 Ryx5 Ryx4 Ryx3 Ryx2 Ryx1

Vdiff = 0V

tRIP2

tRIP3

tRIP4

tRIP5

tRIP6

tRIP0

tRIP1

tRCIP

RCLKx+

x = 1,2

y = A,B,C,D

Vdiff = 0V

tCK12

RCLK1+

Vdiff = 0V

RCLK2+

Note:

Vdiff = (Ryx+) - (Ryx-), (RCLKx+) - (RCLKx-)

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LVDS Data Inputs Timing Diagrams in Single Link

RA1+/- R26’ R25’ R24’ R23’ R22’ G12 R17 R16 R15 R14 R13 R12 G22’’

RB1+/- G27’ G26’ G25’ G24’ G23’ B13 B12 G17 G16 G15 G14 G13 B23’’

RC1+/- HSYNC’ B27’ B26’ B25’ B24’ DE VSYNC HSYNC B17 B16 B15 B14 DE’’

RD1+/- B20’ G21’ G20’ R21’ R20’ xB11 B10 G11 G10 R11 R10 x’’

RCLK1+

Previous Cycle Current Cycle

(2nd pi xel dat a ) (1st pixel data)

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THC63L VD824 Rev.1.03

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LVDS Data Inputs Timing Diagrams in Dual Link

RA1+/- R16’ R15’ R14’ R13’ R12’ G12 R17 R16 R15 R14 R13 R12 G12’’

RB1+/- G17’ G16’ G15’ G14’ G13’ B13 B12 G17 G16 G15 G14 G13 B13’’

RC1+/- HSYNC’ B17’ B16’ B15’ B14’ DE VSYNC HSYNC B17 B16 B15 B14 DE’’

RD1+/- B10’ G11’ G10’ R11’ R10’ xB11 B10 G11 G10 R11 R10 x’’

RA2+/- R26’ R25’ R24’ R23’ R22’ G22 R27 R26 R25 R24 R23 R22 G22’’

RB2+/- G27’ G26’ G25’ G24’ G23’ B23 B22 G27 G26 G25 G24 G23 B23’’

RC2+/- B27’ B26’ B25’ B24’ B27 B26 B25 B24

RD2+/- B20’ G21’ G20’ R21’ R20’ xB21 B20 G21 G20 R21 R20 x’’

RCLK1+

RCLK2+

x’’xxxx’

Previous Cycle Current Cycle

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THC63L VD824 Rev.1.03

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Package

76100

5026

INDEX ∆

PIN No.1

25 51

75

0.22

0.5TYP

1.2MAX

UNITS:mm

14.0SQ TYP

16.0SQ TYP

1.00 TYP

THine Electronics, Inc.

Matsuda Yaesudori Bldg. 6F

1-10-7, Hatchobori,

Chuo-ku, Tokyo, 104-0032 Japan

Tel: 81-3-3555-0666

Fax: 81-3-3555-0677

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THC63L VD824 Rev.1.03

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Notes to Users:

1. The contents of this data sheet are subject to change without prior notice.

2. Circuit diagrams shown in this data sheet are examples of application. Therefore, please pay sufficient attention

when designing circuits. Even if there are incorrect descriptions, we are not responsible for any problem due to

them. Please note that incorrect descriptions sometimes cannot be corrected immediately if found.

3. Our copyright and know-how are included in this data sheet. Duplication of the data sheet and disclosure to other

persons are strictly prohibited without our permission.

4. We are not responsible for any problems of industrial proprietorship occurring during THC63LVD824 use, except

for those directly related to THC63LVD824’s structure, manufacture or functions. THC63LV D824 is designed on

the premise that it should be used for ordinary electronic devices . Therefore, it shall not be used for application s that

require extremely high- reliability (space equipment, nuclear control equip ment, medical equipment that affects peo -

ple’s lives, etc.). In addition, when using THC63LVD824 for traffic signals, safety devices and control/safety units

in transportation equipment, etc., appropriate measures should be taken.

5. We are making the utmost effort to improve the quality and reliability of our products. However, there is a very

slight possib i lity of fai l ure in s emi cond uctor devices. To avoi d d amage to social or offici al org ani zati ons , m uch care

should be taken to provide sufficient redundancy and fail-safe design.

6. No radiation-hardened design is incorporated in THC63LVD824.

7. Judgmen t on whether THC63LVD824 come s un der s trat egi c pr oducts prescri b ed by th e Fo rei gn Ex chang e and F or -

eign Trade Control Law is the user’s responsibility.

8. This technical documen t was provisi onally created during development of THC 63LVD824, so there is a possibility

of differences between it and the product’s final specifications. When designing circuits using THC63LVD824, be

sure to refer to the final technical documents.