QNGAx they FTPs, __. W86C551/W86CS51P _ UART WITH FIFO AND PRINTER PORT CONTROLLER GENERAL DESCRIPTION The W86C551 is an enhanced version of the existing W86C451. The device supports one 16550 compatible UART and one Centronics parallel interface. FEATURES Easily interfaces with most popular microprocessors Pin compatible and functionally compatible with the existing W86C451 Centronics parallel interface * Capable of running all existing 16450 and 16550 software Uses system's 14.31818MHz clock input e In FIFO mode transmitter and receiver are each buffered with 16-byte FIFOs to reduce number of interrupts presented to the CPU Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from serial data e Independently controlled transmit, receive, line status, and data set interrupts e Programmabie baud rate generator e Modem control functions (CTS, RTS, DSR, DTR, Rl, and DCD) e Fully programmable serial-interface characteristics: - 5, 6, 7, or 8-bit characters - Even, odd, or no-parity bit generation and detection - 1, 1.5, or 2-stop bit generation - Baud generation False start bit detection e Internal diagnostic capabilities: - Loopback controls for communications link fault isolation - Break, parity, overrun, framing error simulation Fully prioritized interrupt system controls 40-pin PDIP package for W86C551 and 44-pin PLCC package for W86C551P Publication Release Date: August 1994 -]- Revision Al; Winbond Electronics Corp. SOOM NE ROMO pone ee W86C551/W86C551P PIN CONFIGURATION 40-pin PDIP oo O ay, 400 Vo or Cf 2 ae] Ri oe C] 3 3a] dcp os C4 37 [2] DSA oo O 5 36{2] CTs os C] 6 a5{) MR pe (] 7 34{] OTR o? Ca 3a) ATs SOUT [] g 32 [J INTO CLKOUT C] 4p a1 [0 40 SIN CO o4 30[) Ai CLKIN C] 42 290] a2 BUSY [J 4g 28D) ACE ack Co 14 27 [J AD pe CI 15 26 [J WR sict [] 16 2s] PAT Err C] 17 24[ DLE INT? [1 4g 23) STB sun CJ 19 22[) AFD vss [1] 20 210 INT 44-pin PLCC / f# / v / pO D 0B DpDpobBN OD RC S T 4 3.42 1 #0 c Dp i! DR Roo n oOo Ao nN OD O76 & 4 3 2 1 44 43 42 41 40591 mR De Ca 381 Om D7 Og 371) RTs souT C10 36 INTO CLKOUT 44 35 C AO NC O12 a4 0 NC SIN O49 33 At CLKIN O44 32) A2 BUSY Chis 31) ACE AcK O46 30) RD PE C1718 19 20 21 22 23 24 25 26 27 26 29[) WR UU UU UU UU OU oo / tof VN i / / / / L NS GC N A S$ D P Cc RTL s i F T lt AR T A 1 N T D B E Tinbond EELY = Electronics Corp. PIN DESCRIPTION W83C42 PIN # PIN # VO NAME FUNCTION (40PDIP) | (44PLCC) 1 2 | TO K/B Clock Input 2 3 t XIN Crystal Clock I/P 3 4 0 XOUT Crystal Clock O/P 4 5 | RESETB Chip Reset 5 6 - Vcc Optional +5V Power Supply 6 7 | CSB Chip Select 7 8 - GND Optional Ground Power 8 9 \ RDB /O Read 9 10 | A2 Connect to Address A2 10 11 | WRB /O Write 11, 26 1, 12, 13, - NC Reserved 23, 29, 34 12, 13, 14, 15, VO DO-D7 Data Bus DO - D7 14, 15, 16, 17, 16, 17, 18, 19, 18, 19 20, 21 20 22 - GND Ground Power Supply 21 24 O P20 Bit 0 of Port 2 (RCB: System Reset) 22 25 O P21 Bit 1 of Port 2 (GA20: GATE A20) 23 26 /O P22 Bit 2 of Port 2 24 27 VO P23 Bit 3 of Port 2 25 28 - Vcc Optional +5V Power Supply 27 30 VO P10 Bit 0 of Port 1 28 31 VO P11 Bit 1 of Port 1 29 32 VO Pi2 Bit 2 of Port 1 30 33 VO P13 Bit 3 of Port 1 31 35 | P14 Bit 4 of Port 1 (RAM Jumper Select) 32 36 | P15 Bit 5 of Port 1 (JUMP) 33 37 | P16 Bit 6 of Port 1 (Display Select) 34 38 | P17 Bit 7 of Port 1 (K/B Inhibit Switch) Publication Release Date: July 1994 Revision A3inbond SHY... Electronics Corp. Pin description, continued _W83C42 35 39 oO P24 Bit 4 of Port 2 (OBF O/P Interrupt) 36 40 0 P25 Bit 5 of Port 2 (I/P Buffer Empty) 37 4 Oo P26 Bit 6 of Port 2 (K/B Clock O/P) 38 42 oO P27 Bit 7 of Port 2 (K/B Data O/P) 39 43 | T1 K/B Data Input 40 44 - Vcc +5V Power Supply eeYinbond SEY... togtronics Corp... BLOCK DIAGRAM W83C42 TRANSMIT T_ CONTROL r RECEIVE SCAN TT CONTROL : _____] CODE ROM | TRANSMIT XOUT REGISTER xIN HARDWIRE we ______ CONTROL & ____._| STATUS css) __ SELECT a REGISTER a2. LOGIC RESETa | | Res | STATUS PIO BUFFER } | nputa PN REGISTER OUTPUT Piz DATA | w6o PORT -- P14 (RAM Select) DO- 07 d BUFFER ja 2 WEA INPUT INTERFACE _ P15 (Manufacture Mode) REGISTER | Coen oo - P16 (Display) | P17 (KBNH) | [| Reo | OUTPUT P20 (RCB) REGISTER _ P21 (Gate A20) OUTPUT PR PORT Pas INTERFACE | __ p25 -- P26 (Keyboard Clock) -~- P27 (Keyboard Data) AC TIMING NO. DESCRIPTION MIN. MAX. UNIT T1 Address Setup Time from WRB 0 ns T2 Address Setup Time from RDB 0 ns T3 WRB Strobe Width 20 ns T4 RDB Strobe Width 20 ns T5 Address Hold Time from WRB 0 ns T6 Address Hold Time from RDB 0 nS T7 Data Setup Time 50 ns Publication Release Date: July 1994 Revision A3Yinbond . ae os W83C42 HY Electronics Corp, AC timing, continued NO. DESCRIPTION MIN. MAX. UNIT T8 Data Hold Time 0 ns T9 Gate Delay Time from WRB 10 ns T10 RDB to Drive Data Delay 20 ns T11 RDB to Floating Data Delay 0 20 ns T12 Data Valid After Clock Falling (SEND) 4 ps T13 K/B Clock Period 20 LS T14 =| K/B Clock Pulse Width 10 LS T15 Data Valid Before Clock Falling (RECEIVE) 4 pS T16 K/B ACK After Finish Receiving 20 pS T17 RC Fast Reset Pulse Delay (8 MHz) 2 3 us T18 RC Pulse Width (8 MHz) 6 LS T19 Transmit Timeout 2 mS T20 Data Valid Hold Time 0 pS T21 XIN/XOUT Period ( 6-12 MHz ) 83 167 ns WRITE CYCLE TIMING k 11 > ance ee ei ts ow NCTE kK Tr ~% Te 00-07 ee DATA IN ) re OUTPUT pont x | 17 T18 FAST RESET PULS RC FE COMMANDtinbond ee W83C42 READ CYCLE TIMING A2,CS AEN X x <? 14 a Ts or ACTIVE 9, Tu DO - D7 DATA OUT SEND DATA TO K/B wexy SL PL Ls Ly Lt LL Tyg mk TB (8) SErKDAT) START pp X01 X oa X os X ps X os X 08 X ov X PY grop oe m9 RECEIVE DATA FROM K/B CLOCK (KCLK) De EL er a ma SERIAL DATA START <p X pi Xba Xb Xe be Xe XT XP gro T20> K XIN/XOUT CLOCK mnex CLC LL LL EL <- 721 > Publication Release Date: July 1994 -7- Revision A3finbond W83C42 SS ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNIT Ambient Operating Temperature -0 to +85 C Storage Temperature -65 to +150 C Supply Voltage to Ground Potential -0.3 to +7.0 Vv Applied Input/Output Voltage -0.3 to +7.0 Vv Power Dissipation 50 mw ELECTRICAL CHARACTERISTICS & CAPACITANCE (Ta= 0 C to +70 C, Voo= +5V +5%) SYMBOL DESCRIPTION MIN. TYP. MAX. UNIT VDD Power Supply 4.75 5.0 5.25 Vv TA Operating Temperature 0 25 70 Vv VIH High Level Voltage for TTL 2.0 VpD Vv Min, I/P VIL Low Level Voltage for TTL -0.3 0.8 Vv Max. I/P ad VOH High Level Voltage for TTL Vpp-0.5 Vv Min. O/P VOL Low Level Voltage for TTL 0.5 Vv Max. O/P Rip Min. /P Resist 10K Q Iu /P Leakage Current -10 10 pA ILo O/P Leakage Current -10 10 pA IOL O/P Sink Current 4 mA CL O/P Load Capacity 15 50 pF STATUS REGISTER The status register is an 8-bit read-only register at I/O address hex 64 that holds information about the State of the keyboard controller and interface. It may be read at any time. BIT BIT DESCRIPTION FUNCTION 0 Output Buffer Full 0: Output Buffer Empty 1: Output Buffer FullYinbond a W83C42 TY... Rueetronics Corp. Status register, continued BIT BIT DESCRIPTION FUNCTION 1 Input Buffer Full 0: Input Buffer Empty 1: Input Buffer Full 2 System Flag This bit may be set to 0 or 1 by writing to the system flag bit in the command byte of the keyboard controller. It is set to 0 after a power-on reset 3 Command/data 0: Data Byte : Command Byte : Keyboard is Inhibited : Keyboard is Not Inhibited 4 Inhibit Switch : No Transmit Time Out Error 1 0 1 5 Transmit Time Out 0 1: Transmit Time Out Error 0 1 0 1 : No Receive Time Out Error : Receive Time Out Error : Odd Parity (No Error) : Even Parity (Error) 6 Receive Time Out 7 Parity Error OUTPUT BUFFER The output buffer is an 8-bit read-only register at I/O address hex 60. The keyboard controller uses the output buffer to send the scan code received from the keyboard and data bytes required by command to the system. The output buffer should be read only when the output buffer full bit in the register is 1. INPUT BUFFER The input buffer is an 8-bit write-only register at I/O address hex 60 or 64. Writing to address hex 60 sets a flag that indicates a data write; writing to address hex 64 sets a flag that indicates a command write. Data written to [/O address hex 60 is sent to the keyboard (unless the keyboard controller is expecting a data byte) following the controller's input buffer only if the input buffer full bit in the status register is set to 0. VO PORTS The keyboard controller has two 8-bit I/O ports and two test inputs. One of the ports is assigned for input and the other for output. The controller uses the test inputs to read the state of the keyboard's clock line and data line. The following figures show bit definitions for the input, output, and test-input ports. Publication Release Date: July 1994 -9- Revision A3finbond SEES... Electronics Corp. (A) Input Port Defintions W83C42_ BIT FUNCTION Undefined Undefined Undefined Undefined ploln;|o RAM on The System Board 0: Disable 2nd 256 KB of System Board RAM 1: Enable 2nd 256 KB of System Board RAM Manufacturing Jumper Installed 0: Manufacturing Jumper 1: Jumper Not installed Display Type Switch 0: Primary Display Attached to Color/graphics 0: Primary Display Attached to Monochrome Keyboard Inhibit Switch 0: Keyboard Inhibited 1: Keyboard Not Inhibited (B) Output Port Defintions BIT FUNCTION System Reset Gate A20 Undefined Undefined _Output Buffer Full Input Buffer Empty Keyboard Clock (Output) N [OQ] aye ~a; mM) -|o Keyboard Data (Output) (C) Test-Input Defintions BIT FUNCTION 0 Keyboard Clock (Input) 1 Keyboard Data (Input) -10- afinbond ey... Electronica Corp. COMMANDS (VO ADDRESS HEX 64) ws3a2 COMMAND FUNCTION 20 Read Command Byte of Keyboard Controller 60 Write Command Byte of Keyboard Controller BIT BIT DEFINTIONS 7 Reserved 6 IBM PC Compatible Mode 5 IBM PC Mode 4 Disable Keyboard 3 Inhibit Override 2 System Flag 1 Reserved 0 Enable Output Buffer Full Interrupt AA Self-test BIT BIT DEFINTIONS 00 No Error Detected 01 K/B Clock Line is Stuck Low 02 K/B Clock Line is Stuck High 03 K/B Data Line is Stuck Low 04 K/B Data Line is Stuck High AB Interface Test AD Disable Keyboard Feature AE Enable Keyboard Interface co Read Input Port DO Read Output Port D1 Write Output Port EO Read Test Inputs FO-FF Pulse Output Port -]]- Publication Release Date: July 1994 Revision A3Winbond Electronics Corp. APPLICATION CIRCUIT Asynchronous W83C42 3] xg a (RESETS > 4 RESET ain (saz > a +4 yee Aawa > 10 Wa 3 | D3 Ds DS De D7 +1_. ano RAM SELECT JUMPER MANUFACTURING MODE JUMPER | ReRREBER e.. KEYBOARD INHIGIT SWITCH oO + DISPLAY TYPE SWITCH tae KEYBOARD INTERRUPT = +a KEYBOARD CLOCK as? | 11 KEYBOARD DATA | vee UTA UA | yep KEYBOARD Clocx > ot F T4ALS04 7407 ue 2 _ KEYBOARD DATA > 7407 aL TOF qe | | at -12- alltinbond - | _ W83C42 SEY. Electronics Corp. Application circuit, continued Synchronous (Bete >+2_| xy P10 4A] 2 P11 4 P12 a a RESET P13 RAM SELECT JUMPER ' To PI4RAM NFA ' qe pianan MANFACTURING MODE JUMPER {sa2> a2 PISDIs cs P17ANH DISPLAY TYPE SWITCH ORE > ' BD P20Rce __ Own > wR P21/A20 t--__o-o <CM-pr > P22 KEYBOARD INHIBIT SWITCH ' DO P23 = | Bo ra KEYBOARD INTERRUPT = : O2 P25 03 P2B/KCLK : DS P27MKDAT 0S Ds 7 vec | 9 Po | U?A UTA oo 21. yep LKmROARD cLocK > ver 74ALS04 7407 | U?B $ 4 a: Cxeveoanp para | 7407 ' : l | | eee Publication Release Date: July 1994 -13- Revision A3Electronics Corp. inbend BSED PACKAGE INFORMATION 40-pin PDIP | Synge ewan Mi [Ne Mc iN INC Ne A _ jo | [83 Ai {as [Ta | Ar jas far jouw {3s [se [ac B om foci joa [os joa [os Bi [oo [aos foo fi. ju [as c om co ja jar for [os D |205 [zor [saa [aes t E oss jos joer 4s [152 | the Pes Pi te E ase jose fess 1137 [138 | 138 e: fom feo for [22 i25 | 27 L O12 [ais fora do 33 3S D} QO O a | 1a] es joer fess [oer [eo [ies pine E s | [ew PT fe WVU YUM i Net . Dimension 0 Max & inciuce eek 2.Dimensicn E cogs not include + Dimension D& E include meld | Mines m TTC Base Pane Redetemnes at te eae Seating Plane {f 5 erusin intr : 1 I : 6.General cppearance spec. | fing! visual ThE . 40LD P-DIP (600 mil) PACKAGE OUTLINE i | CADPRAME MATERIAL i APPR, DWG NO. P040-SW: RO REY NC. B : OM SCALE | cuk | DAE | T py fev DESCRIPTION DATE DEN. Aven Laiw | SET NO WV CONTROLLED 8 1 vpaote ere . Lite efective decimel O.xx stead of Qoox Mor 30 -14-Yinbond Electronics Corp. 44-pin PLCC W83C42 Syrso" LDimension in inch |omers.on in ore | Min | Nom | Mex Min {Norm =. Max | A | jaw | | [ax A Ay jac | | fos | ] ' as Az {ors [e190 lois | see [sar | 396 | by jocze {c.02z8 joo3z [ose [or [oa 1 t |) po b core [oor [coz fos: [ose | 056 | S Ly a 4 Co | a) 0.648 [e653 jesse hese [1659 [16.71 = 5 i rE cess C652 [0.652 1646 |16.59 [1671 4 5 | 5 .05 BSC 1 ha? ase CO Ge {6.590 jos:o [oss i495 its49 [6.00 5 oe Ge |essc_loe:o |os30 ass iis49 |*6.00 bof) He _[oeae oe@90 [o7oo i727 [-753 [27.78 : | He [9680 joega [a7oc [17.27 17.53. |'7.78 4 | L_jneso fotoo farce [229 | 254 | 2.79 d | y | | |oo | . Joie ro pe ; Rote: | tOmersion 2 & co not inc-ude interleat a a fleas 2.Dimension t does ret include darrace protrusion /intrusior Comeching dimension + if.ch 4.Genera appearance spec. shoulc be dosed | an an fing: visual inspection soer. | = | [i I | an = | fo i IF fi V4 1 !y i vf i i = | ee BAA Ea jd y [iE 44LD PLC (0.85239) ; ~_ tLe b PACKAGE OUTLIN \ Seating Plane LEADFRAME. NATERIAL AIS! 3/4. APPR, ' WG NO coee-SH" R&D : j REV NO. E OM SCALE i CRK | OWE | - ve , copy jREV KC DESCRPT ON DWE OEN Aven Laiw SHT NC tf} CONTROLLED | 8 1 V.badare form . 2The effective cecire C.xx irsteod cf O.xxx Feo.10 | _in the netic sysier - 15 - Publication Release Date: July 1994 Revision A3=) Winbond rt Electronics Corp. CORPORATE HEADQUARTERS: Winbond Electronics (H.K.) Ltd. Winbond Electronics North America Corp NO. 4, Creation Rd. II Rm. 803 World Trade Square, Tower II, 90 West Plumeric Drive Science-Based Industrial Park 123 Hoi Bun Road, Kwun Tong, San Jose, CA 95134 Hsinchu, Taiwan, R.O.C. Kowloon, Hong Kong U.S.A. TEL: 886-35-770066 TEL: 852-751-6023-7 TEL: 1-408-943-6666 FAX: 886-35-789467 FAX: 852-755-2064 FAX: 1-408-943-6668 TAIPEI SALES OFFICE: 11F, No. 115, Sec. 3, Min Sheng E. Rd, Taipei, Taiwan, R.O.C. TEL: 886-2-719-0505 FAX: 886-2-719-7502 TLX: 16485 WINTPE Note: All data and specifications are subject to change without notice. Publication Release Date: July 1994 Revision A3