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Philips Semiconductors Product specification
N-channel enhancement mode BSP100
TrenchMOS transistor
FEATURES SYMBOL QUICK REFERENCE DATA
• ’Trench’ technology VDSS = 30 V
• Low on-state resistance
• Fast switching ID = 6 A
• High thermal cycling performance
• Low thermal resistance RDS(ON) ≤ 100 mΩ (VGS = 10 V)
RDS(ON) ≤ 200 mΩ (VGS = 4.5 V)
GENERAL DESCRIPTION PINNING SOT223
N-channel enhancement mode PIN DESCRIPTION
field-effect transistor in a plastic
envelope using ’trench’ 1 gate
technology. 2 drain
Applications:-
• Motor and relay drivers 3 source
• d.c. to d.c. converters
• Logic level translator 4 drain (tab)
The BSP100 is supplied in the
SOT223 surface mounting
package.
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDSS Drain-source voltage Tj = 25 ˚C to 150˚C - 30 V
VDGR Drain-gate voltage Tj = 25 ˚C to 150˚C; RGS = 20 kΩ-30V
VGS Gate-source voltage - ± 20 V
IDContinuous drain current Tsp = 25 ˚C - 61A
Tsp = 100 ˚C - 4.4 A
Tamb = 25 ˚C - 3.2 A
IDM Pulsed drain current Tsp = 25 ˚C - 24 A
PDTotal power dissipation Tsp = 25 ˚C - 8.3 W
Tj, Tstg Operating junction and - 65 150 ˚C
storage temperature
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
Rth j-sp Thermal resistance junction to surface mounted, FR4 12 15 K/W
solder point board
Rth j-amb Thermal resistance junction to surface mounted, FR4 70 - K/W
ambient board
d
g
s
4
123
1 Continuous current rating limited by package
February 1999 1 Rev 1.000
Philips Semiconductors Product specification
N-channel enhancement mode BSP100
TrenchMOS transistor
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
EAS Non-repetitive avalanche Unclamped inductive load, IAS = 6 A; - 23 mJ
energy tp = 0.2 ms; Tj prior to avalanche = 25˚C;
VDD ≤ 15 V; RGS = 50 Ω; VGS = 10 V
IAS Non-repetitive avalanche - 6 A
current
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V(BR)DSS Drain-source breakdown VGS = 0 V; ID = 10 µA; 30 - - V
voltage Tj = -55˚C 27 - - V
VGS(TO) Gate threshold voltage VDS = VGS; ID = 1 mA 1 2 2.8 V
Tj = 150˚C 0.4 - - V
Tj = -55˚C - 3.2 V
RDS(ON) Drain-source on-state VGS = 10 V; ID = 2.2 A - 80 100 mΩ
resistance VGS = 4.5 V; ID = 1 A - 120 200 mΩ
VGS = 10 V; ID = 2.2 A; Tj = 150˚C - - 170 mΩ
gfs Forward transconductance VDS = 20 V; ID = 2.2 A 2 4.5 - S
ID(ON) On-state drain current VGS = 10 V; VDS = 1 V; 3.5 - - A
VGS = 4.5 V; VDS = 5 V 2 - - A
IDSS Zero gate voltage drain VDS = 24 V; VGS = 0 V; - 10 100 nA
current VDS = 24 V; VGS = 0 V; Tj = 150˚C - 0.6 10 µA
IGSS Gate source leakage current VGS = ±20 V; VDS = 0 V - 10 100 nA
Qg(tot) Total gate charge ID = 2.3 A; VDD = 15 V; VGS = 10 V - 6 - nC
Qgs Gate-source charge - 0.7 - nC
Qgd Gate-drain (Miller) charge - 0.7 - nC
td on Turn-on delay time VDD = 20 V; RD = 18 Ω;-6-ns
trTurn-on rise time VGS = 10 V; RG = 6 Ω-8-ns
td off Turn-off delay time Resistive load - 21 - ns
tfTurn-off fall time - 15 - ns
LdInternal drain inductance Measured tab to centre of die - 2.5 - nH
LsInternal source inductance Measured from source lead to source - 5 - nH
bond pad
Ciss Input capacitance VGS = 0 V; VDS = 20 V; f = 1 MHz - 250 - pF
Coss Output capacitance - 88 - pF
Crss Feedback capacitance - 54 - pF
February 1999 2 Rev 1.000
Philips Semiconductors Product specification
N-channel enhancement mode BSP100
TrenchMOS transistor
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
ISContinuous source current Tsp = 25 ˚C - - 6 A
(body diode)
ISM Pulsed source current (body - - 24 A
diode)
VSD Diode forward voltage IF = 1.25 A; VGS = 0 V - 0.82 1.2 V
trr Reverse recovery time IF = 1.25 A; -dIF/dt = 100 A/µs; - 69 - ns
Qrr Reverse recovery charge VGS = 0 V; VR = 25 V - 55 - nC
Fig.1. Normalised power dissipation.
PD% = 100
⋅
P
D
/P
D 25 ˚C
= f(T
sp
)
Fig.2. Normalised continuous drain current.
ID% = 100
⋅
I
D
/I
D 25 ˚C
= f(T
sp
); conditions: V
GS
≥
10 V
Fig.3. Safe operating area. T
sp
= 25 ˚C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.4. Transient thermal impedance.
Z
th j-sp
= f(t); parameter D = t
p
/T
0 20 40 60 80 100 120 140
PD% Normalised Power Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
Tsp / C
BSP100
0.1
1
10
100
1 10 100
Drain-Source Voltage, VDS (V)
Peak Pulsed Drain Current, IDM (A)
d.c.
100 ms
10 ms
RDS(on) = VDS/ ID
1 ms
tp = 10 us
100 us
0 20 40 60 80 100 120 140
ID% Normalised Current Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
Tsp / C
BSP100
0.01
0.1
1
10
100
1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01
Pulse width, tp (s)
Peak Pulsed Drain Current, IDM (A)
single pulse
D = 0.5
0.2
0.1
0.05
0.02
tp D = tp/T
D
P
T
February 1999 3 Rev 1.000
Philips Semiconductors Product specification
N-channel enhancement mode BSP100
TrenchMOS transistor
Fig.5. Typical output characteristics, T
j
= 25 ˚C
.
I
D
= f(V
DS
); parameter V
GS
Fig.6. Typical on-state resistance, T
j
= 25 ˚C
.
R
DS(ON)
= f(I
D
); parameter V
GS
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
); parameter T
j
Fig.8. Typical transconductance, T
j
= 25 ˚C
.
g
fs
= f(I
D
)
; parameter T
j
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
)
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
0
1
2
3
4
5
6
7
8
9
10
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Drain-Source Voltage, VDS (V)
Drain Current, ID (A)
3.2 V
3.4 V
4 V
Tj = 25 C
VGS = 20 V
3.6 V
3.8 V
5V
10 V
4.2 V
0
1
2
3
4
5
6
012345678910
Drain current, ID (A)
Transconductance, gfs (S)
Tj = 25 C
150 C
0
0.1
0.2
0.3
0.4
0.5
012345678910
Drain Current, ID (A)
Drain-Source On Resistance, RDS(on) (Ohms)
VGS =5 V
4.2 V
20V
Tj = 25 C
3.8V 4 V
3.6 V
10V
3.2 V3.4 V
-50 0 50 100 150
0
0.5
1
1.5
2SOT223 30V Trench
Tj / C
aNormalised RDS(ON) = f(Tj)
0
1
2
3
4
5
6
7
8
9
10
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
Gate-source voltage, VGS (V)
Drain current, ID (A)
VDS > ID X RDS(ON)
Tj = 25 C 150 C
-60 -40 -20 0 20 40 60 80 100 120 140
Tj / C
VGS(TO) / V
4
3
2
1
0
max.
typ.
min.
February 1999 4 Rev 1.000
Philips Semiconductors Product specification
N-channel enhancement mode BSP100
TrenchMOS transistor
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 ˚C; V
DS
= V
GS
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); parameter V
DS
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
Fig.15. Maximum permissible non-repetitive
avalanche current (I
AS
) versus avalanche time (t
p
);
unclamped inductive load
012345
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01 Sub-Threshold Conduction
typmin max
0
1
2
3
4
5
6
7
8
9
10
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5
Drain-Source Voltage, VSDS (V)
Source-Drain Diode Current, IF (A)
Tj = 25 C
150 C
VGS = 0 V
10
100
1000
0.1 1 10 100
Drain-Source Voltage, VDS (V)
Capacitances, Ciss, Coss, Crss (pF)
Ciss
Coss
Crss
BSP100
0.1
1
10
1E-06 1E-05 1E-04 1E-03 1E-02
Avalanche time, tp (s)
Non-repetitive Avalanche current, IAS (A)
25 C
VDS
ID tp
Tj prior to avalanche =125 C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
012345678910
Gate charge, QG (nC)
Gate-source voltage, VGS (V)
ID = 2.3A
Tj = 25 C
VDD = 15 V
February 1999 5 Rev 1.000
Philips Semiconductors Product specification
N-channel enhancement mode BSP100
TrenchMOS transistor
PRINTED CIRCUIT BOARD
Dimensions in mm.
Fig.16. PCB for thermal resistance and power rating for SOT223.
PCB: FR4 epoxy glass (1.6 mm thick), copper laminate (35
µ
m thick).
36
60
9
10
4.6
18
4.5
7
15
50
February 1999 6 Rev 1.000
Philips Semiconductors Product specification
N-channel enhancement mode BSP100
TrenchMOS transistor
MECHANICAL DATA
Fig.17. SOT223 surface mounting package.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to Discrete Semiconductor Packages, Data Handbook SC18.
3. Epoxy meets UL94 V0 at 1/8".
UNIT A
1
b
p
cDEe
1
H
E
L
p
Qywv
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
mm 0.10
0.01
1.8
1.5 0.80
0.60
b
1
3.1
2.9 0.32
0.22 6.7
6.3 3.7
3.3 2.3
e
4.6 7.3
6.7 1.1
0.7 0.95
0.85 0.1 0.10.2
DIMENSIONS (mm are the original dimensions)
SOT223 96-11-11
97-02-28
w
M
b
p
D
b
1
e
1
e
A
A
1
L
p
Q
detail X
H
E
E
v
M
A
AB
B
c
y
0 2 4 mm
scale
A
X
132
4
Plastic surface mounted package; collector pad for good heat transfer; 4 leads SOT223
February 1999 7 Rev 1.000
Philips Semiconductors Product specification
N-channel enhancement mode BSP100
TrenchMOS transistor
DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
February 1999 8 Rev 1.000
