DATA SHEET SK70704/SK70707 or SK70708 1168 kbps HDSL Data Pump Chip Set P. 4 a Orctersie- ie The HDSL Data Pump is a chip set consisting of the fol- lowing two devices: * SK70704 Analog Core Chip (ACC) * SK70707 (68-pin PLCC) or $K70708 (44-pin PLCC) HDSL Digital Transceiver (HDX) The HDSL Data Pump is a 2-wire transceiver which pro- vides echo-cancelling and 2B1Q line coding. It incorpo- rates transmit pulse shaping, filtering, line drivers. receive equalization, timing and data recovery to provide 1168 kbps, clear-channel, data pipe transmission. The Data Pump provides Near-End Cross-Talk (NEXT) perfor- mance in excess of that required over all ETS] test loops. Typical transmission range on 0.4 mm cable exceeds 3.6 km in a noise-free environment or 2.8 km with a 0 dB mar- gin over 10 uVNHZ ETSI noise. The Data Pump meets the requirements of ETSI ETR-152. It provides one end of a single-channel HDSL transmission system from the twisted pair interface back to the Data Pump/HDSL data interface. The Data Pump can be used at either the NTU or the LTU end of the interface. Applications + El (2-pair) and fractional El transport N-channel digital pair-gain * Wireless base station to switch interface * Campus and private networking * High-Speed digital modems HDSL Data Pump Block Diagram Hox CK9M Scramble TDATA TFP Control RDATA RFP ICLK LTU LOSW REFCLK Circuit DATA ADDR CTRL 5-22 AUGUST 1997 Revision 3.0 Fully integrated, 2-chip set for interfacing to 2-wire HDSL lines at 1168 kbps Single +5 V supply Integrated line drivers, filters and hybrid circuits re- sult in greatly reduced external logic and simplified support circuitry requirements Simple line interface circuitry, via transformer cou- pling, to twisted pair line Internal ACC voltage reference Integrated VCXO circuitry Converts serial binary data to scrambled 2B1Q encoded data Self-contained activation/start-up state machine for simplified single loop designs Programmable for either line termination (LTU) or network termination (NTU) applications Compliant with ETSI ETR-152 (1995) Design allows for operation in either Software Con- trol or stand alone Hardware Control mode Typical power consumption less than 1.2 W allowing remote power feeding for repeater and NTU equip- ment Input or Output Reference Clock of 18.688 MHz Digital representation of receive signal level and noise margin values available for SNR controlled ac- tivation ACC TCK TTiP TSGN t Encoder TMAG TRING ADO ADT A/D Modulator RTIP BRING RRING BTIP IBIAS Xt K3 VCO xo VPLL AGCKIK FS o Various OTR Blocks