The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 16 H8S/2268Group, H8S/2264Group Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2000 Series H8S/2268 HD64F2268 HD6432268 HD6432268W H8S/2266 HD64F2266 HD6432266 HD6432266W H8S/2265 HD64F2265 HD6432265 HD6432265W H8S/2264 HD6432264 HD6432264W H8S/2262 HD6432262 HD6432262W Rev.3.00 2003.8.28 Rev. 3.00, 08/03, page ii of xxxviii Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. Rev. 3.00, 08/03, page iii of xxxviii General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed. Rev. 3.00, 08/03, page iv of xxxviii Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules * * CPU and System-Control Modules On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix 10. Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index Rev. 3.00, 08/03, page v of xxxviii Preface This LSI is a high-performance microcontroller (MCU) made up of the H8S/2000 CPU with an internal 32-bit configuration as its core, and the peripheral functions required to configure a system. A single-power flash memory (F-ZTATTM)* version and a masked-ROM version are available for this LSI's ROM. The F-ZTAT version provides flexibility as it can be reprogrammed in no time to cope with all situations from the early stages of mass production to full-scale mass production. This is particularly applicable to application devices with specifications that will most probably change. Note: * F-ZTATTM is a trademark of Renesas Technology Corp. Target Users: This manual was written for users who will be using the H8S/2268 Group and H8S/2264 Group in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the H8S/2268 Group and H8S/2264 Group to the target users. Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a detailed description of the instruction set. Notes on reading this manual: * In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. * In order to understand the details of the CPU's functions Read the H8S/2600 Series, H8S/2000 Series Programming Manual. * In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 24, List of Registers. Examples: Register name: The following notation is used for cases when the same or a similar function, e.g. 16-bit timer pulse unit or serial communication, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) Bit order: The MSB is on the left and the LSB is on the right. Rev. 3.00, 08/03, page vi of xxxviii List of on-chip peripheral functions: Group Name H8S/2268 Group H8S/2264 Group Product Name H8S/2268, 2266, 2265 H8S/2264, 2262 PC break controller (PBC) X2 Data transfer controller (DTC) X1 16-bit timer pulse unit (TPU) X3 X2 8-bit timer (TMR_0 to TMR_3) X4 X2 8-bit reload timer (TMR_4) X4 Watch dog timer (WDT) X2 X2 Serial communication interface (SCI) X3 X3 I C bus interface (IIC) X 2 (option) X 1 (option) A/D converter X 10 X 10 2 D/A converter X2 LCD controller/driver 40 SEG/4 COM 40 SEG/4 COM DTMF generation circuit X1 Ports 1, 3, 4, 7, 9, F, H, J to N 1, 3, 4, 7, 9, F, H, J to L External interrupts 14 13 Interrupt priorities 8 levels Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/eng/ H8S/2268 Group, H8S/2264 Group manuals: Document Title Document No. H8S/2268 Group, H8S/2264 Group Hardware Manual This manual H8S/2600 Series, H8S/2000 Series Programming Manual ADE-602-083 Rev. 3.00, 08/03, page vii of xxxviii User's manuals for development tools: Document Title Document No. H8S, H8/300 Series C/C++ Compiler, Assembler, Optimized Linkage Editor User's Manual ADE-702-247 H8S, H8/300 Series Simulator/Debugger User's Manual ADE-702-282 H8S, H8/300 Series High-performance Embedded Workshop, High-performance Debugging Interface Tutorial ADE-702-231 High-performance Embedded Workshop User's Manual ADE-702-201 Application Notes: Document Title Document No. C/C++ Compiler Guide ADE-702-189 F-ZTAT Technical Q & A ADE-502-046 Rev. 3.00, 08/03, page viii of xxxviii Contents Section 1 Overview........................................................................................... 1 1.1 1.2 1.3 1.4 Features ............................................................................................................................. 1 Internal Block Diagram..................................................................................................... 3 Pin Arrangement ............................................................................................................... 5 Pin Functions .................................................................................................................... 7 Section 2 CPU................................................................................................... 11 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 Features ............................................................................................................................. 11 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU .................................. 12 2.1.2 Differences from H8/300 CPU ............................................................................ 13 2.1.3 Differences from H8/300H CPU.......................................................................... 13 CPU Operating Modes ...................................................................................................... 14 2.2.1 Normal Mode....................................................................................................... 14 2.2.2 Advanced Mode ................................................................................................... 15 Address Space ................................................................................................................... 18 Register Configuration ...................................................................................................... 19 2.4.1 General Registers ................................................................................................. 20 2.4.2 Program Counter (PC) ......................................................................................... 21 2.4.3 Extended Control Register (EXR) (H8S/2268 Group Only)................................ 21 2.4.4 Condition-Code Register (CCR) .......................................................................... 22 2.4.5 Initial Values of CPU Registers ........................................................................... 23 Data Formats ..................................................................................................................... 24 2.5.1 General Register Data Formats ............................................................................ 24 2.5.2 Memory Data Formats ......................................................................................... 26 Instruction Set ................................................................................................................... 27 2.6.1 Table of Instructions Classified by Function ....................................................... 28 2.6.2 Basic Instruction Formats .................................................................................... 37 Addressing Modes and Effective Address Calculation ..................................................... 38 2.7.1 Register DirectRn............................................................................................. 39 2.7.2 Register Indirect@ERn .................................................................................... 39 2.7.3 Register Indirect with Displacement@(d:16, ERn) or @(d:32, ERn).............. 39 2.7.4 Register Indirect with Post-Increment or Pre-Decrement@ERn+ or @-ERn .. 39 2.7.5 Absolute Address@aa:8, @aa:16, @aa:24, or @aa:32.................................... 39 2.7.6 Immediate#xx:8, #xx:16, or #xx:32 ................................................................. 40 2.7.7 Program-Counter Relative@(d:8, PC) or @(d:16, PC).................................... 40 2.7.8 Memory Indirect@@aa:8 ................................................................................ 40 2.7.9 Effective Address Calculation.............................................................................. 41 Processing States............................................................................................................... 44 Usage Notes ...................................................................................................................... 46 Rev. 3.00, 08/03, page ix of xxxviii 2.9.1 2.9.2 2.9.3 TAS Instruction.................................................................................................... 46 STM/LDM Instruction ......................................................................................... 46 Bit Manipulation Instructions .............................................................................. 46 Section 3 MCU Operating Modes .....................................................................47 3.1 3.2 3.3 3.4 Operating Mode Selection ................................................................................................ 47 Register Description.......................................................................................................... 47 3.2.1 Mode Control Register (MDCR) ......................................................................... 48 Operating Mode ................................................................................................................ 48 Address Map ..................................................................................................................... 49 Section 4 Exception Handling ...........................................................................51 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 Exception Handling Types and Priority............................................................................ 51 Exception Sources and Exception Vector Table ............................................................... 52 Reset ................................................................................................................................. 53 4.3.1 Reset Exception Handling.................................................................................... 53 4.3.2 Interrupts after Reset............................................................................................ 54 4.3.3 State of On-Chip Peripheral Modules after Reset Release................................... 54 Traces (Supported only by the H8S/2268 Group)............................................................. 55 Interrupts........................................................................................................................... 55 Trap Instruction................................................................................................................. 56 Stack Status after Exception Handling.............................................................................. 57 Usage Note........................................................................................................................ 57 Section 5 Interrupt Controller............................................................................59 5.1 5.2 5.3 5.4 5.5 Features............................................................................................................................. 59 Input/Output Pins .............................................................................................................. 62 Register Descriptions ........................................................................................................ 63 5.3.1 System Control Register (SYSCR) ...................................................................... 63 5.3.2 Interrupt Priority Registers A to G, I to M, and O (IPRA to IPRG, IPRI to IPRM, IPRO) (H8S/2268 Group Only) ........................ 65 5.3.3 IRQ Enable Register (IER) .................................................................................. 66 5.3.4 IRQ Sense Control Registers H and L (ISCRH and ISCRL) ............................... 67 5.3.5 IRQ Status Register (ISR).................................................................................... 69 5.3.6 Wakeup Interrupt Request Register (IWPR)........................................................ 71 5.3.7 Interrupt Enable Register 1 (IENR1) ................................................................... 71 Interrupt Sources............................................................................................................... 72 5.4.1 External Interrupts ............................................................................................... 72 5.4.2 Internal Interrupts ................................................................................................ 75 5.4.3 Interrupt Exception Handling Vector Table......................................................... 75 Operation .......................................................................................................................... 79 5.5.1 Interrupt Control Modes and Interrupt Operation ................................................ 79 5.5.2 Interrupt Control Mode 0 ..................................................................................... 82 Rev. 3.00, 08/03, page x of xxxviii 5.6 5.5.3 Interrupt Control Mode 2 (H8S/2268 Group Only) ............................................. 84 5.5.4 Interrupt Exception Handling Sequence .............................................................. 85 5.5.5 Interrupt Response Times .................................................................................... 87 5.5.6 DTC Activation by Interrupt (H8S/2268 Group Only) ........................................ 88 Usage Notes ...................................................................................................................... 88 5.6.1 Contention between Interrupt Generation and Disabling..................................... 88 5.6.2 Instructions that Disable Interrupts ...................................................................... 89 5.6.3 When Interrupts Are Disabled ............................................................................. 89 5.6.4 Interrupts during Execution of EEPMOV Instruction.......................................... 89 Section 6 PC Break Controller (PBC) .............................................................. 91 6.1 6.2 6.3 6.4 Features ............................................................................................................................. 91 Register Descriptions ........................................................................................................ 92 6.2.1 Break Address Register A (BARA) ..................................................................... 92 6.2.2 Break Address Register B (BARB)...................................................................... 93 6.2.3 Break Control Register A (BCRA) ...................................................................... 93 6.2.4 Break Control Register B (BCRB)....................................................................... 94 Operation........................................................................................................................... 94 6.3.1 PC Break Interrupt Due to Instruction Fetch ....................................................... 94 6.3.2 PC Break Interrupt Due to Data Access............................................................... 94 6.3.3 Notes on PC Break Interrupt Handling ................................................................ 95 6.3.4 Operation in Transitions to Power-Down Modes ................................................ 95 6.3.5 When Instruction Execution Is Delayed by One State ......................................... 96 Usage Notes ...................................................................................................................... 97 6.4.1 Module Stop Mode Setting .................................................................................. 97 6.4.2 PC Break Interrupts.............................................................................................. 97 6.4.3 CMFA and CMFB ............................................................................................... 97 6.4.4 PC Break Interrupt when DTC Is Bus Master...................................................... 97 6.4.5 PC Break Set for Instruction Fetch at Address Following BSR, JSR, JMP, TRAPA, RTE, or RTS Instruction ....................................................................... 97 6.4.6 I Bit Set by LDC, ANDC, ORC, or XORC Instruction ....................................... 97 6.4.7 PC Break Set for Instruction Fetch at Address Following Bcc Instruction.......... 98 6.4.8 PC Break Set for Instruction Fetch at Branch Destination Address of Bcc Instruction ..................................................................................................... 98 Section 7 Bus Controller................................................................................... 99 7.1 7.2 Basic Timing ..................................................................................................................... 99 7.1.1 On-Chip Memory Access Timing (ROM, RAM) ................................................ 99 7.1.2 On-Chip Peripheral Module Access Timing (H'FFFDAC to H'FFFFBF) ........... 100 7.1.3 On-Chip Peripheral Module Access Timing (H'FFFC30 to H'FFFCA3)............. 100 Bus Arbitration (H8S/2268 Group Only).......................................................................... 101 7.2.1 Order of Priority of the Bus Masters.................................................................... 101 7.2.2 Bus Transfer Timing ............................................................................................ 102 Rev. 3.00, 08/03, page xi of xxxviii 7.2.3 Resets and the Bus Controller.............................................................................. 102 Section 8 Data Transfer Controller (DTC) ........................................................103 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 Features............................................................................................................................. 103 Register Descriptions ........................................................................................................ 105 8.2.1 DTC Mode Register A (MRA) ............................................................................ 106 8.2.2 DTC Mode Register B (MRB)............................................................................. 107 8.2.3 DTC Source Address Register (SAR).................................................................. 107 8.2.4 DTC Destination Address Register (DAR).......................................................... 107 8.2.5 DTC Transfer Count Register A (CRA) .............................................................. 108 8.2.6 DTC Transfer Count Register B (CRB)............................................................... 108 8.2.7 DTC Enable Register (DTCER) .......................................................................... 108 8.2.8 DTC Vector Register (DTVECR)........................................................................ 109 Activation Sources ............................................................................................................ 109 Location of Register Information and DTC Vector Table ................................................ 110 Operation .......................................................................................................................... 113 8.5.1 Normal Mode....................................................................................................... 114 8.5.2 Repeat Mode........................................................................................................ 115 8.5.3 Block Transfer Mode ........................................................................................... 116 8.5.4 Chain Transfer ..................................................................................................... 117 8.5.5 Interrupts.............................................................................................................. 118 8.5.6 Operation Timing................................................................................................. 119 8.5.7 Number of DTC Execution States ....................................................................... 120 Procedures for Using DTC................................................................................................ 122 8.6.1 Activation by Interrupt......................................................................................... 122 8.6.2 Activation by Software ........................................................................................ 122 Examples of Use of DTC .................................................................................................. 122 8.7.1 Normal Mode....................................................................................................... 122 8.7.2 Software Activation ............................................................................................. 123 Usage Notes ...................................................................................................................... 124 8.8.1 Module Stop Mode Setting .................................................................................. 124 8.8.2 On-Chip RAM ..................................................................................................... 124 8.8.3 DTCE Bit Setting................................................................................................. 124 Section 9 I/O Ports.............................................................................................125 9.1 9.2 Port 1................................................................................................................................. 131 9.1.1 Port 1 Data Direction Register (P1DDR)............................................................. 131 9.1.2 Port 1 Data Register (P1DR)................................................................................ 131 9.1.3 Port 1 Register (PORT1)...................................................................................... 132 9.1.4 Pin Functions ....................................................................................................... 132 Port 3................................................................................................................................. 136 9.2.1 Port 3 Data Direction Register (P3DDR)............................................................. 136 9.2.2 Port 3 Data Register (P3DR)................................................................................ 137 Rev. 3.00, 08/03, page xii of xxxviii 9.2.3 Port 3 Register (PORT3)...................................................................................... 137 9.2.4 Port 3 Open Drain Control Register (P3ODR)..................................................... 138 9.2.5 Pin Functions ....................................................................................................... 138 9.3 Port 4................................................................................................................................. 141 9.3.1 Port 4 Register (PORT4)...................................................................................... 141 9.3.2 Pin Functions ....................................................................................................... 141 9.4 Port 7................................................................................................................................. 142 9.4.1 Port 7 Data Direction Register (P7DDR)............................................................. 142 9.4.2 Port 7 Data Register (P7DR)................................................................................ 142 9.4.3 Port 7 Register (PORT7)...................................................................................... 143 9.4.4 Pin Functions ....................................................................................................... 143 9.5 Port 9................................................................................................................................. 145 9.5.1 Port 9 Register (PORT9)...................................................................................... 145 9.5.2 Pin Functions ....................................................................................................... 145 9.6 Port F................................................................................................................................. 146 9.6.1 Port F Data Direction Register (PFDDR) ............................................................ 146 9.6.2 Port F Data Register (PFDR) ............................................................................... 146 9.6.3 Port F Register (PORTF) ..................................................................................... 147 9.6.4 Pin Functions ....................................................................................................... 147 9.7 Port H................................................................................................................................ 148 9.7.1 Port H Data Direction Register (PHDDR) ........................................................... 148 9.7.2 Port H Data Register (PHDR) .............................................................................. 148 9.7.3 Port H Register (PORTH) .................................................................................... 149 9.7.4 Pin Functions ....................................................................................................... 149 9.8 Port J ................................................................................................................................. 151 9.8.1 Port J Data Direction Register (PJDDR).............................................................. 152 9.8.2 Port J Data Register (PJDR)................................................................................. 152 9.8.3 Port J Register (PORTJ)....................................................................................... 153 9.8.4 Port J Pull-Up MOS Control Register (PJPCR)................................................... 153 9.8.5 Wakeup Control Register (WPCR)...................................................................... 154 9.8.6 Pin Functions ....................................................................................................... 154 9.8.7 Input Pull-Up MOS Function............................................................................... 155 9.9 Port K................................................................................................................................ 156 9.9.1 Port K Data Direction Register (PKDDR) ........................................................... 156 9.9.2 Port K Data Register (PKDR) .............................................................................. 156 9.9.3 Port K Register (PORTK) .................................................................................... 157 9.9.4 Pin Functions ....................................................................................................... 157 9.10 Port L ................................................................................................................................ 158 9.10.1 Port L Data Direction Register (PLDDR) ............................................................ 158 9.10.2 Port L Data Register (PLDR)............................................................................... 158 9.10.3 Port L Register (PORTL)..................................................................................... 159 9.10.4 Pin Functions ....................................................................................................... 159 9.11 Port M (H8S/2268 Group Only) ....................................................................................... 160 Rev. 3.00, 08/03, page xiii of xxxviii 9.11.1 Port M Data Direction Register (PMDDR).......................................................... 160 9.11.2 Port M Data Register (PMDR) ............................................................................ 160 9.11.3 Port M Register (PORTM) .................................................................................. 161 9.11.4 Pin Functions ....................................................................................................... 161 9.12 Port N (H8S/2268 Group Only) ........................................................................................ 162 9.12.1 Port N Data Direction Register (PNDDR) ........................................................... 162 9.12.2 Port N Data Register (PNDR).............................................................................. 162 9.12.3 Port N Register (PORTN).................................................................................... 163 9.12.4 Pin Functions ....................................................................................................... 163 Section 10 16-Bit Timer Pulse Unit (TPU) .......................................................165 10.1 Features............................................................................................................................. 165 10.2 Input/Output Pins .............................................................................................................. 170 10.3 Register Descriptions ........................................................................................................ 171 10.3.1 Timer Control Register (TCR)............................................................................. 172 10.3.2 Timer Mode Register (TMDR) ............................................................................ 175 10.3.3 Timer I/O Control Register (TIOR) ..................................................................... 177 10.3.4 Timer Interrupt Enable Register (TIER) .............................................................. 186 10.3.5 Timer Status Register (TSR)................................................................................ 187 10.3.6 Timer Counter (TCNT)........................................................................................ 191 10.3.7 Timer General Register (TGR) ............................................................................ 191 10.3.8 Timer Start Register (TSTR) ............................................................................... 192 10.3.9 Timer Synchro Register (TSYR) ......................................................................... 193 10.4 Interface to Bus Master ..................................................................................................... 194 10.4.1 16-Bit Registers ................................................................................................... 194 10.4.2 8-Bit Registers ..................................................................................................... 194 10.5 Operation .......................................................................................................................... 195 10.5.1 Basic Functions.................................................................................................... 195 10.5.2 Synchronous Operation........................................................................................ 200 10.5.3 Buffer Operation (H8S/2268 Group Only) .......................................................... 202 10.5.4 PWM Modes........................................................................................................ 205 10.5.5 Phase Counting Mode (H8S/2268 Group Only) .................................................. 210 10.6 Interrupt Sources............................................................................................................... 215 10.7 DTC Activation (H8S/2268 Group Only)......................................................................... 216 10.8 A/D Converter Activation................................................................................................. 216 10.9 Operation Timing.............................................................................................................. 217 10.9.1 Input/Output Timing ............................................................................................ 217 10.9.2 Interrupt Signal Timing........................................................................................ 221 10.10 Usage Notes ...................................................................................................................... 224 10.10.1 Module Stop Mode Setting .................................................................................. 224 10.10.2 Input Clock Restrictions ...................................................................................... 224 10.10.3 Caution on Period Setting .................................................................................... 225 10.10.4 Contention between TCNT Write and Clear Operations..................................... 225 Rev. 3.00, 08/03, page xiv of xxxviii 10.10.5 Contention between TCNT Write and Increment Operations.............................. 226 10.10.6 Contention between TGR Write and Compare Match ......................................... 226 10.10.7 Contention between Buffer Register Write and Compare Match (H8S/2268 Group Only)....................................................................................... 227 10.10.8 Contention between TGR Read and Input Capture.............................................. 228 10.10.9 Contention between TGR Write and Input Capture............................................. 228 10.10.10 Contention between Buffer Register Write and Input Capture (H8S/2268 Group Only)................................................................................... 229 10.10.11 Contention between Overflow/Underflow and Counter Clearing.................... 230 10.10.12 Contention between TCNT Write and Overflow/Underflow........................... 231 10.10.13 Multiplexing of I/O Pins .................................................................................. 231 10.10.14 Interrupts in Module Stop Mode ...................................................................... 231 Section 11 8-Bit Timers .................................................................................... 233 11.1 8-Bit Timer Module (TMR_0, TMR_1, TMR_2, and TMR_3)........................................ 233 11.1.1 Features................................................................................................................ 233 11.2 Input/Output Pins .............................................................................................................. 235 11.3 Register Descriptions ........................................................................................................ 235 11.3.1 Timer Counter (TCNT)........................................................................................ 236 11.3.2 Time Constant Register A (TCORA)................................................................... 236 11.3.3 Time Constant Register B (TCORB) ................................................................... 236 11.3.4 Timer Control Register (TCR) ............................................................................. 237 11.3.5 Timer Control/Status Register (TCSR) ................................................................ 239 11.4 Operation........................................................................................................................... 243 11.4.1 Pulse Output......................................................................................................... 243 11.5 Operation Timing.............................................................................................................. 244 11.5.1 TCNT Incrementation Timing ............................................................................. 244 11.5.2 Timing of CMFA and CMFB Setting When a Compare-Match Occurs.............. 244 11.5.3 Timing of Timer Output When a Compare-Match Occurs .................................. 245 11.5.4 Timing of Compare-Match Clear When a Compare-Match Occurs .................... 245 11.5.5 TCNT External Reset Timing .............................................................................. 246 11.5.6 Timing of Overflow Flag (OVF) Setting ............................................................. 246 11.6 Operation with Cascaded Connection ............................................................................... 247 11.6.1 16-Bit Count Mode .............................................................................................. 247 11.6.2 Compare-Match Count Mode .............................................................................. 247 11.7 Interrupt Sources ............................................................................................................... 248 11.7.1 Interrupt Sources and DTC Activation ................................................................ 248 11.7.2 A/D Converter Activation.................................................................................... 248 11.8 Usage Notes ...................................................................................................................... 249 11.8.1 Contention between TCNT Write and Clear........................................................ 249 11.8.2 Contention between TCNT Write and Increment ................................................ 249 11.8.3 Contention between TCOR Write and Compare-Match ...................................... 250 11.8.4 Contention between Compare-Matches A and B ................................................. 250 Rev. 3.00, 08/03, page xv of xxxviii 11.9 11.10 11.11 11.12 11.8.5 Switching of Internal Clocks and TCNT Operation ............................................ 251 11.8.6 Contention between Interrupts and Module Stop Mode ...................................... 252 8-Bit Reload Timer (TMR_4) (H8S/2268 Group Only) ................................................... 253 11.9.1 Features................................................................................................................ 253 11.9.2 Input/Output Pins................................................................................................. 254 Register Descriptions ........................................................................................................ 255 11.10.1 Timer Control Registers 4 to 7 (TCR_4 to TCR_7) ............................................ 255 11.10.2 Timer Counters 4 to 7 (TCNT4 to TCNT7)......................................................... 256 11.10.3 Time Reload Registers 4 to 7 (TLR_4 to TLR_7) ............................................... 256 Operation .......................................................................................................................... 257 11.11.1 Interval Timer Operation ..................................................................................... 257 11.11.2 Automatic Reload Timer Operation..................................................................... 258 11.11.3 Cascaded Connection........................................................................................... 258 Usage Notes ...................................................................................................................... 260 11.12.1 Conflict between Write to TLR and Count Up/Automatic Reload ...................... 260 11.12.2 Switchover of Internal Clock and TCNT Operation ............................................ 260 11.12.3 Interrupt during Module Stop .............................................................................. 260 Section 12 Watchdog Timer (WDT) .................................................................261 12.1 Features............................................................................................................................. 261 12.2 Register Descriptions ........................................................................................................ 263 12.2.1 Timer Counter (TCNT)........................................................................................ 263 12.2.2 Timer Control/Status Register (TCSR)................................................................ 263 12.2.3 Reset Control/Status Register (RSTCSR) (only WDT_0) ................................... 267 12.3 Operation .......................................................................................................................... 268 12.3.1 Watchdog Timer Mode ........................................................................................ 268 12.3.2 Interval Timer Mode............................................................................................ 269 12.3.3 Timing of Setting Overflow Flag (OVF) ............................................................. 270 12.3.4 Timing of Setting Watchdog Timer Overflow Flag (WOVF) ............................. 270 12.4 Interrupt Sources............................................................................................................... 271 12.5 Usage Notes ...................................................................................................................... 271 12.5.1 Notes on Register Access..................................................................................... 271 12.5.2 Contention between Timer Counter (TCNT) Write and Increment ..................... 272 12.5.3 Changing Value of CKS2 to CKS0...................................................................... 273 12.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode................ 273 12.5.5 Internal Reset in Watchdog Timer Mode............................................................. 273 12.5.6 OVF Flag Clearing in Interval Timer Mode ........................................................ 273 Section 13 Serial Communication Interface (SCI) ............................................275 13.1 Features............................................................................................................................. 275 13.2 Input/Output Pins .............................................................................................................. 279 13.3 Register Descriptions ........................................................................................................ 279 13.3.1 Receive Shift Register (RSR) .............................................................................. 280 Rev. 3.00, 08/03, page xvi of xxxviii 13.4 13.5 13.6 13.7 13.8 13.9 13.3.2 Receive Data Register (RDR) .............................................................................. 280 13.3.3 Transmit Data Register (TDR)............................................................................. 280 13.3.4 Transmit Shift Register (TSR) ............................................................................. 280 13.3.5 Serial Mode Register (SMR)................................................................................ 281 13.3.6 Serial Control Register (SCR).............................................................................. 284 13.3.7 Serial Status Register (SSR) ................................................................................ 289 13.3.8 Smart Card Mode Register (SCMR) .................................................................... 295 13.3.9 Bit Rate Register (BRR) ...................................................................................... 296 13.3.10 Serial Expansion Mode Register (SEMR_0) ....................................................... 304 Operation in Asynchronous Mode .................................................................................... 308 13.4.1 Data Transfer Format ........................................................................................... 308 13.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode .......................................................... 310 13.4.3 Clock.................................................................................................................... 311 13.4.4 SCI Initialization (Asynchronous Mode) ............................................................. 311 13.4.5 Serial Data Transmission (Asynchronous Mode) ................................................ 312 13.4.6 Serial Data Reception (Asynchronous Mode)...................................................... 315 Multiprocessor Communication Function......................................................................... 319 13.5.1 Multiprocessor Serial Data Transmission ............................................................ 320 13.5.2 Multiprocessor Serial Data Reception ................................................................. 322 Operation in Clocked Synchronous Mode ........................................................................ 325 13.6.1 Clock.................................................................................................................... 325 13.6.2 SCI Initialization (Clocked Synchronous Mode) ................................................. 325 13.6.3 Serial Data Transmission (Clocked Synchronous Mode) .................................... 327 13.6.4 Serial Data Reception (Clocked Synchronous Mode).......................................... 329 13.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) ............................................................................. 331 Operation in Smart Card Interface .................................................................................... 333 13.7.1 Pin Connection Example...................................................................................... 333 13.7.2 Data Format (Except for Block Transfer Mode) .................................................. 333 13.7.3 Block Transfer Mode ........................................................................................... 335 13.7.4 Receive Data Sampling Timing and Reception Margin....................................... 335 13.7.5 Initialization ......................................................................................................... 336 13.7.6 Serial Data Transmission (Except for Block Transfer Mode).............................. 337 13.7.7 Serial Data Reception (Except for Block Transfer Mode) ................................... 340 13.7.8 Clock Output Control........................................................................................... 341 Interrupt Sources ............................................................................................................... 343 13.8.1 Interrupts in Normal Serial Communication Interface Mode............................... 343 13.8.2 Interrupts in Smart Card Interface Mode ............................................................. 345 Usage Notes ...................................................................................................................... 345 13.9.1 Module Stop Mode Setting .................................................................................. 345 13.9.2 Break Detection and Processing (Asynchronous mode only) .............................. 345 13.9.3 Mark State and Break Detection (Asynchronous mode only).............................. 346 Rev. 3.00, 08/03, page xvii of xxxviii 13.9.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) .................................................................... 346 13.9.5 Restrictions on Use of DTC (H8S/2268 Group Only) ......................................... 346 13.9.6 Operation in Case of Mode Transition................................................................. 347 13.9.7 Switching from SCK Pin Function to Port Pin Function: .................................... 350 13.9.8 Assignment and Selection of Registers................................................................ 351 Section 14 I2C Bus Interface (IIC) (Option)......................................................353 14.1 Features............................................................................................................................. 353 14.2 Input/Output Pins .............................................................................................................. 356 14.3 Register Descriptions ........................................................................................................ 357 14.3.1 I2C Bus Data Register (ICDR) ............................................................................. 357 14.3.2 Slave Address Register (SAR)............................................................................. 359 14.3.3 Second Slave Address Register (SARX) ............................................................. 359 14.3.4 I2C Bus Mode Register (ICMR)........................................................................... 360 14.3.5 Serial Control Register X (SCRX)....................................................................... 363 14.3.6 I2C Bus Control Register (ICCR)......................................................................... 364 14.3.7 I2C Bus Status Register (ICSR) ........................................................................... 368 14.3.8 DDC Switch Register (DDCSWR) ...................................................................... 371 14.4 Operation .......................................................................................................................... 371 14.4.1 I2C Bus Data Format............................................................................................ 371 14.4.2 Master Transmit Operation .................................................................................. 373 14.4.3 Master Receive Operation.................................................................................... 374 14.4.4 Slave Receive Operation...................................................................................... 377 14.4.5 Slave Transmit Operation .................................................................................... 379 14.4.6 IRIC Setting Timing and SCL Control ................................................................ 382 14.4.7 Operation Using the DTC (H8S/2268 Group Only) ............................................ 383 14.4.8 Noise Chancellor.................................................................................................. 384 14.4.9 Sample Flowcharts............................................................................................... 384 14.5 Usage Notes ...................................................................................................................... 389 Section 15 A/D Converter .................................................................................397 15.1 Features............................................................................................................................. 397 15.2 Input/Output Pins .............................................................................................................. 399 15.3 Register Descriptions ........................................................................................................ 400 15.3.1 A/D Data Registers A to D (ADDRA to ADDRD) ............................................. 400 15.3.2 A/D Control/Status Register (ADCSR) ............................................................... 401 15.3.3 A/D Control Register (ADCR) ............................................................................ 403 15.4 Operation .......................................................................................................................... 403 15.4.1 Single Mode......................................................................................................... 404 15.4.2 Scan Mode ........................................................................................................... 405 15.4.3 Input Sampling and A/D Conversion Time ......................................................... 406 15.4.4 External Trigger Input Timing............................................................................. 407 Rev. 3.00, 08/03, page xviii of xxxviii 15.5 Interrupt Source................................................................................................................. 408 15.6 A/D Conversion Accuracy Definitions ............................................................................. 408 15.7 Usage Notes ...................................................................................................................... 410 15.7.1 Module Stop Mode Setting .................................................................................. 410 15.7.2 Permissible Signal Source Impedance ................................................................. 410 15.7.3 Influences on Absolute Accuracy ........................................................................ 410 15.7.4 Range of Analog Power Supply and Other Pin Settings ...................................... 411 15.7.5 Notes on Board Design ........................................................................................ 411 15.7.6 Notes on Noise Countermeasures ........................................................................ 411 Section 16 D/A Converter................................................................................. 413 16.1 Features ............................................................................................................................. 413 16.2 Input/Output Pins .............................................................................................................. 414 16.3 Register Description.......................................................................................................... 414 16.3.1 D/A Data Registers 0 and 1 (DADR0 and DADR1)............................................ 414 16.3.2 D/A Control Register (DACR) ............................................................................ 415 16.4 Operation........................................................................................................................... 416 16.5 Usage Notes ...................................................................................................................... 417 16.5.1 Analog Power Supply Current in Software Standby Mode ................................. 417 16.5.2 Setting for Module Stop Mode............................................................................. 417 Section 17 LCD Controller/Driver.................................................................... 419 17.1 Features ............................................................................................................................. 419 17.2 Input/Output Pins .............................................................................................................. 421 17.3 Register Descriptions ........................................................................................................ 422 17.3.1 LCD Port Control Register (LPCR)..................................................................... 422 17.3.2 LCD Control Register (LCR)............................................................................... 424 17.3.3 LCD Control Register 2 (LCR2).......................................................................... 426 17.4 Operation........................................................................................................................... 430 17.4.1 Settings up to LCD Display ................................................................................. 430 17.4.2 Relationship between LCD RAM and Display .................................................... 431 17.4.3 Triple Step-Up Voltage Circuit (Supported Only by the H8S/2268 Group)........ 436 17.4.4 Operation in Power-Down Modes ....................................................................... 437 17.4.5 Low-Power LCD Drive........................................................................................ 438 17.4.6 Boosting the LCD Drive Power Supply............................................................... 440 Section 18 DTMF Generation Circuit............................................................... 441 18.1 Features ............................................................................................................................. 441 18.2 Input/Output Pins .............................................................................................................. 442 18.3 Register Descriptions ........................................................................................................ 443 18.3.1 DTMF Control Register (DTCR)......................................................................... 443 18.3.2 DTMF Load Register (DTLR) ............................................................................. 444 18.4 Operation........................................................................................................................... 445 Rev. 3.00, 08/03, page xix of xxxviii 18.4.1 Output Waveform ................................................................................................ 445 18.4.2 Operation Flow .................................................................................................... 446 18.5 Application Circuit Example ............................................................................................ 447 18.6 Usage Notes ...................................................................................................................... 447 Section 19 RAM ................................................................................................449 Section 20 ROM ................................................................................................451 20.1 20.2 20.3 20.4 20.5 20.6 20.7 20.8 20.9 20.10 20.11 20.12 20.13 20.14 Features............................................................................................................................. 451 Mode Transitions .............................................................................................................. 452 Block Configuration.......................................................................................................... 456 Input/Output Pins .............................................................................................................. 459 Register Descriptions ........................................................................................................ 459 20.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 460 20.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 461 20.5.3 Erase Block Register 1 (EBR1) ........................................................................... 462 20.5.4 Erase Block Register 2 (EBR2) ........................................................................... 463 20.5.5 RAM Emulation Register (RAMER)................................................................... 463 20.5.6 Flash Memory Power Control Register (FLPWCR) ............................................ 464 20.5.7 Serial Control Register X (SCRX)....................................................................... 465 On-Board Programming Modes........................................................................................ 466 20.6.1 Boot Mode ........................................................................................................... 466 20.6.2 Programming/Erasing in User Program Mode..................................................... 469 Flash Memory Emulation in RAM ................................................................................... 470 Flash Memory Programming/Erasing ............................................................................... 472 20.8.1 Program/Program-Verify ..................................................................................... 472 20.8.2 Erase/Erase-Verify............................................................................................... 474 20.8.3 Interrupt Handling when Programming/Erasing Flash Memory.......................... 474 Program/Erase Protection ................................................................................................. 476 20.9.1 Hardware Protection ............................................................................................ 476 20.9.2 Software Protection.............................................................................................. 476 20.9.3 Error Protection.................................................................................................... 476 Interrupt Handling when Programming/Erasing Flash Memory....................................... 477 Programmer Mode ............................................................................................................ 477 Power-Down States for Flash Memory............................................................................. 479 Flash Memory Programming and Erasing Precautions..................................................... 479 Note on Switching from F-ZTAT Version to Masked ROM Version .............................. 485 Section 21 Clock Pulse Generator .....................................................................487 21.1 Register Descriptions ........................................................................................................ 488 21.1.1 System Clock Control Register (SCKCR) ........................................................... 488 21.1.2 Low-Power Control Register (LPWRCR) ........................................................... 489 21.2 System Clock Oscillator.................................................................................................... 491 Rev. 3.00, 08/03, page xx of xxxviii 21.3 21.4 21.5 21.6 21.7 21.8 21.2.1 Connecting a Crystal Resonator........................................................................... 491 21.2.2 External Clock Input ............................................................................................ 492 21.2.3 Notes on Switching External Clock ..................................................................... 494 Duty Adjustment Circuit ................................................................................................... 495 Medium-Speed Clock Divider .......................................................................................... 495 Bus Master Clock Selection Circuit .................................................................................. 495 Subclock Oscillator ........................................................................................................... 495 21.6.1 Connecting 32.768-kHz Crystal Resonator.......................................................... 495 21.6.2 Handling Pins when Subclock not Required........................................................ 496 Subclock Waveform Generation Circuit ........................................................................... 496 Usage Notes ...................................................................................................................... 497 21.8.1 Note on Crystal Resonator ................................................................................... 497 21.8.2 Note on Board Design.......................................................................................... 497 21.8.3 Note on Using a Crystal Resonator...................................................................... 497 Section 22 Power-Down Modes ....................................................................... 499 22.1 Register Description.......................................................................................................... 503 22.1.1 Standby Control Register (SBYCR) .................................................................... 503 22.1.2 Module Stop Control Registers A to D (MSTPCRA to MSTPCRD) .................. 505 22.2 Medium-Speed Mode........................................................................................................ 507 22.3 Sleep Mode ....................................................................................................................... 508 22.3.1 Sleep Mode .......................................................................................................... 508 22.3.2 Exiting Sleep Mode.............................................................................................. 508 22.4 Software Standby Mode.................................................................................................... 509 22.4.1 Software Standby Mode....................................................................................... 509 22.4.2 Clearing Software Standby Mode ........................................................................ 509 22.4.3 Oscillation Settling Time after Clearing Software Standby Mode....................... 510 22.4.4 Software Standby Mode Application Example .................................................... 510 22.5 Hardware Standby Mode .................................................................................................. 511 22.5.1 Hardware Standby Mode ..................................................................................... 511 22.5.2 Clearing Hardware Standby Mode....................................................................... 511 22.5.3 Hardware Standby Mode Timing......................................................................... 512 22.6 Module Stop Mode ........................................................................................................... 512 22.7 Watch Mode...................................................................................................................... 513 22.7.1 Transition to Watch Mode ................................................................................... 513 22.7.2 Exiting Watch Mode ............................................................................................ 513 22.8 Sub-Sleep Mode................................................................................................................ 514 22.8.1 Transition to Sub-Sleep Mode ............................................................................. 514 22.8.2 Exiting Sub-Sleep Mode ...................................................................................... 514 22.9 Sub-Active Mode .............................................................................................................. 515 22.9.1 Transition to Sub-Active Mode............................................................................ 515 22.9.2 Exiting Sub-Active Mode .................................................................................... 515 22.10 Direct Transitions.............................................................................................................. 516 Rev. 3.00, 08/03, page xxi of xxxviii 22.10.1 Direct Transitions from High-Speed Mode to Sub-Active Mode ........................ 516 22.10.2 Direct Transitions from Sub-Active Mode to High-Speed Mode ........................ 516 22.11 Usage Notes ...................................................................................................................... 516 22.11.1 I/O Port Status...................................................................................................... 516 22.11.2 Current Dissipation during Oscillation Settling Wait Period............................... 516 22.11.3 DTC Module Stop (Supported only by the H8S/2268 Group)............................. 516 22.11.4 On-Chip Peripheral Module Interrupt.................................................................. 517 22.11.5 Writing to MSTPCR ............................................................................................ 517 22.11.6 Entering Subactive / Watch Mode and DTC Module Stop (Supported only by H8S/2268 Group) ................................................................. 517 Section 23 Power Supply Circuit.......................................................................519 23.1 When Internal Power Step-Down Circuit is Used............................................................. 519 Section 24 List of Registers...............................................................................521 24.1 Register Addresses (by function module, in address order).............................................. 522 24.2 Register Bits...................................................................................................................... 529 24.3 Register States in Each Operating Mode .......................................................................... 536 Section 25 Electrical Characteristics .................................................................543 25.1 Power Supply Voltage and Operating Frequency Range .................................................. 543 25.2 Electrical Characteristics of H8S/2268 Group .................................................................. 545 25.2.1 Absolute Maximum Ratings ................................................................................ 545 25.2.2 DC Characteristics ............................................................................................... 546 25.2.3 AC Characteristics ............................................................................................... 560 25.2.4 A/D Conversion Characteristics........................................................................... 565 25.2.5 D/A Conversion Characteristics........................................................................... 566 25.2.6 LCD Characteristics............................................................................................. 567 25.2.7 DTMF Characteristics.......................................................................................... 569 25.2.8 Flash Memory Characteristics ............................................................................. 570 25.3 Electrical Characteristics of H8S/2264 Group .................................................................. 571 25.3.1 Absolute Maximum Ratings ................................................................................ 571 25.3.2 DC Characteristics ............................................................................................... 572 25.3.3 AC Characteristics ............................................................................................... 581 25.3.4 A/D Conversion Characteristics........................................................................... 585 25.3.5 LCD Characteristics............................................................................................. 586 25.4 Operation Timing.............................................................................................................. 587 25.4.1 Oscillator Settling Timing.................................................................................... 587 25.4.2 Control Signal Timings........................................................................................ 587 25.4.3 Timing of On-Chip Peripheral Modules .............................................................. 588 25.5 Usage Note........................................................................................................................ 590 Rev. 3.00, 08/03, page xxii of xxxviii Appendix A I/O Port States in Each Pin State.................................................. 591 A.1 A.2 I/O Port State in Each Pin State of H8S/2268 Group........................................................ 591 I/O Port State in Each Pin State of H8S/2264 Group........................................................ 592 Appendix B Product Codes............................................................................... 594 Appendix C Package Dimensions..................................................................... 600 Main Revisions and Additions in this Edition .................................................... 603 Index ......................................................................................................... 609 Rev. 3.00, 08/03, page xxiii of xxxviii Rev. 3.00, 08/03, page xxiv of xxxviii Figures Section 1 Figure 1.1 Figure 1.2 Figure 1.3 Figure 1.4 Overview Internal Block Diagram of H8S/2268 Group................................................................. 3 Internal Block Diagram of H8S/2264 Group................................................................. 4 Pin Arrangement of H8S/2268 Group ........................................................................... 5 Pin Arrangement of H8S/2264 Group ........................................................................... 6 Section 2 CPU Figure 2.1 Exception Vector Table (Normal Mode)..................................................................... 15 Figure 2.2 Stack Structure in Normal Mode ................................................................................. 15 Figure 2.3 Exception Vector Table (Advanced Mode)................................................................. 16 Figure 2.4 Stack Structure in Advanced Mode ............................................................................. 17 Figure 2.5 Memory Map............................................................................................................... 18 Figure 2.6 CPU Registers ............................................................................................................. 19 Figure 2.7 Usage of General Registers ......................................................................................... 20 Figure 2.8 Stack Status ................................................................................................................. 21 Figure 2.9 General Register Data Formats (1).............................................................................. 24 Figure 2.9 General Register Data Formats (2).............................................................................. 25 Figure 2.10 Memory Data Formats............................................................................................... 26 Figure 2.11 Instruction Formats (Examples) ................................................................................ 38 Figure 2.12 Branch Address Specification in Memory Indirect Mode ......................................... 41 Figure 2.13 State Transitions ........................................................................................................ 45 Section 3 MCU Operating Modes Figure 3.1 Address Map (1).......................................................................................................... 49 Figure 3.1 Address Map (2).......................................................................................................... 50 Section 4 Figure 4.1 Figure 4.2 Figure 4.3 Exception Handling Reset Sequence (Advanced Mode with On-chip ROM Enabled)................................ 54 Stack Status after Exception Handling (Advanced Mode) .......................................... 57 Operation when SP Value Is Odd................................................................................ 58 Section 5 Interrupt Controller Figure 5.1 Block Diagram of Interrupt Controller for H8S/2268 Group ...................................... 60 Figure 5.2 Block Diagram of Interrupt Controller for H8S/2264 Group ...................................... 61 Figure 5.3 Block Diagram of IRQn Interrupts.............................................................................. 72 Figure 5.4 Set Timing for IRQnF ................................................................................................. 73 Figure 5.5 Block Diagram of Interrupts WKP7 to WKP0 ............................................................ 74 Figure 5.6 IWPFn Setting Timing ................................................................................................ 74 Figure 5.7 Block Diagram of Interrupt Control Operation for H8S/2268 Group ......................... 80 Figure 5.8 Block Diagram of Interrupt Control Operation for H8S/2264 Group ......................... 80 Figure 5.9 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0...... 83 Figure 5.10 Flowchart of Procedure Up to Interrupt Acceptance in Control Mode 2................... 85 Rev. 3.00, 08/03, page xxv of xxxviii Figure 5.11 Interrupt Exception Handling .................................................................................... 86 Figure 5.12 Contention between Interrupt Generation and Disabling .......................................... 88 Section 6 PC Break Controller (PBC) Figure 6.1 Block Diagram of PC Break Controller....................................................................... 92 Figure 6.2 Operation in Power-Down Mode Transitions.............................................................. 96 Section 7 Figure 7.1 Figure 7.2 Figure 7.3 Bus Controller On-Chip Memory Access Cycle.................................................................................. 99 On-Chip Peripheral Module Access Cycle (H'FFFDAC to H'FFFFBF) ................... 100 On-Chip Peripheral Module Access Cycle (H'FFFC30 to H'FFFCA3)..................... 101 Section 8 Data Transfer Controller (DTC) Figure 8.1 Block Diagram of DTC ............................................................................................. 104 Figure 8.2 Block Diagram of DTC Activation Source Control .................................................. 110 Figure 8.3 The Location of DTC Register Information in Address Space.................................. 111 Figure 8.4 Correspondence between DTC Vector Address and Register Information ............... 111 Figure 8.5 Flowchart of DTC Operation..................................................................................... 114 Figure 8.6 Memory Mapping in Normal Mode .......................................................................... 115 Figure 8.7 Memory Mapping in Repeat Mode ........................................................................... 116 Figure 8.8 Memory Mapping in Block Transfer Mode............................................................... 117 Figure 8.9 Chain Transfer Operation .......................................................................................... 118 Figure 8.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode).................... 119 Figure 8.11 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2) ...................................... 119 Figure 8.12 DTC Operation Timing (Example of Chain Transfer) ............................................ 120 Section 9 I/O Ports Figure 9.1 Types of Open Drain Outputs.................................................................................... 138 Section 10 16-Bit Timer Pulse Unit (TPU) Figure 10.1 Block Diagram of TPU for H8S/2268 Group.......................................................... 168 Figure 10.2 Block Diagram of TPU for H8S/2264 Group.......................................................... 169 Figure 10.3 16-Bit Register Access Operation [ Bus Master TCNT (16 Bits) ] .................... 194 Figure 10.4 8-Bit Register Access Operation [ Bus Master TCR (Upper 8 Bits) ]................ 194 Figure 10.5 8-Bit Register Access Operation [ Bus Master TMDR (Lower 8 Bits) ]............ 195 Figure 10.6 8-Bit Register Access Operation [ Bus Master TCR and TMDR (16 Bits) ]...... 195 Figure 10.7 Example of Counter Operation Setting Procedure .................................................. 196 Figure 10.8 Free-Running Counter Operation ............................................................................ 197 Figure 10.9 Periodic Counter Operation ..................................................................................... 197 Figure 10.10 Example of Setting Procedure for Waveform Output by Compare Match............ 198 Figure 10.11 Example of 0 Output/1 Output Operation ............................................................. 198 Figure 10.12 Example of Toggle Output Operation ................................................................... 199 Figure 10.13 Example of Input Capture Operation Setting Procedure ....................................... 199 Figure 10.14 Example of Input Capture Operation..................................................................... 200 Figure 10.15 Example of Synchronous Operation Setting Procedure ........................................ 201 Rev. 3.00, 08/03, page xxvi of xxxviii Figure 10.16 Figure 10.17 Figure 10.18 Figure 10.19 Figure 10.20 Figure 10.21 Figure 10.22 Figure 10.23 Figure 10.24 Figure 10.25 Figure 10.26 Figure 10.27 Figure 10.28 Figure 10.29 Figure 10.30 Figure 10.31 Figure 10.32 Figure 10.33 Figure 10.34 Figure 10.35 Figure 10.36 Figure 10.37 Figure 10.38 Figure 10.39 Figure 10.40 Figure 10.41 Figure 10.42 Figure 10.43 Figure 10.44 Figure 10.45 Figure 10.46 Figure 10.47 Figure 10.48 Figure 10.49 Figure 10.50 Figure 10.51 Figure 10.52 Figure 10.53 Figure 10.54 Example of Synchronous Operation...................................................................... 202 Compare Match Buffer Operation ......................................................................... 203 Input Capture Buffer Operation............................................................................. 203 Example of Buffer Operation Setting Procedure................................................... 203 Example of Buffer Operation (1)........................................................................... 204 Example of Buffer Operation (2)........................................................................... 205 Example of PWM Mode Setting Procedure .......................................................... 207 Example of PWM Mode Operation (1) ................................................................. 207 Example of PWM Mode Operation (2) ................................................................. 208 Example of PWM Mode Operation (3) ................................................................. 209 Example of Phase Counting Mode Setting Procedure........................................... 210 Example of Phase Counting Mode 1 Operation .................................................... 211 Example of Phase Counting Mode 2 Operation .................................................... 212 Example of Phase Counting Mode 3 Operation .................................................... 213 Example of Phase Counting Mode 4 Operation .................................................... 214 Count Timing in Internal Clock Operation............................................................ 217 Count Timing in External Clock Operation........................................................... 217 Output Compare Output Timing............................................................................ 218 Input Capture Input Signal Timing........................................................................ 218 Counter Clear Timing (Compare Match) .............................................................. 219 Counter Clear Timing (Input Capture) .................................................................. 219 Buffer Operation Timing (Compare Match).......................................................... 220 Buffer Operation Timing (Input Capture) ............................................................. 220 TGI Interrupt Timing (Compare Match) ............................................................... 221 TGI Interrupt Timing (Input Capture) ................................................................... 221 TCIV Interrupt Setting Timing.............................................................................. 222 TCIU Interrupt Setting Timing (H8S/2268 Group Only) ...................................... 222 Timing for Status Flag Clearing by CPU .............................................................. 223 Timing for Status Flag Clearing by DTC Activation (H8S/2268 Group Only)..... 223 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode (H8S/2268 Group Only) ........................................................................................ 224 Contention between TCNT Write and Clear Operations....................................... 225 Contention between TCNT Write and Increment Operations ............................... 226 Contention between TGR Write and Compare Match........................................... 227 Contention between Buffer Register Write and Compare Match .......................... 227 Contention between TGR Read and Input Capture ............................................... 228 Contention between TGR Write and Input Capture .............................................. 229 Contention between Buffer Register Write and Input Capture.............................. 229 Contention between Overflow and Counter Clearing............................................ 230 Contention between TCNT Write and Overflow................................................... 231 Section 11 8-Bit Timers Figure 11.1 Block Diagram of 8-Bit Timer Module ................................................................... 234 Rev. 3.00, 08/03, page xxvii of xxxviii Figure 11.2 Example of Pulse Output......................................................................................... 243 Figure 11.3 Count Timing for Internal Clock Input.................................................................... 244 Figure 11.4 Count Timing for External Clock Input................................................................... 244 Figure 11.5 Timing of CMF Setting ........................................................................................... 245 Figure 11.6 Timing of Timer Output .......................................................................................... 245 Figure 11.7 Timing of Compare-Match Clear ............................................................................ 245 Figure 11.8 Timing of Clearing by External Reset Input............................................................ 246 Figure 11.9 Timing of OVF Setting............................................................................................ 246 Figure 11.10 Contention between TCNT Write and Clear ......................................................... 249 Figure 11.11 Contention between TCNT Write and Increment.................................................. 249 Figure 11.12 Contention between TCOR Write and Compare-Match........................................ 250 Figure 11.13 Block Diagram of 8-Bit Reload Timer .................................................................. 254 Figure 11.14 Operation in Interval Timer Mode......................................................................... 257 Figure 11.15 Operation in Automatic Reload Timer Mode........................................................ 258 Figure 11.16 Channel Relationship of Cascaded Connection..................................................... 259 Section 12 Figure 12.1 Figure 12.2 Figure 12.3 Figure 12.4 Figure 12.5 Figure 12.6 Figure 12.7 Figure 12.8 Watchdog Timer (WDT) Block Diagram of WDT_0 ...................................................................................... 262 Block Diagram of WDT_1 ...................................................................................... 262 Watchdog Timer Mode Operation........................................................................... 269 Interval Timer Mode Operation............................................................................... 269 Timing of OVF Setting............................................................................................ 270 Timing of WOVF Setting........................................................................................ 270 Writing to TCNT and TCSR (example for WDT_0)............................................... 272 Contention between TCNT Write and Increment.................................................... 272 Section 13 Figure 13.1 Figure 13.2 Figure 13.3 Figure 13.4 Figure 13.5 Serial Communication Interface (SCI) Block Diagram of SCI_0 ......................................................................................... 277 Block Diagram of SCI_1 or SCI_2.......................................................................... 278 Example of Internal Base Clock when Average Transfer Rate is Selected (1) ....... 306 Example of Internal Base Clock when Average Transfer Rate is Selected (2) ....... 307 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) .................................................. 308 Figure 13.6 Receive Data Sampling Timing in Asynchronous Mode ........................................ 310 Figure 13.7 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) ............................................................................................. 311 Figure 13.8 Sample SCI Initialization Flowchart ....................................................................... 312 Figure 13.9 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit)..................................................... 313 Figure 13.10 Sample Serial Transmission Flowchart ................................................................. 314 Figure 13.11 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit)................................................... 315 Figure 13.12 Sample Serial Reception Data Flowchart (1) ........................................................ 317 Figure 13.12 Sample Serial Reception Data Flowchart (2) ........................................................ 318 Rev. 3.00, 08/03, page xxviii of xxxviii Figure 13.13 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) ........................................... 320 Figure 13.14 Sample Multiprocessor Serial Transmission Flowchart ........................................ 321 Figure 13.15 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) .............................. 322 Figure 13.16 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 323 Figure 13.16 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 324 Figure 13.17 Data Format in Synchronous Communication (For LSB-First) ............................ 325 Figure 13.18 Sample SCI Initialization Flowchart ..................................................................... 326 Figure 13.19 Sample SCI Transmission Operation in Clocked Synchronous Mode .................. 327 Figure 13.20 Sample Serial Transmission Flowchart ................................................................. 328 Figure 13.21 Example of SCI Operation in Reception ............................................................... 329 Figure 13.22 Sample Serial Reception Flowchart....................................................................... 330 Figure 13.23 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations ...... 332 Figure 13.24 Schematic Diagram of Smart Card Interface Pin Connections.............................. 333 Figure 13.25 Normal Smart Card Interface Data Format............................................................ 334 Figure 13.26 Direct Convention (SDIR = SINV = O/E = 0) ...................................................... 334 Figure 13.27 Inverse Convention (SDIR = SINV = O/E = 1)..................................................... 334 Figure 13.28 Receive Data Sampling Timing in Smart Card Mode (Using Clock of 372 Times the Transfer Rate) ...................................................... 336 Figure 13.29 Retransfer Operation in SCI Transmit Mode......................................................... 338 Figure 13.30 TEND Flag Generation Timing in Transmission Operation.................................. 338 Figure 13.31 Example of Transmission Processing Flow........................................................... 339 Figure 13.32 Retransfer Operation in SCI Receive Mode .......................................................... 340 Figure 13.33 Example of Reception Processing Flow ................................................................ 341 Figure 13.34 Timing for Fixing Clock Output Level.................................................................. 341 Figure 13.35 Clock Halt and Restart Procedure ......................................................................... 342 Figure 13.36 Example of Clocked Synchronous Transmission by DTC .................................... 346 Figure 13.37 Sample Flowchart for Mode Transition during Transmission ............................... 348 Figure 13.38 Asynchronous Transmission Using Internal Clock ............................................... 348 Figure 13.39 Synchronous Transmission Using Internal Clock ................................................. 349 Figure 13.40 Sample Flowchart for Mode Transition during Reception .................................... 349 Figure 13.41 Operation when Switching from SCK Pin Function to Port Pin Function ............ 350 Figure 13.42 Operation when Switching from SCK Pin Function to Port Pin Function (Example of Preventing Low-Level Output) ......................................................... 351 Section 14 Figure 14.1 Figure 14.2 Figure 14.3 Figure 14.4 Figure 14.5 Figure 14.6 I2C Bus Interface (IIC) (Option) Block Diagram of I2C Bus Interface........................................................................ 355 I2C Bus Interface Connections (Example: This LSI as Master) .............................. 356 I2C Bus Data Formats (I2C Bus Formats)................................................................ 372 I2C Bus Data Format (Serial Format) ...................................................................... 372 I2C Bus Timing........................................................................................................ 372 Master Transmit Mode Operation Timing Example (MLS = WAIT = 0) ............... 374 Rev. 3.00, 08/03, page xxix of xxxviii Figure 14.7 (1) Master Receive Mode Operation Timing Example (MLS = ACKB = 0, WAIT = 1) ........................................................................ 376 Figure 14.7 (2) Master Receive Mode Operation Timing Example (MLS = ACKB = 0, WAIT = 1) ........................................................................ 376 Figure 14.8 Example of Slave Receive Mode Operation Timing (1) (MLS = ACKB = 0) ........ 378 Figure 14.9 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0) ........ 379 Figure 14.10 Example of Slave Transmit Mode Operation Timing (MLS = 0) ......................... 381 Figure 14.11 IRIC Setting Timing and SCL Control.................................................................. 382 Figure 14.12 Block Diagram of Noise Chancellor...................................................................... 384 Figure 14.13 Sample Flowchart for Master Transmit Mode....................................................... 385 Figure 14.14 Sample Flowchart for Master Receive Mode ........................................................ 386 Figure 14.15 Sample Flowchart for Slave Receive Mode .......................................................... 387 Figure 14.16 Sample Flowchart for Slave Transmit Mode......................................................... 388 Figure 14.17 Points for Attention Concerning Reading of Master Receive Data ....................... 392 Figure 14.18 Flowchart and Timing of Start Condition Instruction Issuance for Retransmission...................................................................................................... 393 Figure 14.19 Timing of Stop Condition Issuance ....................................................................... 394 Section 15 Figure 15.1 Figure 15.2 Figure 15.3 A/D Converter Block Diagram of A/D Converter ........................................................................... 398 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) ............ 404 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected) ........................................................ 405 Figure 15.4 A/D Conversion Timing .......................................................................................... 406 Figure 15.5 External Trigger Input Timing ................................................................................ 407 Figure 15.6 A/D Conversion Accuracy Definitions (1) .............................................................. 409 Figure 15.7 A/D Conversion Accuracy Definitions (2) .............................................................. 409 Figure 15.8 Example of Analog Input Circuit ............................................................................ 410 Figure 15.9 Example of Analog Input Protection Circuit ........................................................... 412 Figure 15.10 Analog Input Pin Equivalent Circuit ..................................................................... 412 Section 16 D/A Converter Figure 16.1 Block Diagram of D/A Converter ........................................................................... 413 Figure 16.2 D/A Converter Operation Example ......................................................................... 416 Section 17 Figure 17.1 Figure 17.2 Figure 17.3 Figure 17.4 Figure 17.5 Figure 17.6 Figure 17.7 Figure 17.8 LCD Controller/Driver Block Diagram of LCD Controller/Driver .............................................................. 420 A Waveform 1/2 Duty 1/2 Vias............................................................................... 428 Handling of LCD Drive Power Supply when Using 1/2 Duty ................................ 430 LCD RAM Map (1/4 Duty) ..................................................................................... 431 LCD RAM Map (1/3 Duty) ..................................................................................... 432 LCD RAM Map (1/2 Duty) ..................................................................................... 432 LCD RAM Map (Static Mode)................................................................................ 433 Output Waveforms for Each Duty Cycle (A Waveform) ........................................ 434 Rev. 3.00, 08/03, page xxx of xxxviii Figure 17.9 Output Waveforms for Each Duty Cycle (B Waveform) ........................................ 435 Figure 17.10 Connection when Triple Step-Up Voltage Circuit Used (Supported Only by the H8S/2268 Group) ............................................................ 437 Figure 17.11 Example of Low-Power-Consumption LCD Drive Operation .............................. 439 Figure 17.12 Connection of External Split-Resistance ............................................................... 440 Section 18 Figure 18.1 Figure 18.2 Figure 18.3 Figure 18.4 Figure 18.5 DTMF Generation Circuit DTMF Frequencies.................................................................................................. 441 DTMF Generation Circuit Diagram ........................................................................ 442 TONED Pin Output Equivalent Circuit................................................................... 445 TONED Pin Output Waveform (Row or Column Group Alone) ............................ 445 Example of HA16808ANT Connection .................................................................. 447 Section 20 ROM Figure 20.1 Block Diagram of Flash Memory............................................................................ 452 Figure 20.2 Flash Memory State Transitions.............................................................................. 453 Figure 20.3 Boot Mode............................................................................................................... 454 Figure 20.4 User Program Mode (Example)............................................................................... 455 Figure 20.5 Flash Memory Block Configuration (H8S/2268) .................................................... 457 Figure 20.6 Flash Memory Block Configuration (H8S/2266 and H8S/2265) ............................ 458 Figure 20.7 Programming/Erasing Flowchart Example in User Program Mode ........................ 469 Figure 20.8 Flowchart for Flash Memory Emulation in RAM ................................................... 470 Figure 20.9 Example of RAM Overlap Operation...................................................................... 471 Figure 20.10 Program/Program-Verify Flowchart...................................................................... 473 Figure 20.11 Erase/Erase-Verify Flowchart ............................................................................... 475 Figure 20.12 Socket Adapter Pin Correspondence Diagram ...................................................... 478 Figure 20.13 Power-On/Off Timing (Boot Mode)...................................................................... 482 Figure 20.14 Power-On/Off Timing (User Program Mode) ....................................................... 483 Figure 20.15 Mode Transition Timing (Example: Boot Mode User Mode User Program Mode) ............................ 484 Section 21 Clock Pulse Generator Figure 21.1 Block Diagram of Clock Pulse Generator ............................................................... 487 Figure 21.2 Connection of Crystal Resonator (Example) ........................................................... 491 Figure 21.3 Crystal Resonator Equivalent Circuit ...................................................................... 492 Figure 21.4 External Clock Input (Examples) ............................................................................ 492 Figure 21.5 External Clock Input Timing................................................................................... 493 Figure 21.6 External Clock Switching Circuit (Examples)......................................................... 494 Figure 21.7 External Clock Switching Timing (Examples)........................................................ 494 Figure 21.8 Example Connection of 32.768-kHz Crystal Resonator.......................................... 495 Figure 21.9 Equivalence Circuit for 32.768-kHz Crystal Resonator .......................................... 496 Figure 21.10 Pin Handling When Subclock Not Required ......................................................... 496 Figure 21.11 Note on Board Design of Oscillator Circuit .......................................................... 497 Rev. 3.00, 08/03, page xxxi of xxxviii Section 22 Figure 22.1 Figure 22.2 Figure 22.3 Figure 22.4 Power-Down Modes Mode Transition Diagram ....................................................................................... 501 Medium-Speed Mode Transition and Clearance Timing......................................... 508 Software Standby Mode Application Example ....................................................... 511 Hardware Standby Mode Timing ............................................................................ 512 Section 23 Power Supply Circuit Figure 23.1 Power Supply Connections when Internal Power Supply Step-Down Circuit is Used ....................................... 519 Section 25 Electrical Characteristics Figure 25.1 Power Supply Voltage and Operating Ranges (1) ................................................... 543 Figure 25.1 Power Supply Voltage and Operating Ranges (2) ................................................... 544 Figure 25.2 Output Load Circuit................................................................................................. 560 Figure 25.3 Output Load Circuit................................................................................................. 581 Figure 25.4 Oscillator Settling Timing ....................................................................................... 587 Figure 25.5 Reset Input Timing .................................................................................................. 587 Figure 25.6 Interrupt Input Timing............................................................................................. 588 Figure 25.7 TPU Clock Input Timing......................................................................................... 588 Figure 25.8 8-Bit Timer Clock Input Timing ............................................................................. 588 Figure 25.9 SCK Clock Input Timing......................................................................................... 588 Figure 25.10 SCI Input/Output Timing (Clock Synchronous Mode) ......................................... 589 Figure 25.11 I2C Bus Interface Input/Output Timing (Option) .................................................. 589 Figure 25.12 TONED Load Circuit (Supported only by the H8S/2268 Group) ......................... 589 Appendix C Package Dimensions Figure C.1 TFP-100B Package Dimensions ............................................................................... 600 Figure C.2 TFP-100G Package Dimensions ............................................................................... 601 Figure C.3 FP-100B Package Dimensions.................................................................................. 602 Rev. 3.00, 08/03, page xxxii of xxxviii Tables Section 1 Overview Table 1.1 Pin Functions ................................................................................................................ 7 Section 2 Table 2.1 Table 2.2 Table 2.3 Table 2.4 Table 2.4 Table 2.5 Table 2.6 Table 2.7 Table 2.7 Table 2.8 Table 2.9 Table 2.10 Table 2.11 Table 2.12 Table 2.13 Table 2.13 CPU Instruction Classification ............................................................................................ 27 Operation Notation ..................................................................................................... 28 Data Transfer Instructions........................................................................................... 29 Arithmetic Operations Instructions (1) ....................................................................... 30 Arithmetic Operations Instructions (2) ....................................................................... 31 Logic Operations Instructions..................................................................................... 32 Shift Instructions......................................................................................................... 32 Bit Manipulation Instructions (1)................................................................................ 33 Bit Manipulation Instructions (2)................................................................................ 34 Branch Instructions ..................................................................................................... 35 System Control Instructions........................................................................................ 36 Block Data Transfer Instructions ............................................................................ 37 Addressing Modes .................................................................................................. 38 Absolute Address Access Ranges ........................................................................... 40 Effective Address Calculation (1)........................................................................... 42 Effective Address Calculation (2)........................................................................... 43 Section 3 MCU Operating Modes Table 3.1 MCU Operating Mode Selection ................................................................................ 47 Section 4 Exception Handling Table 4.1 Exception Types and Priority...................................................................................... 51 Table 4.2 Exception Handling Vector Table .............................................................................. 52 Table 4.3 Status of CCR and EXR after Trace Exception Handling........................................... 55 Table 4.4 Status of CCR and EXR* after Trap Instruction Exception Handling........................ 56 Section 5 Interrupt Controller Table 5.1 Pin Configuration........................................................................................................ 62 Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities..................................... 76 Table 5.3 Interrupt Control Modes ............................................................................................. 79 Table 5.4 Interrupts Selected in Each Interrupt Control Mode (1) ............................................. 81 Table 5.5 Interrupts Selected in Each Interrupt Control Mode (2) ............................................. 81 Table 5.6 Operations and Control Signal Functions in Each Interrupt Control Mode................ 82 Table 5.7 Interrupt Response Times (States) .............................................................................. 87 Table 5.8 Number of States in Interrupt Handling Routine Execution Status ............................ 87 Section 8 Data Transfer Controller (DTC) Table 8.1 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs................... 112 Table 8.2 Register Information in Normal Mode...................................................................... 115 Rev. 3.00, 08/03, page xxxiii of xxxviii Table 8.3 Table 8.4 Table 8.5 Table 8.6 Register Information in Repeat Mode....................................................................... 116 Register Information in Block Transfer Mode.......................................................... 117 DTC Execution Status............................................................................................... 120 Number of States Required for Each Execution Status............................................. 121 Section 9 I/O Ports Table 9.1 H8S/2268 Group Port Functions (1) ......................................................................... 126 Table 9.1 H8S/2264 Group Port Functions (2) ......................................................................... 129 Table 9.2 Input Pull-Up MOS States (Port J) ........................................................................... 155 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.1 TPU Functions ...................................................................................................... 166 Table 10.2 TPU Pins............................................................................................................... 170 Table 10.3 CCLR0 to CCLR2 (Channel 0) (H8S/2268 Group Only)..................................... 173 Table 10.4 CCLR0 to CCLR2 (Channels 1 and 2) ................................................................. 173 Table 10.5 TPSC0 to TPSC2 (Channel 0) (H8S/2268 Group Only)....................................... 174 Table 10.6 TPSC0 to TPSC2 (Channel 1) .............................................................................. 174 Table 10.7 TPSC0 to TPSC2 (Channel 2) .............................................................................. 175 Table 10.8 MD0 to MD3 ........................................................................................................ 176 Table 10.9 TIORH_0 (Channel 0) (H8S/2268 Group Only)................................................... 178 Table 10.10 TIORL_0 (Channel 0) (H8S/2268 Group Only) ................................................... 179 Table 10.11 TIOR_1 (Channel 1) ............................................................................................. 180 Table 10.12 TIOR_2 (Channel 2) ............................................................................................. 181 Table 10.13 TIORH_0 (Channel 0) (H8S/2268 Group Only)................................................... 182 Table 10.14 TIORL_0 (Channel 0) (H8S/2268 Group Only) ................................................... 183 Table 10.15 TIOR_1 (Channel 1) ............................................................................................. 184 Table 10.16 TIOR_2 (Channel 2) ............................................................................................. 185 Table 10.17 Register Combinations in Buffer Operation.......................................................... 202 Table 10.18 PWM Output Registers and Output Pins .............................................................. 206 Table 10.19 Phase Counting Mode Clock Input Pins ............................................................... 210 Table 10.20 Up/Down-Count Conditions in Phase Counting Mode 1...................................... 211 Table 10.21 Up/Down-Count Conditions in Phase Counting Mode 2...................................... 212 Table 10.22 Up/Down-Count Conditions in Phase Counting Mode 3...................................... 213 Table 10.23 Up/Down-Count Conditions in Phase Counting Mode 4...................................... 214 Table 10.24 TPU Interrupts ...................................................................................................... 215 Section 11 8-Bit Timers Table 11.1 Pin Configuration.................................................................................................. 235 Table 11.2 8-Bit Timer Interrupt Sources ............................................................................... 248 Table 11.3 Timer Output Priorities ......................................................................................... 250 Table 11.4 Switching of Internal Clock and TCNT Operation ............................................... 251 Section 12 Watchdog Timer (WDT) Table 12.1 WDT Interrupt Source .......................................................................................... 271 Rev. 3.00, 08/03, page xxxiv of xxxviii Section 13 Serial Communication Interface (SCI) Table 13.1 Pin Configuration.................................................................................................. 279 Table 13.2 The Relationships between The N Setting in BRR and Bit Rate B....................... 296 Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ........................... 297 Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ........................... 298 Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3) ........................... 299 Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (4) ........................... 300 Table 13.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 300 Table 13.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) ................ 301 Table 13.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)..................... 302 Table 13.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) .... 302 Table 13.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode) (When n = 0 and S = 372)..................................................................................... 303 Table 13.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) (When S = 372)..................................................................................................... 303 Table 13.10 Serial Transfer Formats (Asynchronous Mode).................................................... 309 Table 13.11 SSR Status Flags and Receive Data Handling ...................................................... 316 Table 13.12 Interrupt Sources of Serial Communication Interface Mode ................................ 344 Table 13.13 Interrupt Sources in Smart Card Interface Mode .................................................. 345 Section 14 I2C Bus Interface (IIC) (Option) Table 14.1 Pin Configuration.................................................................................................. 356 Table 14.2 Transfer Format .................................................................................................... 360 Table 14.3 I2C Transfer Rate .................................................................................................. 362 Table 14.4 Flags and Transfer States ...................................................................................... 368 Table 14.5 Flags and Transfer States ...................................................................................... 383 Table 14.6 I2C Bus Timing (SCL and SDA Output)............................................................... 389 Table 14.7 Permissible SCL Rise Time (tsr) Values ............................................................... 390 Table 14.8 I2C Bus Timing (with Maximum Influence of tSr/tSf)............................................ 391 Section 15 A/D Converter Table 15.1 Pin Configuration.................................................................................................. 399 Table 15.2 Analog Input Channels and Corresponding ADDR Registers .............................. 400 Table 15.3 A/D Conversion Time (Single Mode)................................................................... 407 Table 15.4 A/D Conversion Time (Scan Mode) ..................................................................... 407 Table 15.5 A/D Converter Interrupt Source............................................................................ 408 Table 15.6 Analog Pin Specifications..................................................................................... 412 Section 16 D/A Converter Table 16.1 Pin Configuration.................................................................................................. 414 Table 16.2 D/A Conversion Control ....................................................................................... 415 Section 17 LCD Controller/Driver Table 17.1 Pin Configuration.................................................................................................. 421 Table 17.2 Duty Cycle and Common Function Selection....................................................... 423 Rev. 3.00, 08/03, page xxxv of xxxviii Table 17.3 Table 17.4 Table 17.5 Table 17.6 Table 17.7 Segment Driver Selection (1) (H8S/2268 Group)................................................. 423 Segment Driver Selection (2) (H8S/2264 Group)................................................. 424 Frame Frequency Selection................................................................................... 426 Output Levels........................................................................................................ 436 Power-Down Modes and Display Operation ........................................................ 438 Section 18 DTMF Generation Circuit Table 18.1 Pin Configuration.................................................................................................. 442 Table 18.2 Frequency Deviation Between DTMF Output Signals And Typical Signals........ 446 Section 20 ROM Table 20.1 Differences between Boot Mode and User Program Mode .................................. 453 Table 20.2 Pin Configuration.................................................................................................. 459 Table 20.3 Setting On-Board Programming Modes................................................................ 466 Table 20.4 Boot Mode Operation ........................................................................................... 468 Table 20.5 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible ............................................................................................................. 468 Table 20.6 Flash Memory Operating States............................................................................ 479 Table 20.7 Registers Present in F-ZTAT Version but Absent in Masked ROM Version ....... 485 Section 21 Clock Pulse Generator Table 21.1 Damping Resistance Value ................................................................................... 491 Table 21.2 Crystal Resonator Characteristics ......................................................................... 492 Table 21.3 External Clock Input Conditions........................................................................... 493 Table 21.4 External Clock Input Conditions (Duty Adjustment Circuit not Used) ................ 493 Section 22 Power-Down Modes Table 22.1 LSI Internal States in Each Mode ......................................................................... 499 Table 22.2 Low Power Dissipation Mode Transition Conditions........................................... 502 Table 22.3 Oscillation Settling Time Settings ........................................................................ 510 Section 25 Electrical Characteristics Table 25.1 Absolute Maximum Ratings ................................................................................. 545 Table 25.2 DC Characteristics (1)........................................................................................... 546 Table 25.2 DC Characteristics (2)........................................................................................... 548 Table 25.2 DC Characteristics (3)........................................................................................... 550 Table 25.2 DC Characteristics (4) Preliminary ............................................................. 552 Table 25.2 DC Characteristics (5)........................................................................................... 554 Table 25.2 DC Characteristics (6) Preliminary ............................................................. 556 Table 25.3 Permissible Output Currents ................................................................................. 558 Table 25.4 Bus Drive Characteristics (1)................................................................................ 559 Table 25.4 Bus Drive Characteristics (2)................................................................................ 560 Table 25.5 Clock Timing ........................................................................................................ 561 Table 25.6 Control Signal Timing .......................................................................................... 562 Table 25.7 Timing of On-Chip Peripheral Modules ............................................................... 563 Table 25.8 I2C Bus Timing ..................................................................................................... 564 Rev. 3.00, 08/03, page xxxvi of xxxviii Table 25.9 Table 25.10 Table 25.11 Table 25.12 Table 25.13 Table 25.14 Table 25.15 Table 25.15 Table 25.15 Table 25.15 Table 25.16 Table 25.17 Table 25.17 Table 25.18 Table 25.19 Table 25.20 Table 25.21 Table 25.22 Table 25.23 A/D Conversion Characteristics............................................................................ 565 D/A Conversion Characteristics............................................................................ 566 LCD Characteristics.............................................................................................. 567 DTMF Characteristics........................................................................................... 569 Flash Memory Characteristics .............................................................................. 570 Absolute Maximum Ratings ................................................................................. 571 DC Characteristics (1)........................................................................................... 572 DC Characteristics (2)........................................................................................... 573 DC Characteristics (3)........................................................................................... 575 DC Characteristics (4)........................................................................................... 577 Permissible Output Currents ................................................................................. 579 Bus Drive Characteristics (1)................................................................................ 580 Bus Drive Characteristics (2)................................................................................ 581 Clock Timing ........................................................................................................ 582 Control Signal Timing .......................................................................................... 582 Timing of On-Chip Peripheral Modules ............................................................... 583 I2C Bus Timing ..................................................................................................... 584 A/D Conversion Characteristics............................................................................ 585 LCD Characteristics.............................................................................................. 586 Rev. 3.00, 08/03, page xxxvii of xxxviii Rev. 3.00, 08/03, page xxxviii of xxxviii Section 1 Overview 1.1 Features * High-speed H8S/2000 central processing unit with an internal 16-bit architecture Upward-compatible with H8/300 and H8/300H CPUs on an object level Sixteen 16-bit general registers 65 basic instructions * Various peripheral functions Interrupt controller PC break controller (supported only by the H8S/2268 Group) Data transfer controller (DTC) (supported only by the H8S/2268 Group) 16-bit timer-pulse unit (TPU) 8-bit timer (TMR) Watchdog timer (WDT) Serial communication interface (SCI) I2C bus interface (option) A/D converter D/A converter (supported only by the H8S/2268 Group) LCD controller/driver DTMF generation circuit (supported only by the H8S/2268 Group) * On-chip memory H8S/2268 Group: ROM Model ROM RAM Flash memory version HD64F2268 256 kbytes 16 kbytes HD64F2266 128 kbytes 8 kbytes HD64F2265 128 kbytes 4 kbytes HD6432268 256 kbytes 16 kbytes HD6432268W 256 kbytes 16 kbytes HD6432266 128 kbytes 8 kbytes HD6432266W 128 kbytes 8 kbytes Masked ROM version Remarks HD6432265 128 kbytes 4 kbytes HD6432265W 128 kbytes 4 kbytes Rev. 3.00, 08/03, page 1 of 612 H8S/2264 Group: ROM Model ROM RAM Masked ROM version HD6432264 128 kbytes 4 kbytes HD6432264W 128 kbytes 4 kbytes HD6432262 64 kbytes 2 kbytes HD6432262W 64 kbytes 2 kbytes Remarks * General I/O ports I/O pins: 67 (supported only by the H8S/2268 Group) 51 (supported only by the H8S/2264 Group) Input-only pins: 11 * Supports various power-down states * Compact package Package (Code) Body Size TQFP-100 TFP-100B 14.0 0.5 mm TQFP-100 TFP-100G 12.0 0.4 mm QFP-100 FP-100B Rev. 3.00, 08/03, page 2 of 612 x 14.0 mm x 12.0 mm 14.0 x 14.0 mm Pin Pitch 0.5 mm 1.2 Internal Block Diagram PN7/SEG40 PN6/SEG39 PN5/SEG38 PN4/SEG37 PN3/SEG36 PN2/SEG35 PN1/SEG34 PN0/SEG33 V1 V2 V3 C1 C2 CVcc Vcc Vss Vss Figure 1.1 shows the internal block diagram of the H8S/2268 Group and figure 1.2 shows that of the H8S/2264 Group. DTMF 8 bit timer (4 channels+4 channels) A/D converter(10 channels) WDT0 WDT1 (sub clock) Peripheral address bus Port M Port 3 TPU (3 channels) Port L LCD (40SEG/4COM) Port K RAM PL7 / SEG24 PL6 / SEG23 PL5 / SEG22 PL4 /SEG21 PL3 / SEG20 PL2 / SEG19 PL1 / SEG18 PL0 / SEG17 PK7 / SEG16 PK6 / SEG15 PK5 / SEG14 PK4 /SEG13 PK3 / SEG12 PK2 / SEG11 PK1 / SEG10 PK0 / SEG9 Port J IIC (2 channels) (option) PM7 / SEG32 PM6 / SEG31 PM5 / SEG30 PM4 /SEG29 PM3 / SEG28 PM2 / SEG27 PM1 / SEG26 PM0 / SEG25 PJ7 / WKP7/SEG8 PJ6 / WKP6/SEG7 PJ5 / WKP5/SEG6 PJ4 / WKP4/SEG5 PJ3 / WKP3/SEG4 PJ2 / WKP2/SEG3 PJ1 / WKP1/SEG2 PJ0 / WKP0/SEG1 Port H ROM Port 7 SCI (3 channels) PH7/TONED/TMCI4 PH3/COM4 PH2/COM3 PH1/COM2 PH0/COM1 D/A converter(2 channels) Port 9 Vref AVcc AVss P96/AN8/DA0 P97/AN9/DA1 Port 4 P47/AN7 P46/AN6 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0 Port 1 P10/TIOCA0 P11/TIOCB0 P12/TIOCC0/TCLKA P13/TIOCD0/TCLKB P14/TIOCA1/IRQ0 P15/TIOCB1/TCLKC P16/TIOCA2/IRQ1 P17/TIOCB2/TCLKD PF3/ADTRG/IRQ3 PC break controller (2 channels) Peripheral data bus DTC Port F P35/SCK1/SCL0/IRQ5 P34/RxD1/SDA0 P33/TxD1/SCL1 P32/SCK0/SDA1/IRQ4 P31/RxD0 P30/TxD0 Bus controller Sub Clock pulse generator H8S/2000 CPU Interrupt controller P7 0 / T M R I 0 1 / T M C I 0 1 P7 1 / T M R I 2 3 / T M C I 2 3 P72/ T M O 0 P73/ T M O 1 P74/ T M O 2 P75/ T M O 3 / S C K 2 P76/RxD2 P77/TxD2 Internal data bus System clock pulse generator MD2 MD1 EXTAL XTAL OSC1 OSC2 STBY RES NMI FWE Internal address bus Port N Figure 1.1 Internal Block Diagram of H8S/2268 Group Rev. 3.00, 08/03, page 3 of 612 Port L PL7/SEG24 PL6/SEG23 PL5/SEG22 PL4/SEG21 PL3/SEG20 PL2/SEG19 PL1/SEG18 PL0/SEG17 Port K PK7/SEG16 PK6/SEG15 PK5/SEG14 PK4/SEG13 PK3/SEG12 PK2/SEG11 PK1/SEG10 PK0/SEG9 Port J PJ7/WKP7/SEG8 PJ6/WKP6/SEG7 PJ5/WKP5/SEG6 PJ4/WKP4/SEG5 PJ3/WKP3/SEG4 PJ2/WKP2/SEG3 PJ1/WKP1/SEG2 PJ0/WKP0/SEG1 Port H Peripheral address bus Interrupt controller Peripheral data bus Bus controller Internal data bus Sub Clock pulse generator H8S/2000 CPU Internal address bus System clock pulse generator SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 V1 V2 V3 CVcc Vcc Vss Vss MD2 MD1 EXTAL XTAL OSC1 OSC2 STBY RES NMI FWE SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 PH7 PH3/COM4 PH2/COM3 PH1/COM2 PH0/COM1 P70/TMRI01/TMCI01 P71 P72/TMO0 P73/TMO1 P74 P75/SCK2 P76/RxD2 P77/TxD2 Port 7 SCI (3 channels) ROM IIC (1 channel) (option) RAM LCD (40SEG/4COM) TPU (2 channels) Port 3 WDT0 A/D converter (10 channels) WDT1 (sub clock) Port 4 Port 9 P96/AN8 P97/AN9 Vref AVcc AVss P10 P11 P12 / TCLKA P13 / TCLKB P14 / TIOCA1/IRQ0 P15 / TIOCB1 / TCLKC P16 / TIOCA2/IRQ1 P17 / TIOCB2 Port 1 P47 / AN7 P46 / AN6 P45 / AN5 P44 / AN4 P43 / AN3 P42 / AN2 P41 / AN1 P40 / AN0 PF3/ADTRG/IRQ3 8 bit timer (2 channels) Port F P35/SCK1/SCL0 P34/RxD1/SDA0 P33/TxD1 P32/SCK0/IRQ4 P31/RxD0 P30/TxD0 Figure 1.2 Internal Block Diagram of H8S/2264 Group Rev. 3.00, 08/03, page 4 of 612 1.3 Pin Arrangement FP-100B TFP-100B TFP-100G (TOP VIEW) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6 P47/AN7 P96/AN8/DA0 P97/AN9/DA1 AVss P17/TIOCB2/TCLKD P16/TIOCA2/IRQ1 P15/TIOCB1/TCLKC P14/TIOCA1/IRQ0 P13/TIOCD0/TCLKB P12/TIOCC0/TCLKA P11/TIOCB0 P10/TIOCA0 PJ0/WKP0/SEG1 PJ1/WKP1/SEG2 PJ2/WKP2/SEG3 PJ3/WKP3/SEG4 PJ4/WKP4/SEG5 PJ5/WKP5/SEG6 PJ6/WKP6/SEG7 PJ7/WKP7/SEG8 PM6/SEG31 PM5/SEG30 PM4/SEG29 PM3/SEG28 PM2/SEG27 PM1/SEG26 PM0/SEG25 PL7/SEG24 PL6/SEG23 PL5/SEG22 PL4/SEG21 CVcc PL3/SEG20 Vss PL2/SEG19 PL1/SEG18 PL0/SEG17 PK7/SEG16 PK6/SEG15 PK5/SEG14 PK4/SEG13 PK3/SEG12 PK2/SEG11 PK1/SEG10 PK0/SEG9 P30/TxD0 P31/RxD0 P32/SCK0/SDA1/IRQ4 P33/TxD1/SCL1 P34/RxD1/SDA0 P35/SCK1/SCL0/IRQ5 PF3/ADTRG/IRQ3 C2 C1 V3 V2 V1 PH3/COM4 PH2/COM3 PH1/COM2 PH0/COM1 PN7/SEG40 PN6/SEG39 PN5/SEG38 PN4/SEG37 PN3/SEG36 PN2/SEG35 PN1/SEG34 PN0/SEG33 PM7/SEG32 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P70/TMRI01/TMCI01 P71/TMRI23/TMCI23 P72/TMO0 P73/TMO1 P74/TMO2 P75/TMO3/SCK2 P76/RxD2 P77/TxD2 MD2 FWE EXTAL Vss XTAL Vcc STBY NMI RES OSC1 OSC2 MD1 PH7/TONED/TMCI4 AVcc Vref P40/AN0 P41/AN1 Figure 1.3 shows the pin arrangement of the H8S/2268 Group and figure 1.4 shows that of the H8S/2264 Group. Figure 1.3 Pin Arrangement of H8S/2268 Group Rev. 3.00, 08/03, page 5 of 612 P70/TMRI01/TMCI01 P71 P72/TMO0 P73/TMO1 P74 P75/SCK2 P76/RxD2 P77/TxD2 MD2 FWE EXTAL Vss XTAL Vcc STBY NMI RES OSC1 OSC2 MD1 PH7 AVcc Vref P40/AN0 P41/AN1 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 FP-100B TFP-100B TFP-100G (TOP VIEW) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 PL7/SEG24 PL6/SEG23 PL5/SEG22 PL4/SEG21 CVcc PL3/SEG20 Vss PL2/SEG19 PL1/SEG18 PL0/SEG17 PK7/SEG16 PK6/SEG15 PK5/SEG14 PK4/SEG13 PK3/SEG12 PK2/SEG11 PK1/SEG10 PK0/SEG9 P30/TxD0 P31/RxD0 P32/SCK0/IRQ4 P33/TxD1 P34/RxD1/SDA0 P35/SCK1/SCL0 PF3/ADTRG/IRQ3 NC* NC* V3 V2 V1 PH3/COM4 PH2/COM3 PH1/COM2 PH0/COM1 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 Note: * The NC pin should be open. Figure 1.4 Pin Arrangement of H8S/2264 Group Rev. 3.00, 08/03, page 6 of 612 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6 P47/AN7 P96/AN8 P97/AN9 AVss P17/TIOCB2 P16/TIOCA2/IRQ1 P15/TIOCB1/TCLKC P14/TIOCA1/IRQ0 P13/TCLKB P12/TCLKA P11 P10 PJ0/WKP0/SEG1 PJ1/WKP1/SEG2 PJ2/WKP2/SEG3 PJ3/WKP3/SEG4 PJ4/WKP4/SEG5 PJ5/WKP5/SEG6 PJ6/WKP6/SEG7 PJ7/WKP7/SEG8 1.4 Pin Functions Table 1.1 lists the pins functions. Table 1.1 Pin Functions Type Symbol Pin NO. I/O Function Power supply Vcc 62 Input Power supply pin. Connect this pin to the system power supply. CVcc 12 Input Connect this pin to Vss via a capacitor (H8S/2268 Group: 0.1 F/0.2 F and H8S/2264 Group: 0.2 F) for voltage stabilization. Note that applying a voltage exceeding 4.3 V, the absolute maximum rating, to the CVcc pin may cause fatal damages on this LSI. Do not connect the power supply to the CVcc pin. See section 23, Power Supply Circuit, for connecting examples. V3 V2 V1 85 86 87 Input Power supply pins for the LCD controller/driver. With an internal power supply division resistor, these pins are normally left open. Power supply should be within the range of Vcc V1 V2 V3 Vss. When the triple step-up voltage circuit* is used, the V3 pin is used for the LCD input reference power supply. Vss 14 64 Input Ground pins. Connect this pin to the system power supply (0 V). XTAL 63 Input EXTAL 65 Input For connection to a crystal resonator. This pin can be also used for external clock input. For examples of crystal resonator connection and external clock input, see section 21, Clock Pulse Generator. OSC1 58 Input OSC2 57 Input Operating MD2, MD1 67 mode control 56 Input Sets the operating mode. Inputs at these pins should not be changed during operation. Be sure to fix the levels of the mode pins (MD2, MD1) by pull-down or pull-up, except for mode changing. Clock System control Connects to a 32.768 kHz crystal resonator. See section 21, Clock Pulse Generator, for typical connection diagrams for a crystal resonator. RES 59 Input Reset input pin. When this pin is low, the chip enters in the power-on reset state. STBY 61 Input When this pin is low, a transition is made to hardware standby mode. FWE 66 Input Enables/disables programming the flash memory. Rev. 3.00, 08/03, page 7 of 612 Type Symbol Pin NO. I/O Function Interrupts NMI 60 Input Nonmaskable interrupt pin. If this pin is not used, it should be fixed-high. IRQ5* IRQ4 IRQ3 IRQ1 IRQ0 81 78 82 40 38 Input These pins request a maskable interrupt. WKP7 to WKP0 26 to 33 Input These pins request a wakeup interrupt. This interrupt is maskable. 41 39 37 36 Input These pins input an external clock. TIOCA0* TIOCB0* TIOCC0* TIOCD0* 34 35 36 37 Input/ Output Pins for the TGRA_0 to TGRD_0 input capture input or output compare output, or PWM output. TIOCA1 TIOCB1 38 39 Input/ Output Pins for the TGRA_1 and TGRB_1 input capture input or output compare output, or PWM output. TIOCA2 TIOCB2 40 41 Input/ Output Pins for the TGRA_2 and TGRB_2 input capture input or output compare output, or PWM output. TMO3* TMO2* TMO1 TMO0 70 71 72 73 Output Compare-match output pins TMCI23* TMCI01 TMCI4* 74 75 55 Input Pins for external clock input to the counter TMRI23* TMRI01 74 75 Input Counter reset input pins. TxD2 TxD1 TxD0 68 79 76 Output Data output pins RxD2 RxD1 RxD0 69 80 77 Input Data input pins SCK2 SCK1 SCK0 70 81 78 Input/ Output Clock input/output pins 16-bit timer- TCLKD* pulse unit TCLKC (TPU) TCLKB TCLKA 8-bit timer Serial communication Interface (SCI)/smart card interface Rev. 3.00, 08/03, page 8 of 612 Type Symbol Pin NO. I/O Function I C bus interface (optional) SCL1* SCL0 79 81 Input/ Output I C clock input/output pins. SDA1* SDA0 78 80 Input/ Output I C data input/output pins. A/D converter AN9 to AN0 43 to 52 Input Analog input pins ADTRG 82 Input Pin for input of an external trigger to start A/D conversion D/A converter* DA1 DA0 43 44 Output Analog output pins for the D/A converter*. A/D converter, D/A converter* AVcc 54 Input Power supply pin for the A/D converter, D/A converter* and DTMF generation circuit*. If none of the A/D converter, D/A converter* and DTMF generation circuit* is used, connect this pin to the system power supply (+5 V). AVss 42 Input Ground pin for the A/D converter, D/A converter*, and DTMF generator*. Connect this pin to the system power supply (0 V). Vref 53 Input Reference voltage input pin for the A/D converter and D/A converter*. If neither the A/D converter nor D/A converter* is used, connect this pin to the system power supply (+5 V). 2 LCD controller/ driver 2 2 SEG40 to 92 to 100, Output SEG 1 1 to 11, 13, 15 to 33 LCD segment output pins COM4 to COM1 88 to 91 Output LCD common output pins C2* C1* 83 84 -- Pins for the step-up voltage capacitor of the LCD drive power supply. DTMF generation circuit* TONED 55 Output DTMF signal output pin. I/O ports P17 to P10 41 to 34 Input/ Output 8-bit I/O pins P35 to P30 81 to 76 Input/ Output 6-bit I/O pins P47 to P40 45 to 52 Input 8-bit input pins P77 to P70 68 to 75 Input/ Output 8-bit I/O pins Rev. 3.00, 08/03, page 9 of 612 Type Symbol Pin NO. I/O Function I/O ports P97 P96 43 44 Input 2-bit input pins PF3 82 Input/ Output 1-bit I/O pin PH7 55 Input 1-bit input pin PH3 to PH0 88 to 91 Input/ Output 4-bit I/O pins PJ7 to PJ0 26 to 33 Input/ Output 8-bit I/O pins PK7 to PK0 18 to 25 Input/ Output 8-bit I/O pins PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 8 9 10 11 13 15 16 17 Input/ Output 8-bit I/O pins PM7* PM6* PM5* PM4* PM3* PM2* PM1* PM0* 100 1 2 3 4 5 6 7 Input/ Output 8-bit I/O pins PN7 to PN0* 92 to 99 Input/ Output 8-bit I/O pins Note: * Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 10 of 612 Section 2 CPU The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2000 CPU. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes. 2.1 Features * Upward-compatible with H8/300 and H8/300H CPU Can execute H8/300 and H8/300H CPU object programs * General-register architecture Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers * Sixty-five basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] * 16-Mbyte address space Program: 16 Mbytes Data: 16 Mbytes * High-speed operation All frequently-used instructions execute in one or two states 8/16/32-bit register-register add/subtract : 1 state 8 x 8-bit register-register multiply : 12 states 16 / 8-bit register-register divide : 12 states 16 x 16-bit register-register multiply : 20 states 32 / 16-bit register-register divide : 20 states CPUS213A_000020020700 Rev. 3.00, 08/03, page 11 of 612 * Two CPU operating modes Normal mode* Advanced mode * Power-down state Transition to power-down state by a SLEEP instruction CPU clock speed selection Note: * Normal mode is not available in this LSI. 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are shown below. * Register configuration The MAC register is supported by the H8S/2600 CPU only. * Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported by the H8S/2600 CPU only. * The number of execution states of the MULXU and MULXS instructions; Execution States Instruction Mnemonic H8S/2600 H8S/2000 MULXU MULXU.B Rs, Rd 3 12 MULXU.W Rs, ERd 4 20 MULXS.B Rs, Rd 4 13 MULXS.W Rs, ERd 5 21 MULXS In addition, there are differences in address space, CCR and EXR* register functions, and powerdown modes, etc., depending on the model. Note: * Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 12 of 612 2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements: * More general registers and control registers Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been added. * Expanded address space Normal mode supports the same 64-kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space. * Enhanced addressing The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Signed multiply and divide instructions have been added. Two-bit shift instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions execute twice as fast. 2.1.3 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements: * Additional control register One 8-bit control registers have been added. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Two-bit shift instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions execute twice as fast. Rev. 3.00, 08/03, page 13 of 612 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space. The mode is selected by the mode pins. 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU. * Address Space Linear access is provided to a maximum address space of 64 kbytes. * Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even when the corresponding general register (Rn) is used as an address register. If the general register is referenced in the register indirect addressing mode with pre-decrement (@-Rn) or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding extended register (En) will be affected. * Instruction Set All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. * Exception Vector Table and Memory Indirect Branch Addresses In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. Figure 2.1 shows the structure of the exception vector table in normal mode. For details of the exception vector table, see section 4, Exception Handling. The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table. * Stack Structure When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR) and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.2. EXR is not pushed onto the stack in interrupt control mode 0. For details, see section 4, Exception Handling. Note: * Normal mode is not available in this LSI. Rev. 3.00, 08/03, page 14 of 612 H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Reset exception vector (Reserved for system use) Exception vector table Exception vector 1 Exception vector 2 Figure 2.1 Exception Vector Table (Normal Mode) SP PC (16 bits) EXR*1 SP 2 (SP * Reserved*1,*3 ) CCR CCR*3 PC (16 bits) (a) Subroutine Branch (b) Exception Handling Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. lgnored when returning. Figure 2.2 Stack Structure in Normal Mode 2.2.2 Advanced Mode * Address Space Linear access is provided to a maximum 16-Mbyte address space. * Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. * Instruction Set All instructions and addressing modes can be used. Rev. 3.00, 08/03, page 15 of 612 * Exception Vector Table and Memory Indirect Branch Addresses In advanced mode, the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.3). For details of the exception vector table, see section 4, Exception Handling. H'00000000 Reserved Reset exception vector H'00000003 H'00000004 H'00000007 H'00000008 Exception vector table Exception vector 3 H'0000000B H'0000000C H'00000010 Reserved Exception vector 1 Figure 2.3 Exception Vector Table (Advanced Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode, the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits is a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of this range is also the exception vector table. * Stack Structure In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR*) are pushed onto the stack in exception handling, they are stored as shown in figure 2.4. When EXR* is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling. Note: * Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 16 of 612 EXR*1, *4 SP SP Reserved PC (24 bits) (a) Subroutine Branch (SP *2 Reserved*1, *3, *4 ) CCR PC (24 bits) (b) Exception Handling Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used (The H8S/2264 Group SP always points here). 3. Ignored when returning. 4. Supported only by the H8S/2268 Group. Figure 2.4 Stack Structure in Advanced Mode Rev. 3.00, 08/03, page 17 of 612 2.3 Address Space Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes. H'0000 H'00000000 64-kbyte 16-Mbyte H'FFFF Program area H'00FFFFFF Data area H'FFFFFFFF (a) Normal Mode (b) Advanced Mode Note: Normal mode is not available in this LSI Figure 2.5 Memory Map Rev. 3.00, 08/03, page 18 of 612 2.4 Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR*), and an 8-bit condition code register (CCR). Note: * Supported only by the H8S/2268 Group. General Registers (Rn) and Extended Registers (En) 15 0 7 0 7 0 ER0 E0 R0H R0L ER1 E1 R1H R1L ER2 E2 R2H R2L ER3 E3 R3H R3L ER4 E4 R4H R4L ER5 E5 R5H R5L ER6 E6 R6H R6L ER7 (SP) E7 R7H R7L Control Registers (CR) 23 0 PC 7 6 5 4 3 2 1 0 - - - - I2 I1 I0 EXR*1 T 7 6 5 4 3 2 1 0 CCR I UI H U N Z V C Legend :Stack pointer SP :Program counter PC EXR :Extended control register*1 T :Trace bit*1 I2 to I0 :Interrupt mask bits*1 CCR :Condition-code register*1 I :Interrupt mask bit UI :User bit or interrupt mask bit*2 Notes: 1. Supported only by the H8S/2268 Group. 2. The interrupt mask bit is not available in this LSI. H U N Z V C :Half-carry flag :User bit :Negative flag :Zero flag :Overflow flag :Carry flag Figure 2.6 CPU Registers Rev. 3.00, 08/03, page 19 of 612 2.4.1 General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit 2egisters. The usage of each register can be selected independently. General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the stack. * Address registers * 32-bit registers * 16-bit registers * 8-bit registers E registers (extended registers) (E0 to E7) ER registers (ER0 to ER7) RH registers (R0H to R7H) R registers (R0 to R7) RL registers (R0L to R7L) Figure 2.7 Usage of General Registers Rev. 3.00, 08/03, page 20 of 612 Free area SP (ER7) Stack area Figure 2.8 Stack Status 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0.) 2.4.3 Extended Control Register (EXR) (H8S/2268 Group Only) EXR is an 8-bit register that manipulates the LDC, STC, ANDC, ORC, and XORC instructions. When these instructions except for the STC instruction is executed, all interrupts including NMI will be masked for three states after execution is completed. Bit Bit Name Initial Value R/W Description 7 T 0 R/W Trace Bit When this bit is set to 1, a trace exception is generated each time an instruction is executed. When this bit is cleared to 0, instructions are executed in sequence. 6 to 3 1 Reserved These bits are always read as 1. 2 I2 1 R/W 1 I1 1 R/W 0 I0 1 R/W These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller. Rev. 3.00, 08/03, page 21 of 612 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. Bit Bit Name Initial Value R/W 7 I 1 R/W Description Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 by hardware at the start of an exception-handling sequence. For details, refer to section 5, Interrupt Controller. 6 UI Undefined R/W User Bit or Interrupt Mask Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit cannot be used as an interrupt mask bit in this LSI. 5 H Undefined R/W Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 4 U Undefined R/W User Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. 3 N Undefined R/W Negative Flag Stores the value of the most significant bit of data as a sign bit. 2 Z Undefined R/W Zero Flag Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Rev. 3.00, 08/03, page 22 of 612 Bit Bit Name Initial Value 1 V Undefined R/W R/W Description Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. 0 C Undefined R/W Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * Add instructions, to indicate a carry * Subtract instructions, to indicate a borrow * Shift and rotate instructions, to indicate a carry The carry flag is also used as a bit accumulator by bit manipulation instructions. 2.4.5 Initial Values of CPU Registers Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace bit in EXR* to 0, and sets the interrupt mask bits in CCR and EXR* to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset. Note: * Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 23 of 612 2.5 Data Formats The H8S/2000 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2.9 shows the data formats in general registers. Data Type Register Number Data Format 7 1-bit data RnH 1-bit data RnL 4-bit BCD data RnH 4-bit BCD data RnL Byte data RnH 0 Don't care 7 6 5 4 3 2 1 0 7 Don't care 7 7 6 5 4 3 2 1 0 4 3 Upper 0 0 Lower Don't care 7 Don't care 7 4 3 Upper 0 Don't care MSB LSB 7 Byte data RnL 0 Don't care MSB Figure 2.9 General Register Data Formats (1) Rev. 3.00, 08/03, page 24 of 612 0 Lower LSB Data Type Register Number Word data Rn Data Format 15 0 MSB Word data LSB En 15 0 MSB LSB Longword data ERn 31 16 15 MSB En 0 Rn LSB [Legend] ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.9 General Register Data Formats (2) Rev. 3.00, 08/03, page 25 of 612 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches. When ER7 is used as an address register to access the stack, the operand size should be word or longword. Data Type Address Data Format 1-bit data Address L 7 Byte data Address L MSB Word data Address 2M MSB 7 0 6 5 4 3 2 Address 2N 0 LSB LSB Address 2M+1 Longword data 1 MSB Address 2N+1 Address 2N+2 Address 2N+3 Figure 2.10 Memory Data Formats Rev. 3.00, 08/03, page 26 of 612 LSB 2.6 Instruction Set The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Instruction Classification Function Instructions Data transfer MOV 1 1 POP* , PUSH* Arithmetic operations Types B/W/L 5 W/L LDM, STM 3 Size L 3 MOVFPE* , MOVTPE* B ADD, SUB, CMP, NEG B/W/L ADDX, SUBX, DAA, DAS B INC, DEC B/W/L ADDS, SUBS L MULXU, DIVXU, MULXS, DIVXS B/W EXTU, EXTS W/L 4 19 TAS* B Logic operations AND, OR, XOR, NOT B/W/L 4 Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR B/W/L 8 Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR B 14 Branch Bcc* , JMP, BSR, JSR, RTS 5 System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP 9 1 2 Block data transfer EEPMOV Total: 65 Notes: B-byte; W-word; L-longword. 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. 2. Bcc is the general name for conditional branch instructions. 3. Cannot be used in this LSI. 4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Rev. 3.00, 08/03, page 27 of 612 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Operation Notation Symbol Description Rd General register (destination) * Rs General register (source) * Rn General register* ERn General register (32-bit register) (EAd) Destination operand (EAs) Source operand EXR Extended control register* CCR Condition-code register N N (negative) flag in CCR Z Z (zero) flag in CCR V V (overflow) flag in CCR C C (carry) flag in CCR PC Program counter SP Stack pointer #IMM Immediate data disp Displacement + Addition - Subtraction x Multiplication 1 1 1 2 / Division Logical AND Logical OR Logical XOR Move NOT (logical complement) :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length Notes: 1. General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). 2. Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 28 of 612 Table 2.3 Data Transfer Instructions Instruction Size* Function MOV B/W/L (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B Cannot be used in this LSI. MOVTPE B Cannot be used in this LSI. POP W/L @SP+ Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. PUSH W/L Rn @-SP Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP. LDM L @SP+ Rn (register list) Pops two or more general registers from the stack. STM L Rn (register list) @-SP Pushes two or more general registers onto the stack. Note: * Refers to the operand size. B: Byte W: Word L: Longword Rev. 3.00, 08/03, page 29 of 612 Table 2.4 Arithmetic Operations Instructions (1) Instruction Size* Function ADD B/W/L Rd Rs Rd, Rd #IMM Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.) B Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry on byte data in two general registers, or on immediate data and data in a general register. B/W/L Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) L Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. B Rd decimal adjust Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. MULXU B/W Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. MULXS B/W Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. DIVXU B/W Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. SUB ADDX SUBX INC DEC ADDS SUBS DAA DAS Note: * Refers to the operand size. B: Byte W: Word L: Longword Rev. 3.00, 08/03, page 30 of 612 Table 2.4 Arithmetic Operations Instructions (2) 1 Instruction Size* Function DIVXS B/W Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. CMP B/W/L Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. NEG B/W/L 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register. EXTU W/L Rd (zero extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. EXTS W/L Rd (sign extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. B @ERd - 0, 1 (<bit 7> of @ERd) Tests memory contents, and sets the most significant bit (bit 7) to 1. 2 TAS* Notes: 1. Refers to the operand size. B: Byte W: Word L: Longword 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Rev. 3.00, 08/03, page 31 of 612 Table 2.5 Logic Operations Instructions Instruction Size* Function AND B/W/L Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data. XOR B/W/L Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. NOT B/W/L (Rd) (Rd) Takes the one's complement of general register contents. Note: * Refers to the operand size. B: Byte W: Word L: Longword Table 2.6 Shift Instructions Instruction Size* Function SHAL B/W/L Rd (shift) Rd Performs an arithmetic shift on general register contents. 1-bit or 2-bit shifts are possible. B/W/L Rd (shift) Rd Performs a logical shift on general register contents. 1-bit or 2-bit shifts are possible. B/W/L Rd (rotate) Rd Rotates general register contents. 1-bit or 2-bit rotations are possible. B/W/L Rd (rotate) Rd Rotates general register contents through the carry flag. 1-bit or 2-bit rotations are possible. SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note: * Refers to the operand size. B: Byte W: Word L: Longword Rev. 3.00, 08/03, page 32 of 612 Table 2.7 Bit Manipulation Instructions (1) Instruction Size* Function BSET B 1 (<bit-No.> of <EAd>) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 (<bit-No.> of <EAd>) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BNOT B (<bit-No.> of <EAd>) (<bit-No.> of <EAd>) Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BTST B (<bit-No.> of <EAd>) Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BAND B C (<bit-No.> of <EAd>) C ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIAND B C (<bit-No.> of <EAd>) C ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BOR B C (<bit-No.> of <EAd>) C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIOR B C (<bit-No.> of <EAd>) C ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. Note: * Refers to the operand size. B: Byte Rev. 3.00, 08/03, page 33 of 612 Table 2.7 Bit Manipulation Instructions (2) Instruction Size* Function BXOR B C (<bit-No.> of <EAd>) C XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C (<bit-No.> of <EAd>) C XORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD B (<bit-No.> of <EAd>) C Transfers a specified bit in a general register or memory operand to the carry flag. BILD B (<bit-No.> of <EAd>) C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data. BST B C (<bit-No.> of <EAd>) Transfers the carry flag value to a specified bit in a general register or memory operand. BIST B C (<bit-No.> of <EAd>) Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data. Note: * Refers to the operand size. B: Byte Rev. 3.00, 08/03, page 34 of 612 Table 2.8 Branch Instructions Instruction Size Function Bcc Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description Condition BRA(BT) Always (true) Always BRN(BF) Never (false) Never BHI High CZ=0 BLS Low or same CZ=1 BCC(BHS) Carry clear (high or same) C=0 BCS(BLO) Carry set (low) C=1 BNE Not equal Z=0 BEQ Equal Z=1 BVC Overflow clear V=0 BVS Overflow set V=1 BPL Plus N=0 BMI Minus N=1 BGE Greater or equal NV=0 BLT Less than NV=1 BGT Greater than Z(N V) = 0 BLE Less or equal Z(N V) = 1 JMP Branches unconditionally to a specified address. BSR Branches to a subroutine at a specified address. JSR Branches to a subroutine at a specified address. RTS Returns from a subroutine Rev. 3.00, 08/03, page 35 of 612 Table 2.9 System Control Instructions 1 Instruction Size* Function TRAPA Starts trap-instruction exception handling. RTE Returns from an exception-handling routine. SLEEP Causes a transition to a power-down state. LDC B/W (EAs) CCR, (EAs) EXR* Moves the source operand contents or immediate data to CCR or 2 2 EXR* . Although CCR and EXR* are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. STC B/W CCR (EAd), EXR* (EAd) 2 Transfers CCR or EXR* contents to a general register or memory. 2 Although CCR and EXR* are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. ANDC B CCR #IMM CCR, EXR #IMM EXR* 2 Logically ANDs the CCR or EXR* contents with immediate data. ORC B CCR #IMM CCR, EXR #IMM EXR* 2 Logically ORs the CCR or EXR* contents with immediate data. XORC B CCR #IMM CCR, EXR #IMM EXR* 2 Logically XORs the CCR or EXR* contents with immediate data. NOP PC + 2 PC Only increments the program counter. 2 2 2 2 2 Notes: 1. Refers to the operand size. B: Byte W: Word 2. Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 36 of 612 Table 2.10 Block Data Transfer Instructions Instruction Size Function EEPMOV.B if R4L 0 then Repeat @ER5+ @ER6+ R4L-1 R4L Until R4L = 0 else next; EEPMOV.W if R4 0 then Repeat @ER5+ * @ER6+ R4-1 * R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. 2.6.2 Basic Instruction Formats This LSI instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.11 shows examples of instruction formats. * Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. * Register Field Specifies a general register. Address registers are specified by 3 bits, and data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. * Effective Address Extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. * Condition Field Specifies the branching condition of Bcc instructions. Rev. 3.00, 08/03, page 37 of 612 (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rm rn ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op rn rm MOV.B @(d:16, Rn), Rm, etc. EA(disp) (4) Operation field, effective address extension, and condition field op cc EA(disp) BRA d:16, etc. Figure 2.11 Instruction Formats (Examples) 2.7 Addressing Modes and Effective Address Calculation The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except programcounter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or the absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.11 Addressing Modes No. Addressing Mode Symbol 1 Register direct Rn 2 Register indirect @ERn 3 Register indirect with displacement @(d:16,ERn)/@(d:32,ERn) 4 Register indirect with post-increment Register indirect with pre-decrement @ERn+ @-ERn 5 Absolute address @aa:8/@aa:16/@aa:24/@aa:32 6 Immediate #xx:8/#xx:16/#xx:32 7 Program-counter relative @(d:8,PC)/@(d:16,PC) 8 Memory indirect @@aa:8 Rev. 3.00, 08/03, page 38 of 612 2.7.1 Register Direct Rn The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. 2.7.2 Register Indirect @ERn The register field of the instruction code specifies an address register (ERn) which contains the address of the operand on memory. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). 2.7.3 Register Indirect with Displacement @(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. 2.7.4 Register Indirect with Post-Increment or Pre-Decrement @ERn+ or @-ERn Register indirect with post-increment @ERn+: The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For the word or longword transfer instructions, the register value should be even. Register indirect with pre-decrement @-ERn: The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result is the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For the word or longword transfer instructions, the register value should be even. 2.7.5 Absolute Address @aa:8, @aa:16, @aa:24, or @aa:32 The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). Table 2.12 indicates the accessible absolute address ranges. To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can access the entire address space. Rev. 3.00, 08/03, page 39 of 612 A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2.12 Absolute Address Access Ranges Absolute Address Data address Normal Mode* Advanced Mode 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF 16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF 32 bits (@aa:32) Program instruction address Note: 2.7.6 * H'000000 to H'FFFFFF 24 bits (@aa:24) Normal mode is not available in this LSI. Immediate #xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. 2.7.7 Program-Counter Relative @(d:8, PC) or @(d:16, PC) This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. 2.7.8 Memory Indirect @@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode*, H'000000 to H'0000FF in advanced mode). In normal mode, the memory operand is a word operand and the branch address is 16 bits long. In advanced mode, the memory operand is a longword operand, the first byte of which is assumed to be 0 (H'00). Rev. 3.00, 08/03, page 40 of 612 Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling. If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) Note: * Normal mode is not available in this LSI. Specified by @aa:8 Branch address Specified by @aa:8 Reserved Branch address (a) Normal Mode* (a) Advanced Mode Note: * Normal mode is not available in this LSI. Figure 2.12 Branch Address Specification in Memory Indirect Mode 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Rev. 3.00, 08/03, page 41 of 612 Table 2.13 Effective Address Calculation (1) No 1 Addressing Mode and Instruction Format op 2 Effective Address Calculation Effective Address (EA) Register direct(Rn) rm Operand is general register contents. rn Register indirect(@ERn) 0 31 op 3 31 24 23 0 Don't care General register contents r Register indirect with displacement @(d:16,ERn) or @(d:32,ERn) 0 31 General register contents op r 31 disp Sign extension Register indirect with post-increment or pre-decrement *Register indirect with post-increment @ERn+ op disp 0 31 31 24 23 1, 2, or 4 0 31 General register contents 31 24 23 Don't care op r 1, 2, or 4 Operand Size Byte Word Longword Rev. 3.00, 08/03, page 42 of 612 0 Don't care General register contents r *Register indirect with pre-decrement @-ERn 0 0 31 4 24 23 Don't care Offset 1 2 4 0 Table 2.13 Effective Address Calculation (2) No 5 Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address @aa:8 31 op @aa:16 31 op 0 H'FFFF 24 23 16 15 0 Don't care Sign extension abs @aa:24 31 op 8 7 24 23 Don't care abs 24 23 0 Don't care abs @aa:32 op 31 6 Immediate #xx:8/#xx:16/#xx:32 op 7 0 24 23 Don't care abs Operand is immediate data. IMM 0 23 Program-counter relative PC contents @(d:8,PC)/@(d:16,PC) op disp 23 0 Sign extension disp 31 24 23 0 Don't care 8 Memory indirect @@aa:8 * Normal mode* 8 7 31 op abs 0 abs H'000000 15 0 31 24 23 Don't care Memory contents 16 15 0 H'00 * Advanced mode 31 op abs 8 7 H'000000 31 0 abs 0 31 24 23 Don't care 0 Memory contents Note: * Normal mode is not available in this LSI. Rev. 3.00, 08/03, page 43 of 612 2.8 Processing States The H8S/2000 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.13 indicates the state transitions. * Reset State In this state, the CPU and all on-chip peripheral modules are initialized and not operating. When the RES input goes low, all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. For details, refer to section 4, Exception Handling. The reset state can also be entered by a watchdog timer overflow. * Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to an exception source, such as a reset, trace, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. For further details, refer to section 4, Exception Handling. * Program Execution State In this state, the CPU executes program instructions in sequence. * Bus-Released State (H8S/2268 Group only) In a product which has a bus master other than the CPU, such as a data transfer controller (DTC), the bus-released state occurs when the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts operations. * Power-down State This is a power-down state in which the CPU stops operating. The program stop state occurs when a SLEEP instruction is executed or the CPU enters hardware standby mode. For further details, refer to section 22, Power-Down Modes. Rev. 3.00, 08/03, page 44 of 612 End of bus request*4 Bus request*4 En d o ha f ex nd ce lin pti g on Re qu es tf or ex ce pt ion ha nd lin g Program execution state s bu 4 4 f SLEEP instruction, * * o st d est SSBY = 0 ue En qu q re re s Bu Bus-released state*4 Sleep mode t pt rru ues req SLEEP instruction, SSBY = 1 Inte Exception handling state External interrupt request Software standby mode RES= High STBY= High, RES= Low Reset state *1 Hardware standby mode*2 Power-down state*3 Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. A transition can also be made to the reset state when the watchdog timer overflows. 2. From any state, a transition to hardware standby mode occurs when STBY goes low. 3. Apart from these states, there are also the watch mode, subactive mode, and the subsleep mode. See section 22, Power-Down Modes. 4. Supported only by the H8S/2268 Group. Figure 2.13 State Transitions Rev. 3.00, 08/03, page 45 of 612 2.9 Usage Notes 2.9.1 TAS Instruction Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not generated by the Renesas H8S and H8/300 Series C/C++ compilers. If the TAS instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or ER5 is used. 2.9.2 STM/LDM Instruction With the STM or LDM instruction, the ER7 register is used as the stack pointer, and thus cannot be used as a register that allows save (STM) or restore (LDM) operation. With a single STM or LDM instruction, two to four registers can be saved or restored. The available registers are as follows: For two registers: ER0 and ER1, ER2 and ER3, or ER4 and ER5 For three registers: ER0 to ER2, or ER4 to ER6 For four registers: ER0 to ER3 For the Renesas Technology H8S or H8/300 Series C/C++ Compiler, the STM/LDM instruction including ER7 is not created. 2.9.3 Bit Manipulation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions are used to read data in byte-wise, operate the data in bit-wise, and write the result of the bit-wise operation in bit-wise again. Therefore, special care is necessary to use these instructions for the registers and the ports that include writeonly bit. The BCLR instruction can be used to clear to 0 the flags in the internal I/O registers. In this time, if it is obvious that the flag has been set to 1 in the interrupt handler, there is no need to read the flag beforehand. Rev. 3.00, 08/03, page 46 of 612 Section 3 MCU Operating Modes 3.1 Operating Mode Selection This LSI supports the advanced single-chip mode. The operating mode is determined by the setting of the mode pins (MD2 and MD1). Only mode 7 can be used in this LSI. Therefore, all mode pins must be fixed high. Do not change the mode pin settings during operation. Table 3.1 MCU Operating Mode Selection External Data Bus MCU Operating Mode MD2 MD1 CPU Operating Mode Description On-Chip ROM Initial Width Max. Width 7 1 Advanced mode Single-chip mode Enabled 3.2 1 Register Description The following register is related to the operating mode. * Mode control register (MDCR) Rev. 3.00, 08/03, page 47 of 612 3.2.1 Mode Control Register (MDCR) MDCR monitors the current operating mode. Bit Bit Name Initial Value R/W Descriptions 7 1 R/W Reserved This bit is always read as 1 and cannot be modified. 6 to 3 All 0 Reserved 2 MDS2 R Mode Select 2 and 1 1 MDS1 R These bits indicate the input levels at pins MD2 and MD1 (the current operating mode). Bits MDS2 and MDS1 correspond to MD2 and MD1, respectively. MDS2 and MDS1 are read-only bits and they cannot be written to. The mode pin (MD2 and MD1) input levels are latched into these bits when MDCR is read. These latches are canceled by a reset. These latches are canceled by a reset. 0 1 Reserved These bits are always read as 0 and cannot be modified. This bit is always read as 1 and cannot be modified. 3.3 Operating Mode The CPU can access a 16-Mbyte address space in advanced mode. On-chip ROM is valid and the external address cannot be used. Rev. 3.00, 08/03, page 48 of 612 3.4 Address Map Figure 3.1 shows the address map in each operating mode. H8S/2268 H8S/2266 ROM: 256 kbytes, RAM: 16 kbytes Mode 7 Advanced single-chip mode H'000000 ROM: 128 kbytes, RAM: 8 kbytes Mode 7 Advanced single-chip mode H'000000 On-chip RAM On-chip RAM H'01FFFF H'03FFFF H'FFB000 On-chip RAM H'FFEFBF H'FFF800 H'FFFF3F H'FFFF60 Internal I/O registers Internal I/O registers H'FFFFC0 H'FFFFFF H'FFD000 H'FFEFBF H'FFF800 H'FFFF3F H'FFFF60 On-chip RAM Internal I/O registers Internal I/O registers H'FFFFC0 On-chip RAM H'FFFFFF On-chip RAM Figure 3.1 Address Map (1) Rev. 3.00, 08/03, page 49 of 612 H8S/2265 and H8S/2264 H8S/2262 ROM: 128 kbytes, RAM: 4 kbytes Mode 7 Advanced single-chip mode H'000000 ROM: 64 kbytes, RAM: 2 kbytes Mode 7 Advanced single-chip mode H'000000 On-chip RAM On-chip RAM H'00FFFF H'01FFFF H'FFE000 H'FFEFBF H'FFF800 H'FFFF3F H'FFFF60 On-chip RAM Internal I/O registers Internal I/O registers H'FFFFC0 H'FFFFFF H'FFE800 H'FFEFBF H'FFF800 H'FFFF3F H'FFFF60 On-chip RAM Internal I/O registers Internal I/O registers H'FFFFC0 On-chip RAM H'FFFFFF On-chip RAM Figure 3.1 Address Map (2) Rev. 3.00, 08/03, page 50 of 612 Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trace*, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Trap instruction exception handling requests are accepted at all times in program execution state. Exception sources, the stack structure, and operation of the CPU vary depending on the interrupt control mode set by the INTM0 and INTM1 bits in SYSCR. Table 4.1 Exception Types and Priority Priority Exception Type Start of Exception Handling High Reset Starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows. The CPU enters the reset state when the RES pin is low. Trace* Starts when execution of the current instruction or exception handling ends, if the trace (T) bit in the EXR is set to 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not executed after execution of an RTE instruction. Interrupt Starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. Trap instruction Started by execution of a trap instruction (TRAPA). Trap instruction exception handling requests are accepted at all times in program execution state. Low Note: * Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 51 of 612 4.2 Exception Sources and Exception Vector Table Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Table 4.2 Exception Handling Vector Table Exception Source Vector Number Vector Address Advanced Mode* Reset 0 H'0000 to H'0003 Reserved for system use 1 H'0004 to H'0007 2 H'0008 to H'000B 3 H'000C to H'000F 4 H'0010 to H'0013 5 H'0014 to H'0017 Direct transitions* 6 H'0018 to H'001B External interrupt (NMI) 7 H'001C to H'001F Trap instruction (four sources) 8 H'0020 to H'0023 9 H'0024 to H'0027 10 H'0028 to H'002B 4 Trace* 3 11 H'002C to H'002F 12 H'0030 to H'0033 13 H'0034 to H'0037 14 H'0038 to H'003B 15 H'003C to H'003F IRQ0 16 H'0040 to H'0043 IRQ1 17 H'0044 to H'0047 18 H'0048 to H'004B Reserved for system use External interrupt Reserved for system use External interrupt IRQ3 19 H'004C to H'004F IRQ4 20 H'0050 to H'0053 21 H'0054 to H'0057 4 IRQ5* Rev. 3.00, 08/03, page 52 of 612 1 Exception Source Vector Number Vector Address Advanced Mode* Reserved for system use 22 H'0058 to H'005B 23 H'005C to H'005F Internal interrupt* 24 107 H'0060 to H'0063 H'01AC to H'01AF External interrupt WKP0 to WKP7 108 H'01B0 to H'01B3 Internal interrupt 120 123 H'01E0 to H'01E3 H'01EC to H'01EF 2 1 Notes: 1. Lower 16 bits of the address. 2. For details of internal interrupt vectors, see section 5.4.3, Interrupt Exception Handling Vector Table. 3. For details on direct transitions, see section 22.10, Direct Transitions. 4. Supported only by the H8S/2268 Group. 4.3 Reset A reset has the highest exception priority. When the RES pin goes low, all processing halts and this LSI enters the reset. A reset initializes the internal state of the CPU and the registers of on-chip peripheral modules. The interrupt control mode is 0 immediately after reset. When the RES pin goes high from the low state, this LSI starts reset exception handling. The chip can also be reset by overflow of the watchdog timer. For details see section 12, Watchdog Timer (WDT). 4.3.1 Reset Exception Handling When the RES pin goes low, this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at power-up. To reset the chip during operation, hold the RES pin low for at least 20 states. When the RES pin goes high after being held low for the necessary time, this LSI starts reset exception handling as follows. 1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized, the T bit in EXR* is cleared to 0, and the I bits in EXR* and CCR is set to 1. 2. The reset exception handling vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Note: * Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 53 of 612 Figures 4.1 shows an example of the reset sequence. Vector fetch Prefetch of first Internal processing program instruction (1) (3) RES Internal address bus (5) Internal read signal Internal write signal Internal data bus High (2) (4) (6) (1)(3) Reset exception handling vector address(when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Figure 4.1 Reset Sequence (Advanced Mode with On-chip ROM Enabled) 4.3.2 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx: SP). 4.3.3 State of On-Chip Peripheral Modules after Reset Release After reset release, MSTPCRA is initialized to H'3F, MSTPCRB to MSTPCRD are initialized to H'FF, and all modules except the DTC (only for the H8S/2268 Group) enter module stop mode. Consequently, on-chip peripheral module registers cannot be read or written to. Register reading and writing is enabled when the module stop mode is exited. Rev. 3.00, 08/03, page 54 of 612 4.4 Traces (Supported only by the H8S/2268 Group) Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is not affected by interrupt masking. Table 4.3 shows the state of CCR and EXR after execution of trace exception handling. Trace mode is canceled by clearing the T bit in EXR to 0. Interrupts are accepted even within the trace exception handling routine. The T bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the RTE instruction, trace mode resumes. Trace exception handling is not carried out after execution of the RTE instruction. Table 4.3 Status of CCR and EXR after Trace Exception Handling CCR UI EXR Interrupt Control Mode I 0 Trace exception handling cannot be used. 2 1 -- I2 to I0 -- T 0 [Legend] 1: Set to 1 0: Cleared to 0 --: Retains value prior to execution 4.5 Interrupts Interrupts are controlled by the interrupt controller. The interrupt controller of the H8S/2268 Group has two interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiplexed interrupt control. For details, refer to section 5, Interrupt Controller. Interrupt exception handling is conducted as follows: 1. The values in the program counter (PC), condition code register (CCR), and extended control register (EXR)* are saved to the stack. 2. The interrupt mask bit is updated and the T bit* is cleared to 0. 3. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution begins from that address. Note: * Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 55 of 612 4.6 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. Trap instruction exception handling is conducted as follows: 1. The values in the program counter (PC), condition code register (CCR), and extended control register (EXR)* are saved to the stack. 2. The interrupt mask bit is updated and the T bit* is cleared. 3. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution starts from that address. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.4 shows the status of CCR and EXR* after execution of trap instruction exception handling. Table 4.4 Status of CCR and EXR* after Trap Instruction Exception Handling CCR EXR* Interrupt Control Mode I UI I2 to I0 T 0 1 -- -- -- 2* 1 -- -- 0 [Legend] 1: Set to 1 0: Cleared to 0 --: Retains value prior to execution Note: * Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 56 of 612 4.7 Stack Status after Exception Handling Figures 4.2 shows the stack after completion of trap instruction exception handling and interrupt exception handling. EXR SP RESERVED*1 SP CCR PC (24 bit) PC (24 bit) Interrupt control mode 0 Interrupt control mode*2 Note: 1. Ignored on return 2. Supported only by the H8S/2268 Group. Figure 4.2 Stack Status after Exception Handling (Advanced Mode) 4.8 Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @-SP) PUSH.L ERn (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W Rn (or MOV.W @SP+, Rn) POP.L ERn (or MOV.L @SP+, ERn) Setting SP to an odd value may lead to a malfunction. Figure 4.3 shows an example of what happens when the SP value is odd. Rev. 3.00, 08/03, page 57 of 612 CCR SP R1L SP H'FFFEFA H'FFFEFB PC PC H'FFFEFC H'FFFEFD SP H'FFFEFF SP set to H'FFFEFF TRAP instruction executed MOV.B R1L, @-ER7 executed Data saved above SP Contents of CCR lost Legend CCR : PC : R1L : SP : Condition code register Program counter General register R1L Stack pointer Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. Figure 4.3 Operation when SP Value Is Odd Rev. 3.00, 08/03, page 58 of 612 Section 5 Interrupt Controller 5.1 Features This LSI controls interrupts with the interrupt controller. The interrupt controller has the following features: * Two interrupt control modes (H8S/2268 Group only) Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). * Priorities settable with IPR (H8S/2268 Group only) An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI. NMI is assigned the highest priority level of 8, and can be accepted at all times. * Independent vector addresses All interrupt sources except WKP7 to WKP0 are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. * External interrupts H8S/2268 Group: 14 (NMI, IRQ5 to IRQ3, IRQ1, IRQ0, and WKP7 to WKP0) H8S/2264 Group: 13 (NMI, IRQ4, IRQ3, IRQ1, IRQ0, and WKP7 to WKP0) NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge can be selected for NMI. Falling edge, rising edge, or both edge detection, or level sensing, can be independently selected for IRQ5 to IRQ3, IRQ1, and IRQ0. WKP7 to WKP0 are accepted at a falling edge * DTC control (H8S/2268 Group only) The DTC can be activated by an interrupt request. A block diagram of the interrupt controller for the H8S/2268 Group is shown in figure 5.1, and that for the H8S/2264 Group is shown in figure 5.2 Rev. 3.00, 08/03, page 59 of 612 CPU INTM1, INTM0 SYSCR NMIEG NMI input NMI input unit IRQ input IRQ input unit ISR ISCR WKP input IER WKP input unit IWPR Interrupt request Vector number Priority determination I CCR IENR1 I2 to I0 Internal interrupt request SWDTEND to TEI2 EXR IPR Interrupt controller [Legend] ISCR: IRQ sense control register IRQ enable register IER: ISR: IRQ status register IENR1: Interrupt enable register1 IWPR: Wakeup interrupt request register IPR: Interrupt priority register SYSCR: System control register Figure 5.1 Block Diagram of Interrupt Controller for H8S/2268 Group Rev. 3.00, 08/03, page 60 of 612 CPU INTM1, INTM0 SYSCR NMIEG NMI input NMI input unit IRQ input IRQ input unit ISR ISCR WKP input IER WKP input unit IWPR Interrupt request Vector number Priority determination I IENR1 CCR Internal interrupt request WOVI0 to TEI2 Interrupt controller [Legend] ISCR: IRQ sense control register IRQ enable register IER: IRQ status register ISR: IENR1: Interrupt enable register1 IWPR: Wakeup interrupt request register SYSCR: System control register Figure 5.2 Block Diagram of Interrupt Controller for H8S/2264 Group Rev. 3.00, 08/03, page 61 of 612 5.2 Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Pin Configuration Name I/O Function NMI Input Nonmaskable external interrupt Rising or falling edge can be selected IRQ5* Input IRQ4 Input Maskable external interrupts Rising, falling, or both edges, or level sensing, can be selected IRQ3 Input IRQ2 Input IRQ1 Input IRQ0 Input WKP7 Input WKP6 Input WKP5 Input WKP4 Input WKP3 Input WKP2 Input WKP1 Input WKP0 Input Note: * Maskable external interrupts Accepted at a falling edge Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 62 of 612 5.3 Register Descriptions The interrupt controller has the following registers. * System control register (SYSCR) * IRQ sense control register H (ISCRH) * IRQ sense control register L (ISCRL) * IRQ enable register (IER) * IRQ status register (ISR) * Interrupt priority register A (IPRA)* * Interrupt priority register B (IPRB)* * Interrupt priority register C (IPRC)* * Interrupt priority register D (IPRD)* * Interrupt priority register E (IPRE)* * Interrupt priority register F (IPRF)* * Interrupt priority register G (IPRG)* * Interrupt priority register I (IPRI)* * Interrupt priority register J (IPRJ)* * Interrupt priority register K (IPRK)* * Interrupt priority register L (IPRL)* * Interrupt priority register M (IPRM)* * Interrupt priority register O (IPRO)* * Wakeup interrupt request register (IWPR) * Interrupt enable register 1 (IENR1) Note: * Supported only by the H8S/2268 Group. 5.3.1 System Control Register (SYSCR) SYSCR selects the interrupt control mode and the detected edge for NMI. Rev. 3.00, 08/03, page 63 of 612 Bit Bit Name Initial Value R/W Descriptions 7 0 R/W Reserved The write value should always be 0. 6 0 Reserved This bit is always read as 0, and cannot be modified. 5 INTM1 0 R/W Interrupt Control Mode 1 and 0 4 INTM0 0 R/W H8S/2268 Group: These bits select the control mode of the interrupt controller. 00: Interrupt control mode 0 (interrupts are controlled by the I bit.) 01: Setting prohibited 10: Interrupt control mode 2 (Interrupts are controlled by the I2 to I0 bits and IPR.) 11: Setting prohibited H8S/2264 Group: The write value should always be 0. 00: Interrupt control mode 0 (interrupts are controlled by the I bit.) 01: Setting prohibited 10: Setting prohibited 11: Setting prohibited 3 NMIEG 0 R/W NMI Edge Select Selects the valid edge of the NMI interrupt input. 0: An interrupt is requested at the falling edge of NMI input 1: An interrupt is requested at the rising edge of NMI input 2 0 R/W Reserved The write value should always be 0. 1 0 Reserved This bit is always read as 0, and cannot be modified. 0 1 R/W Reserved The write value should always be 0. Rev. 3.00, 08/03, page 64 of 612 5.3.2 Interrupt Priority Registers A to G, I to M, and O (IPRA to IPRG, IPRI to IPRM, IPRO) (H8S/2268 Group Only) The IPR registers are thirteen 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than NMI. The correspondence between interrupt sources and IPR settings is shown in table 5.2. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 0 to 2 and 4 to 6 sets the priority of the corresponding interrupt. Bit Bit Name Initial Value R/W Description 7 0 Reserved This bit is always read as 0, and cannot be modified. 6 IPR6 1 R/W Sets the priority of the corresponding interrupt source 5 IPR5 1 R/W 000: Priority level 0 (Lowest) 4 IPR4 1 R/W 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (Highest) 3 0 Reserved This bit is always read as 0, and cannot be modified. 2 IPR2 1 R/W Sets the priority of the corresponding interrupt source. 1 IPR1 1 R/W 000: Priority level 0 (Lowest) 0 IPR0 1 R/W 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (Highest) Rev. 3.00, 08/03, page 65 of 612 5.3.3 IRQ Enable Register (IER) IER controls the enabling and disabling of interrupt requests IRQn (H8S/2268 Group: n = 5 to 3, 1, 0; H8S/2264 Group: n = 4, 3, 1, 0). Bit Bit Name Initial Value R/W Description 7, 6 All 0 R/W Reserved The write value should always be 0. 5 IRQ5E 0 R/W H8S/2268 Group: IRQ5 Enable The IRQ5 interrupt request is enabled when this bit is 1. H8S/2264 Group: Reserved The write value should always be 0. 4 IRQ4E 0 R/W IRQ4 Enable The IRQ4 interrupt request is enabled when this bit is 1. 3 IRQ3E 0 R/W IRQ3 Enable The IRQ3 interrupt request is enabled when this bit is 1. 2 0 R/W Reserved The write value should always be 0. 1 IRQ1E 0 R/W IRQ1 Enable The IRQ1 interrupt request is enabled when this bit is 1. 0 IRQ0E 0 R/W IRQ0 Enable The IRQ0 interrupt request is enabled when this bit is 1. Rev. 3.00, 08/03, page 66 of 612 5.3.4 IRQ Sense Control Registers H and L (ISCRH and ISCRL) The ISCR registers select the source that generates an interrupt request at pins IRQn (H8S/2268 Group: n = 5 to 3, 1, 0; H8S/2264 Group: n = 4, 3, 1, 0). Specifiable sources are the falling edge, rising edge, or both edge detection, and level sensing. Bit Bit Name Initial Value R/W 15 to 12 All 0 R/W Description Reserved The write value should always be 0. 11 IRQ5SCB 0 R/W H8S/2268 Group: 10 IRQ5SCA 0 R/W IRQ5 Sense Control B IRQ5 Sense Control A 00: Interrupt request generated at IRQ5 input level low 01: Interrupt request generated at falling edge of IRQ5 input 10: Interrupt request generated at rising edge of IRQ5 input 11: Interrupt request generated at both falling and rising edges of IRQ5 input H8S/2264 Group: Reserved The write value should always be 0. 9 IRQ4SCB 0 R/W 8 IRQ4SCA 0 R/W IRQ4 Sense Control B IRQ4 Sense Control A 00: Interrupt request generated at IRQ4 input level low 01: Interrupt request generated at falling edge of IRQ4 input 10: Interrupt request generated at rising edge of IRQ4 input 11: Interrupt request generated at both falling and rising edges of IRQ4 input Rev. 3.00, 08/03, page 67 of 612 Bit Bit Name Initial Value R/W Description 7 IRQ3SCB 0 R/W 6 IRQ3SCA 0 R/W IRQ3 Sense Control B IRQ3 Sense Control A 00: Interrupt request generated at IRQ3 input level low 01: Interrupt request generated at falling edge of IRQ3 input 10: Interrupt request generated at rising edge of IRQ3 input 11: Interrupt request generated at both falling and rising edges of IRQ3 input 5, 4 All 0 R/W Reserved The write value should always be 0. 3 IRQ1SCB 0 R/W 2 IRQ1SCA 0 R/W IRQ1 Sense Control B IRQ1 Sense Control A 00: Interrupt request generated at IRQ1 input level low 01: Interrupt request generated at falling edge of IRQ1 input 10: Interrupt request generated at rising edge of IRQ1 input 11: Interrupt request generated at both falling and rising edges of IRQ1 input 1 IRQ0SCB 0 R/W 0 IRQ0SCA 0 R/W IRQ0 Sense Control B IRQ0 Sense Control A 00: Interrupt request generated at IRQ0 input level low 01: Interrupt request generated at falling edge of IRQ0 input 10: Interrupt request generated at rising edge of IRQ0 input 11: Interrupt request generated at both falling and rising edges of IRQ0 input Rev. 3.00, 08/03, page 68 of 612 5.3.5 IRQ Status Register (ISR) ISR indicates the status of IRQn (H8S/2268 Group: n = 5 to 3, 1, 0; H8S/2264 Group: n = 4, 3, 1, 0) interrupt requests. Bit Bit Name Initial Value R/W Description 7, 6 All 0 R/W Reserved The write value should always be 0. 5 IRQ5F 0 1 R/(W)* H8S/2268 Group: IRQ5 Flag Indicates the status of an IRQ5 interrupt request. [Setting condition] * When the interrupt source selected by the ISCR registers occurs [Clearing conditions] * Cleared by reading IRQ5F flag when IRQ5F = 1, then writing 0 to IRQ5F flag * When interrupt exception handling is executed when low-level detection is set and IRQ5 input is high level * When IRQ5 interrupt exception handling is executed when falling, rising, or both-edge detection is set * When the DTC is activated by an IRQ5 interrupt, and the DISEL bit in MRB of the DTC is cleared to 0 H8S/2264 Group: Reserved The write value should always be 0. Rev. 3.00, 08/03, page 69 of 612 Bit Bit Name Initial Value R/W Description 4 IRQ4F 0 R/(W)* 2 3 IRQ3F 0 R/(W)* 2 IRQ4 and IRQ3 Flags Indicate the status of IRQ4 and IRQ3 interrupt requests. [Setting condition] * When the interrupt source selected by the ISCR registers occurs [Clearing conditions] 2 0 R/W * Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag * When interrupt exception handling is executed when low-level detection is set and IRQn input is high * When IRQn interrupt exception handling is executed when falling, rising, or both-edge detection is set * When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the DTC is cleared to 0 (H8S/2268 Group only) Reserved The write value should always be 0. 2 IRQ1 and IRQ0 Flags 2 Indicate the status of IRQ1 and IRQ0 interrupt requests. 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)* [Setting condition] * When the interrupt source selected by the ISCR registers occurs [Clearing conditions] * Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag * When interrupt exception handling is executed when low-level detection is set and IRQn input is high * When IRQn interrupt exception handling is executed when falling, rising, or both-edge detection is set * When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the DTC is cleared to 0 (H8S/2268 Group only) Notes: 1. In the H8S/2268 Group, only 0 can be written to this bit to clear the flag. In the H8S/2264 Group, this bit is readable/writable. 2. Only 0 can be written to this bit to clear the flag. Rev. 3.00, 08/03, page 70 of 612 5.3.6 Wakeup Interrupt Request Register (IWPR) IWPR indicates the status of WKP7 to WKP0 interrupt requests. Bit Bit Name Initial Value R/W 7 IWPF7 0 R/(W)* Wakeup Interrupt Request Flags 6 IWPF6 0 R/(W)* Indicate the status of WKP7 to WKP0 interrupt requests. 5 IWPF5 0 R/(W)* [Setting condition] 4 IWPF4 0 3 IWPF3 0 R/(W)* When WKP7 to WKP0 pins are set as wakeup inputs and R/(W)* these pins have a falling edge. 2 IWPF2 0 1 IWPF1 0 R/(W)* [Clearing condition] R/(W)* When this bit reads 1 and then write 0. 0 IWPF0 0 R/(W)* Description Note: Only 0 can be written to this bit to clear the flag. 5.3.7 Interrupt Enable Register 1 (IENR1) IENR1 enables/disables wakeup interrupt requests. Bit Bit Name Initial Value R/W Description 7 IENWP 0 R/W Wakeup Interrupt Enable Enables/disables WKP7 to WKP0 interrupt requests 0: WKP7 to WKP0 pin interrupt requests are disabled. 1: WKP7 to WKP0 pin interrupt requests are enabled. 6 to 1 All 0 Reserved These bits are always read as 0 and cannot be modified. 0 0 R/W Reserved This bit should always be 0 when it is read. Rev. 3.00, 08/03, page 71 of 612 5.4 Interrupt Sources 5.4.1 External Interrupts There are 14 external interrupts for the H8S/2268 Group: NMI, IRQ5 to IRQ3, IRQ1, IRQ0, and WKP7 to WKP0, and 13 external interrupts for the H8S/2264 Group: NMI, IRQ4, IRQ3, IRQ1, IRQ0, and WKP7 to WKP0. These interrupts can be used to restore this LSI from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin. IRQn Interrupts (H8S/2268 Group: n = 5 to 3, 1 and 0; H8S/2264 Group: n = 4, 3, 1 and 0): IRQn interrupts are requested by an input signal at IRQn pins. IRQn interrupts have the following features: * Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at IRQn pins. * Enabling or disabling of IRQn interrupt requests can be selected with IER. * The interrupt priority level can be set with IPR. (H8S/2268 Group only) * The status of IRQn interrupt requests is indicated in ISR. ISR flags can be cleared to 0 by software. A block diagram of IRQn interrupts is shown in figure 5.3. IRQnE IRQnSCA, IRQnSCB IRQnF Edge / level detection circuit S Q R IRQn input Clear signal Note: H8S/2268 Group: n = 5 to 3, 1, 0 H8S/2264 Group: n = 4, 3, 1, 0 Figure 5.3 Block Diagram of IRQn Interrupts Rev. 3.00, 08/03, page 72 of 612 IRQn interrupt request The set timing for IRQnF is shown in figure 5.4. IRQn Input Pin IRQnF Note: H8S/2268 Group: n = 5 to 3, 1, 0 H8S/2264 Group: n = 4, 3, 1, 0 Figure 5.4 Set Timing for IRQnF The detection of IRQn interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR to 0; and use the pin as an I/O pin for another function. IRQnF interrupt request flag is set to 1 when the setting condition is satisfied, regardless of IER settings. Accordingly, refer to only necessary flags. WKP7 to WKP0 Interrupts:WKP7 to WKP0 interrupts are requested by falling edge input signal at WKP7 to WKP0 pins. WKP7 to WKP0 interrupts have the following features: * WPCR selects whether the PJn/WKPn/SEGn+1 pin is used as the PJn pin or WKPn pin when the PJn/WKPn/SEGn+1 pin is not used as the SEGn+1 pin. (n=7 to 0) For pin switching, see 9.8.5 Wakeup Control Register (WPCR). * IENR1 can be used to select enabling or disabling of WKP7 to WKP0 interrupt requests. * IPR sets the interrupt priority level. (H8S/2268 Group only) * IWPR indicates the status of WKP7 to WKP0 interrupt requests. IWPR flag can be cleared to 0 by software. The block diagram of interrupts WKP7 to WKP0 is shown in figure 5.5. Rev. 3.00, 08/03, page 73 of 612 IENWP Falling edge WKP7 to WKP0 Interrupt request IWPF7 detection circuit S WKP7 Input Q R Falling edge IWPF6 detection circuit S WKP6 Input Q R - - - - - - - - - - - - - - - - Falling edge IWPF0 detection circuit S WKP0 Input Q R Clear signal Figure 5.5 Block Diagram of Interrupts WKP7 to WKP0 Figure 5.6 shows the IWPFn setting timing. WKPn input IWPFn (n = 7 to 0) Figure 5.6 IWPFn Setting Timing The vector number for the WKP7 to WKP0 interrupt exception handling is 108. Eight interrupt pins are assigned to one vector number. Accordingly, determine the source using an exception handling routine. The detection of interrupts WKP7 to WKP0 does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR to 0; and use the pin as an I/O pin for another function. IRQnF interrupt Rev. 3.00, 08/03, page 74 of 612 request flag is set to 1 when the setting condition is satisfied, regardless of IER settings. Accordingly, refer to only necessary flags. 5.4.2 Internal Interrupts For each on-chip peripheral module, there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1 for a particular interrupt source, an interrupt request is issued to the interrupt controller. 5.4.3 Interrupt Exception Handling Vector Table Table 5.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Priorities among modules can be set by means of the IPR. (H8S/2268 Group only) Modules set at the same priority will conform to their default priorities. Priorities within a module are fixed. Rev. 3.00, 08/03, page 75 of 612 Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities Vector Address*1 Interrupt Source Origin of Interrupt Source Vector Number Advanced Mode External Pin NMI 7 H'001C IRQ0 16 H'0040 IPRA6 to IPRA4 IRQ1 17 H'0044 IPRA2 to IPRA0 IPRB6 to IPRB4 IPR*2 *3 High Reserved 18 H'0048 IRQ3 19 H'004C 20 H'0050 IRQ5* 21 H'0054 Reserved 22 23 H'0058 H'005C IPRC6 to IPRC4 DTC*3 SWDTEND (completion of software initiation data transfer) 24 H'0060 IPRC2 to IPRC0 Watchdog timer 0 WOVI0 (interval timer 0) 25 H'0064 IPRD6 to IPRD4 PC break*3 PC break 27 H'006C IPRE6 to IPRE4 A/D ADI (completion of A/D conversion) 28 H'0070 IPRE2 to IPRE0 Watchdog timer 1 WOVI1 (interval timer 1) 29 H'0074 Reserved 30 31 H'0078 H'007C TPU channel 0*3 TGI0A (TGR0A input capture/compare-match) 32 H'0080 TGI0B (TGR0B input capture/compare-match) 33 H'0084 TGI0C (TGR0C input capture/compare-match) 34 H'0088 TGI0D (TGR0D input capture/compare- match) 35 H'008C TCI0V (overflow 0) 36 H'0090 Reserved 37 38 39 H'0094 H'0098 H'009C IRQ4 3 Rev. 3.00, 08/03, page 76 of 612 Priority IPRB2 to IPRB0 IPRF6 to IPRF4 Low Vector Address*1 Origin of Interrupt Source Vector Number Advanced Mode IPR*2 *3 Priority TGI1A (TGR1A input capture/compare-match) 40 H'00A0 IPRF2 to IPRF0 High TGI1B (TGR1B input capture/compare-match) 41 H'00A4 TCI1V (overflow 1) 42 H'00A8 TCI1U (underflow 1) * 43 H'00AC TGI2A (TGR2A input capture/compare-match) 44 H'00B0 TGI2B (TGR2B input capture/compare-match) 45 H'00B4 TCI2V (overflow 2) 46 H'00B8 47 H'00BC 8-bit timer channel CMIA0 0 (compare-match A0) 64 H'0100 CMIB0 (compare-match B0) 65 H'0104 OVI0 (overflow 0) 66 H'0108 Reserved 67 H'010C 8-bit timer channel CMIA1 1 (compare-match A1) 68 H'0110 CMIB1 (compare-match B1) 69 H'0114 OVI1 (overflow 1) 70 H'0118 Reserved 71 H'011C SCI channel 0 ERI0 (receive error 0) 80 H'0140 RXI0 (receive completion 0) 81 H'0144 TXI0 (transmit data empty 0) 82 H'0148 TEI0 (transmit end 0) 83 H'014C ERI1 (receive error 1) 84 H'0150 RXI1 (receive completion 1) 85 H'0154 TXI1 (transmit data empty 1) 86 H'0158 TEI1 (transmit end 1) 87 H'015C Interrupt Source TPU channel 1 3 TPU channel 2 3 TCI2U (underflow 2) * SCI channel 1 IPRG6 to IPRG4 IPRI6 to IPRI4 IPRI2 to IPRI0 IPRJ2 to IPRJ0 IPRK6 to IPRK4 Low Rev. 3.00, 08/03, page 77 of 612 Vector Address*1 Vector Number Advanced Mode IPR*2 *3 Priority 8-bit timer channel CMIA2 2*3 (compare-match A2) 92 H'0170 IPRL6 to IPRL4 High CMIB2 (compare-match B2) 93 H'0174 OVI2 (overflow 2) 94 H'0178 Reserved 95 H'017C 8-bit timer channel CMIA3 3*3 (compare-match A3) 96 H'0180 CMIB3 (compare-match B3) 97 H'0184 OVI3 (overflow 3) 98 H'0188 Reserved 99 H'018C IIC channel 0 (option) IICI0 (1-byte transmission/ 100 reception completion) H'0190 Reserved 101 H'0194 IICI1 (1-byte transmission/ 102 reception completion) H'0198 Reserved 103 H'019C OVI4 (overflow 4) 104 H'01A0 OVI5 (overflow 5) 105 H'01A4 OVI6 (overflow 6) 106 H'01A8 OVI7 (overflow 7) 107 H'01AC External pins WKP7 to WKP0 108 H'01B0 IPRM2 to IPRM0 SCI channel 2 ERI2 (receive error 2) 120 H'01E0 IPRO6 to IPRO4 RXI2 (receive completion 2) 121 H'01E4 TXI2 (transmit data empty 2) 122 H'01E8 TEI2 (transmit end 2) 123 H'01EC Interrupt Source 3 IIC channel 1* (option) 8-bit reload timer channels 4 to 7*3 Origin of Interrupt Source IPRL2 to IPRL0 IPRM6 to IPRM4 Low Notes: 1. Lower 16 bits of the start address. 2. IPR6 to IPR4, and IPR2 to IPR0 bits are reserved, because these bits have no corresponding interruption. These bits are always read as 0 and cannot be modified. 3. Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 78 of 612 5.5 Operation 5.5.1 Interrupt Control Modes and Interrupt Operation Interrupt operations in the H8S/2268 differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In the case of IRQ interrupts, WKP interrupts and on-chip peripheral module interrupts, an enable bit is provided for each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt sources for which the enable bits are set to 1 are controlled by the interrupt controller. Table 5.3 shows the interrupt control modes. The interrupt controller performs interrupt control according to the interrupt control mode set by the INTM1 and INTM0 bits in SYSCR, the priorities set in IPR*, and the masking state indicated by the I bit in the CPU's CCR, and bits I2 to I0 in EXR*. Table 5.3 Interrupt Control Modes SYSCR Interrupt Priority Setting Control Mode INTM1 INTM0 Registers* 0 0 2* 1 Note: * Interrupt Mask Bits Description 0 I Interrupt mask control is performed by the I bit. 1 Setting prohibited 0 IPR I2 to I0 8-level interrupt mask control is performed by bits I2 to I0. 8 priority levels can be set with IPR. 1 Setting prohibited Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 79 of 612 Figures 5.7 and 5.8 show block diagrams of the priority decision circuits for the H8S/2268 Group and H8S/2264 Group, respectively. Interrupt control mode 0 I Interrupt acceptance control Default priority determination Interrupt source Vector number 8-level mask control IPR I2 to I0 Interrupt control mode 2 Figure 5.7 Block Diagram of Interrupt Control Operation for H8S/2268 Group Interrupt control mode 0 Interrupt source I Interrupt acceptance control Default priority determination Vector number Figure 5.8 Block Diagram of Interrupt Control Operation for H8S/2264 Group Rev. 3.00, 08/03, page 80 of 612 Interrupt Acceptance Control: In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR. Table 5.4 shows the interrupts selected in each interrupt control mode. Table 5.4 Interrupts Selected in Each Interrupt Control Mode (1) Interrupt Mask Bits Interrupt Control Mode I Selected Interrupts 0 0 All interrupts 1 NMI interrupts X All interrupts 2* Legend: Note: * X: Don't care Supported only by the H8S/2268 Group. 8-Level Control (H8S/2268 Group Only): In interrupt control mode 2, 8-level mask level determination is performed for the selected interrupts in interrupt acceptance control according to the interrupt priority level (IPR). The interrupt source selected is the interrupt with the highest priority level, and whose priority level set in IPR is higher than the mask level. Table 5.5 Interrupts Selected in Each Interrupt Control Mode (2) Interrupt Control Mode Selected Interrupts 0 All interrupts 2 Highest-priority-level (IPR) interrupt whose priority level is greater than the mask level (IPR > I2 to I0). Default Priority Determination: When an interrupt is selected by 8-level control, its priority is determined and a vector number is generated. If the same value is set for IPR, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated (H8S/2268 Group only). Interrupt sources with a lower priority than the accepted interrupt source are held pending. Table 5.6 shows operations and control signal functions in each interrupt control mode. Rev. 3.00, 08/03, page 81 of 612 Table 5.6 Operations and Control Signal Functions in Each Interrupt Control Mode Interrupt Setting Control Mode INTM1 INTM0 0 0 3 2* 1 0 0 Interrupt Acceptance Control 3 8-Level Control* I2 to I0* IPR* Default Priority Determination T (Trace) X * O O IM PR O T 3 I O IM X * 1 3 2 [Legend] Interrupt operation control performed O: X: No operation. (All interrupts enabled) IM: Used as interrupt mask bit PR: Sets priority. : Not used. Notes: 1. Set to 1 when interrupt is accepted. 2. Keep the initial setting. 3. Supported only by the H8S/2268 Group. 5.5.2 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts, WKP interrupts and on-chip peripheral module interrupts can be set by means of the I bit in the CPU's CCR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1. Figure 5.9 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending. If the I bit is cleared, an interrupt request is accepted. 3. Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to the priority system is accepted, and other interrupt requests are held pending. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI. 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Rev. 3.00, 08/03, page 82 of 612 Program execution status Interrupt generated No Yes Yes NMI No No Hold pending I=0 Yes IRQ0 No No Yes IRQ1 Yes TEI2 Yes Save PC and CCR I=1 Read vector address Branch to interrupt handling routine Figure 5.9 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0 Rev. 3.00, 08/03, page 83 of 612 5.5.3 Interrupt Control Mode 2 (H8S/2268 Group Only) Eight-level masking is implemented for IRQ interrupts, WKP interrupts and on-chip peripheral module interrupts by comparing the interrupt mask level set by bits I2 to I0 of EXR in the CPU with IPR. Figure 5.10 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. When interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the interrupt priority levels set in IPR is selected, and lower-priority interrupt requests are held pending. If a number of interrupt requests with the same priority are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5.2 is selected. 3. Next, the priority of the selected interrupt request is compared with the interrupt mask level set in EXR. An interrupt request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with a priority higher than the interrupt mask level is accepted. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of the accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'7. 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Rev. 3.00, 08/03, page 84 of 612 Program execution status Interrupt generated? No Yes Yes NMI No Level 7 interrupt? No Yes Mask level 6 or below? Yes Level 6 interrupt? No No Yes Level 1 interrupt? Mask level 5 or below? No No Yes Yes Mask level 0? No Yes Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5.10 Flowchart of Procedure Up to Interrupt Acceptance in Control Mode 2 5.5.4 Interrupt Exception Handling Sequence Figure 5.11 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Rev. 3.00, 08/03, page 85 of 612 Figure 5.11 Interrupt Exception Handling Rev. 3.00, 08/03, page 86 of 612 (1) (2) (4) (3) Internal operation Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2) (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.) (5) SP-2 (7) SP-4 (1) Internal data bus Internal write signal Internal read signal Internal address bus Interrupt request signal Interrupt level determination Instruction Wait for end of instruction prefetch Interrupt acceptance (7) (8) (10) (9) (12) (11) Internal operation (14) (13) Interrupt service routine instruction prefetch Saved PC and saved CCR Vector address Interrupt handling routine start address (Vector address contents) Interrupt handling routine start address ((13) = (10)(12)) First instruction of interrupt handling routine (6) (6) (8) (9) (11) (10) (12) (13) (14) (5) stack Vector fetch 5.5.5 Interrupt Response Times This LSI is capable of fast word transfer to on-chip memory, has the program area in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing. Table 5.7 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.7 are explained in table 5.8. Table 5.7 Interrupt Response Times (States) 5 Normal Mode* No. Execution Status 1 Advanced Mode INTM1 = 0 INTM1 = 1 INTM1 = 0 INTM1 = 1 1 Interrupt priority determination* 3 3 3 3 2 Number of wait states until 2 executing instruction ends* 1 to 19 + 2*SI 1 to 19 + 2*SI 1 to 19 + 2*SI 1 to 19 + 2*SI 3 PC, CCR, EXR stack save 2*SK 3*SK 2*SK 3*SK 4 Vector fetch SI SI 2*SI 2*SI 2*SI 2*SI 2*SI 2*SI 2 2 2 2 11 to 31 12 to 32 12 to 32 13 to 33 5 6 3 Instruction fetch* 4 Internal processing* Total (using on-chip memory) Notes: 1. 2. 3. 4. 5. Table 5.8 Two states in case of internal interrupt. Refers to MULXS and DIVXS instructions. Prefetch after interrupt acceptance and interrupt handling routine prefetch. Internal processing after interrupt acceptance and internal processing after vector fetch. Not available in this LSI. Number of States in Interrupt Handling Routine Execution Status Object of Access External Device * 8 Bit Bus Symbol Instruction fetch SI Branch address read SJ Stack manipulation SK 16 Bit Bus Internal Memory 2-State Access 3-State Access 2-State Access 3-State Access 1 4 6 + 2m 2 3+m [Legend] m: Number of wait states in an external device access. Note: * Cannot be used in this LSI. Rev. 3.00, 08/03, page 87 of 612 5.5.6 DTC Activation by Interrupt (H8S/2268 Group Only) The DTC can be activated by an interrupt. For details, see section 8, Data Transfer Controller (DTC). 5.6 Usage Notes 5.6.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, and if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt source flag is cleared to 0. Figure 5.12 shows an example in which the CMIEA bit in the TCR register of the 8-bit timer is cleared to 0. TCR write cycle by CPU CMIA exception handling Internal address bus TCR address Internal write signal CMIEA CMFA CMIA interrupt signal Figure 5.12 Contention between Interrupt Generation and Disabling Rev. 3.00, 08/03, page 88 of 612 The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. 5.6.2 Instructions that Disable Interrupts The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions are executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.6.3 When Interrupts Are Disabled There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ORC, or XORC instruction. 5.6.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the move is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W R4,R4 BNE L1 Rev. 3.00, 08/03, page 89 of 612 Rev. 3.00, 08/03, page 90 of 612 Section 6 PC Break Controller (PBC) The H8S/2268 Group includes a PC break controller (PBC), while the H8S/2264 Group does not. The PC break controller (PBC) provides functions that simplify program debugging. Using these functions, it is easy to create a self-monitoring debugger, enabling programs to be debugged with the chip alone, without using an in-circuit emulator. A block diagram of the PC break controller is shown in figure 6.1. 6.1 Features * Two break channels (A and B) * 24-bit break address Bit masking possible * Four types of break compare conditions Instruction fetch Data read Data write Data read/write * Bus master Either CPU or CPU/DTC can be selected * The timing of PC break exception handling after the occurrence of a break condition is as follows: Immediately before execution of the instruction fetched at the set address (instruction fetch) Immediately after execution of the instruction that accesses data at the set address (data access) * Module stop mode can be set PBC0000B_000020020700 Rev. 3.00, 08/03, page 91 of 612 BCRA Mask control Output control BARA Control logic Comparator Match signal Internal address PC break interrupt Access status Match signal Mask control BARB Output control Control logic Comparator BCRB Figure 6.1 Block Diagram of PC Break Controller 6.2 Register Descriptions The PC break controller has the following registers. * Break address register A (BARA) * Break address register B (BARB) * Break control register A (BCRA) * Break control register B (BCRB) 6.2.1 Break Address Register A (BARA) BARA is a 32-bit readable/writable register that specifies the channel A break address. Bit Bit Name Initial Value 31 to 24 Undefined R/W Description Reserved These bits are read as an undefined value and cannot be modified. 23 to 0 BAA23 to BAA0 H'000000 Rev. 3.00, 08/03, page 92 of 612 R/W These bits set the channel A PC break address. 6.2.2 Break Address Register B (BARB) BARB is the channel B break address register. The bit configuration is the same as for BARA. 6.2.3 Break Control Register A (BCRA) BCRA controls channel A PC breaks. Bit 7 Bit Name CMFA Initial Value 0 R/W Description 1 R/(W)* Condition Match Flag A [Setting condition] When a condition set for channel A is satisfied [Clearing condition] 2 When 0 is written to CMFA after reading* CMFA = 1 6 CDA 0 R/W CPU Cycle/DTC Cycle Select A Selects the channel A break condition bus master. 0: CPU 1: CPU or DTC 5 BAMRA2 0 R/W Break Address Mask Register A2 to A0 4 BAMRA1 0 R/W 3 BAMRA0 0 R/W These bits specify which bits of the break address set in BARA are to be masked. 000: BAA23 - 0 (All bits are unmasked) 001: BAA23 - 1 (Lowest bit is masked) 010: BAA23 - 2 (Lower 2 bits are masked) 011: BAA23 - 3 (Lower 3 bits are masked) 100: BAA23 - 4 (Lower 4 bits are masked) 101: BAA23 - 8 (Lower 8 bits are masked) 110: BAA23 - 12 (Lower 12 bits are masked) 111: BAA23 - 16 (Lower 16 bits are masked) 2 CSELA1 0 R/W Break Condition Select 1 CSELA0 0 R/W Selects break condition of channel A. 00: Instruction fetch is used as break condition 01: Data read cycle is used as break condition 10: Data write cycle is used as break condition 11: Data read/write cycle is used as break condition 0 BIEA 0 R/W Break Interrupt Enable When this bit is 1, the PC break interrupt request of channel A is enabled. Notes: 1. Only a 0 can be written to this bit to clear the flag. 2. Read the state wherein CMFA = 1 twice or more, when the CMFA is polled after inhibiting the PC break interruption. Rev. 3.00, 08/03, page 93 of 612 6.2.4 Break Control Register B (BCRB) BCRB is the channel B break control register. The bit configuration is the same as for BCRA. 6.3 Operation The operation flow from break condition setting to PC break interrupt exception handling is shown in section 6.3.1, PC Break Interrupt Due to Instruction Fetch, and 6.3.2, PC Break Interrupt Due to Data Access, taking the example of channel A. 6.3.1 PC Break Interrupt Due to Instruction Fetch 1. Set the break address in BARA. For a PC break caused by an instruction fetch, set the address of the first instruction byte as the break address. 2. Set the break conditions in BCR. Set bit 6 (CDA) to 0 to select the CPU because the bus master must be the CPU for a PC break caused by an instruction fetch. Set the address bits to be masked to bits 3 to 5 (BAMA2 to 0). Set bits 1 and 2 (CSELA1 to 0) to 00 to specify an instruction fetch as the break condition. Set bit 0 (BIEA) to 1 to enable break interrupts. 3. When the instruction at the set address is fetched, a PC break request is generated immediately before execution of the fetched instruction, and the condition match flag (CMFA) is set. 4. After priority determination by the interrupt controller, PC break interrupt exception handling is started. 6.3.2 PC Break Interrupt Due to Data Access 1. Set the break address in BARA. For a PC break caused by a data access, set the target ROM, RAM, I/O, or external address space address as the break address. Stack operations and branch address reads are included in data accesses. 2. Set the break conditions in BCRA. Select the bus master with bit 6 (CDA). Set the address bits to be masked to bits 3 to 5 (BAMA2 to 0). Set bits 1 and 2 (CSELA1 to 0) to 01, 10, or 11 to specify data access as the break condition. Set bit 0 (BIEA) to 1 to enable break interrupts. 3. After execution of the instruction that performs a data access on the set address, a PC break request is generated and the condition match flag (CMFA) is set. 4. After priority determination by the interrupt controller, PC break interrupt exception handling is started. Rev. 3.00, 08/03, page 94 of 612 6.3.3 Notes on PC Break Interrupt Handling * When a PC break interrupt is generated at the transfer address of an EEPMOV.B instruction PC break exception handling is executed after all data transfers have been completed and the EEPMOV.B instruction has ended. * When a PC break interrupt is generated at a DTC transfer address PC break exception handling is executed after the DTC has completed the specified number of data transfers, or after data for which the DISEL bit is set to 1 has been transferred. 6.3.4 Operation in Transitions to Power-Down Modes The operation when a PC break interrupt is set for an instruction fetch at the address after a SLEEP instruction is shown below. * When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to sleep mode: After execution of the SLEEP instruction, a transition is not made to sleep mode, and PC break interrupt handling is executed. After execution of PC break interrupt handling, the instruction at the address after the SLEEP instruction is executed (figure 6.2 (A)). * When the SLEEP instruction causes a transition from high speed (medium speed) mode to subactive mode (figure 6.2 (B)). * When the SLEEP instruction causes a transition from subactive mode to high speed (medium speed) mode (figure 6.2 (C)). * When the SLEEP instruction causes a transition to software standby mode: After execution of the SLEEP instruction, a transition is made to the respective mode, and PC break interrupt handling is not executed. However, the CMFA or CMFB flag is set (figure 6.2 (D)). Rev. 3.00, 08/03, page 95 of 612 SLEEP instruction execution SLEEP instruction execution SLEEP instruction execution SLEEP instruction execution PC break exception handling System clock subclock Subclock system clock, oscillation settling time Transition to respective mode Execution of instruction after sleep instruction Direct transition exception handling Direct transition exception handling (D) (A) PC break exception handling Subactive mode PC break exception handling Execution of instruction after sleep instruction Execution of instruction after sleep instruction (B) (C) High-speed (medium-speed) mode Figure 6.2 Operation in Power-Down Mode Transitions 6.3.5 When Instruction Execution Is Delayed by One State While the break interrupt enable bit is set to 1, instruction execution is one state later than usual. * For 1-word branch instructions (Bcc d:8, BSR, JSR, JMP, TRAPA, RTE, and RTS) in on-chip ROM or RAM. * When break interruption by instruction fetch is set, the set address indicates on-chip ROM or RAM space, and that address is used for data access, the instruction that executes the data access is one state later than in normal operation. * When break interruption by instruction fetch is set and a break interrupt is generated, if the executing instruction immediately preceding the set instruction has one of the addressing modes shown below, and that address indicates on-chip ROM or RAM, the instruction will be one state later than in normal operation. Addressing modes: @ERn, @(d:16,ERn), @(d:32,ERn), @-ERn/ERn+, @aa:8, @aa:24, @aa:32, @(d:8,PC), @(d:16,PC), @@aa:8 * When break interruption by instruction fetch is set and a break interrupt is generated, if the executing instruction immediately preceding the set instruction is NOP or SLEEP, or has #xx, Rn as its addressing mode, and that instruction is located in on-chip ROM or RAM, the instruction will be one state later than in normal operation. Rev. 3.00, 08/03, page 96 of 612 6.4 Usage Notes 6.4.1 Module Stop Mode Setting PBC operation can be disabled or enabled using the module stop control register. The initial setting is for PBC operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 22, Power-Down Modes. 6.4.2 PC Break Interrupts The PC break interrupt is shared by channels A and B. The channel from which the request was issued must be determined by the interrupt handler. 6.4.3 CMFA and CMFB The CMFA and CMFB flags are not automatically cleared to 0, so 0 must be written to CMFA or CMFB after first reading the flag while it is set to 1. If the flag is left set to 1, another interrupt will be requested after interrupt handling ends. 6.4.4 PC Break Interrupt when DTC Is Bus Master A PC break interrupt generated when the DTC is the bus master is accepted after the bus has been transferred to the CPU by the bus controller. 6.4.5 PC Break Set for Instruction Fetch at Address Following BSR, JSR, JMP, TRAPA, RTE, or RTS Instruction When a PC break is set for an instruction fetch at an address following a BSR, JSR, JMP, TRAPA, RTE, or RTS instruction: Even if the instruction at the address following a BSR, JSR, JMP, TRAPA, RTE, or RTS instruction is fetched, it is not executed, and so a PC break interrupt is not generated by the instruction fetch at the next address. 6.4.6 I Bit Set by LDC, ANDC, ORC, or XORC Instruction When the I bit is set by an LDC, ANDC, ORC, or XORC instruction, a PC break interrupt becomes valid two states after the end of the executing instruction. If a PC break interrupt is set for the instruction following one of these instructions, since interrupts, including NMI, are disabled for a 3-state period in the case of LDC, ANDC, ORC, and XOR, the next instruction is always executed. For details, see section 5, Interrupt Controller. Rev. 3.00, 08/03, page 97 of 612 6.4.7 PC Break Set for Instruction Fetch at Address Following Bcc Instruction When a PC break is set for an instruction fetch at an address following a Bcc instruction: A PC break interrupt is generated if the instruction at the next address is executed in accordance with the branch condition, and is not generated if the instruction at the next address is not executed. 6.4.8 PC Break Set for Instruction Fetch at Branch Destination Address of Bcc Instruction When a PC break is set for an instruction fetch at the branch destination address of a Bcc instruction: A PC break interrupt is generated if the instruction at the branch destination is executed in accordance with the branch condition, and is not generated if the instruction at the branch destination is not executed. Rev. 3.00, 08/03, page 98 of 612 Section 7 Bus Controller The H8S/2000 CPU is driven by a system clock, denoted by the symbol . The bus controller controls a memory cycle and a bus cycle. Different methods are used to access on-chip memory and on-chip peripheral modules. In the H8S/2268 Group, the bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the CPU and data transfer controller (DTC). 7.1 Basic Timing The period from one rising edge of to the next is referred to as a "state". The memory cycle or bus cycle consists of one, two, or four states. Different methods are used to access on-chip memory, on-chip peripheral modules, and the external address space. 7.1.1 On-Chip Memory Access Timing (ROM, RAM) On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and word transfer instruction. Figure 7.1 shows the on-chip memory access cycle. Bus cycle T1 Internal address bus Read access Internal read signal Internal data bus Write access Address Read data Internal write signal Internal data bus Write data Figure 7.1 On-Chip Memory Access Cycle Rev. 3.00, 08/03, page 99 of 612 7.1.2 On-Chip Peripheral Module Access Timing (H'FFFDAC to H'FFFFBF) Addresses H'FFFDAC to H'FFFFBF in the on-chip peripheral modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. For details, refer to section 24, List of Registers. Figure 7.2 shows access timing for the on-chip peripheral modules (H'FFFDAC to H'FFFFBF). Bus cycle T1 T2 Internal address bus Read access Internal read signal Internal data bus Write access Address Read data Internal write signal Internal data bus Write data Figure 7.2 On-Chip Peripheral Module Access Cycle (H'FFFDAC to H'FFFFBF) 7.1.3 On-Chip Peripheral Module Access Timing (H'FFFC30 to H'FFFCA3) Addresses H'FFFC30 to H'FFFCA3 on the on-chip peripheral modules and registers are accessed in four states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. For details, refer to section 24, List of Registers. Figure 7.3 shows access timing for the on-chip peripheral modules (H'FFFC30 to H'FFFCA3). The on-chip module of which address is between H'FFFC30 to H'FFFCA3 includes LCD, DTMF*, TMR4*, ports H to L and ports M* and N*. The registers are WKP register and module stop control register D. Note: * Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 100 of 612 Bus cycle T1 T2 T3 T4 Internal address bus Address Internal read signal Read access Internal data bus Read data Internal write signal Write access Internal data bus Write data Figure 7.3 On-Chip Peripheral Module Access Cycle (H'FFFC30 to H'FFFCA3) 7.2 Bus Arbitration (H8S/2268 Group Only) The Bus Controller has a bus arbiter that arbitrates bus master operations. There are two bus masters, the CPU and DTC, which perform read/write operations when they control the bus. 7.2.1 Order of Priority of the Bus Masters Each bus master requests the bus by means of a bus request signal. The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master making the request. If there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. The order of priority of the bus masters is as follows: (High) DTC > CPU (Low) Rev. 3.00, 08/03, page 101 of 612 7.2.2 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. The CPU is the lowest-priority bus master, and if a bus request is received from the DTC, the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of the bus is as follows: * The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between such operations. For details, refer to section 2.7, Bus States During Instruction Execution, in the H8S/2600 Series, H8S/2000 Series Programming Manual. * If the CPU is in sleep mode, it transfers the bus immediately. The DTC sends the bus arbiter a request for the bus when an activation request is generated. 7.2.3 Resets and the Bus Controller In a reset, the H8S/2268, including the bus controller, enters the reset state at that point, and an executing bus cycle is discontinued. Rev. 3.00, 08/03, page 102 of 612 Section 8 Data Transfer Controller (DTC) The H8S/2268 Group includes a data transfer controller (DTC), while the H8S/2264 Group does not. The DTC can be activated by an interrupt or software, to transfer data. Figure 8.1 shows a block diagram of the DTC. The DTC's register information is stored in the on-chip RAM. When the DTC is used, the RAME bit in SYSCR must be set to 1. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information. 8.1 Features * Transfer is possible over any number of channels * Three transfer modes Normal, repeat, and block transfer modes are available * One activation source can trigger a number of data transfers (chain transfer) * The direct specification of 16-Mbyte address space is possible * Activation by software is possible * Transfer can be set in byte or word units * A CPU interrupt can be requested for the interrupt that activated the DTC * Module stop mode can be set DTCH808B_000020020700 Rev. 3.00, 08/03, page 103 of 612 Internal address bus Internal data bus DTC mode registers A and B DTC transfer count registers A and B DTC source address register DTC destination address register DTC enable registers A to F and I DTC vector register Figure 8.1 Block Diagram of DTC Rev. 3.00, 08/03, page 104 of 612 Register information MRA MRB CRA CRB DAR SAR Control logic DTC service request CPU interrupt request [Legend] MRA, MRB: CRA, CRB: SAR: DAR: DTCERA to DTCERF and DTCERI: DTVECR: On-chip RAM DTC DTVECR Interrupt request DTCERA to DTCERF and DTCERI Interrupt controller 8.2 Register Descriptions The DTC has the following registers. * DTC mode register A (MRA) * DTC mode register B (MRB) * DTC source address register (SAR) * DTC destination address register (DAR) * DTC transfer count register A (CRA) * DTC transfer count register B (CRB) These six registers cannot be directly accessed from the CPU. When activated, the DTC reads a set of register information that is stored in on-chip RAM to the corresponding DTC registers and transfers data. After the data transfer, it writes a set of updated register information back to the RAM. * DTC enable registers (DTCER) * DTC vector register (DTVECR) Rev. 3.00, 08/03, page 105 of 612 8.2.1 DTC Mode Register A (MRA) MRA selects the DTC operating mode. Bit Bit Name Initial Value 7 SM1 Undefined Source Address Mode 1 and 0 6 SM0 Undefined These bits specify an SAR operation after a data transfer. R/W Description 0X: SAR is fixed 10: SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) 11: SAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) 5 DM1 Undefined Destination Address Mode 1 and 0 4 DM0 Undefined These bits specify a DAR operation after a data transfer. 0X: DAR is fixed 10: DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) 11: DAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) 3 MD1 Undefined DTC Mode 1 and 0 2 MD0 Undefined These bits specify the DTC transfer mode. 00: Normal mode 01: Repeat mode 10: Block transfer mode 11: Setting prohibited 1 DTS Undefined DTC Transfer Mode Select Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode. 0: Destination side is repeat area or block area 1: Source side is repeat area or block area 0 Sz Undefined DTC Data Transfer Size Specifies the size of data to be transferred. 0: Byte-size transfer 1: Word-size transfer [Legend] X: Don't care Rev. 3.00, 08/03, page 106 of 612 8.2.2 DTC Mode Register B (MRB) MRB is an 8-bit register that selects the DTC operating mode. Bit Bit Name Initial Value 7 CHNE Undefined R/W Description DTC Chain Transfer Enable This bit specifies a chain transfer. For details, refer to 8.5.4, Chain Transfer. In data transfer with CHNE set to 1, determination of the end of the specified number of transfers, clearing of the interrupt source flag, and clearing of DTCER, are not performed. 0: DTC data transfer completed (waiting for start) 1: DTC data transfer (reads new register information and transfers data) 6 DISEL Undefined DTC Interrupt Select This bit specifies whether CPU interrupt is disabled or enabled after a data transfer. 0: Interrupt request is issued to the CPU when the specified data transfer is completed. 1: DTC issues interrupt request to the CPU in every data transfer (DTC does not clear the interrupt request flag that is a cause of the activation). 5 to 0 Undefined Reserved These bits have no effect on DTC operation. The write value should always be 0. 8.2.3 DTC Source Address Register (SAR) SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 8.2.4 DTC Destination Address Register (DAR) DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address. Rev. 3.00, 08/03, page 107 of 612 8.2.5 DTC Transfer Count Register A (CRA) CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. In repeat mode or block transfer mode, the CRA is divided into two parts; the upper 8 bits (CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count reaches H'00. 8.2.6 DTC Transfer Count Register B (CRB) CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. 8.2.7 DTC Enable Register (DTCER) DTCER is comprised of seven registers; DTCERA to DTCERF and DTCERI, and is a register that specifies DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is shown in table 8.1. For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR for reading and writing. If all interrupts are masked, multiple activation sources can be set at one time (only at the initial setting) by writing data after executing a dummy read on the relevant register. Bit Bit Name Initial Value R/W Description 7 DTCE7 0 R/W DTC Activation Enable 6 DTCE6 0 R/W 5 DTCE5 0 R/W Setting this bit to 1 specifies a relevant interrupt source as a DTC activation source. 4 DTCE4 0 R/W [Clearing conditions] 3 DTCE3 0 R/W * 2 DTCE2 0 R/W When the DISEL bit is 1 and the data transfer has ended 1 DTCE1 0 R/W * When the specified number of transfers have ended 0 DTCE0 0 R/W * These bits are not cleared when the DISEL bit is 0 and the specified number of transfers have not been completed Rev. 3.00, 08/03, page 108 of 612 8.2.8 DTC Vector Register (DTVECR) DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. Bit Bit Name Initial Value R/W Description 7 SWDTE 0 R/W DTC Software Activation Enable Setting this bit to 1 activates DTC. Only a 1 can be written to this bit. [Clearing conditions] * When the DISEL bit is 0 and the specified number of transfers have not ended * When 0 s written to the DISEL bit after a softwareactivated data transfer end interrupt (SWDTEND) request has been sent to the CPU. * When the DISEL bit is 1 and data transfer has ended, the specified number of transfers have ended, or software-activated data transfer is in process, this bit will not be cleared. 6 DTVEC6 0 R/W DTC Software Activation Vectors 0 to 6 5 DTVEC5 0 R/W 4 DTVEC4 0 R/W These bits specify a vector number for DTC software activation. 3 DTVEC3 0 R/W 2 DTVEC2 0 R/W The vector address is expressed as H'0400 + (vector number x 2). For example, when DTVEC6 to DTVEC0 = H'10, the vector address is H'0420. 1 DTVEC1 0 R/W These bits are writable when SWDTE=0. 0 DTVEC0 0 R/W 8.3 Activation Sources The DTC operates when activated by an interrupt or by a write to DTVECR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source or corresponding DTCER bit is cleared. The activation source flag, in the case of RXI0, for example, is the RDRF flag of SCI_0. When an interrupt has been designated a DTC activation source, the existing CPU mask level and interrupt controller priorities have no effect. If there is more than one activation source at the same time, the DTC operates in accordance with the default priorities. Rev. 3.00, 08/03, page 109 of 612 Figure 8.2 shows a block diagram of activation source control. For details, see section 5, Interrupt Controller. Source flag cleared Clear controller Clear DTCER Clear request Select IRQ interrupt Interrupt request DTVECR DTC Selection circuit On-chip peripheral module CPU Interrupt controller Interrupt mask Figure 8.2 Block Diagram of DTC Activation Source Control 8.4 Location of Register Information and DTC Vector Table Locate the register information in the on-chip RAM (addresses: H'FFEBC0 to H'FFEFBF). Register information should be located at an address that is a multiple of four within the range. Locating the register information in address space is shown in figure 8.3. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information. In the case of chain transfer, register information should be located in consecutive areas as shown in figure 8.3, and the register information start address should be located at the vector address corresponding to the interrupt source. Figure 8.4 shows the correspondence between DTC vector address and register information. The DTC reads the start address of the register information from the vector address set for each activation source, and then reads the register information from that start address. When the DTC is activated by software, the vector address is obtained from: H'0400 + (DTVECR[6:0] x 2). For example, if DTVECR is H'10, the vector address is H'0420. The configuration of the vector address is the same in both normal* and advanced modes, a 2-byte unit being used in both cases. These two bytes specify the lower bits of the register information start address. Note: * Normal mode cannot be used in this LSI. Rev. 3.00, 08/03, page 110 of 612 Lower address 0 Register information start address 1 2 MRA SAR MRB DAR Register information CRB CRA Chain transfer 3 MRA SAR MRB DAR Register information for 2nd transfer in chain transfer CRB CRA 4 bytes Figure 8.3 The Location of DTC Register Information in Address Space DTC vector address Register information start address Register information Chain transfer Figure 8.4 Correspondence between DTC Vector Address and Register Information Rev. 3.00, 08/03, page 111 of 612 Table 8.1 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Interrupt Source Origin of Interrupt Source DTC Vector Number Vector Address Software Write to DTVECR DTVECR H'0400 + vector number x 2 External pin IRQ0 16 H'0420 DTCEA7 IRQ1 17 H'0422 DTCEA6 IRQ3 19 H'0426 DTCEA4 IRQ4 20 H'0428 DTCEA3 IRQ5 21 H'042A DTCEA2 ADI 28 (A/D conversion end) H'0438 DTCEB6 A/D TPU Channel 0 TPU Channel 1 TPU Channel 2 8-bit timer channel 0 8-bit timer channel 1 SCI channel 0 SCI channel 1 8-bit timer channel 2 8-bit timer channel 3 IIC channel 0 (optional) DTCE* TGI0A 32 H'0440 DTCEB5 TGI0B 33 H'0442 DTCEB4 TGI0C 34 H'0444 DTCEB3 TGI0D 35 H'0446 DTCEB2 TGI1A 40 H'0450 DTCEB1 TGI1B 41 H'0452 DTCEB0 TGI2A 44 H'0458 DTCEC7 TGI2B 45 H'045A DTCEC6 CMIA0 64 H'0480 DTCED3 CMIB0 65 H'0482 DTCED2 CMIA1 68 H'0488 DTCED1 CMIB1 69 H'048A DTCED0 RXI0 81 H'04A2 DTCEE3 TXI0 82 H'04A4 DTCEE2 RXI1 85 H'04AA DTCEE1 TXI1 86 H'04AC DTCEE0 CMIA2 92 H'04B8 DTCEF5 CMIB2 93 H'04BA DTCEF4 CMIA3 96 H'04C0 DTCEF3 CMIB3 97 H'04C2 DTCEF2 IICI0 100 H'04C8 DTCEF1 Rev. 3.00, 08/03, page 112 of 612 Priority High Low Interrupt Source Origin of Interrupt Source DTC Vector Number Vector Address DTCE* Priority IIC channel 1 (optional) IICI1 102 H'04CC DTCEF0 High SCI channel 2 RXI2 121 H'04F2 DTCEI7 TXI2 122 H'04F4 DTCEI6 Note: 8.5 * Low DTCE bits with no corresponding interrupt are reserved, and should be written with 0. Operation Register information is stored in on-chip RAM. When activated, the DTC reads register information in on-chip RAM and transfers data. After the data transfer, the DTC writes updated register information back to the memory. The pre-storage of register information in memory makes it possible to transfer data over any required number of channels. The transfer mode can be specified as normal, repeat, and block transfer mode. Setting the CHNE bit in MRB to 1 makes it possible to perform a number of transfers with a single activation source (chain transfer). The 24-bit SAR designates the DTC transfer source address, and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed depending on its register information. Figure 8.5 shows the flowchart of DTC operation. Rev. 3.00, 08/03, page 113 of 612 Start Read DTC vector Next transfer Read register infomation Data transfer Write register information CHNE=1 Yes No Transfer Counter=0 or DISEL=1 Yes No Clear an activeation flag Clear DTCER End Interupt exception handling Figure 8.5 Flowchart of DTC Operation 8.5.1 Normal Mode In normal mode, one operation transfers one byte or one word of data. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have been completed, a CPU interrupt can be requested. Table 8.2 lists the register information in normal mode. Figure 8.6 shows the memory mapping in normal mode. Rev. 3.00, 08/03, page 114 of 612 Table 8.2 Register Information in Normal Mode Name Abbreviation Function DTC source address register SAR Designates source address DTC destination address register DAR Designates destination address DTC transfer count register A CRA Designates transfer count DTC transfer count register B CRB Not used SAR DAR Transfer Figure 8.6 Memory Mapping in Normal Mode 8.5.2 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated. In repeat mode the transfer counter value does not reach H'00, and therefore CPU interrupts cannot be requested when DISEL = 0. Table 8.3 lists the register information in repeat mode. Figure 8.7 shows the memory mapping in repeat mode. Rev. 3.00, 08/03, page 115 of 612 Table 8.3 Register Information in Repeat Mode Name Abbreviation Function DTC source address register SAR Designates source address DTC destination address register DAR Designates destination address DTC transfer count register AH CRAH Holds number of transfers DTC transfer count register AL CRAL Designates transfer count DTC transfer count register B CRB Not used SAR or DAR Repeat area Transfer DAR or SAR Figure 8.7 Memory Mapping in Repeat Mode 8.5.3 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. The block size can be between 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored. The other address register is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have been completed, a CPU interrupt is requested. Table 8.4 lists the register information in block transfer mode. Figure 8.8 shows the memory mapping in block transfer mode. Rev. 3.00, 08/03, page 116 of 612 Table 8.4 Register Information in Block Transfer Mode Name Abbreviation Function DTC source address register SAR Designates source address DTC destination address register DAR Designates destination address DTC transfer count register AH CRAH Holds block size DTC transfer count register AL CRAL Designates block size count DTC transfer count register B CRB Transfer count First block SAR or DAR Block area Transfer DAR or SAR Nth block Figure 8.8 Memory Mapping in Block Transfer Mode 8.5.4 Chain Transfer Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 8.9 shows the memory map for chain transfer. When activated, the DTC reads the register information start address stored at the vector address, and then reads the first register information at that start address. After the data transfer, the CHNE bit will be tested. When it has been set to 1, DTC reads the next register information located in a Rev. 3.00, 08/03, page 117 of 612 consecutive area and performs the data transfer. These sequences are repeated until the CHNE bit is cleared to 0. In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt source flag for the activation source is not affected. Source Destination Register information CHNE=1 DTC vector address Register information start address Register information CHNE=0 Source Destination Figure 8.9 Chain Transfer Operation 8.5.5 Interrupts An interrupt request is issued to the CPU when the DTC has completed the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control. In the case of software activation, a software-activated data transfer end interrupt (SWDTEND) is generated. Rev. 3.00, 08/03, page 118 of 612 When the DISEL bit is 1 and one data transfer has been completed, or the specified number of transfers have been completed, after data transfer ends the SWDTE bit is held at 1 and an SWDTEND interrupt is generated. The interrupt handling routine will then clear the SWDTE bit to 0. When the DTC is activated by software, an SWDTEND interrupt is not generated during a data transfer wait or during data transfer even if the SWDTE bit is set to 1. 8.5.6 Operation Timing Figure 8.10 to 8.12 show the DTC operation timings. DTC activation request DTC request Data transfer Vector read Address Read Write Transfer information read Transfer information write Figure 8.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode) DTC activation request DTC request Data transfer Vector read Address Read Write Read Write Transfer information read Transfer information write Figure 8.11 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2) Rev. 3.00, 08/03, page 119 of 612 DTC activation request DTC request Data transfer Data transfer Read Write Read Write Vector read Address Transfer information read Transfer information write Transfer information read Transfer information write Figure 8.12 DTC Operation Timing (Example of Chain Transfer) 8.5.7 Number of DTC Execution States Table 8.5 lists execution status for a single DTC data transfer, and table 8.6 shows the number of states required for each execution status. Table 8.5 DTC Execution Status Mode Vector Read I Register Information Read/Write Data Read J K Data Write L Internal Operations M Normal 1 6 1 1 3 Repeat 1 6 1 1 3 Block transfer 1 6 N N 3 [Legend] N: Block size (initial setting of CRAH and CRAL) Rev. 3.00, 08/03, page 120 of 612 Table 8.6 Number of States Required for Each Execution Status Object to be Accessed OnChip RAM OnChip ROM Bus width 32 16 Internal I/O Registers 8 16 External Devices* 8 16 Access states 1 1 2 2 2 3 2 3 Execution Vector read SI Status 1 4 6+ 2m 2 3+m Register information read/write SJ 1 Byte data read SK 1 1 2 2 2 3+m 2 3+m Word data read SK 1 1 4 2 4 6+ 2m 2 3+m Byte data write SL 1 1 2 2 2 3+m 2 3+m Word data write SL 1 1 4 2 4 6+ 2m 3+m Internal operation SM 1 2 [Legend] m: The number of wait states for accessing external devices. Note: * Cannot be used in this LSI. The number of execution states is calculated from using the formula below. Note that is the sum of all transfers activated by one activation event (the number in which the CHNE bit is set to 1, plus 1). Number of execution states = I * SI + (J * SJ + K * SK + L * SL) + M * SM For example, when the DTC vector address table is located in the on-chip ROM, normal mode is set, and data is transferred from on-chip ROM to an internal I/O register, then the time required for the DTC operation is 13 states. The time from activation to the end of the data write is 10 states. Rev. 3.00, 08/03, page 121 of 612 8.6 Procedures for Using DTC 8.6.1 Activation by Interrupt The procedure for using the DTC with interrupt activation is as follows: 1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in on-chip RAM. 2. Set the start address of the register information in the DTC vector address. 3. Set the corresponding bit in DTCER to 1. 4. Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC is activated when an interrupt used as an activation source is generated. 5. After one data transfer has been completed, or after the specified number of data transfers have been completed, the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to continue transferring data, set the DTCE bit to 1. 8.6.2 Activation by Software The procedure for using the DTC with software activation is as follows: 1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in on-chip RAM. 2. Set the start address of the register information in the DTC vector address. 3. Check that the SWDTE bit is 0. 4. Write 1 to SWDTE bit and the vector number to DTVECR. 5. Check the vector number written to DTVECR. 6. After one data transfer has been completed, if the DISEL bit is 0 and a CPU interrupt is not requested, the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit to 1. When the DISEL bit is 1, or after the specified number of data transfers have been completed, the SWDTE bit is held at 1 and a CPU interrupt is requested. 8.7 Examples of Use of DTC 8.7.1 Normal Mode An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. 1. Set MRA to a fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the SCI RDR address in SAR, the start address of the RAM area where the data will be received in DAR, and 128 (H'0080) in CRA. CRB can be set to any value. 2. Set the start address of the register information at the DTC vector address. Rev. 3.00, 08/03, page 122 of 612 3. Set the corresponding bit in DTCER to 1. 4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception complete (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts. 5. Each time the reception of one byte of data has been completed on the SCI, the RDRF flag in SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is automatically cleared to 0. 6. When CRA becomes 0 after the 128 data transfers have been completed, the RDRF flag is held at 1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt handling routine will perform wrap-up processing. 8.7.2 Software Activation An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. 1. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE = 0). Set the transfer source address (H'1000) in SAR, the destination address (H'2000) in DAR, and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB. 2. Set the start address of the register information at the DTC vector address (H'04C0). 3. Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated by software. 4. Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0. 5. Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this indicates that the write failed. This is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. To activate this transfer, go back to step 3. 6. If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred. 7. After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear the SWDTE bit to 0 and perform other wrap-up processing. Rev. 3.00, 08/03, page 123 of 612 8.8 Usage Notes 8.8.1 Module Stop Mode Setting DTC operation can be disabled or enabled using the module stop control register. The initial setting is for DTC operation to be enabled. Register access is disabled by setting module stop mode. Module stop mode cannot be set during DTC operation. For details, refer to section 22, Power-Down Modes. 8.8.2 On-Chip RAM The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. 8.8.3 DTCE Bit Setting For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts are masked, multiple activation sources can be set at one time (only at the initial setting) by writing data after executing a dummy read on the relevant register. Rev. 3.00, 08/03, page 124 of 612 Section 9 I/O Ports The H8S/2268 Group has ten I/O ports (ports 1, 3, 7, F, H, and J to N), and two input-only port (ports 4 and 9). The H8S/2264 Group has eight I/O ports (ports 1, 3, 7, F, H, and J to L), and two input-only port (ports 4 and 9). Table 9.1 summarizes the port functions. The pins of each port also have other functions such as input/output or interrupt input pins of on-chip peripheral modules. Each I/O port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, and a port register (PORT) used to read the pin states. The input-only ports do not have DDR and DR registers. Port J has a built-in input pull-up MOS function and an input pull-up MOS control register (PCR) to control the on/off state of input pull-up MOS. Port 3 includes an open-drain control register (ODR) that controls the on/off state of the output buffer PMOS. All the I/O ports can drive a single TTL load and a 30 pF capacitive load. The P34 and P35 pins on port 3 are NMOS push pull outputs. Pins IRQ and WKP are Schmitt-trigger inputs. Pins PH0 to PH3 and ports J to N in the H8S/2268 Group and pins PH0 to PH3 and ports J to L in the H8S/2264 Group are shared as LCD segment pins and common pins. They can be selected on an 8-bit basis. Rev. 3.00, 08/03, page 125 of 612 Table 9.1 H8S/2268 Group Port Functions (1) Port and Other Functions Name Port Description Port 1 P17/TIOCB2/TCLKD General I/O port also functioning as TPU I/O P16/TIOCA2/IRQ1 pins and interrupt input P15/TIOCB1/TCLKC pins P14/TIOCA1/IRQ0 Input/Output and Output Type P13/TIOCD0/TCLKB P12/TIOCC0/TCLKA P11/TIOCB0 P10/TIOCA0 Port 3 General I/O port also functioning as SCI_0 2 and SCI_1 I/O pins, I C bus interface I/O pins, and interrupt input pins P35/SCK1/SCL0/IRQ5 P34/RxD1/SDA0 P33/TxD1/SDA0 P32/SCK0/SDA1/IRQ4 P31/RxD0 P30/TxD0 Port 4 General input port also P47/AN7 functioning as A/D P46/AN6 converter analog input P45/AN5 pins P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0 Port 7 General I/O port also P77/TxD2 functioning as SCI_2 P76/RxD2 I/O pins and 8-bit timer P75/TMO3/SCK2 I/O pins P74/TMO2 P73/TMO1 P72/TMO0 P71/TMRI23/TMCI23 P70/TMRI01/TMCI01 Rev. 3.00, 08/03, page 126 of 612 Specifiable of open drain output Port and Other Functions Name Port Description Port 9 General input port also P97/AN9/DA1 functioning as A/D P96/AN8/DA0 converter analog input and D/A converter analog output pins Port F General I/O port also PF3/ADTRG/IRQ3 functioning as interrupt input pins and an A/D converter input pins Port H General input port PH7 General I/O port also functioning as LCD common output pins PH3/COM4 Input/Output and Output Type PH2/COM3 PH1/COM2 PH0/COM1 Port J General I/O port also functioning as wakeup input pins and LCD segment output pins PJ7/WKP7/SEG8 Built-in input pull-up MOS PJ6/WKP6/SEG7 PJ5/WKP5/SEG6 PJ4/WKP4/SEG5 PJ3/WKP3/SEG4 PJ2/WKP2/SEG3 PJ1/WKP1/SEG2 PJ0/WKP0/SEG1 Port K General I/O port also functioning as LCD segment output pins PK7/SEG16 PK6/SEG15 PK5/SEG14 PK4/SEG13 PK3/SEG12 PK2/SEG11 PK1/SEG10 PK0/SEG9 Rev. 3.00, 08/03, page 127 of 612 Port Description Port L General I/O port also functioning as LCD segment output pins Port and Other Functions Name PL7/SEG24 PL6/SEG23 PL5/SEG22 PL4/SEG21 PL3/SEG20 PL2/SEG19 PL1/SEG18 PL0/SEG17 Port M General I/O port also functioning as LCD segment output pins PM7/SEG32 PM6/SEG31 PM5/SEG30 PM4/SEG29 PM3/SEG28 PM2/SEG27 PM1/SEG26 PM0/SEG25 Port N General I/O port also functioning as LCD segment output pins PN7/SEG40 PN6/SEG39 PN5/SEG38 PN4/SEG37 PN3/SEG36 PN2/SEG35 PN1/SEG34 PN0/SEG33 Rev. 3.00, 08/03, page 128 of 612 Input/Output and Output Type Table 9.1 H8S/2264 Group Port Functions (2) Port and Other Functions Name Port Description Port 1 P17/TIOCB2 General I/O port also functioning as TPU I/O P16/TIOCA2/IRQ1 pins and interrupt input P15/TIOCB1/TCLKC pins P14/TIOCA1/IRQ0 Input/Output and Output Type P13/TCLKB P12/TCLKA P11 P10 Port 3 General I/O port also functioning as SCI_0 2 and SCI_1 I/O pins, I C bus interface I/O pins, and interrupt input pins P35/SCK1/SCL0 P34/RxD1/SDA0 Specifiable of open drain output P33/TxD1 P32/SCK0/IRQ4 P31/RxD0 P30/TxD0 Port 4 General input port also P47/AN7 functioning as A/D P46/AN6 converter analog input P45/AN5 pins P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0 Port 7 General I/O port also P77/TxD2 functioning as SCI_2 P76/RxD2 I/O pins and 8-bit timer P75/SCK2 I/O pins P74 P73/TMO1 P72/TMO0 P71 P70/TMRI01/TMCI01 Port 9 General input port also P97/AN9 functioning as A/D P96/AN8 converter analog inputs Rev. 3.00, 08/03, page 129 of 612 Port and Other Functions Name Port Description Port F General I/O port also PF3/ADTRG/IRQ3 functioning as interrupt input pins and an A/D converter input pins Port H General input port PH7 General I/O port also functioning as LCD common output pins PH3/COM4 Input/Output and Output Type PH2/COM3 PH1/COM2 PH0/COM1 Port J General I/O port also functioning as wakeup input pins and LCD segment output pins PJ7/WKP7/SEG8 PJ6/WKP6/SEG7 PJ5/WKP5/SEG6 PJ4/WKP4/SEG5 PJ3/WKP3/SEG4 PJ2/WKP2/SEG3 PJ1/WKP1/SEG2 PJ0/WKP0/SEG1 Port K General I/O port also functioning as LCD segment output pins PK7/SEG16 PK6/SEG15 PK5/SEG14 PK4/SEG13 PK3/SEG12 PK2/SEG11 PK1/SEG10 PK0/SEG9 Port L General I/O port also functioning as LCD segment output pins PL7/SEG24 PL6/SEG23 PL5/SEG22 PL4/SEG21 PL3/SEG20 PL2/SEG19 PL1/SEG18 PL0/SEG17 Rev. 3.00, 08/03, page 130 of 612 Built-in input pull-up MOS 9.1 Port 1 Port 1 is an 8-bit I/O port and has the following registers. * Port 1 data direction register (P1DDR) * Port 1 data register (P1DR) * Port 1 register (PORT1) 9.1.1 Port 1 Data Direction Register (P1DDR) P1DDR specifies input or output of the port 1 pins using the individual bits. P1DDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7 P17DDR 0 W 6 P16DDR 0 W 5 P15DDR 0 W When a pin is specified as a general purpose I/O port, setting this bit to 1 makes the corresponding port 1 pin an output pin. Clearing this bit to 0 makes the pin an input pin. 4 P14DDR 0 W 3 P13DDR 0 W 2 P12DDR 0 W 1 P11DDR 0 W 0 P10DDR 0 W 9.1.2 Port 1 Data Register (P1DR) P1DR stores output data for port 1 pins. Bit Bit Name Initial Value R/W Description 7 P17DR 0 R/W 6 P16DR 0 R/W Output data for a pin is stored when the pin is specified as a general purpose output port. 5 P15DR 0 R/W 4 P14DR 0 R/W 3 P13DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W 0 P10DR 0 R/W Rev. 3.00, 08/03, page 131 of 612 9.1.3 Port 1 Register (PORT1) PORT1 shows the pin states. This register cannot be modified. Bit Bit Name Initial Value R/W Description 7 P17 * R 6 P16 * R 5 P15 * R If a port 1 read is performed while P1DDR bits are set to 1, the P1DR values are read. If a port 1 read is performed while P1DDR bits are cleared to 0, the pin states are read. 4 P14 * R 3 P13 * R 2 P12 * R 1 P11 * R 0 P10 * R Note: * 9.1.4 Determined by the states of pins P17 to P10. Pin Functions Port 1 pins also function as TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD*, TIOCA0*, TIOCB0*, TIOCC0*, TIOCD0*, TIOCA1, TIOCB1, TIOCA2, and TIOCB2) and external interrupt input pins (IRQ0 and IRQ1). Port 1 pin functions are shown below. For the setting of the TPU channel, see section 10, 16-Bit Timer Pulse Unit (TPU). Note: * Supported only by the H8S/2268 Group. * P17/TIOCB2/TCLKD* 3 The pin function is switched as shown below according to the combination of the TPU channel 2 setting, TPSC2 to TPS0 bits in TCR0*, and the P17DDR bit. TPU Channel 2 Setting Output 0 1 TIOCB2 output P17 input P17 output P17DDR Pin function Input or Initial Value 1 TIOCB2 input* 2 3 TCLKD input* * Notes: 1. This pin functions as TIOCB2 input when TPU channel 2 timer operating mode is set to 3 normal operation or phase counting mode* and IOB3 in TIOR_2 is set to 1. 2. In the H8S/2268 Group, this pin functions as TCLKD input when TPSC2 to TPSC0 in 3 TCR0 are set to 111 or when channel 2 is set to phase counting mode* . 3. Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 132 of 612 * P16/TIOCA2/IRQ1 The pin function is switched as shown below according to the combination of the TPU channel 2 setting and the P16DDR bit. TPU Channel 2 Setting P16DDR Pin function Output Input or Initial Value 0 TIOCA2 output P16 input 1 P16 output 1 TIOCA2 input* IRQ1 input* 2 Notes: 1. This pin functions as TIOCA2 input when TPU channel 2 timer operating mode is set to 3 normal operation or phase counting mode* and IOA3 in TIOR_2 is 1. 2. When this pin is used as an external interrupt pin, do not specify other functions. 3. Supported only by the H8S/2268 Group. * P15/TIOCB1/TCLKC The pin function is switched as shown below according to the combination of the TPU channel 1 setting, TPSC2 to TPSC0 bits in TCR0*3 and TCR2, and the P15DDR bit. TPU Channel 1 Setting P15DDR Pin function Output Input or Initial Value 0 1 TIOCB1 output P15 input P15 output 1 TIOCB1 input* 2 TCLKC input* Notes: 1. This pin functions as TIOCB1 input when TPU channel 1 timer operating mode is set to 3 normal operation or phase counting mode* and IOB3 to IOB0 in TIOR_1 are set to10xx. 3 2. This pin functions as TCLKC inputs when TPSC2 to TPSC0 in TCR0* or TCR2 are set 3 to 110 or TCLKC input when channel 2 is set to phase counting mode* . 3. Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 133 of 612 * P14/TIOCA1/IRQ0 The pin function is switched as shown below according to the combination of the TPU channel 1 setting and the P14DDR bit. TPU Channel 1 Setting Output 0 TIOCA1 output P14 input P14DDR Pin function Input or Initial Value 1 P14 output 1 TIOCA1 input* IRQ0 input* 2 Notes: 1. This pin functions as TIOCA1 input when TPU channel 1 timer operating mode is set to 3 normal operation or phase counting mode* and IOA3 to IOA0 in TIOR_1 are set to 10xx. 2. When this pin is used as an external interrupt pin, do not specify other functions. 3. Supported only by the H8S/2268 Group. * P13/TIOCD0* /TCLKB 3 The pin function is switched as shown below according to the combination of the TPU channel 3 3 0* setting, TPSC2 to TPSC0 bits in TCR0* , TCR1 and TCR2, and the P13DDR bit. 3 TPU Channel 0 Setting* Output P13DDR Pin function Input or Initial Value 0 3 TIOCD0 output* 1 P13 input P13 output 1 3 TIOCD0 input* * 2 TCLKB input* Notes: 1. In the H8S/2268 Group, this pin functions as TIOCD0 input when TPU channel 0 timer operating mode is set to normal operation and IOD3 to IOD0 in TIORL_0 are set to 10xx. 2. This pin functions as TCLKB input when TPSC2 to TPSC0 are set to 101 in any of 3 TCR0* , TCR1 and TCR2. TCLKB input, or when channel 1 is set to phase counting 3 mode* . 3. Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 134 of 612 * P12/TIOCC0* /TCLKA 3 The pin function is switched as shown below according to the combination of the TPU channel 3 3 0* setting, TPSC2 to TPSC0 bits in TCR2, TCR1 and TCR0* , and the P12DDR bit. 3 TPU Channel 0 Setting* Output Input or Initial Value P12DDR 0 3 Pin function TIOCC0 output* 1 P12 input P12 output 1 3 TIOCC0 input* * 2 TCLKA input* Notes: 1. In the H8S/2268 Group, TIOCC0 input when TPU channel 0 timer operating mode is set to normal operation and IOC3 to IOC0 in TIORL_0 are set to 10xx. 2. This functions as TCLKA input when TPSC2 to TPSC0 are set to 100 in any of TCR2, 3 3 TCR1 and TCR0* or when channel 1 is set to phase counting mode* . 3. Supported only by the H8S/2268 Group. * P11/TIOCB0* 2 The pin function is switched as shown below according to the combination of the TPU channel 2 0* setting and the P11DDR bit. 2 TPU Channel 0 Setting* Output Input or Initial Value P11DDR 0 2 Pin function TIOCB0 output* 1 P11 input P11 output 1 2 TIOCB0 input* * Notes: 1. In the H8S/2268 Group, this pin functions as TIOCB0 input when TPU channel 0 timer operating mode is set to normal operation and IOB3 to IOB0 in TIORH_0 are set to 10xx. 2. Supported only by the H8S/2268 Group. * P10/TIOCA0* 2 The pin function is switched as shown below according to the combination of the TPU channel 2 0* setting and the P10DDR bit. 2 TPU Channel 0 Setting* P10DDR Pin function Output Input or Initial Value 0 2 TIOCA0 output* 1 P10 input P10 output 1 2 TIOCA0 input* * Notes: 1. In the H8S/2268 Group, this pin functions as TIOCA0 input when TPU channel 0 timer operating mode is set to normal operation and IOA3 to IOA0 in TIORH_0 are set to 10xx. 2. Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 135 of 612 9.2 Port 3 Port 3 is a 6-bit I/O port and has the following registers. * Port 3 data direction register (P3DDR) * Port 3 data register (P3DR) * Port 3 register (PORT3) * Port 3 open drain control register (P3ODR) 9.2.1 Port 3 Data Direction Register (P3DDR) P3DDR specifies input or output of the port 3 pins using the individual bits. P3DDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value 7, 6 Undefined R/W Description Reserved These bits are always read as undefined value and cannot be modified. 5 P35DDR 0 W 4 P34DDR 0 W 3 P33DDR 0 W 2 P32DDR 0 W 1 P31DDR 0 W 0 P30DDR 0 W Rev. 3.00, 08/03, page 136 of 612 When a pin is specified as a general purpose I/O port, setting this bit to 1 makes the corresponding port 3 pin an output port. Clearing this bit to 0 makes the pin an input port. 9.2.2 Port 3 Data Register (P3DR) P3DR stores output data for port 3 pins. Bit Bit Name Initial Value 7, 6 Undefined R/W Description Reserved These bits are always read as undefined value and cannot be modified. 5 P35DR 0 R/W 4 P34DR 0 R/W 3 P33DR 0 R/W 2 P32DR 0 R/W 1 P31DR 0 R/W 0 P30DR 0 R/W 9.2.3 Port 3 Register (PORT3) Output data for a pin is stored when the pin is specified as a general purpose output port. PORT3 shows the pin states. This register cannot be modified. Bit Bit Name Initial Value 7, 6 Undefined R/W Description Reserved These bits are always read as undefined value and cannot be modified. 5 P35 * R 4 P34 * R 3 P33 * R 2 P32 * R 1 P31 * R P30 * R 0 Note: * If a port 3 read is performed while P3DDR bits are set to 1, the P3DR values are read. If a port 3 read is performed while P3DDR bits are cleared to 0, the pin states are read. Determined by the states of pins P35 to P30. Rev. 3.00, 08/03, page 137 of 612 9.2.4 Port 3 Open Drain Control Register (P3ODR) P3ODR controls on/off state of the PMOS for port 3 pins. Bit Bit Name Initial Value 7, 6 Undefined R/W Description Reserved These bits are always read as undefined value and cannot be modified. 5 P35ODR 0 R/W 4 P34ODR 0 R/W 3 P33ODR 0 R/W 2 P32ODR 0 R/W 1 P31ODR 0 R/W 0 P30ODR 0 R/W 9.2.5 Pin Functions When each of P33ODR to P30ODR bits is set to 1, the corresponding pins P33 to P30 function as NMOS open drain outputs. When cleared to 0, the corresponding pins function as CMOS outputs. When each of P35ODR and P34ODR bits is set to 1, the corresponding pins P35 and P34 function as NMOS open drain outputs. When they are cleared to 0, the corresponding pins function as NMOS push pull outputs. The port 3 pins also function as SCI I/O input pins (TxD0, RxD0, SCK0, TxD1, RxD1, and SCK1), I2C bus interface I/O pins (SCL0, SDA0, SCL1*, and SDA1*), and as external interrupt input pins (IRQ4 and IRQ5*). As shown in figure 9.1, when the pins P34, P35, SCL0 or SDA0 type open drain output is used, a bus line is not affected even if the power supply for this LSI fails. Use (a) type open drain output when using a bus line having a state in which the power is not supplied to this LSI. PMOS Off NMOS Off 1 0 Output Input Output Input (a) Open drain output type for P34, P35, SCLO and SDA0 pins (b) Open drain output type for P33 to P30, SCL1* and SDA1* pins Figure 9.1 Types of Open Drain Outputs Note: * Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 138 of 612 The functions of port 3 pins are shown below. * P35/SCK1/SCL0/IRQ5* 2 The pin function is switched as shown below according to the combination of the ICE bit in ICCR_0 of IIC_0, C/A bit in SMR of SCI_1, CKE0 and CKE1 bits in SCR and the P35DDR bit. ICE 0 CKE1 1 0 C/A 1 0 0 0 P35DDR 0 Pin functions 1 P35 input pin P35 output pin 0 1 0 CKE0 1 SCK1 output SCK1 output SCK1 input pin pin pin SCL0 I/O pin IRQ5 Input * * 1 2 Notes: 1. When this pin is used as an external interrupt pin, do not specify other functions. 2. Supported only by the H8S/2268 Group. * P34/RxD1/SDA0 The pin function is switched as shown below according to the combination of the ICE bit in ICCR_0 of IIC_0, RXD1S bit in SCKCR2*, RE bit in SCR of SCI_1 and the P34DDR bit. ICE 0 RXD1S* 0 RE 0 P34DDR 0 Pin functions Note: * 1 1 1 P34 input pin P34 output pin 1 0 1 RxD1 input pin P34 input pin P34 output pin SDAO I/O pin Supported only by the H8S/2264 Group. Rev. 3.00, 08/03, page 139 of 612 * P33/TxD1/SCL1* The pin function is switched as shown below according to the combination of the ICE bit* in ICCR_1 of IIC_1, TE bit in SCR of SCI_1 and the P33DDR bit. ICE* 0 TE 1 0 0 1 P33 input pin P33 output pin TxD1 output pin SCL1 I/O pin* P33DDR Pin functions Note: * 1 Supported only by the H8S/2268 Group. * P32/SCK0/SDA1* /IRQ4 2 2 The pin function is switched as shown below according to the combination of the ICE bit* in ICCR_1 of IIC_1, C/A bit in SMR of SCI_0, CKE0 and CKE1 bits in SCR and the P32DDR bit. 2 ICE* 0 CKE1 0 C/A Pin functions 1 0 1 0 1 0 0 CKE0 P32DDR 1 0 0 1 P32 input pin P32 output pin SCK0 output SCK0 output SCK0 input pin pin pin SDA1 I/O 2 pin* IRQ4 Input * 1 Notes: 1. When this pin is used as an external interrupt pin, do not specify other functions. 2. Supported only by the H8S/2268 Group. * P31/RxD0 The pin function is switched as shown below according to the combination of the RE bit in SCR of SCI_0 and the P31DDR bit. RE P31DDR Pin functions 0 1 0 1 P31 input pin P31 output pin RxD0 input pin Rev. 3.00, 08/03, page 140 of 612 * P30/TxD0 The pin function is switched as shown below according to the combination of the TE bit in SCR of SCI_0 and the P30DDR bit. TE 0 0 1 P30 input pin P30 output pin TxD0 output pin P30DDR Pin functions 9.3 1 Port 4 Port 4 is an 8-bit input-only port and has the following register. * Port 4 register (PORT4) 9.3.1 Port 4 Register (PORT4) PORT4 shows port 4 pin states. This register cannot be modified. Bit Bit Name Initial Value R/W Description 7 P47 * R 6 P46 * R The pin states are always read when a port 4 read is performed. 5 P45 * R 4 P44 * R 3 P43 * R 2 P42 * R 1 P41 * R 0 P40 * R Note: 9.3.2 * Determined by the states of pins P47 to P40. Pin Functions Port 4 pins also function as A/D converter analog input pins (AN0 to AN7). Rev. 3.00, 08/03, page 141 of 612 9.4 Port 7 Port 7 is an 8-bit I/O port and has the following registers. * Port 7 data direction register (P7DDR) * Port 7 data register (P7DR) * Port 7 register (PORT7) 9.4.1 Port 7 Data Direction Register (P7DDR) P7DDR specifies input or output of the port 7 pins using the individual bits. P7DDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7 P77DDR 0 W 6 P76DDR 0 W 5 P75DDR 0 W When a pin is specified as a general purpose I/O port, setting this bit to 1 makes the corresponding port 7 pin an output pin. Clearing this bit to 0 makes the pin an input pin. 4 P74DDR 0 W 3 P73DDR 0 W 2 P72DDR 0 W 1 P71DDR 0 W 0 P70DDR 0 W 9.4.2 Port 7 Data Register (P7DR) P7DR stores output data for port 7 pins. Bit Bit Name Initial Value R/W Description 7 P77DR 0 R/W 6 P76DR 0 R/W Output data for a pin is stored when the pin is specified as a general purpose output port. 5 P75DR 0 R/W 4 P74DR 0 R/W 3 P73DR 0 R/W 2 P72DR 0 R/W 1 P71DR 0 R/W 0 P70DR 0 R/W Rev. 3.00, 08/03, page 142 of 612 9.4.3 Port 7 Register (PORT7) PORT7 shows the pin states. This register cannot be modified. Bit Bit Name Initial Value R/W Description 7 P77 * R 6 P76 * R 5 P75 * R If a port 1 read is performed while P7DDR bits are set to 1, the P7DR values are read. If a port 1 read is performed while P7DDR bits are cleared to 0, the pin states are read. 4 P74 * R 3 P73 * R 2 P72 * R 1 P71 * R 0 P70 * R Note: * 9.4.4 Determined by the states of pins P77 to P70. Pin Functions Port 7 pins also function as the 8-bit timer I/O pins (TMRI01, TMCI01, TMRI23*, TMCI23*, TMO0, TMO1, TMO2*, and TMO3*) and SCI I/O pins (SCK2, RxD2 and TxD2). Port 7 pin functions are shown below. Note: * Supported only by the H8S/2268 Group. * P77/TxD2 The pin function is switched as shown below according to the combination of the TE bit in SCR of SCI_2 and the P77DDR bit. TE 0 P77DDR Pin functions 1 0 1 P77 input pin P77 output pin TxD2 output pin * P76/RxD2 The pin function is switched as shown below according to the combination of the RE bit in SCR of SCI_2 and the P76DDR bit. RE P76DDR Pin functions 0 1 0 1 P76 input pin P76 output pin RxD2 Input pin Rev. 3.00, 08/03, page 143 of 612 * P75/TMO3*/SCK2 The pin function is switched as shown below according to the combination of the OS3 to OS0 bits in TCSR_3* of the 8-bit timer, the C/A bit in SMR of SCI_2, the CKE0 and CKE1 bits in SCR and the P75DDR bit. OS3 to OS0* All bits are 0 CKE1 1 1 1 0 C/A 0 CKE0 0 P75DDR 0 Pin functions Note: Any bit is 1 * 1 P75 input pin P75 output pin SCK2 output SCK2 output SCK2 input TMO3 pin pin pin output pin* Supported only by the H8S/2268 Group. * P74/TMO2* The pin function is switched as shown below according to the combination of the OS3 to OS0 bits in TCSR_2* of the 8-bit timer and the P74DDR bit. OS3 to OS0* P74DDR Pin functions Note: * All bits are 0 Any bit is 1 0 1 P74 input pin P74 output pin TMO2 output pin* Supported only by the H8S/2268 Group. * P73/TMO1 The pin function is switched as shown below according to the combination of the OS3 to OS0 bits in TCSR_1 of the 8-bit timer and the P73DDR bit. OS3 to OS0 P73DDR Pin functions All bits are 0 Any bit is 1 0 1 P73 input pin P73 output pin TMO1 output pin * P72/TMO0 The pin function is switched as shown below according to the combination of the OS3 to OS0 bits in TCSR_0 of the 8-bit timer and the P72DDR bit. OS3 to OS0 P72DDR Pin functions All bits are 0 Any bit is 1 0 1 P72 input pin P72 output pin TMO0 output pin Rev. 3.00, 08/03, page 144 of 612 * P71/TMRI23*/TMCI23* The pin function is switched as shown below according to the P71DDR bit. P71DDR Pin functions 0 1 P71 input pin P71 output pin TMRI23/TMCI23 input pin* Note: Supported only by the H8S/2268 Group. * * P70/TMRI01/TMCI01 The pin function is switched as shown below according to the P70DDR bit. P70DDR Pin functions 0 1 P70 input pin P70 output pin TMRI01/TMCI01 input pin 9.5 Port 9 Port 9 is a 2-bit input-only port and has the following register. * Port 9 register (PORT9) 9.5.1 Port 9 Register (PORT9) PORT9 shows port 9 pin states. This register cannot be modified. Bit Bit Name Initial Value R/W Description 7 P97 * R 6 P96 * R The pin states are always read when these bits are read. 5 to 0 Undefined R Reserved These bits are always read as undefined value and cannot be modified. Note: 9.5.2 * Determined by the states of pins P97 and P96. Pin Functions Port 9 pins also function as A/D converter analog input pins (AN8 and AN9) and D/A converter analog output pins (DA0 and DA1)*. Note: * Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 145 of 612 9.6 Port F Port F is a 1-bit I/O port and has the following register. * Port F data direction register (PFDDR) * Port F data register (PFDR) * Port F register (PORTF) 9.6.1 Port F Data Direction Register (PFDDR) PFDDR specifies input or output the port F pins using the individual bits. PFDDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value 7 to 4 Undefined R/W Description Reserved These bits are always read as undefined value and cannot be modified. 3 PF3DDR 0 W 2 to 0 Undefined When a pin is specified as a general purpose I/O port, setting this bit to 1 makes the corresponding port F pin an output pin. Clearing this bit to 0 makes the pin an input pin. Reserved These bits are always read as undefined value and cannot be modified. 9.6.2 Port F Data Register (PFDR) PFDR stores output data for port F pins. Bit Bit Name Initial Value 7 to 4 Undefined R/W Description Reserved These bits are always read as undefined value and cannot be modified. 3 PF3DR 0 R/W 2 to 0 Undefined Output data for a pin is stored when the pin is specified as a general purpose output port. Reserved These bits are always read as undefined value and cannot be modified. Rev. 3.00, 08/03, page 146 of 612 9.6.3 Port F Register (PORTF) PORTF shows the pin states. This register cannot be modified. Bit Bit Name Initial Value 7 to 4 Undefined R/W Description Reserved These bits are always read as undefined value and cannot be modified. 3 PF3 * 2 to 0 Undefined R If this bit is read while PFDDR is set to 1, the PFDR value is read. If this bit is read while PFDDR is cleared, the PF3 pin states are read. Reserved These bits are always read as undefined value and cannot be modified. Note: * 9.6.4 Determined by the states of PF3 pin. Pin Functions Port F pins also function as an external interrupt input pin (IRQ3) and A/D trigger output pin (ADTRG). Port F pin functions are shown below. * PF3/ADTRG/IRQ3 The pin function is switched as shown below according to the combination of the TRGS1 and TRGS0 bits of ADCR of the A/D converter and the PF3DDR bit. PF3DDR Pin functions 0 1 PF3 input pin PF3 output pin ADTRG Input pin* 1 IRQ3 input pin* 2 Notes: 1. When TRGS0 = TRGS1 = 1, port F is used as the ADTRG input pin. 2. When this port is used as an external interrupt pin, do not specify other functions. Rev. 3.00, 08/03, page 147 of 612 9.7 Port H Port H is a 1-bit input and 4-bit I/O port. Port H has the following registers. * Port H data direction register (PHDDR) * Port H data register (PHDR) * Port H register (PORTH) 9.7.1 Port H Data Direction Register (PHDDR) PHDDR specifies input or output the port H pins using the individual bits. PHDDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value 7 to 4 Undefined R/W Description Reserved These bits are always read as undefined value and cannot be modified. 3 PH3DDR 0 W 2 PH2DDR 0 W 1 PH1DDR 0 W 0 PH0DDR 0 W 9.7.2 Port H Data Register (PHDR) When a pin is specified as a general purpose I/O port, setting these bits to 1 makes the corresponding port H pin an output pin. Clearing this bit to 0 makes the pin an input pin. PHDR stores output data for port H. Bit Bit Name Initial Value 7 to 4 Undefined R/W Description Reserved These bits are always read as undefined value and cannot be modified. 3 PH3DR 0 R/W 2 PH2DR 0 R/W 1 PH1DR 0 R/W 0 PH0DR 0 R/W Rev. 3.00, 08/03, page 148 of 612 Output data for a pin is stored when the pin is specified as a general purpose output port. 9.7.3 Port H Register (PORTH) PORTH shows the pin states and cannot be modified. Bit Bit Name Initial Value R/W Description 7 PH7 * R When this bit is read, PH7 pin status is always read. 6 to 4 Undefined Reserved These bits are always read as undefined value and cannot be modified. 3 PH3 * R 2 PH2 * R 1 PH1 * R 0 PH0 * R Note: 9.7.4 * If these bits are read while the corresponding PHDDR bits are set to 1, the PHDR value is read. If these bits are read while PHDDR bits are cleared to 0, the pin states are read. Determined by the states of pins PH7 and PH3 to PH0. Pin Functions Port H pins also function as a DTMF generation circuit analog output pin (TONED)*, 8-bit reload timer input pin (TMCI4)*, and LCD driver common output pins (COM4 to COM1). Port H pin functions are shown below. Note: * Supported only by the H8S/2268 Group. * PH7/TONED/TMCI4 (H8S/2268 Group) The pin function is switched as shown below according to the combination of the CLOE and RWOE bits in DTCR of the DTMF generation circuit. CLOE, RWOE Pin functions All bits are 0 Any bit is 1 1 PH7 input pin* TONED output pin 1 2 TMCI4 input pin* * Notes: 1. Voltage applied to PH7 and TMCI4 should be within the range of AVss (PH7, TMCI4) AVcc. 2. When this port is used as TMCI4 input pin, do not specify other functions. * PH7 (H8S/2264 Group) This is an input pin. Voltage applied to this pin should be within the range of Vss (PH7) Vcc. Rev. 3.00, 08/03, page 149 of 612 * PH3/COM4 The pin function is switched as shown below according to the combination of the DTS1, DTS0, CMX, and SGS3 to SGS0 bits of LPCR, the SUPS* bit of LCR2 of the LCD controller/driver and the PH3DDR bit. SGS3 to SGS0 B'0000 H8S/2268 Group: B'0001, B'001X, or B'010X H8S/2264 Group: B'001X or B'010X DTS1, DTS0 B'XX B'0X B'10 CMX 0 1 SUPS* PH3DDR Pin functions 0 1 0 1 PH3 input pin PH3 output pin PH3 input pin PH3 output pin B'11 1 1 1 PH3 output pin Setting prohibited COM4 output pin COM4 output pin 0 0 0 COM4 PH3 output input pin pin [Legend] X: Don't care Note: * Supported only by the H8S/2268 Group. * PH2/COM3 The pin function is switched as shown below according to the combination of the DTS1, DTS0, CMX, SGS3 to SGS0 bits of LPCR of the LCD controller/driver, and PH2DDR bit. SGS3 to SGS0 B'0000 H8S/2268 Group: B'0001, B'001X or B'010X H8S/2264 Group: B'001X or B'010X DTS1, DTS0 B'XX PH2DDR Pin functions B'0X CMX 0 PH2 input pin [Legend] X: Don't care Rev. 3.00, 08/03, page 150 of 612 B'1X 0 1 0 PH2 output pin PH2 input pin 1 1 PH2 output pin COM3 output pin * PH1/COM2 The pin function is switched as shown below according to the combination of the DTS1, DTS0, CMX, SGS3 to SGS0 bits of LPCR of the LCD controller/driver, and PH2DDR bit. SGS3 to SGS0 B'0000 H8S/2268 Group: B'0001, B'001X or B'010X H8S/2264 Group: B'001X or B'010X DTS1, DTS0 B'XX B'00 CMX PH1DDR Pin functions Other than B'00X 0 0 1 0 PH1 input pin PH1 output pin 1 1 PH1 input pin PH1 output pin COM2 output pin [Legend] X: Don't care * PH0/COM1 The pin function is switched as shown below according to the combination of the SGS3 to SGS0 bits in LPCR of the LCD controller/driver and the PH0DDR bit. SGS3 to SGS0 B'0000 H8S/2268 Group: B'0001, B'001X or B'010X H8S/2264 Group: B'001X or B'010X PH0DDR Pin functions 0 1 PH0 input pin PH0 output pin COM1 output pin [Legend] X: Don't care 9.8 Port J Port J is an 8-bit I/O port and has the following registers. * Port J data direction register (PJDDR) * Port J data register (PJDR) * Port J register (PORTJ) * Port J pull-up MOS control register (PJPCR) * Wakeup control register (WPCR) Rev. 3.00, 08/03, page 151 of 612 9.8.1 Port J Data Direction Register (PJDDR) PJDDR specifies input or output the port J pins using the individual bits. PJDDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7 PJ7DDR 0 W 6 PJ6DDR 0 W 5 PJ5DDR 0 W When a pin is specified as a general purpose I/O port, setting this bit to 1 makes the corresponding port J pin an output pin. Clearing this bit to 0 makes the pin an input pin. 4 PJ4DDR 0 W 3 PJ3DDR 0 W 2 PJ2DDR 0 W 1 PJ1DDR 0 W 0 PJ0DDR 0 W 9.8.2 Port J Data Register (PJDR) PJDR stores output data for port J pins. Bit Bit Name Initial Value R/W Description 7 PJ7DR 0 R/W 6 PJ6DR 0 R/W Output data for a pin is stored when the pin is specified as a general purpose output port. 5 PJ5DR 0 R/W 4 PJ4DR 0 R/W 3 PJ3DR 0 R/W 2 PJ2DR 0 R/W 1 PJ1DR 0 R/W 0 PJ0DR 0 R/W Rev. 3.00, 08/03, page 152 of 612 9.8.3 Port J Register (PORTJ) PORTJ shows port J pin states. This register cannot be modified. Bit Bit Name Initial Value R/W Description 7 PJ7 * R 6 PJ6 * R 5 PJ5 * R If a port J read is performed while PJDDR bits are set to 1, the PJDR values are read. If a port J read is performed while PADDR bits are cleared to 0, the pin states are read. 4 PJ4 * R 3 PJ3 * R 2 PJ2 * R 1 PJ1 * R 0 PJ0 * R Note: 9.8.4 * Determined by the states of pins PJ7 to PJ0. Port J Pull-Up MOS Control Register (PJPCR) PJPCR controls the input pull-up MOS function for each bit. Bit Bit Name Initial Value R/W Description 7 PJ7PCR 0 R/W 6 PJ6PCR 0 R/W When a pin is specified as an input port, setting the corresponding bit to 1 turns on the input pull-up MOS for that pin. 5 PJ5PCR 0 R/W 4 PJ4PCR 0 R/W 3 PJ3PCR 0 R/W 2 PJ2PCR 0 R/W 1 PJ1PCR 0 R/W 0 PJ0PCR 0 R/W Rev. 3.00, 08/03, page 153 of 612 9.8.5 Wakeup Control Register (WPCR) WPCR controls switching of port J pin functions. For details on interrupt request flags, refer to 5.3.6, Wakeup Interrupt Request Register (IWPR). Bit Bit Name Initial Value R/W Description 7 WPC7 0 R/W 6 WPC6 0 R/W When these bits are set to 1, the corresponding PJn/WKPn pin becomes the WKPn input pin. When cleared, they become the PJn input/output pin. 5 WPC5 0 R/W 4 WPC4 0 R/W 3 WPC3 0 R/W 2 WPC2 0 R/W 1 WPC1 0 R/W 0 WPC0 0 R/W 9.8.6 Pin Functions (n = 7 to 0) Port J pins also function as wakeup input pins (WKP7 to WKP0) and LCD driver segment output pins (SEG8 to SEG1). Port J pin functions are shown below. * PJn/WKPn/SEGn+1 The pin function is switched as shown below according to the combination of the SGS3 to SGS0 bits in LPCR of the LCD driver/controller, WKP7 to WKP0 bits in WPCR, and PJnDDR bit. SGS3 to SGS0 H8S/2268 Group: B'00XX or B'0100 B'0101 H8S/2264 Group: B'0000, B'001X, or B'0100 0 1 PJn input pin PJn output pin WKPn input pin SEGn+1 output pin WPCn PJnDDR Pin functions 0 [Legend] X: Don't care Note: n = 7 to 0 Rev. 3.00, 08/03, page 154 of 612 1 9.8.7 Input Pull-Up MOS Function Port J has a built-in input pull-up MOS function that can be controlled by software. Input pull-up MOS can be specified as on or off on an individual bit basis. When port J is set to port input and wakeup input, PJDDR is cleared to 0, and then PJPCR is set to 1, the input pull-up MOS is turned on. The input pull-up MOS function is in the off state after a reset, and in hardware standby mode. The prior state is retained in software standby mode. Table 9.2 summarizes the input pull-up MOS states in port J. Table 9.2 Input Pull-Up MOS States (Port J) Pin States Reset Hardware Standby Mode Software Standby Mode In Other Operations Segment output and port output OFF OFF OFF OFF ON/OFF ON/OFF Port input and wakeup input [Legend] OFF : Input pull-up MOS is always off. ON/OFF : On when PJDDR = 0 and PJPCR = 1; otherwise off. Rev. 3.00, 08/03, page 155 of 612 9.9 Port K Port K is an 8-bit I/O port and has the following registers. * Port K data direction register (PKDDR) * Port K data register (PKDR) * Port K register (PORTK) 9.9.1 Port K Data Direction Register (PKDDR) PKDDR specifies input or output the port K pins using the individual bits. PKDDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7 PK7DDR 0 W 6 PK6DDR 0 W 5 PK5DDR 0 W When a pin is specified as a general purpose I/O port, setting this bit to 1 makes the corresponding port K pin an output port. Clearing this bit to 0 makes the pin an input port. 4 PK4DDR 0 W 3 PK3DDR 0 W 2 PK2DDR 0 W 1 PK1DDR 0 W 0 PK0DDR 0 W 9.9.2 Port K Data Register (PKDR) PKDR stores output data for port K pins. Bit Bit Name Initial Value R/W Description 7 PK7DR 0 R/W 6 PK6DR 0 R/W Output data for a pin is stored when the pin is specified as a general purpose output port. 5 PK5DR 0 R/W 4 PK4DR 0 R/W 3 PK3DR 0 R/W 2 PK2DR 0 R/W 1 PK1DR 0 R/W 0 PK0DR 0 R/W Rev. 3.00, 08/03, page 156 of 612 9.9.3 Port K Register (PORTK) PORTK shows port K pin states. This register cannot be modified. Bit Bit Name Initial Value R/W Description 7 PK7 * R 6 PK6 * R 5 PK5 * R If a port K read is performed while PKDDR bits are set to 1, the PKDR values are read. If a port K read is performed while PKDDR bits are cleared to 0, the pin states are read. 4 PK4 * R 3 PK3 * R 2 PK2 * R 1 PK1 * R 0 PK0 * R Note: * 9.9.4 Determined by the states of pins PK7 to PK0. Pin Functions Port K pins also function as LCD driver segment output pins (SEG16 to SEG9). Port K pin functions are shown below. * PKn/SEGn+9 The pin function is switched as shown below according to the combination of the SGS3 to SGS0 bits in LPCR of the LCD driver/controller and PKnDDR bit. SGS3 to SGS0 H8S/2268 Group: B'00XX B'010X H8S/2264 Group: B'0000 or B'001X PKnDDR Pin functions 0 1 PKn input pin PKn output pin SEGn+9 output pin [Legend] X: Don't care Note: n = 7 to 0 Rev. 3.00, 08/03, page 157 of 612 9.10 Port L Port L is an 8-bit I/O port and has the following registers. * Port L data direction register (PLDDR) * Port L data register (PLDR) * Port L register (PORTL) 9.10.1 Port L Data Direction Register (PLDDR) PLDDR specifies input or output of the port L pins using the individual bits. PLDDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7 PL7DDR 0 W 6 PL6DDR 0 W 5 PL5DDR 0 W When a pin is specified as a general purpose I/O port, setting this bit to 1 makes the corresponding port L pin an output port. Clearing this bit to 0 makes the pin an input port. 4 PL4DDR 0 W 3 PL3DDR 0 W 2 PL2DDR 0 W 1 PL1DDR 0 W 0 PL0DDR 0 W 9.10.2 Port L Data Register (PLDR) PLDR stores output data for port L pins. Bit Bit Name Initial Value R/W Description 7 PL7DR 0 R/W 6 PL6DR 0 R/W Output data for a pin is stored when the pin is specified as a general purpose output port. 5 PL5DR 0 R/W 4 PL4DR 0 R/W 3 PL3DR 0 R/W 2 PL2DR 0 R/W 1 PL1DR 0 R/W 0 PL0DR 0 R/W Rev. 3.00, 08/03, page 158 of 612 9.10.3 Port L Register (PORTL) PORTL shows port L pin states. This register cannot be modified. Bit Bit Name Initial Value R/W Description 7 PL7 * R 6 PL6 * R 5 PL5 * R If a port L read is performed while PLDDR bits are set to 1, the PLDR values are read. If a port L read is performed while PLDDR bits are cleared to 0, the pin states are read. 4 PL4 * R 3 PL3 * R 2 PL2 * R 1 PL1 * R 0 PL0 * R Note: * 9.10.4 Determined by the states of pins PL7 to PL0. Pin Functions Port L pins also function as LCD driver segment output pins (SEG24 to SEG17). Port L pin functions are shown below. * PLn/SEGn+17 The pin function is switched as shown below according to the combination of the SGS3 to SGS0 bits in LPCR of the LCD driver/controller and PLnDDR bit. SGS3 to SGS0 H8S/2268 Group: B'000X or B'0010 B'0011 or B'010X H8S/2264 Group: B'00X0 PLnDDR Pin functions 0 1 PLn input pin PLn output pin SEGn+17 output pin [Legend] X: Don't care Note: n = 7 to 0 Rev. 3.00, 08/03, page 159 of 612 9.11 Port M (H8S/2268 Group Only) Port M is an 8-bit I/O port and has the following registers. * Port M data direction register (PMDDR) * Port M data register (PMDR) * Port M register (PORTM) 9.11.1 Port M Data Direction Register (PMDDR) PMDDR specifies input or output of the port M pins using the individual bits. PMDDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7 PM7DDR 0 W 6 PM6DDR 0 W 5 PM5DDR 0 W When a pin is specified as a general purpose I/O port, setting this bit to 1 makes the corresponding port M pin an output port. Clearing this bit to 0 makes the pin an input port. 4 PM4DDR 0 W 3 PM3DDR 0 W 2 PM2DDR 0 W 1 PM1DDR 0 W 0 PM0DDR 0 W 9.11.2 Port M Data Register (PMDR) PMDR stores output data for port M pins. Bit Bit Name Initial Value R/W Description 7 PM7DR 0 R/W 6 PM6DR 0 R/W Output data for a pin is stored when the pin is specified as a general purpose output port. 5 PM5DR 0 R/W 4 PM4DR 0 R/W 3 PM3DR 0 R/W 2 PM2DR 0 R/W 1 PM1DR 0 R/W 0 PM0DR 0 R/W Rev. 3.00, 08/03, page 160 of 612 9.11.3 Port M Register (PORTM) PORTM shows port M pin states. Bit Bit Name Initial Value R/W Description 7 PM7 * R 6 PM6 * R 5 PM5 * R If a port M read is performed while PMDDR bits are set to 1, the PMDR values are read. If a port M read is performed while PMDDR bits are cleared to 0, the pin states are read. 4 PM4 * R 3 PM3 * R 2 PM2 * R 1 PM1 * R 0 PM0 * R Note: * 9.11.4 Determined by the states of pins PM7 to PM0. Pin Functions Port M pins also function as LCD driver segment output pins (SEG32 to SEG25). Port M pin functions are shown below. * PMn/SEGn+25 The pin function is switched as shown below according to the combination of the SGS3 to SGS0 bits in LPCR of the LCD driver/controller and PMnDDR bit. SGS3 to SGS0 PMnDDR Pin functions B'000X B'001X or B'010X 0 1 PMn input pin PMn output pin SEGn+25 output pin [Legend] X: Don't care Note: n = 7 to 0 Rev. 3.00, 08/03, page 161 of 612 9.12 Port N (H8S/2268 Group Only) Port N is an 8-bit I/O port and has the following registers. * Port N data direction register (PNDDR) * Port N data register (PNDR) * Port N register (PORTN) 9.12.1 Port N Data Direction Register (PNDDR) PNDDR specifies input or output of the port N pins using the individual bits. PNDDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7 PN7DDR 0 W 6 PN6DDR 0 W 5 PN5DDR 0 W When a pin is specified as a general purpose I/O port, setting this bit to 1 makes the corresponding port N pin an output port. Clearing this bit to 0 makes the pin an input port. 4 PN4DDR 0 W 3 PN3DDR 0 W 2 PN2DDR 0 W 1 PN1DDR 0 W 0 PN0DDR 0 W 9.12.2 Port N Data Register (PNDR) PNDR stores output data for port N pins. Bit Bit Name Initial Value R/W Description 7 PN7DR 0 R/W 6 PN6DR 0 R/W Output data for a pin is stored when the pin is specified as a general purpose output port. 5 PN5DR 0 R/W 4 PN4DR 0 R/W 3 PN3DR 0 R/W 2 PN2DR 0 R/W 1 PN1DR 0 R/W 0 PN0DR 0 R/W Rev. 3.00, 08/03, page 162 of 612 9.12.3 Port N Register (PORTN) PORTN shows port N pin states. Bit Bit Name Initial Value R/W Description 7 PN7 * R 6 PN6 * R 5 PN5 * R If a port N read is performed while PNDDR bits are set to 1, the PNDR values are read. If a port N read is performed while PNDDR bits are cleared to 0, the pin states are read. 4 PN4 * R 3 PN3 * R 2 PN2 * R 1 PN1 * R 0 PN0 * R Note: * 9.12.4 Determined by the states of pins PN7 to PN0. Pin Functions Port N pins also function as LCD driver segment output pins (SEG40 to SEG33). Port N pin functions are shown below. * PNn/SEGn+33 The pin function is switched as shown below according to the combination of the SGS3 to SGS0 bits in LPCR of the LCD driver/contoller and PNnDDR bit. SGS3 to SGS0 PNnDDR Pin functions B'0000 B'0001, B'001X, or B'010X 0 1 PNn input pin PNn output pin SEGn+33 output pin [Legend] X: Don't care Note: n = 7 to 0 Rev. 3.00, 08/03, page 163 of 612 Rev. 3.00, 08/03, page 164 of 612 Section 10 16-Bit Timer Pulse Unit (TPU) The H8S/2268 Group has an on-chip 16-bit timer pulse unit (TPU) comprised of three 16-bit timer channels, and the H8S/2264 Group has the TPU comprised of two 16-bit timer channels. The function list of the TPU is shown in table 10.1. A block diagram of the TPU for the H8S/2268 Group and that for the H8S/2264 Group are shown figures 10.1 and 10.2, respectively. 10.1 Features * Maximum 8-pulse input/output (H8S/2268 Group) * Maximum 4-pulse input/output (H8S/2264 Group) * Selection of 7 or 8 counter input clocks for each channel * The following operations can be set for each channel: Waveform output at compare match Input capture function Counter clear operation Synchronous operation: Multiple timer counters (TCNT) can be written to simultaneously Simultaneous clearing by compare match and input capture is possible Register simultaneous input/output is possible by synchronous counter operation PWM output with any duty level is possible A maximum 7-phase (H8S/2268 Group)/3-phase (H8S/2264 Group) PWM output is possible in combination with synchronous operation * Buffer operation settable for channel 0 (H8S/2268 Group only) * Phase counting mode settable independently for each of channels 1 and 2 (H8S/2268 Group only) * Fast access via internal 16-bit bus * 13-type interrupt sources (H8S/2268 Group) * 6-type interrupt sources (H8S/2264 Group) * Register data can be transmitted automatically * A/D converter conversion start trigger can be generated * Module stop mode can be set TIMTPU3B_000020030700 Rev. 3.00, 08/03, page 165 of 612 Table 10.1 TPU Functions 1 Item Channel 0* Channel 1 Channel 2 Count clock /1 /4 /16 /64 TCLKA TCLKB TCLKC TCLKD /1 /4 /16 /64 /256 TCLKA TCLKB /1 /4 /16 /64 /1024 TCLKA TCLKB TCLKC General registers (TGR) TGRA_0 TGRB_0 TGRA_1 TGRB_1 TGRA_2 TGRB_2 General registers/ 1 buffer registers* TGRC_0 TGRD_0 I/O pins TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 Counter clear function TGR compare match or TGR compare match or TGR compare match or input capture input capture input capture Compare match output 0 output 1 output Toggle output Input capture function Synchronous operation PWM mode Phase counting 1 mode* 1 Buffer operation* 1 DTC activation* TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture A/D converter trigger TGRA_0 compare match or input capture TGRA_1 compare match or input capture TGRA_2 compare match or input capture Rev. 3.00, 08/03, page 166 of 612 Item Interrupt sources 1 Channel 0* 5 sources Channel 1 Channel 2 1 4 sources* 1 3 sources* 2 3 sources* 4 sources* 2 * Compare match or input capture 0A * Compare match or input capture 1A * Compare match or input capture 2A * Compare match or input capture 0B * Compare match or input capture 1B * Compare match or input capture 2B * Compare match or input capture 0C * Overflow * Overflow * Underflow*1 * Underflow*1 * Compare match or input capture 0D * Overflow [Legend] : Possible : Not possible Notes: 1. Supported only by the H8S/2268 Group. 2. Supported only by the H8S/2264 Group. Rev. 3.00, 08/03, page 167 of 612 A/D convertion start request signal TGRD TGRC TGRB TGRB TGRB TCNT TCNT TGRA TCNT TGRA TSR TSR Module data bus TIER TIER TIER TGRA TSTR Bus interface Internal data bus TSR TIOR TIOR TIORH TIORL Common Control logic TMDR Channel 2 TCR TMDR Channel 1 TCR Channel 2: Channel 0 Channel 1: Control logic for channel 0 to 2 TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TMDR Input/output pins Channel 0: TCR External clock: /1 /4 /16 /64 /256 /1024 TCLKA TCLKB TCLKC TCLKD TSYR Clock input Internal clock: Interrupt request signals Channel 0: TGI0A TGI0B TGI0C TGI0D TCI0V Channel 1: TGI1A TGI1B TCI1V TCI1U Channel 2: TGI2A TGI2B TCI2V TCI2U [Legend] TSTR: TSYR: TCR: TMDR: Timer start register Timer synchro register Timer control register Timer mode register TIOR(H, L): TIER: TSR: TGR(A, B, C, D): Timer I/O control registers (H, L) Timer interrupt enable register Timer status register TImer general registers (A, B, C, D) Figure 10.1 Block Diagram of TPU for H8S/2268 Group Rev. 3.00, 08/03, page 168 of 612 A/D convertion start request signal TGRB TGRB TCNT TCNT TGRA TSR Module data bus TIER TIER TSR TIOR TGRA Bus interface Internal data bus TSTR Control logic TMDR Channel 2 TIOR Channel 2: TCR Common TIOCA1 TIOCB1 TIOCA2 TIOCB2 TMDR Channel 1: Channel 1 Input/output pins Control logic for channel 1 to 2 External clock: TCR /1 /4 /16 /64 /256 /1024 TCLKA TCLKB TCLKC TSYR Clock input Internal clock: Interrupt request signals Channel 1: TGI1A TGI1B TCI1V TCI1U Channel 2: TGI2A TGI2B TCI2V TCI2U [Legend] TSTR: TSYR: TCR: TMDR: Timer start register Timer synchro register Timer control register Timer mode register TIOR: TIER: TSR: TGR(A, B): Timer I/O control registers Timer interrupt enable register Timer status register TImer general registers (A, B) Figure 10.2 Block Diagram of TPU for H8S/2264 Group Rev. 3.00, 08/03, page 169 of 612 10.2 Input/Output Pins Table 10.2 TPU Pins Channel Symbol I/O Function All TCLKA Input External clock A input pin (Channel 1 phase counting mode A phase input*) TCLKB Input External clock B input pin (Channel 1 phase counting mode B phase input*) TCLKC Input External clock C input pin (Channel 2 phase counting mode A phase input*) TCLKD* Input External clock D input pin (Channel 2 phase counting mode B phase input*) TIOCA0 I/O TGRA_0 input capture input/output compare output/PWM output pin TIOCB0 I/O TGRB_0 input capture input/output compare output/PWM output pin TIOCC0 I/O TGRC_0 input capture input/output compare output/PWM output pin 0* 1 2 Note: * TIOCD0 I/O TGRD_0 input capture input/output compare output/PWM output pin TIOCA1 I/O TGRA_1 input capture input/output compare output/PWM output pin TIOCB1 I/O TGRB_1 input capture input/output compare output/PWM output pin TIOCA2 I/O TGRA_2 input capture input/output compare output/PWM output pin TIOCB2 I/O TGRB_2 input capture input/output compare output/PWM output pin Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 170 of 612 10.3 Register Descriptions The TPU has the following registers. To distinguish registers in each channel, an underscore and the channel number are added as a suffix to the register name; TCR for channel 0 is expressed as TCR_0. * Timer control register_0 (TCR_0)* * Timer mode register_0 (TMDR_0)* * Timer I/O control register H_0 (TIORH_0)* * Timer I/O control register L_0 (TIORL_0)* * Timer interrupt enable register_0 (TIER_0)* * Timer status register_0 (TSR_0)* * Timer counter_0 (TCNT_0)* * Timer general register A_0 (TGRA_0)* * Timer general register B_0 (TGRB_0)* * Timer general register C_0 (TGRC_0)* * Timer general register D_0 (TGRD_0)* * Timer control register_1 (TCR_1) * Timer mode register_1 (TMDR_1) * Timer I/O control register _1 (TIOR_1) * Timer interrupt enable register_1 (TIER_1) * Timer status register_1 (TSR_1) * Timer counter_1 (TCNT_1) * Timer general register A_1 (TGRA_1) * Timer general register B_1 (TGRB_1) * Timer control register_2 (TCR_2) * Timer mode register_2 (TMDR_2) * Timer I/O control register_2 (TIOR_2) * Timer interrupt enable register_2 (TIER_2) * Timer status register_2 (TSR_2) * Timer counter_2 (TCNT_2) * Timer general register A_2 (TGRA_2) * Timer general register B_2 (TGRB_2) Common Registers * Timer start register (TSTR) * Timer synchro register (TSYR) Note: * Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 171 of 612 10.3.1 Timer Control Register (TCR) The TCR registers control the TCNT operation for each channel. The H8S/2268 Group TPU has a total of three TCR registers and the H8S/2264 Group TPU has a total of two TCR registers, one for each channel (channels 0 to 2, or 1 and 2). TCR register settings should be conducted only when TCNT operation is stopped. Bit Bit Name Initial value R/W Description 7 CCLR2 0 R/W Counter Clear 0 to 2 6 CCLR1 0 R/W 5 CCLR0 0 R/W These bits select the TCNT counter clearing source. See tables 10.3 and 10.4 for details. 4 CKEG1 0 R/W Clock Edge 0 and 1 3 CKEG0 0 R/W These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. /4 both edges = /2 rising edge). Internal clock edge selection is valid when the input clock is /4 or slower. If the input clock is 1, this setting is ignored and count at rising edge is selected. In the H8S/2268 Group, if phase counting mode is used on channels 1 and 2, this setting is ignored and the phase counting mode setting has priority. 00: Count at rising edge 01: Count at falling edge 1X: Count at both edges [Legend] X: Don't care 2 TPSC2 0 R/W Time Prescaler 0 to 2 1 TPSC1 0 R/W 0 TPSC0 0 R/W These bits select the TCNT counter clock. The clock source can be selected independently for each channel. See tables10.5 to10.7 for details. Rev. 3.00, 08/03, page 172 of 612 Table 10.3 CCLR0 to CCLR2 (Channel 0) (H8S/2268 Group Only) Channel Bit 7 CCLR2 Bit 6 CCLR1 Bit 5 CCLR0 Description 0 0 0 0 TCNT clearing disabled 1 TCNT cleared by TGRA compare match/input capture 0 TCNT cleared by TGRB compare match/input capture 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* 0 TCNT clearing disabled 1 TCNT cleared by TGRC compare match/input 2 capture* 0 TCNT cleared by TGRD compare match/input 2 capture* 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* 1 1 0 1 Notes: 1. Synchronous operation is set by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. Table 10.4 CCLR0 to CCLR2 (Channels 1 and 2) Channel Bit 7 Bit 6 2 Reserved* CCLR1 Bit 5 CCLR0 Description 1, 2 0 0 TCNT clearing disabled 1 TCNT cleared by TGRA compare match/input capture 0 TCNT cleared by TGRB compare match/input capture 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* 0 1 Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1. 2. Bit 7 is reserved in channels 1 and 2. It is always read as 0 and cannot be modified. Rev. 3.00, 08/03, page 173 of 612 Table 10.5 TPSC0 to TPSC2 (Channel 0) (H8S/2268 Group Only) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 0 0 0 0 Internal clock: counts on /1 1 Internal clock: counts on /4 1 0 Internal clock: counts on /16 1 Internal clock: counts on /64 0 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 0 External clock: counts on TCLKC pin input 1 External clock: counts on TCLKD pin input 1 1 Table 10.6 TPSC0 to TPSC2 (Channel 1) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 1 0 0 0 Internal clock: counts on /1 1 Internal clock: counts on /4 0 Internal clock: counts on /16 1 Internal clock: counts on /64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 0 Internal clock: counts on /256 1 Setting prohibited 1 1 0 1 Note: * This setting is ignored when channel 1 is in phase counting mode (H8S/2268 Group only). Rev. 3.00, 08/03, page 174 of 612 Table 10.7 TPSC0 to TPSC2 (Channel 2) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 2 0 0 0 Internal clock: counts on /1 1 Internal clock: counts on /4 1 0 Internal clock: counts on /16 1 Internal clock: counts on /64 0 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 0 External clock: counts on TCLKC pin input 1 Internal clock: counts on /1024 1 1 Note: 10.3.2 * This setting is ignored when channel 2 is in phase counting mode (H8S/2268 Group only). Timer Mode Register (TMDR) The TMDR registers are used to set the operating mode of each channel. The H8S/2268 Group TPU has three TMDR registers and the H8S/2264 Group TPU has two TMDR registers, one for each channel (channels 0 to 2, or 1 and 2). TMDR register settings should be changed only when TCNT operation is stopped. Bit Bit Name Initial value R/W Description 7, 6 All 1 Reserved 5 BFB 0 R/W These bits are always read as 1 and cannot be modified. H8S/2268 Group: Buffer Operation B Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated. In channels 1 and 2, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: TGRB operates normally 1: TGRB and TGRD used together for buffer operation H8S/2264 Group: Reserved These bits are always read as 0 and cannot be modified. Rev. 3.00, 08/03, page 175 of 612 Bit Bit Name Initial value R/W 4 BFA 0 R/W Description H8S/2268 Group: Buffer Operation A Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1 and 2, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified. 0: TGRA operates normally 1:TGRA and TGRC used together for buffer operation H8S/2264 Group: Reserved These bits are always read as 0 and cannot be modified. 3 MD3 0 R/W Modes 0 to 3 2 MD2 0 R/W These bits are used to set the timer operating mode. 1 MD1 0 R/W 0 MD0 0 R/W MD3 is a reserved bit. In a write, it should always be written with 0. See table 10.8 for details. Table 10.8 MD0 to MD3 Bit 3 1 MD3* Bit 2 2 MD2* Bit 1 MD1 Bit 0 MD0 Description 0 0 0 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 0 Phase counting mode 1 1 Phase counting mode 2 0 Phase counting mode 3 1 Phase counting mode 4 X 1 1 0 1 1 X X [Legend] X: Don't care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set in the H8S/2264 Group or for channels 0 in the H8S/2268 Group. In this case, 0 should always be written to MD2. Rev. 3.00, 08/03, page 176 of 612 10.3.3 Timer I/O Control Register (TIOR) The TIOR registers control the TGR registers. The H8S/2268 Group TPU has four TIOR registers and the H8S/2264 Group TPU has two TIOR registers, two for channel 0, and one each for channels 1 and 2. Care is required as TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. In the H8S/2268 Group, when TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. * TIORH_0 (H8S/2268 Group only), TIOR_1, TIOR_2 Bit Bit Name Initial value R/W Description 7 IOB3 All 0 R/W I/O Control B0 to B3 6 IOB2 Specify the function of TGRB. 5 IOB1 For details, refer to table 10.9, 10.11, and 10.12. 4 IOB0 3 IOA3 2 IOA2 Specify the function of TGRA. 1 IOA1 For details, refer to table 10.13, 10.15, and 10.16. 0 IOA0 All 0 R/W I/O Control A0 to A3 * TIORL_0 (H8S/2268 Group only) Bit Bit Name Initial value R/W Description 7 IOD3 All 0 R/W I/O Control D0 to D3 6 IOD2 Specify the function of TGRD. 5 IOD1 For details, refer to table 10.10. 4 IOD0 3 IOC3 2 IOC2 Specify the function of TGRC. 1 IOC1 For details, refer to table 10.14. 0 IOC0 All 0 R/W I/O Control C0 to C3 Rev. 3.00, 08/03, page 177 of 612 Table 10.9 TIORH_0 (Channel 0) (H8S/2268 Group Only) Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_0 Function 0 0 0 0 Output compare register 1 TIOCB0 Pin Function Output disabled Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 0 0 1 Input capture register Capture input source is TIOCB0 pin Input capture at rising edge Capture input source is TIOCB0 pin Input capture at falling edge 1 X Capture input source is TIOCB0 pin Input capture at both edges 1 X X [Legend] X: Don't care Rev. 3.00, 08/03, page 178 of 612 Setting disabled Table 10.10 TIORL_0 (Channel 0) (H8S/2268 Group Only) Description Bit 7 IOD3 Bit 6 IOD2 Bit 5 IOD1 Bit 4 IOD0 TGRD_0 Function 0 0 0 0 Output compare register* 1 TIOCD0 Pin Function Output disabled Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 0 0 1 Input capture register* Capture input source is TIOCD0 pin Input capture at rising edge Capture input source is TIOCD0 pin Input capture at falling edge 1 X Capture input source is TIOCD0 pin Input capture at both edges 1 X X Setting disabled [Legend] X: Don't care Note: * When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 3.00, 08/03, page 179 of 612 Table 10.11 TIOR_1 (Channel 1) Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_1 Function 0 0 0 0 Output compare register 1 TIOCB1 Pin Function Output disabled Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 0 0 1 Input capture register Capture input source is TIOCB1 pin Input capture at rising edge Capture input source is TIOCB1 pin Input capture at falling edge 1 X Capture input source is TIOCB1 pin Input capture at both edges 1 X X [Legend] X: Don't care Rev. 3.00, 08/03, page 180 of 612 Setting disabled Table 10.12 TIOR_2 (Channel 2) Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_2 Function 0 0 0 0 Output compare register 1 TIOCB2 Pin Function Output disabled Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 0 1 Input capture register Capture input source is TIOCB2 pin Input capture at rising edge Capture input source is TIOCB2 pin Input capture at falling edge 1 X Capture input source is TIOCB2 pin Input capture at both edges [Legend] X: Don't care Rev. 3.00, 08/03, page 181 of 612 Table 10.13 TIORH_0 (Channel 0) (H8S/2268 Group Only) Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_0 Function 0 0 0 0 Output compare register 1 TIOCA0 Pin Function Output disabled Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 0 0 1 Input capture register Capture input source is TIOCA0 pin Input capture at rising edge Capture input source is TIOCA0 pin Input capture at falling edge 1 X Capture input source is TIOCA0 pin Input capture at both edges 1 X X [Legend] X: Don't care Rev. 3.00, 08/03, page 182 of 612 Setting disabled Table 10.14 TIORL_0 (Channel 0) (H8S/2268 Group Only) Description Bit 3 IOC3 Bit 2 IOC2 Bit 1 IOC1 Bit 0 IOC0 TGRC_0 Function 0 0 0 0 Output compare register* 1 TIOCC0 Pin Function Output disabled Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 0 0 1 Input capture register* Capture input source is TIOCC0 pin Input capture at rising edge Capture input source is TIOCC0 pin Input capture at falling edge 1 X Capture input source is TIOCC0 pin Input capture at both edges 1 X X Setting disabled [Legend] X: Don't care Note: * When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 3.00, 08/03, page 183 of 612 Table 10.15 TIOR_1 (Channel 1) Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_1 Function 0 0 0 0 Output compare register 1 TIOCA1 Pin Function Output disabled Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 0 0 1 Input capture register Capture input source is TIOCA1 pin Input capture at rising edge Capture input source is TIOCA1 pin Input capture at falling edge 1 X Capture input source is TIOCA1 pin Input capture at both edges 1 X X [Legend] X: Don't care Rev. 3.00, 08/03, page 184 of 612 Setting disabled Table 10.16 TIOR_2 (Channel 2) Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_2 Function 0 0 0 0 Output compare register 1 TIOCA2 Pin Function Output disabled Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 0 1 Input capture register Capture input source is TIOCA2 pin Input capture at rising edge Capture input source is TIOCA2 pin Input capture at falling edge 1 X Capture input source is TIOCA2 pin Input capture at both edges [Legend] X: Don't care Rev. 3.00, 08/03, page 185 of 612 10.3.4 Timer Interrupt Enable Register (TIER) The TIER registers control enabling or disabling of interrupt requests for each channel. The H8S/2268 Group TPU has three TIER registers and the H8S/2264 Group TPU has two TIER registers, one for each channel (channels 0 to 2, or 1 and 2). Bit Bit Name Initial value R/W Description 7 TTGE 0 R/W A/D Conversion Start Request Enable Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match. 0: A/D conversion start request generation disabled 1: A/D conversion start request generation enabled 6 1 Reserved This bit is always read as 1 and cannot be modified. 5 TCIEU 0 R/W H8S/2268 Group: Underflow Interrupt Enable Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1 and 2. In channel 0, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TCIU) by TCFU disabled 1: Interrupt requests (TCIU) by TCFU enabled H8S/2264 Group: The write value should always be 0. 4 TCIEV 0 R/W Overflow Interrupt Enable Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. 0: Interrupt requests (TCIV) by TCFV disabled 1: Interrupt requests (TCIV) by TCFV enabled 3 TGIED 0 R/W TGR Interrupt Enable D Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channel 0. In channels 1 and 2, bit 3 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TGID) by TGFD bit disabled 1: Interrupt requests (TGID) by TGFD bit enabled Rev. 3.00, 08/03, page 186 of 612 Bit Bit Name Initial value R/W 2 TGIEC 0 R/W Description TGR Interrupt Enable C Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channel 0. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TGIC) by TGFC bit disabled 1: Interrupt requests (TGIC) by TGFC bit enabled 1 TGIEB 0 R/W TGR Interrupt Enable B Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB bit disabled 1: Interrupt requests (TGIB) by TGFB bit enabled 0 TGIEA 0 R/W TGR Interrupt Enable A Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. 0: Interrupt requests (TGIA) by TGFA bit disabled 1: Interrupt requests (TGIA) by TGFA bit enabled 10.3.5 Timer Status Register (TSR) The TSR registers indicate the status of each channel. The H8S/2268 Group TPU has three TSR registers and the H8S/2264 Group TPU has two TSR registers, one for each channel (channels 0 to 2, or 1 and 2). Bit Bit Name Initial value R/W Description 7 TCFD 1 R H8S/2268 Group: Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1 and 2. In channel 0, bit 7 is reserved. It is always read as 1 and cannot be modified. 0: TCNT counts down 1: TCNT counts up H8S/2264 Group: Reserved This bit is always read as 1 and cannot be modified. Rev. 3.00, 08/03, page 187 of 612 Bit Bit Name Initial value R/W Description 6 1 Reserved This bit is always read as 1 and cannot be modified. 5 TCFU 0 1 R/(W)* H8S/2268 Group: Underflow Flag Status flag that indicates that TCNT underflow has occurred when channels 1 and 2 are set to phase counting mode. Only 0 can be written, for flag clearing. In channel 0, bit 5 is reserved. It is always read as 0 and cannot be modified. [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 H8S/2264 Group: Reserved This bit is always read as 0 and cannot be modified. 4 TCFV 0 1 R/(W)* Overflow Flag Status flag that indicates that TCNT overflow has occurred. Only 0 can be written, for flag clearing. [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 Rev. 3.00, 08/03, page 188 of 612 Bit 3 Bit Name TGFD Initial value 0 R/W Description 1 R/(W)* H8S/2268 Group: Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channel 0. Only 0 can be written, for flag clearing. In channels 1 and 2, bit 3 is reserved. It is always read as 0 and cannot be modified. [Setting conditions] * When TCNT = TGRD and TGRD is functioning as output compare register * When TCNT value is transferred to TGRD by input capture signal and TGRD is functioning as input capture register [Clearing conditions] * When DTC is activated by TGID interrupt and the DISEL bit of MRB in DTC is 0 * When 0 is written to TGFD after reading TGFD = 1 H8S/2264 Group: Reserved This bit is always read as 0 and cannot be modified. Rev. 3.00, 08/03, page 189 of 612 Bit 2 Bit Name TGFC Initial value 0 R/W Description 1 R/(W)* H8S/2268 Group: Input Capture/Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channel 0. Only 0 can be written, for flag clearing. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and cannot be modified. [Setting conditions] * When TCNT = TGRC and TGRC is functioning as output compare register * When TCNT value is transferred to TGRC by input capture signal and TGRC is functioning as input capture register [Clearing conditions] * When DTC is activated by TGIC interrupt and the DISEL bit of MRB in DTC is 0 * When 0 is written to TGFC after reading TGFC = 1 H8S/2264 Group: Reserved This bit is always read as 0 and cannot be modified. 1 TGFB 0 1 R/(W)* Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. Only 0 can be written, for flag clearing. [Setting conditions] * When TCNT = TGRB and TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal and TGRB is functioning as input capture register [Clearing conditions] Rev. 3.00, 08/03, page 190 of 612 * When DTC*2 is activated by TGIB interrupt and the DISEL bit of MRB in DTC*2 is 0 * When 0 is written to TGFB after reading TGFB = 1 Bit 0 Bit Name TGFA Initial value 0 R/W Description 1 R/(W)* Input Capture/Output Compare Flag A Status flag that indicates the occurrence of TGRA input capture or compare match. Only 0 can be written, for flag clearing. [Setting conditions] * When TCNT = TGRA and TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal and TGRA is functioning as input capture register [Clearing conditions] * When DTC*2 is activated by TGIA interrupt and the DISEL bit of MRB in DTC*2 is 0 * When 0 is written to TGFA after reading TGFA = 1 Notes: 1. Only 0 can be written to this bit to clear the flag. 2. Supported only by the H8S/2268 Group. 10.3.6 Timer Counter (TCNT) The TCNT registers are 16-bit readable/writable counters. The H8S/2268 Group TPU has three TCNT counters and the H8S/2264 Group TPU has two TCNT counters, one for each channel (channels 0 to 2, or 1 and 2). The TCNT counters are initialized to H'0000 by a reset, or in hardware standby mode. The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. 10.3.7 Timer General Register (TGR) The TGR registers are dual function 16-bit readable/writable registers, functioning as either output compare or input capture registers. The H8S/2268 Group TPU has eight TGR registers and the H8S/2264 Group TPU has four TGR registers, four for channel 0 and two each for channels 1 and 2. TGR is initialized to H'FFFF at reset or in hardware standby mode. The TGR registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. In the H8S/2268 Group, TGRC and TGRD for channel 0 can also be designated for operation as buffer registers. TGR buffer register combinations are TGRATGRC and TGRBTGRD. Rev. 3.00, 08/03, page 191 of 612 10.3.8 Timer Start Register (TSTR) TSTR selects operation/stoppage for channels 0 to 2 in the H8S/2268 Group and for channels 1 and 2 in the H8S/2264 Group. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. Bit Bit Name Initial value R/W Description 7 to 3 All 0 Reserved The write value should always be 0. 2 CST2 0 R/W Counter Start 0 to 2 (CST0 to CST2) 1 CST1 0 R/W These bits select operation or stoppage for TCNT. 0 CST0* 0 R/W If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_n count operation is stopped 1: TCNT_n performs count operation (n = 0 to 2) Note: * In the H8S/2264 Group, this bit is reserved. The write value should always be 0. Rev. 3.00, 08/03, page 192 of 612 10.3.9 Timer Synchro Register (TSYR) TSYR selects independent operation or synchronous operation of the TCNT counters for channels 0 to 2 in the H8S/2268 Group and for channels 1 and 2 in the H8S/2264 Group. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit Bit Name Initial value R/W Description 7 to 3 0 Reserved The write value should always be 0. 2 SYNC2 0 R/W Timer Synchro 0 to 2 1 SYNC1 0 R/W 0 SYNC0* 0 R/W These bits are used to select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source must also be set by means of bits CCLR0 to CCLR2 in TCR. 0: TCNT_n operates independently (TCNT presetting/ clearing is unrelated to other channels) 1: TCNT_n performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible (n = 0 to 2) Note: * In the H8S/2264 Group, this bit is reserved. The write value should always be 0. Rev. 3.00, 08/03, page 193 of 612 10.4 Interface to Bus Master 10.4.1 16-Bit Registers TCNT and TGR are 16-bit registers. As the data bus to the master is 16 bits wide, these registers can be read or written to in 8-bit units; 16-bit access must always be used. An example of 16-bit register access operation is shown in figure 10.3. Bus master Internal data bus H L Module data bus Bus interface TCNTH TCNTL Figure 10.3 16-Bit Register Access Operation [ Bus Master TCNT (16 Bits) ] 10.4.2 8-Bit Registers Registers other than TCNT and TGR are 8-bit. As the data bus to the CPU is 16 bits wide, these registers can be read and written to in 16-bit units. They can also be read and written to in 8-bit units. Examples of 8-bit register access operation are shown in figure 10.4, 10.5, and 10.6. Internal data bus Bus master H L Module data bus Bus interface TCR Figure 10.4 8-Bit Register Access Operation [ Bus Master TCR (Upper 8 Bits) ] Rev. 3.00, 08/03, page 194 of 612 Bus master Internal data bus H L Module data bus Bus interface TMDR Figure 10.5 8-Bit Register Access Operation [ Bus Master TMDR (Lower 8 Bits) ] Bus master Internal data bus H L Module data bus Bus interface TCR TMDR Figure 10.6 8-Bit Register Access Operation [ Bus Master TCR and TMDR (16 Bits) ] 10.5 Operation 10.5.1 Basic Functions Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Counter Operation: When one of bits CST0 to CST2 in the H8S/2268 Group or one of bits CST1 and CST2 in the H8S/2264 Group is set to 1 in TSTR, the TCNT counter for the corresponding channel begins counting. TCNT can operate as a free-running counter, periodic counter, for example. 1. Example of count operation setting procedure Figure 10.7 shows an example of the count operation setting procedure. Rev. 3.00, 08/03, page 195 of 612 Operation selection Select counter clock [1] Periodic counter Select counter clearing source Free-running counter [2] [3] Select output compare register Set period [4] Start count operation [5] <Periodic counter> Start count operation <Free-running counter> [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0* in TCR. [3] Designate the TGR selected in [2] as an output compare register by means of TIOR. [4] Set the periodic counter cycle in the TGR selected in [2]. [5] Set the CST bit in TSTR to 1 to start the counter operation. Note: * In the H8S/2264 Group, bits CCLR1 and CCLR0 in TCR. Figure 10.7 Example of Counter Operation Setting Procedure 2. Free-running count operation and periodic count operation Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again from H'0000. Figure 10.8 illustrates free-running counter operation. Rev. 3.00, 08/03, page 196 of 612 TCNT value H'FFFF H'0000 Time CST bit TCFV Figure 10.8 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR0 to CCLR2 in the H8S/2268 Group TCR or bits CCLR0 and CCLR1 in the H8S/2264 Group TCR. After the settings have been made, TCNT starts up-count operation as a periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt. After a compare match, TCNT starts counting up again from H'0000. Figure 10.9 illustrates periodic counter operation. Counter cleared by TGR compare match TCNT value TGR H'0000 Time CST bit Flag cleared by software or DTC* activation TGF Note: * Supported only by the H8S/2268 Group. Figure 10.9 Periodic Counter Operation Rev. 3.00, 08/03, page 197 of 612 Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match. 1. Example of setting procedure for waveform output by compare match Figure 10.10 shows an example of the setting procedure for waveform output by compare match. [1] Select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of TIOR. The set initial value is output at the TIOC pin unit the first compare match occurs. [2] Set the timing for compare match generation in TGR. [3] Set the CST bit in TSTR to 1 to start the count operation. Input selection [1] Select waveform output mode [2] Set output timing [3] Start count operation < Waveform output > Figure 10.10 Example of Setting Procedure for Waveform Output by Compare Match 2. Examples of waveform output operation Figure 10.11 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made such that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change. TCNT value H'FFFF TGRA TGRB Time H'0000 No change No change 1 output TIOCA No change TIOCB No change Figure 10.11 Example of 0 Output/1 Output Operation Rev. 3.00, 08/03, page 198 of 612 0 output Figure 10.12 shows an example of toggle output. In this example, TCNT has been designated as a periodic counter (with counter clearing on compare match B), and settings have been made such that the output is toggled by both compare match A and compare match B. TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA Time H'0000 Toggle output TIOCB Toggle output TIOCA Figure 10.12 Example of Toggle Output Operation Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. 1. Example of input capture operation setting procedure Figure 10.13 shows an example of the input capture operation setting procedure. Input selection Select input capture input Start count [1] Designate TGR as an input capture register by means of TIOR, and select rising edge, falling edge, or both edges as the input capture source and input signal edge. [2] Set the CST bit in TSTR to 1 to start the count operation. [1] [2] <Input capture operation> Figure 10.13 Example of Input Capture Operation Setting Procedure Rev. 3.00, 08/03, page 199 of 612 2. Example of input capture operation Figure 10.14 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, the falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT. Counter cleared by TIOCB input (falling edge) TCNT value H'0180 H'0160 H'0010 H'0005 Time H'0000 TIOCA TGRA H'0005 H'0160 H'0010 TIOCB TGRB H'0180 Figure 10.14 Example of Input Capture Operation 10.5.2 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 2 in the H8S/2268 Group or channels 1 and 2 in the H8S/2264 Group can all be designated for synchronous operation. Example of Synchronous Operation Setting Procedure: Figure 10.15 shows an example of the synchronous operation setting procedure. Rev. 3.00, 08/03, page 200 of 612 Synchronous operation selection Set synchronous operation [1] Synchronous presetting Set TCNT Synchronous clearing [2] Clearing source generation channel? No Yes <Synchronous presetting> Select counter clearing source [3] Set synchronous counter clearing [4] Start count [5] Start count [5] <Counter clearing> <Synchronous clearing> [1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. [2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. [3] Use bits CCLR2 to CCLR0* in TCR to specify TCNT clearing by input capture/output compare, etc. [4] Use bits CCLR2 to CCLR0* in TCR to designate synchronous clearing for the counter clearing source. [5] Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation. Note: * In the H8S/2264 Group, bits CCRL1 and CCLR0 in TCR. Figure 10.15 Example of Synchronous Operation Setting Procedure Example of Synchronous Operation: Figure 10.16 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2 in the H8S/2268 Group, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this time, synchronous presetting, and synchronous clearing by TGRB_0 compare match, are performed for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle. For details on PWM modes, see section 10.5.4, PWM Modes. Rev. 3.00, 08/03, page 201 of 612 Synchronous clearing by TGRB_0 compare match TCNT0 to TCNT2 values TGRB_0 TGRB_1 TGRA_0 TGRB_2 TGRA_1 TGRA_2 Time H'0000 TIOCA0 TIOCA1 TIOCA2 Figure 10.16 Example of Synchronous Operation 10.5.3 Buffer Operation (H8S/2268 Group Only) Buffer operation, provided for channel 0, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 10.17 shows the register combinations used in buffer operation. Table 10.17 Register Combinations in Buffer Operation Channel Timer General Register Buffer Register 0 TGRA_0 TGRC_0 TGRB_0 TGRD_0 Rev. 3.00, 08/03, page 202 of 612 * When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 10.17. Compare match signal Timer general register Buffer register Comparator TCNT Figure 10.17 Compare Match Buffer Operation * When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 10.18. Input capture signal Timer general register Buffer register TCNT Figure 10.18 Input Capture Buffer Operation Example of Buffer Operation Setting Procedure: Figure 10.19 shows an example of the buffer operation setting procedure. Buffer operation Select TGR function [1] Set buffer operation [2] Start count [3] [1] Designate TGR as an input capture register or output compare register by means of TIOR. [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. [3] Set the CST bit in TSTR to 1 start the count operation. <Buffer operation> Figure 10.19 Example of Buffer Operation Setting Procedure Rev. 3.00, 08/03, page 203 of 612 Examples of Buffer Operation: 1. When TGR is an output compare register Figure 10.20 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. As buffer operation has been set, when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time that compare match A occurs. For details on PWM modes, see section 10.5.4, PWM Modes. TCNT value TGRB_0 H'0520 H'0450 H'0200 TGRA_0 Time H'0000 H'0450 TGRC_0 H'0200 H'0520 Transfer TGRA_0 H'0200 H'0450 TIOCA Figure 10.20 Example of Buffer Operation (1) 2. When TGR is an input capture register Figure 10.21 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in TGRA upon the occurrence of input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC. Rev. 3.00, 08/03, page 204 of 612 TCNT value H'0F07 H'09FB H'0532 H'0000 Time TIOCA TGRA H'0532 TGRC H'0F07 H'09FB H'0532 H'0F07 Figure 10.21 Example of Buffer Operation (2) 10.5.4 PWM Modes In PWM mode, PWM waveforms are output from the output pins. The output level can be selected as 0, 1, or toggle output in response to a compare match of each TGR. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below. * PWM mode 1 H8S/2268 Group: PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The output specified by bits IOA0 to IOA3 and IOC0 to IOC3 in TIOR is output from the TIOCA and TIOCC pins at compare matches A and C, and the output specified by bits IOB0 to IOB3 and IOD0 to IOD3 in TIOR is output at compare matches B and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, PWM output is enable up to 4 phases. H8S/2264 Group: PWM output is generated from the TIOCA pin by pairing TGRA with TGRB. The output specified by bits IOA0 to IOA3 in TIOR is output from the TIOCA pin at compare match A, and the output specified by bits IOB0 to IOB3 in TIOR is output at compare match B. The Rev. 3.00, 08/03, page 205 of 612 initial output value is the value set in TGRA. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, PWM output is enable up to 2 phases. * PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, PWM output is enabled up to 7 phases in the H8S/2268 Group or 3 phases in the H8S/2264 Group by using also synchronous operation. The correspondence between PWM output pins and registers is shown in table 10.18. Table 10.18 PWM Output Registers and Output Pins Output Pins Channel 1 0* 2 Registers PWM Mode 1 PWM Mode 2* TGRA_0 TIOCA0 TIOCA0 TGRB_0 TGRC_0 TIOCB0 TIOCC0 TGRD_0 1 TGRA_1 2 TGRA_2 TIOCD0 TIOCA1 TGRB_1 TGRB_2 TIOCC0 TIOCA1 TIOCB1 TIOCA2 TIOCA2 TIOCB2 Notes: 1. Supported only by the H8S/2268 Group. 2. In PWM mode 2, PWM output is not possible for the TGR register in which the period is set. Rev. 3.00, 08/03, page 206 of 612 Example of PWM Mode Setting Procedure: Figure 10.22 shows an example of the PWM mode setting procedure. PWM mode Select counter clock [1] Select counter clearing source [2] Select waveform output level [3] Set TGR [4] Set PWM mode [5] Start count [6] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0* in TCR to select the TGR to be used as the TCNT clearing source. [3] Use TIOR to designate the TGR as an output compare register, and select the initial value and output value. [4] Set the cycle in the TGR selected in [2], and set the duty in the other the TGR. [5] Select the PWM mode with bits MD3 to MD0 in TMDR. [6] Set the CST bit in TSTR to 1 start the count operation. Note: * In the H8S/2264 Group, bits CCLR1 and CCLR0 in TCR. <PWM mode> Figure 10.22 Example of PWM Mode Setting Procedure Examples of PWM Mode Operation: Figure 10.23 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the period, and the values set in the TGRB registers are used as the duty levels. TCNT value Counter cleared by TGRA compare match TGRA TGRB H'0000 Time TIOCA Figure 10.23 Example of PWM Mode Operation (1) Rev. 3.00, 08/03, page 207 of 612 Figure 10.24 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), outputting a 5-phase PWM waveform, in the H8S/2268 Group. In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs are used as the duty levels. Counter cleared by TGRB_1 compare match TCNT value TGRB_1 TGRA_1 TGRD_0 TGRC_0 TGRB_0 TGRA_0 H'0000 Time TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 Figure 10.24 Example of PWM Mode Operation (2) Rev. 3.00, 08/03, page 208 of 612 Figure 10.25 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode. TCNT value TGRB rewritten TGRA TGRB TGRB rewritten TGRB rewritten H'0000 Time 0% duty TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB rewritten TGRB H'0000 Time 100% duty TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB TGRB rewritten Time H'0000 TIOCA 100% duty 0% duty Figure 10.25 Example of PWM Mode Operation (3) Rev. 3.00, 08/03, page 209 of 612 10.5.5 Phase Counting Mode (H8S/2268 Group Only) In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1 and 2. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC0 to TPSC2 and bits CKEG0 and CKEG1 in TCR. However, the functions of bits CCLR0 and CCLR1 in TCR, and of TIOR, TIER, and TGR, are valid, and input capture/compare match and interrupt functions can be used. If overflow occurs when TCNT is counting up, the TCFV flag in TSR is set; if underflow occurs when TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag reveals whether TCNT is counting up or down. Table 10.19 shows the correspondence between external clock pins and channels. Table 10.19 Phase Counting Mode Clock Input Pins External Clock Pins Channels A-Phase B-Phase When channel 1 is set to phase counting mode TCLKA TCLKB When channel 2 is set to phase counting mode TCLKC TCLKD Example of Phase Counting Mode Setting Procedure: Figure 10.26 shows an example of the phase counting mode setting procedure. [1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the CST bit in TSTR to 1 to start the count operation. Phase counting mode Select phase counting mode [1] Start count [2] <Phase counting mode> Figure 10.26 Example of Phase Counting Mode Setting Procedure Rev. 3.00, 08/03, page 210 of 612 Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. 1. Phase counting mode 1 Figure 10.27 shows an example of phase counting mode 1 operation, and table 10.20 summarizes the TCNT up/down-count conditions. TCLKA(channel 1) TCLKC(channel 2) TCLKB(channel 1) TCLKD(channel 2) TCNT value Down-count Up-count Time Figure 10.27 Example of Phase Counting Mode 1 Operation Table 10.20 Up/Down-Count Conditions in Phase Counting Mode 1 TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) High level Operation Up-count Low level Low level High level High level Down-count Low level High level Low level [Legend] : Rising edge : Falling edge Rev. 3.00, 08/03, page 211 of 612 2. Phase counting mode 2 Figure 10.28 shows an example of phase counting mode 2 operation, and table 10.21 summarizes the TCNT up/down-count conditions. TCLKA(channel 1) TCLKC(channel 2) TCLKB(channel 1) TCLKD(channel 2) TCNT value Up-count Down-count Time Figure 10.28 Example of Phase Counting Mode 2 Operation Table 10.21 Up/Down-Count Conditions in Phase Counting Mode 2 TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) Operation High level Don't care Low level Don't care Low level Don't care High level Up-count High level Don't care Low level Don't care [Legend] : Rising edge : Falling edge Rev. 3.00, 08/03, page 212 of 612 High level Don't care Low level Down-count 3. Phase counting mode 3 Figure 10.29 shows an example of phase counting mode 3 operation, and table 10.22 summarizes the TCNT up/down-count conditions. TCLKA(channel 1) TCLKC(channel 2) TCLKB(channel 1) TCLKD(channel 2) TCNT value Down-count Up-count Time Figure 10.29 Example of Phase Counting Mode 3 Operation Table 10.22 Up/Down-Count Conditions in Phase Counting Mode 3 TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) Operation High level Don't care Low level Don't care Low level Don't care High level Up-count High level Down-count Low level Don't care High level Don't care Low level Don't care [Legend] : Rising edge : Falling edge Rev. 3.00, 08/03, page 213 of 612 4. Phase counting mode 4 Figure 10.30 shows an example of phase counting mode 4 operation, and table 10.23 summarizes the TCNT up/down-count conditions. TCLKA(channels 1) TCLKC(channels 2) TCLKB(channels 1) TCLKD(channels 2) TCNT value Down-count Up-count Time Figure 10.30 Example of Phase Counting Mode 4 Operation Table 10.23 Up/Down-Count Conditions in Phase Counting Mode 4 TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) High level Operation Up-count Low level Low level Don't care High level High level Down-count Low level High level Low level [Legend] : Rising edge : Falling edge Rev. 3.00, 08/03, page 214 of 612 Don't care 10.6 Interrupt Sources There are three kinds of TPU interrupt source for the H8S/2268 Group; TGR input capture/compare match, TCNT overflow, and TCNT underflow. There are two kinds of TPU interrupt source for the H8S/2264 Group; TGR input capture/compare match and TCNT overflow. Each interrupt source has its own status flag and enable/disabled bit, allowing the generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. In the H8S/2268 Group, relative channel priorities can be changed by the interrupt controller, however the priority order within a channel is fixed. For details, see section 5, Interrupt Controller. Table 10.24 lists the TPU interrupt sources. Table 10.24 TPU Interrupts Channel Name Interrupt Source Interrupt Flag DTC Activation* Priority Level 0* TGI0A TGRA_0 input capture/compare match TGFA_0 Possible High TGI0B TGRB_0 input capture/compare match TGFB_0 Possible TGI0C TGRC_0 input capture/compare match TGFC_0 Possible TGI0D TGRD_0 input capture/compare match TGFD_0 Possible TCI0V TCNT_0 overflow TCFV_0 Not possible TGI1A TGRA_1 input capture/compare match TGFA_1 Possible TGI1B TGRB_1 input capture/compare match TGFB_1 Possible TCI1V TCNT_1 overflow TCFV_1 Not possible TCI1U* TCNT_1 underflow TCFU_1 Not possible TGI2A TGRA_2 input capture/compare match TGFA_2 Possible TGI2B TGRB_2 input capture/compare match TGFB_2 Possible TCI2V TCNT_2 overflow TCFV_2 Not possible TCI2U* TCNT_2 underflow TCFU_2 Not possible 1 2 Note: * Low Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 215 of 612 Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The H8S/2268 Group TPU has eight input capture/compare match interrupts and the H8S/2264 Group TPU has four input capture/compare match interrupts, four for channel 0, and two each for channels 1 and 2. Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The H8S/2268 Group TPU has three overflow interrupts and the H8S/2264 Group TPU has two overflow interrupts, one for each channel (channels 0 to 2, or 1 and 2). Underflow Interrupt (H8S/2268 Group Only): An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The TPU has two underflow interrupts, one each for channels 1 and 2. 10.7 DTC Activation (H8S/2268 Group Only) The DTC can be activated by the TGR input capture/compare match interrupt for a channel. For details, see section 8, Data Transfer Controller (DTC). A total of eight TPU input capture/compare match interrupts can be used as DTC activation sources, four for channel 0, and two each for channels 1 and 2. 10.8 A/D Converter Activation The A/D converter can be activated by the TGRA input capture/compare match for a channel. If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel, a request to begin A/D conversion is sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is begun. In the H8S/2268 Group TPU, a total of three TGRA input capture/compare match interrupts can be used as A/D converter conversion start sources, one for each channel (channels 0 to 2). While in the H8S/2264 Group TPU, a total of two TGRA input capture/compare match interrupts can be used, one for each channel (channels 1 and 2). Rev. 3.00, 08/03, page 216 of 612 10.9 Operation Timing 10.9.1 Input/Output Timing TCNT Count Timing: Figure 10.31 shows TCNT count timing in internal clock operation, and figure 10.32 shows TCNT count timing in external clock operation. Internal clock Rising edge Falling edge TCNT input clock TCNT N-1 N N+1 N+2 Figure 10.31 Count Timing in Internal Clock Operation External clock Rising edge Falling edge Falling edge TCNT input clock TCNT N-1 N N+1 N+2 Figure 10.32 Count Timing in External Clock Operation Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin. After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Rev. 3.00, 08/03, page 217 of 612 Figure 10.33 shows output compare output timing. TCNT input clock N TCNT N+1 N TGR Compare match signal TIOC pin Figure 10.33 Output Compare Output Timing Input Capture Signal Timing: Figure 10.34 shows input capture signal timing. Input capture input Input capture signal TCNT N N+1 N+2 N TGR Figure 10.34 Input Capture Input Signal Timing Rev. 3.00, 08/03, page 218 of 612 N+2 Timing for Counter Clearing by Compare Match/Input Capture: Figure 10.35 shows the timing when counter clearing on compare match is specified, and figure 10.36 shows the timing when counter clearing on input capture is specified. Compare match signal Counter clear signal TCNT N TGR N H'0000 Figure 10.35 Counter Clear Timing (Compare Match) Input capture signal Counter clear signal TCNT TGR N H'0000 N Figure 10.36 Counter Clear Timing (Input Capture) Rev. 3.00, 08/03, page 219 of 612 Buffer Operation Timing (H8S/2268 Group Only): Figures 10.37 and 10.38 show the timing in buffer operation. n TCNT n+1 Compare match signal TGRA, TGRB n TGRC, TGRD N N Figure 10.37 Buffer Operation Timing (Compare Match) Input capture signal TCNT N TGRA, TGRB n TGRC, TGRD N+1 N N+1 n N Figure 10.38 Buffer Operation Timing (Input Capture) Rev. 3.00, 08/03, page 220 of 612 10.9.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 10.39 shows the timing for setting of the TGF flag in TSR on compare match, and TGI interrupt request signal timing. TCNT input clock TCNT N TGR N N+1 Compare match signal TGF flag TGI interrupt Figure 10.39 TGI Interrupt Timing (Compare Match) TGF Flag Setting Timing in Case of Input Capture: Figure 10.40 shows the timing for setting of the TGF flag in TSR on input capture, and TGI interrupt request signal timing. Input capture signal TCNT TGR N N TGF flag TGI interrupt Figure 10.40 TGI Interrupt Timing (Input Capture) Rev. 3.00, 08/03, page 221 of 612 TCFV Flag/TCFU Flag Setting Timing: Figure 10.41 shows the timing for setting of the TCFV flag in TSR on overflow, and TCIV interrupt request signal timing. Figure 10.42 shows the timing for setting of the TCFU flag in TSR on underflow, and TCIU interrupt request signal timing in the H8S/2268 Group. TCNT input clock TCNT (overflow) H'FFFF H'0000 Overflow signal TCFV flag TCIV interrupt Figure 10.41 TCIV Interrupt Setting Timing TCNT input clock TCNT (underflow) H'0000 H'FFFF Underflow signal TCFU flag TCIU interrupt Figure 10.42 TCIU Interrupt Setting Timing (H8S/2268 Group Only) Rev. 3.00, 08/03, page 222 of 612 Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC is activated in the H8S/2268 Group, the flag is cleared automatically. Figure 10.43 shows the timing for status flag clearing by the CPU, and figure 10.44 shows the timing for status flag clearing by the DTC. TSR write cycle T1 T2 Address TSR address Write signal Status flag Interrupt request signal Figure 10.43 Timing for Status Flag Clearing by CPU DTC read cycle T1 T2 DTC write cycle T1 T2 Address Source address Destination address Status flag Interrupt request signal Figure 10.44 Timing for Status Flag Clearing by DTC Activation (H8S/2268 Group Only) Rev. 3.00, 08/03, page 223 of 612 10.10 Usage Notes 10.10.1 Module Stop Mode Setting TPU operation can be disabled or enabled using the module stop control register. The initial setting is for TPU operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 22, Power-Down Modes. 10.10.2 Input Clock Restrictions The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly at narrower pulse widths. In the H8S/2268 Group phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 10.45 shows the input clock conditions in phase counting mode. Overlap Phase Phase differdifference Overlap ence Pulse width Pulse width TCLKA (TCLKC) TCLKB (TCLKD) Pulse width Pulse width Notes: Phase difference and overlap : 1.5 states or more Pulse width : 2.5 states or more Figure 10.45 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode (H8S/2268 Group Only) Rev. 3.00, 08/03, page 224 of 612 10.10.3 Caution on Period Setting When counter clearing on compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: f= (N + 1) Where f : Counter frequency : Operating frequency N : TGR set value 10.10.4 Contention between TCNT Write and Clear Operations If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 10.46 shows the timing in this case. TCNT write cycle T1 T2 TCNT address Address Write signal Counter clear signal TCNT N H'0000 Figure 10.46 Contention between TCNT Write and Clear Operations Rev. 3.00, 08/03, page 225 of 612 10.10.5 Contention between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 10.47 shows the timing in this case. TCNT write cycle T1 T2 TCNT address Address Write signal TCNT input clock TCNT N M TCNT write data Figure 10.47 Contention between TCNT Write and Increment Operations 10.10.6 Contention between TGR Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is inhibited. A compare match does not occur even if the previous value is written. Rev. 3.00, 08/03, page 226 of 612 Figure 10.48 shows the timing in this case. TGR write cycle T1 T2 TGR address Address Write signal Compare match signal Inhibited TCNT N N+1 TGR N M TGR write data Figure 10.48 Contention between TGR Write and Compare Match 10.10.7 Contention between Buffer Register Write and Compare Match (H8S/2268 Group Only) If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR by the buffer operation will be that in the buffer prior to the write. Figure 10.49 shows the timing in this case. TGR write cycle T1 T2 Buffer register address Address Write signal Compare match signal Buffer register write data Buffer register TGR N M N Figure 10.49 Contention between Buffer Register Write and Compare Match Rev. 3.00, 08/03, page 227 of 612 10.10.8 Contention between TGR Read and Input Capture If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be that in the buffer after input capture transfer. Figure 10.50 shows the timing in this case. TGR read cycle T1 T2 TGR address Address Read signal Input capture signal TGR X Internal data bus M M Figure 10.50 Contention between TGR Read and Input Capture 10.10.9 Contention between TGR Write and Input Capture If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 10.51 shows the timing in this case. Rev. 3.00, 08/03, page 228 of 612 TGR write cycle T1 T2 TGR address Address Write signal Input capture signal TCNT M M TGR Figure 10.51 Contention between TGR Write and Input Capture 10.10.10 Contention between Buffer Register Write and Input Capture (H8S/2268 Group Only) If an input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 10.52 shows the timing in this case. Buffer register write cycle T1 T2 Buffer register address Address Write signal Input capture signal TCNT TGR Buffer register N M N M Figure 10.52 Contention between Buffer Register Write and Input Capture Rev. 3.00, 08/03, page 229 of 612 10.10.11 Contention between Overflow/Underflow and Counter Clearing In the H8S/2268 Group, if overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. In the H8S/2264 Group, if overflow and counter clearing occur simultaneously, the TCFV flag in TSR is not set and TCNT clearing takes precedence. Figure 10.53 shows the operation timing when a TGR compare match is specified as the clearing source, and when H'FFFF is set in TGR. TCNT input clock TCNT H'FFFF H'0000 Counter clear signal TGF Disabled TCFV Figure 10.53 Contention between Overflow and Counter Clearing Rev. 3.00, 08/03, page 230 of 612 10.10.12 Contention between TCNT Write and Overflow/Underflow In the H8S/2268 Group, if there is an up-count or down-count in the T2 state of a TCNT write cycle and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. In the H8S/2264 Group, if there is an up-count in the T2 state of a TCNT write cycle and overflow occurs, the TCNT write takes precedence and the TCFV flag in TSR is not set. Figure 10.54 shows the operation timing when there is contention between TCNT write and overflow. TCNT write cycle T1 T2 TCNT address Address Write signal TCNT TCNT write data H'FFFF M TCFV flag Figure 10.54 Contention between TCNT Write and Overflow 10.10.13 Multiplexing of I/O Pins In the H8S/2268 Group, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin. In the H8S/2264 Group, the TCLKC input pin is multiplexed with the TIOCB1 I/O pin. When an external clock is input, compare match output should not be performed from a multiplexed pin. 10.10.14 Interrupts in Module Stop Mode If module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source, or the DTC activation source (the H8S/2268 Group only). Interrupts should therefore be disabled before entering module stop mode. Rev. 3.00, 08/03, page 231 of 612 Rev. 3.00, 08/03, page 232 of 612 Section 11 8-Bit Timers The H8S/2268 Group has an on-chip 8-bit timer module with four channels (TMR_0, TMR_1, TMR_2 and TMR_3) operating on the basis of an 8-bit counter and an 8-bit reload timer with four channels (TMR_4). The H8S/2264 Group has an on-chip 8-bit timer module with two channels (TMR_0 and TMR_1) operating on the basis of an 8-bit counter. 11.1 8-Bit Timer Module (TMR_0, TMR_1, TMR_2, and TMR_3) The 8-bit timer module can be used to count external events and be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two registers. 11.1.1 Features * Selection of clock sources Selected from three internal clocks (/8, /64, and /8192) and an external clock. * Selection of three ways to clear the counters The counters can be cleared on compare-match A or B, or by an external reset signal. * Timer output controlled by two compare-match signals The timer output signal in each channel is controlled by two independent compare-match signals, enabling the timer to be used for various applications, such as the generation of pulse output or PWM output with an arbitrary duty cycle. * Cascading of the two channels The module can operate as a 16-bit timer using channel 0 (channel 2*) as the upper half and channel 1 (channel 3*) as the lower half (16-bit count mode). Channel 1 (channel 3*) can be used to count channel 0 (channel 2*) compare-match occurrences (compare-match count mode). * Multiple interrupt sources for each channel Two compare-match interrupts and one overflow interrupt can be requested independently. * Generation of A/D conversion start trigger Channel 0 compare-match signal can be used as the A/D conversion start trigger. * Module stop mode can be set At initialization, the 8-bit timer operation is halted. Register access is enabled by canceling the module stop mode. Note: * Supported only by the H8S/2268 Group. TIMH220B_000020020700 Rev. 3.00, 08/03, page 233 of 612 Figure 11.1 shows a block diagram of the 8-bit timer module (TMR_0 and TMR_1). External clock sources Internal clock sources TMCI01 TMR0 /8 /64 /8192 Clock 1 Clock 0 Clock select Compare-match A1 Compare-match A0 Comparator A_0 Overflow 1 Overflow 0 TMO TMRI01 TCNT_0 TCORA_1 Comparator A_1 TCNT_1 Clear 0 Clear 1 Compare-match B1 Compare-match B0 Comparator B_0 TMO1 Comparator B_1 Control logic TCORB_0 TCORB_1 TCSR_0 TCSR_1 TCR_0 TCR_1 A/D CMIA0 CMIB0 OVI0 CMIA1 CMIB1 OVI1 Interrupt signals Figure 11.1 Block Diagram of 8-Bit Timer Module [Legend] TCORA_0: Time constant register A_0 TCORB_0: Time constant register B_0 TCNT_0: Timer counter_0 TCSR_0: Timer control/status register_0 TCR_0: Timer control register_0 TCORA_1: Time constant register A_1 TCORB_1: Time constant register B_1 TCNT_1: Timer counter_1 TCSR_1: Timer control/status register_1 TCR_1: Timer control register_1 Rev. 3.00, 08/03, page 234 of 612 Internal bus TCORA_0 11.2 Input/Output Pins Table 11.1 summarizes the input and output pins of the 8-bit timer module. Table 11.1 Pin Configuration Channel Name Symbol I/O Function 0 Timer output TMO0 Output Output controlled by compare-match 1 Timer output TMO1 Output Output controlled by compare-match Common to 0 and 1 Timer clock input TMCI01 Input External clock input for the counter Timer reset input TMRI01 Input External reset input for the counter 2* Timer output TMO2 Output Output controlled by compare-match 3* Timer output TMO3 Output Output controlled by compare-match Common to 2 and 3* Timer clock input TMCI23 Input External clock input for the counter Timer reset input TMRI23 Input External reset input for the counter Note: 11.3 * Supported only by the H8S/2268 Group. Register Descriptions The 8-bit timer has the following registers. For details on the module stop register, refer to section 22.1.2, Module Stop Registers A to D (MSTPCRA to MSTPCRD). * Timer counter_0 (TCNT_0) * Time constant register A_0 (TCORA_0) * Time constant register B_0 (TCORB_0) * Timer control register_0 (TCR_0) * Timer control/status register_0 (TCSR_0) * Timer counter_1 (TCNT_1) * Time constant register A_1 (TCORA_1) * Time constant register B_1 (TCORB_1) * Timer control register_1 (TCR_1) * Timer control/status register_1 (TCSR_1) * Timer counter_2 (TCNT_2)* * Time constant register A_2 (TCORA_2)* * Time constant register B_2 (TCORB_2)* * Timer control register_2 (TCR_2)* * Timer control/status register_2 (TCSR_2)* * Timer counter_3 (TCNT_3)* * Time constant register A_3 (TCORA_3)* Rev. 3.00, 08/03, page 235 of 612 * Time constant register B_3 (TCORB_3)* * Timer control register_3 (TCR_3)* * Timer control/status register_3 (TCSR_3)* Note: * Supported only by the H8S/2268 Group. 11.3.1 Timer Counter (TCNT) Each TCNT is an 8-bit up-counter. TCNT_0 and TCNT_1 (TCNT_2 and TCNT_3) comprise a single 16-bit register, so they can be accessed together by word access. TCNT increments on pulses generated from an internal or external clock source. This clock source is selected by clock select bits CKS2 to CKS0 in TCR. TCNT can be cleared by an external reset input signal or compare-match signals A and B. Counter clear bits CCLR1 and CCLR0 in TCR select the method of clearing. When TCNT overflows from H'FF to H'00, the overflow flag (OVF) in TCSR is set to 1. 11.3.2 Time Constant Register A (TCORA) TCORA is an 8-bit readable/writable register. TCORA_0 and TCORA_1 (TCORA_2 and TCORA_3) comprise a single 16-bit register, so they can be accessed together by word access. TCORA is continually compared with the value in TCNT. When a match is detected, the corresponding compare-match flag A (CMFA) in TCSR is set. Note, however, that comparison is disabled during the T2 state of a TCORA write cycle. The timer output from the TMO pin can be freely controlled by the compare-match signal A and the settings of output select bits OS1 and OS0 in TCSR. The initial value of TCORA is H'FF. 11.3.3 Time Constant Register B (TCORB) TCORB is an 8-bit readable/writable register. TCORB_0 and TCORB_1 (TCORB_2 and TCORB_3) comprise a single 16-bit register, so they can be accessed together by word access. TCORB is continually compared with the value in TCNT. When a match is detected, the corresponding compare-match flag B (CMFB) in TCSR is set. Note, however, that comparison is disabled during the T2 state of a TCORB write cycle. The timer output from the TMO pin can be freely controlled by the compare-match signal B and the settings of output select bits OS1 and OS0 in TCSR. Rev. 3.00, 08/03, page 236 of 612 The initial value of TCORB is H'FF. 11.3.4 Timer Control Register (TCR) TCR selects the TCNT clock source and the time at which TCNT is cleared, and controls interrupt requests. Bit Bit Name Initial Value R/W Description 7 CMIEB 0 R/W Compare-Match Interrupt Enable B Selects whether the CMFB interrupt request (CMIB) is enabled or disabled when the CMFB flag in TCSR is set to 1. 0: CMFB interrupt request (CMIB) is disabled 1: CMFB interrupt request (CMIB) is enabled 6 CMIEA 0 R/W Compare-Match Interrupt Enable A Selects whether the CMFA interrupt request (CMIA) is enabled or disabled when the CMFA flag in TCSR is set to 1. 0: CMFA interrupt request (CMIA) is disabled 1: CMFA interrupt request (CMIA) is enabled 5 OVIE 0 R/W Timer Overflow Interrupt Enable Selects whether the OVF interrupt request (OVI) is enabled or disabled when the OVF flag in TCSR is set to 1. 0: OVF interrupt request (OVI) is disabled 1: OVF interrupt request (OVI) is enabled 4 CCLR1 0 R/W Counter Clear 1 and 0 3 CCLR0 0 R/W These bits select the method by which TCNT is cleared 00: Clearing is disabled 01: Cleared on compare-match A 10: Cleared on compare-match B 11: Cleared on rising edge of external reset input Rev. 3.00, 08/03, page 237 of 612 Bit Bit Name Initial Value R/W Description 2 to 0 CKS2 0 R/W Clock Select 2 to 0 CKS1 0 R/W CKS0 0 R/W The input clock can be selected from three clocks divided from the system clock (). When use of an external clock is selected, three types of count can be selected: at the rising edge, the falling edge, and both rising and falling edges. 000: Clock input disabled 001: /8 internal clock source, counted on the falling edge 010: /64 internal clock source, counted on the falling edge 011: /8192 internal clock source, counted on the falling edge 100: For channel 0: Counted on TCNT1 overflow signal* For channel 1: Counted on TCNT0 compare-matchA signal* For channel 2: Counted on TCNT3 overflow signal* For channel 3: Counted on TCNT2 compare-matchA signal* 101: External clock source, counted at rising edge 110: External clock source, counted at falling edge 111: External clock source, counted at both rising and falling edges Note: * If the count input of channel 0 (channel 2) is the TCNT1 (TCNT3) overflow signal and that of channel 1 (channel 3) is the TCNT0 (TCNT2) compare-match signal, no incrementing clock will be generated. Do not use this setting. Rev. 3.00, 08/03, page 238 of 612 11.3.5 Timer Control/Status Register (TCSR) TCSR indicates status flags and controls compare-match output. * TCSR_0 Bit 7 Bit Name CMFB Initial Value 0 R/W Description 1 R/(W)* Compare-Match Flag B [Setting condition] When TCNT = TCORB [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB. 2 The DTC* is activated by the CMIB interrupt and the 2 DISEL bit = 0 in MRB of the DTC* . 6 CMFA 0 1 R/(W)* Compare-match Flag A [Setting condition] When TCNT = TCORA [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA. 2 The DTC* is activated by the CMIA interrupt and DISEL 2 bit = 0 in MRB of the DTC* . 5 OVF 0 1 R/(W)* Timer Overflow Flag [Setting condition] When TCNT overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 4 ADTE 0 R/W A/D Trigger Enable Enables or disables A/D converter start requests by compare-match A. 0: A/D converter start requests by compare-match A are disabled 1: A/D converter start requests by compare-match A are enabled Rev. 3.00, 08/03, page 239 of 612 Bit Bit Name Initial Value R/W Description 3 OS3 0 R/W Output Select 3 and 2 2 OS2 0 R/W These bits specify how the timer output level is to be changed by a compare-match B of TCORB and TCNT. 00: No change when compare-match B occurs 01: 0 is output when compare-match B occurs 10: 1 is output when compare-match B occurs 11: Output is inverted when compare-match B occurs (toggle output) 1 OS1 0 R/W Output Select 1 and 0 0 OS0 0 R/W These bits specify how the timer output level is to be changed by a compare-match A of TCORA and TCNT. 00: No change when compare-match A occurs 01: 0 is output when compare-match A occurs 10: 1 is output when compare-match A occurs 11: Output is inverted when compare-match A occurs (toggle output) Notes: 1. Only 0 can be written to this bit, to clear the flag. 2. Supported only by the H8S/2268 Group. * TCSR_1 and TCSR_3 Bit 7 Bit Name CMFB Initial Value 0 R/W Description 1 R/(W)* Compare-Match Flag B [Setting condition] When TCNT = TCORB [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB 2 The DTC* is activated by the CMIB interrupt and the 2 DISEL Bit = 0 in MRB of the DTC* . 6 CMFA 0 1 R/(W)* Compare-match Flag A [Setting condition] When TCNT = TCORA [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA 2 The DTC* is activated by the CMIA interrupt and the 2 DISEL Bit = 0 in MRB of the DTC* . Rev. 3.00, 08/03, page 240 of 612 Bit 5 Bit Name OVF Initial Value 0 R/W Description 1 R/(W)* Timer Overflow Flag [Setting condition] When TCNT overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 4 1 Reserved This bit is always read as 1 and cannot be modified. 3 OS3 0 R/W Output Select 3 and 2 2 OS2 0 R/W These bits specify how the timer output level is to be changed by a compare-match B of TCORB and TCNT. 00: No change when compare-match B occurs 01: 0 is output when compare-match B occurs 10: 1 is output when compare-match B occurs 11: Output is inverted when compare-match B occurs (toggle output) 1 OS1 0 R/W Output Select 1 and 0 0 OS0 0 R/W These bits specify how the timer output level is to be changed by a compare-match A of TCORA and TCNT. 00: No change when compare-match A occurs 01: 0 is output when compare-match A occurs 10: 1 is output when compare-match A occurs 11: Output is inverted when compare-match A occurs (toggle output) Notes: 1. Only 0 can be written to this bit, to clear the flag. 2. Supported only by the H8S/2268 Group. * TCSR_2 Bit 7 Bit Name CMFB Initial Value 0 R/W Description 1 R/(W)* Compare-Match Flag B [Setting condition] When TCNT = TCORB [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB 2 The DTC* is activated by the CMIB interrupt and the 2 DISEL Bit = 0 in MRB of the DTC* . Rev. 3.00, 08/03, page 241 of 612 Bit Bit Name Initial Value R/W 6 CMFA 0 R/(W)* Compare-match Flag A Description 1 [Setting condition] When TCNT = TCORA [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA 2 The DTC* is activated by the CMIA interrupt and the 2 DISEL Bit = 0 in MRB of the DTC* . 5 OVF 0 1 R/(W)* Timer Overflow Flag [Setting condition] When TCNT overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 4 0 R/W Reserved This bit is a readable/writable bit, but the write value should always be 0. 3 OS3 0 R/W Output Select 3 and 2 2 OS2 0 R/W These bits specify how the timer output level is to be changed by a compare-match B of TCORB and TCNT. 00: No change when compare-match B occurs 01: 0 is output when compare-match B occurs 10: 1 is output when compare-match B occurs 11: Output is inverted when compare-match B occurs (toggle output) 1 OS1 0 R/W Output Select 1 and 0 0 OS0 0 R/W These bits specify how the timer output level is to be changed by a compare-match A of TCORA and TCNT. 00: No change when compare-match A occurs 01: 0 is output when compare-match A occurs 10: 1 is output when compare-match A occurs 11: Output is inverted when compare-match A occurs (toggle output) Notes: 1. Only 0 can be written to this bit, to clear the flag. 2. Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 242 of 612 11.4 Operation 11.4.1 Pulse Output Figure 11.2 shows an example of arbitrary duty pulse output. 1. Set TCR in CCR1 to 0 and CCLR0 to 1 to clear TCNT by a TCORA compare-match. 2. Set OS3 to OS0 bits in TCSR to B'0110 to output 1 by a TCORA compare-match and 0 by a TCORB compare-match. By the above settings, waveforms with the cycle of TCORA and the pulse width of TCORB can be output without software intervention. TCNT H'FF Counter clear TCORA TCORB H'00 TMO Figure 11.2 Example of Pulse Output Rev. 3.00, 08/03, page 243 of 612 11.5 Operation Timing 11.5.1 TCNT Incrementation Timing Figure 11.3 shows the TCNT count timing with internal clock source. Figure 11.4 shows the TCNT incrementation timing with external clock source. The pulse width of the external clock for incrementation at single edge must be at least 1.5 status, and at least 2.5 states for incrementation at both edges. The counter will not increment correctly if the pulse width is less than these values. Internal clock TCNT input clock TCNT N-1 N N+1 Figure 11.3 Count Timing for Internal Clock Input External clock input pin TCNT input clock TCNT N-1 N N+1 Figure 11.4 Count Timing for External Clock Input 11.5.2 Timing of CMFA and CMFB Setting When a Compare-Match Occurs The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the TCOR and TCNT values match. The compare-match signal is generated at the last state in which the match is true, just before the timer counter is updated. Therefore, when TCOR and TCNT match, the compare-match signal is not generated until the next incrementation clock input. Figure 11.5 shows the timing of CMF flag setting. Rev. 3.00, 08/03, page 244 of 612 TCNT N TCOR N N+1 Compare-match signal CMF Figure 11.5 Timing of CMF Setting 11.5.3 Timing of Timer Output When a Compare-Match Occurs When a compare-match occurs, the timer output changes as specified by the output select bits (OS3 to OS0) in TCSR. Figure 11.6 shows the timing when the output is set to toggle at comparematch A. Compare-match A signal Timer output pin Figure 11.6 Timing of Timer Output 11.5.4 Timing of Compare-Match Clear When a Compare-Match Occurs TCNT is cleared when compare-match A or B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 11.7 shows the timing of this operation. Compare-match signal TCNT N H'00 Figure 11.7 Timing of Compare-Match Clear Rev. 3.00, 08/03, page 245 of 612 11.5.5 TCNT External Reset Timing TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The width of the clearing pulse must be at least 1.5 states. Figure 11.8 shows the timing of this operation. External reset input pin Clear signal TCNT N-1 N H'00 Figure 11.8 Timing of Clearing by External Reset Input 11.5.6 Timing of Overflow Flag (OVF) Setting OVF in TCSR is set to 1 when the timer count overflows (changes from H'FF to H'00). Figure 11.9 shows the timing of this operation. TCNT H'FF H'00 Overflow signal OVF Figure 11.9 Timing of OVF Setting Rev. 3.00, 08/03, page 246 of 612 11.6 Operation with Cascaded Connection If bits CKS2 to CKS0 in one of TCR_0 and TCR_1 (TCR_2 and TCR_3) are set to B'100, the 8bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer can be used (16-bit timer mode) or compare-matches of 8-bit channel 0 (channel 2) can be counted by the timer of channel 1 (channel 3) (compare-match count mode). In the case that channel 0 is connected to channel 1 in cascade, the timer operates as described below. 11.6.1 16-Bit Count Mode When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. * Setting of compare-match flags The CMF flag in TCSR_0 is set to 1 when a 16-bit compare-match occurs. The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare-match occurs. * Counter clear specification If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare-match, the 16-bit counter (TCNT_0 and TCNT_1 together) is cleared when a 16-bit comparematch occurs. The 16-bit counter (TCNT_0 and TCNT_1 together) is cleared even if counter clear by the TMRI01 pin has also been set. The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot be cleared independently. * Pin output Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR_0 is in accordance with the 16-bit compare-match conditions. Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR_1 is in accordance with the lower 8-bit compare-match conditions. 11.6.2 Compare-Match Count Mode When bits CKS2 to CKS0 in TCR_1 are B'100, TCNT_1 counts compare-match A for channel 0. Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag, generation of interrupts, output from the TMO pin, and counter clearing are in accordance with the settings for each channel. Rev. 3.00, 08/03, page 247 of 612 11.7 Interrupt Sources 11.7.1 Interrupt Sources and DTC Activation The 8-bit timer can generate three types of interrupt: CMIA, CMIB, and OVI. Table 11.2 shows the interrupt sources and priority. Each interrupt source can be enabled or disabled independently by interrupt enable bits in TCR. Independent signals are sent to the interrupt controller for each interrupt. In the H8S/2268 Group, it is also possible to activate the DTC by means of CMIA and CMIB interrupts. Table 11.2 8-Bit Timer Interrupt Sources Interrupt source Description Flag DTC Activation* Interrupt Priority CMIA0 TCORA_0 compare-match CMFA Possible High CMIB0 TCORB_0 compare-match CMFB Possible OVI0 TCNT_0 overflow OVF Not possible Low CMIA1 TCORA_1 compare-match CMFA Possible High CMIB1 TCORB_1 compare-match CMFB Possible OVI1 TCNT_1 overflow OVF Not possible Low CMIA2* TCORA_2 compare-match CMFA Possible High CMIB2* TCORB_2 compare-match CMFB Possible OVI2* TCNT_2 overflow OVF Not possible Low CMIA3* TCORA_3 compare-match CMFA Possible High CMIB3* TCORB_3 compare-match CMFB Possible OVI3* TCNT_3 overflow OVF Not possible Note: 11.7.2 * Low Supported only by the H8S/2268 Group. A/D Converter Activation The A/D converter can be activated only by channel 0 compare match A. If the ADTE bit in TCSR0 is set to 1 when the CMFA flag is set to 1 by the occurrence of channel 0 compare match A, a request to start A/D conversion is sent to the A/D converter. If the 8-bit timer conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started. Rev. 3.00, 08/03, page 248 of 612 11.8 Usage Notes 11.8.1 Contention between TCNT Write and Clear If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. Figure 11.10 shows this operation. TCNT write cycle by CPU T1 T2 Address TCNT address Internal write signal Counter clear signal TCNT N H'00 Figure 11.10 Contention between TCNT Write and Clear 11.8.2 Contention between TCNT Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the counter is not incremented. Figure 11.11 shows this operation. TCNT write cycle by CPU T1 T2 Address TCNT address Internal write signal TCNT input clock TCNT N M Counter write data Figure 11.11 Contention between TCNT Write and Increment Rev. 3.00, 08/03, page 249 of 612 11.8.3 Contention between TCOR Write and Compare-Match During the T2 state of a TCOR write cycle, the TCOR write has priority even if a compare-match occurs and the compare-match signal is disabled. Figure 11.12 shows this operation. TCOR write cycle by CPU T1 T2 Address TCOR address Internal write signal TCNT N N+1 TCOR N M TCOR write data Compare-match signal Inhibited Figure 11.12 Contention between TCOR Write and Compare-Match 11.8.4 Contention between Compare-Matches A and B If compare-matches A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output states set for compare-match A and compare-match B, as shown in table 11.3. Table 11.3 Timer Output Priorities Output Setting Priority Toggle output High 1 output 0 output No change Rev. 3.00, 08/03, page 250 of 612 Low 11.8.5 Switching of Internal Clocks and TCNT Operation TCNT may increment erroneously when the internal clock is switched over. Table 11.4 shows the relationship between the timing at which the internal clock is switched (by writing to the CKS1 and CKS0 bits) and the TCNT operation When the TCNT clock is generated from an internal clock, the falling edge of the internal clock pulse is detected. If clock switching causes a change from high to low level, as shown in no. 3 in table 11.4, a TCNT clock pulse is generated on the assumption that the switchover is a falling edge. This increments TCNT. Erroneous incrementation can also happen when switching between internal and external clocks. Table 11.4 Switching of Internal Clock and TCNT Operation Timing of Switchover by Means of CKS1 and No. CKS0 Bits TCNT Clock Operation 1 Switching from low to 1 low* Clock before switchover Clock after switchover TCNT clock TCNT N N+1 CKS bit rewrite 2 TCNT Switching from low to 2 high* H'FF Counter clear TCORA TCORB H'00 TMO Rev. 3.00, 08/03, page 251 of 612 Timing of Switchover by Means of CKS1 and No. CKS0 Bits TCNT Clock Operation 3 Switching from high to 3 low* Clock before switchover Clock after switchover *4 TCNT clock TCNT N N+1 N+2 CKS bit rewrite 4 Switching from high to high Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit rewrite Notes: 1. 2. 3. 4. 11.8.6 Includes switching from low to stop, and from stop to low. Includes switching from stop to high. Includes switching from high to stop. Generated on the assumption that the switchover is a falling edge; TCNT is incremented. Contention between Interrupts and Module Stop Mode If module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DTC activation source. Interrupts should therefore be disabled before entering module stop mode. Rev. 3.00, 08/03, page 252 of 612 11.9 8-Bit Reload Timer (TMR_4) (H8S/2268 Group Only) The 8-bit reload timer comprises an 8-bit up-counter with four channels, and has two functions, the interval function and automatic reload function. 11.9.1 Features * Selection of clock sources Selected from 14 internal clocks (/32768, /8192, /2048, /512, /128, /32, /8, /2, SUB/256, SUB/128, SUB/64, SUB/32, SUB/8 and SUB/2) and an external clock. * Interrupts requested by counter overflow * Operation with cascaded connection (the lower the channel number, the higher the bit in the connected timer) Connecting two timers (channels 4 and 5, channels 5 and 6, or channels 6 and 7): The module operates as a 16-bit timer Connecting three timers (channels 4 to 6 or channels 5 to 7): The module operates as a 24bit timer Connecting four timers (channels 4 to 7): The module operates as a 32-bit timer * Module stop mode can be set At initialization, the 8-bit reload timer is halted. Register access is enabled by canceling the module stop mode. Rev. 3.00, 08/03, page 253 of 612 Figure 11.13 shows a block diagram of the 8-bit reload timer. External clock TMCI4 Internal clock /2 /8 /32 /128 /512 TCR_4 TCR_5 TCR_6 TCR_7 Clock select Clock select Clock select Clock select TCNT_4 TCNT_5 TCNT_6 TCNT_7 TLR_5 TLR_6 TLR_7 /32768 SUB/2 SUB/8 SUB/32 SUB/64 SUB/128 Internal bus /8192 Module bus /2048 reload SUB/256 TLR_4 Bus interface Interrupt contorol OVI4 [Legend] TCR_4: TCNT_4: TLR_4: TCR_5: TCNT_5: TLR_5: OVI5 Timer control register 4 Timer counter 4 Timer reload register 4 Timer control register 5 Timer counter 5 Timer reload register 5 OVI6 TCR_6: TCNT_6: TLR_6: TCR_7: TCNT_7: TLR_7: OVI7 Timer control register 6 Timer counter 6 Timer reload register 6 Timer control register 7 Timer counter 7 Timer reload register 7 Figure 11.13 Block Diagram of 8-Bit Reload Timer 11.9.2 Input/Output Pins The following table shows the pin configuration for the 8-bit timer module. Name Symbol I/O Function Timer clock input pin TMCI4 Input External clock input for the counter Note: Voltage applied to the TMCI4 input pin should be within the range, AVss TMCI4 AVcc. Rev. 3.00, 08/03, page 254 of 612 11.10 Register Descriptions The 8-bit reload timer has the following registers. For details on the module stop control register, refer to section 22.1.2, Module Stop Control Registers A to D (MSTPCRA to MSTPCRD). * Timer control register (TCR) * Timer Counter (TCNT) * Timer reload register (TLR) TCNT or TLR can operate as a 16-bit timer using TCNT_4 or TLR_4 (TCNT_6 or TLR_6) as the upper half and TCNT_5 or TLR_5 (TCNT_7 or TLR_7) as the lower half. 11.10.1 Timer Control Registers 4 to 7 (TCR_4 to TCR_7) TCR selects the automatic reload function and TCNT clock source, and controls interrupt requests. Bit Bit Name Initial Value R/W Description 7 ARSL 0 R/W Automatic Reload Function Select Selects the automatic reload function 0: The interval function is selected 1: The automatic reload function is selected 6 OVF 0 R/(W)* Timer Overflow Flag Indicates that TCNT overflows from H'FF to H'00. 0: [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 1: [Setting condition] When TCNT overflows from H'FF to H'00 5 OVIE 0 R/W Timer Overflow Interrupt Enable Selects whether the OVF interrupt request (OVI) is enabled or disabled when the OVF flag in TCSR is set to 1. 0: OVF interrupt request (OVI) is disabled 1: OVF interrupt request (OVI) is enabled 4, 3 All 1 Reserved These bits are always read as 1 and cannot be modified. Rev. 3.00, 08/03, page 255 of 612 Bit Bit Name Initial Value R/W Description 2 to 0 CKS2 0 R/W Clock Select 2 to 0 CKS1 0 R/W CKS0 0 R/W The input clock can be selected from internal clocks and an external clock, which are divided from the system clock () or subclock (SUB). Channel4 Note: * Channel5 Channel6 Channel7 000: /32768 /8192 /32768 /8192 001: /2048 /512 /2048 /512 010: /128 /32 /128 /32 011: /8 /2 /8 /2 100: SUB /256 SUB /128 SUB /256 SUB /128 101: SUB /64 SUB /32 SUB /64 SUB /32 110: SUB /8 SUB /2 SUB /8 SUB /2 111: TCNT_5 overflow TCNT_6 overflow TCNT_7 overflow Count of the rising clock of the external clock. Only a 0 can be written to this bit, to clear the flag. 11.10.2 Timer Counters 4 to 7 (TCNT4 to TCNT7) Each TCNT is an 8-bit readable up-counter and increments on clock pulses generated from an internal or external clock source. This clock source is selected by clock select bits CKS2 to CKS0 in TCR TCNT_4 and TCNT_5, or TCNT_6 and TCNT_7 comprise a single 16-bit register, and can be accessed simultaneously by word access. When TCNT overflows from H'FF to H'00, the overflow flag (OVF) in TCR is set to 1. TCNT is initialized to H'00 by a reset or in hardware standby mode. 11.10.3 Time Reload Registers 4 to 7 (TLR_4 to TLR_7) Each TLR is an 8-bit writable register and sets a reload value for TCNT. When a reload value is set to TLR, the value is simultaneously load to TCNT and incrementation starts from the value. When TCNT overflows during automatic reload operation, the TLR value is written to TCNT. Therefore, the overflow cycle can be set within the range from 1 to 256 input clock cycles. TLR_4 and TLR_5, or TLR_6 and TLR_7 comprise a single 16-bit register, and can be accessed simultaneously by word access. Rev. 3.00, 08/03, page 256 of 612 TLR is initialized to H'00 by a reset or in hardware standby mode. 11.11 Operation 11.11.1 Interval Timer Operation When the ARSL bit in TCR is set to 0, the timer operates as an interval timer. After a module stop mode is canceled, the timer continues incrementation as an interval timer without stopping because TCNT is initialized to H'00 and TLR is cleared to 0 by a reset. The input clock source can be selected from 14 internal clocks output from the prescaler unit and an external clock from the TMCI4 input pin, using the CKS2 to CKS0 bits in TCR. When a clock is input after the TCNT value has been H'FF, the timer overflows and OVF in TCR is set to 1. At this time, if OVIE in TCR is 1, an interrupt is generated. When an overflow occurs, the TCNT count value is cleared to H'00 and TCNT restarts incrementation. If a value is set to TLR during interval timer operation, the value is also written to TCNT. This operation timing is shown in figure 11.14. TCNT value Overflow H'FF Overflow Overflow Overflow Time H'00 MSTPD5=0 ARSL=0 OVF OVF OVF OVF OVF: Timer overflow interrupt request generation Figure 11.14 Operation in Interval Timer Mode Rev. 3.00, 08/03, page 257 of 612 11.11.2 Automatic Reload Timer Operation When the ARSL bit in TCR is set to 1, the timer operates as an automatic reload timer. When a reload value is set to TLR, the value is also loaded to TCNT simultaneously, and TCNT starts incrementation from the value. If a clock is input after the TCNT count value reaches H'FF, the timer overflows, the TLR value is written to TCNT, and incrementation is continued from the value. Therefore, the overflow cycle can be set within the range from 1 to 256, using a TLR value. Clock sources and interrupts in automatic reload operation are the same as those in interval operation. If TLR is re-set during automatic reload operation, the value is also set to TCNT. This operation timing is shown in figure 11.15. TCNT value Overflow Overflow Overflow Overflow Overflow Overflow H'FF H'80 H'40 H'00 Time MSTPD5=0 ARSL=0 ARSL=1 TLR setting (H'80)) OVF OVF OVF OVF TLR setting (H'40) OVF OVF OVF: Timer overflow interrupt request generation Figure 11.15 Operation in Automatic Reload Timer Mode 11.11.3 Cascaded Connection * Read of TCNT The channel relationship for cascaded connection is shown in figure 11.16. When accessing beyond the word area, for example, when a cascaded connection including channels 5 and 6 is created as shown in (3), and (6) to (8) in the figure, the counter value of the lower channel is read when TCNT5 is read, and the data is stored in the TCNT register. For case (7) where channels 5 to 7 are cascaded, the counter values of channels 6 and 7 are read when TCNT5 is read, and the data is stored in TCNT6/7 registers. Accordingly, when reading cascaded TCNT, read from the upper channel. For a word connection, access in word units. Rev. 3.00, 08/03, page 258 of 612 Upper Lower 1 Channel 4 Channel 5 Channel 6 Channel 7 Channel 4 Channel 5 Channel 6 Channel 7 3 Channel 4 Channel 5 Channel 6 Channel 7 4 Channel 4 Channel 5 Channel 6 Channel 7 5 Channel 4 Channel 5 Channel 6 Channel 7 6 Channel 4 Channel 5 Channel 6 Channel 7 7 Channel 4 Channel 5 Channel 6 Channel 7 Channel 4 Channel 5 Channel 6 Channel 7 2 8 Cascaded connection Figure 11.16 Channel Relationship of Cascaded Connection * Write to TLR When writing to the cascaded TLR, even if a single channel of TLR is written, the system regards that the entire channels of the cascaded TLR are rewritten. At this point in time, the value in the entire cascaded TLR is loaded into the corresponding TCNT. The timer operation starts at the TLR value that is most-recently written in TLR access cycles. * Operation Clock Although each channel usually operates on an individual clock, a cascaded channel operates on the same clock. The operation clock for the lowest cascaded channel is used as a common clock of each channel. In this case, the setting for the clocks of the channels other than the lowest channel is disabled. Rev. 3.00, 08/03, page 259 of 612 * Automatic Reload Function Select and Operation Timing Although the automatic reload function is usually set and implemented in individual channel, a cascaded channel operates according to the setting for the automatic reload function of the highest channel. In this case, the automatic reload function settings for the channels other than the highest channel are disabled. When the automatic reload function is enabled for cascaded channel, the TLR setting value of each channel is automatically reloaded simultaneously in the reload timing of the highest channel. * Timer Overflow Flag (OVF) Although an OVF is usually set to an individual channel independently, an OVF is set to the highest channel of a cascaded channel. In this case, OVFs of the channels other than that of the highest channel is disabled. 11.12 Usage Notes 11.12.1 Conflict between Write to TLR and Count Up/Automatic Reload Even if a count up occurs in the T2 state during TLR write cycles, the counter is not incremented and TLR write (load to TCNT) is carried out instead (as in Figure 11.11). Likewise, if an automatic reload occurs during write cycles, TLR write (load to TCNT) is carried out instead. 11.12.2 Switchover of Internal Clock and TCNT Operation Depending on the timing which the internal clock is switched, TCNT may be incremented (see table 11.4). Likewise, when the clock pulse is changed ( and SUB), TCNT may be incremented, and may not in some cases. Therefore, when the internal clock is changed, resume timer operation by resetting TLR (Write H'00 to TLR when the interval timer is in operation). 11.12.3 Interrupt during Module Stop When module stop mode is entered with an interrupt being requested, the cause of an interrupt to the CPU cannot be cleared. Enter module stop mode after, for example, disabling an interrupt request. Rev. 3.00, 08/03, page 260 of 612 Section 12 Watchdog Timer (WDT) The watchdog timer (WDT) is an 8-bit timer that can generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. The block diagram of the WDT is shown in figures 12.1 to 12.3. 12.1 Features * Selectable from eight counter input clocks for WDT_0 Selectable from 16 counter input clocks for WDT_1 * Switchable between watchdog timer mode and interval timer mode In watchdog timer mode * If the counter in WDT_0 overflows, it is possible to select whether this LSI is internally reset or not. * If the counter in WDT_1 overflows, it is possible to select whether this LSI is internally reset or the internal NMI interrupt is generated. In interval timer mode * If the counter overflows, the WDT generates an interval timer interrupt (WOVI). WDT0105B_000020030700 Rev. 3.00, 08/03, page 261 of 612 Clock Clock select Reset control Internal reset signal* RSTCSR TCNT_0 Internal bus /2 /64 /128 /512 /2048 /8192 /32768 /131072 Internal clock sources Overflow Interrupt control WOVI0 (interrupt request signal) TSCR_0 Bus interface Module bus WDT [Legend] TCSR_0: Timer control/status register0 TCNT_0: Timer counter0 RSTCSR: Reset control/status register Note: * The type of internal reset signal depends on a register setting. Figure 12.1 Block Diagram of WDT_0 WOVI1 (interrupt request signal) Internal NMI (interrupt request signal) Interrupt control Overflow Clock Reset control Clock select Internal reset signal* TSCR_1 Module bus WDT [Legend] TCSR_1: Timer control/status register1 TCNT_1: Timer counter1 Note: * The type of internal reset signal depends on a register setting. Figure 12.2 Block Diagram of WDT_1 Rev. 3.00, 08/03, page 262 of 612 Bus interface SUB/2 SUB/4 SUB/8 SUB/16 SUB/32 SUB/64 SUB/128 SUB/256 Internal bus TCNT_1 /2 /64 /128 /512 /2048 /8192 /32768 /131072 Internal clock sources 12.2 Register Descriptions The WDT has the following registers. To prevent accidental overwriting, TCSR and TCNT have to be written to by a different method to normal registers. For details, refer to section 12.5.1, Notes on Register Access. * Timer counter (TCNT) * Timer control/status register (TCSR) * Reset control/status register (RSTCSR) 12.2.1 Timer Counter (TCNT) TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in TCSR is cleared to 0. 12.2.2 Timer Control/Status Register (TCSR) TCSR functions include selecting the clock source to be input to TCNT and the timer mode. * TCSR_0 Bit 7 Bit Name OVF Initial Value 0 R/W Description 1 R/(W)* Overflow Flag Indicates that TCNT has overflowed. Only a 0 can be written to this bit, to clear the flag. [Setting condition] When TCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. [Clearing conditions] 2 Cleared by reading TCSR* when OVF = 1, then writing 0 to OVF 6 WT/IT 0 R/W Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode 1: Watchdog timer mode Rev. 3.00, 08/03, page 263 of 612 Bit Bit Name Initial Value R/W Description 5 TME 0 R/W Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00. 4, 3 All 1 2 CKS2 0 R/W Clock Select 0 to 2 1 CKS1 0 R/W 0 CKS0 0 R/W Selects the clock source to be input to TCNT. The 3 overflow frequency* for = 20 MHz is enclosed in parentheses. Reserved These bits are always read as 1 and cannot be modified. 000: Clock /2 (frequency: 25.6 s) 001: Clock /64 (frequency: 819.2 s) 010: Clock /128 (frequency: 1.6 ms) 011: Clock /512 (frequency: 6.6 ms) 100: Clock /2048 (frequency: 26.2 ms) 101: Clock /8192 (frequency: 104.9 ms) 110: Clock /32768 (frequency: 419.4 ms) 111: Clock /131072 (frequency: 1.68 s) Notes: 1. Only 0 can be written, for flag clearing. 2. When the OVF flag is polled with the interval timer interrupt disabled, read the OVF bit while it is 1 at least twice. 3. The overflow period is the time from when TCNT starts counting up from H'00 until overflow occurs. Rev. 3.00, 08/03, page 264 of 612 * TCSR_1 Bit 7 Bit Name OVF Initial Value 0 R/W Description 1 R/(W)* Overflow Flag Indicates that TCNT has overflowed. Only a 0 can be written to this bit, to clear the flag. [Setting condition] When TCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. [Clearing conditions] 2 Cleared by reading TCSR* when OVF = 1, then writing 0 to OVF 6 WT/IT 0 R/W Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode 1: Watchdog timer mode 5 TME 0 R/W Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00. 4 PSS 0 R/W Prescaler Select Selects the clock source input to TCNT of WDT_1 0: TCNT counts divided clock of -base prescaler (PSM). 1: TCNT counts divided clock of SUB-base prescaler (PSS) 3 RST/NMI 0 R/W Reset or NMI (REST/NMI) 0: An NMI interrupt is requested. 1: reset is requested. Rev. 3.00, 08/03, page 265 of 612 Bit Bit Name Initial Value R/W Description 2 CKS2 0 R/W Clock Select 0 to 2 1 CKS1 0 R/W 0 CKS0 0 R/W Selects the clock source to be input to TCNT. The 3 overflow frequency* for = 20 MHz or SUB = 32.768 kHz is enclosed in parentheses. When PSS = 0: 000: Clock /2 (frequency: 25.6 s) 001: Clock /64 (frequency: 819.2 s) 010: Clock /128 (frequency: 1.6 ms) 011: Clock /512 (frequency: 6.6 ms) 100: Clock /2048 (frequency: 26.2 ms) 101: Clock /8192 (frequency: 104.9 ms) 110: Clock /32768 (frequency: 419.4 ms) 111: Clock /131072 (frequency: 1.68 s) When PSS = 1: 000: Clock SUB/2 (frequency: 15.6 ms) 001: Clock SUB/4 (frequency: 31.3 ms) 010: Clock SUB/8 (frequency: 62.5 ms) 011: Clock SUB/16 (frequency: 125 ms) 100: Clock SUB/32 (frequency: 250 ms) 101: Clock SUB/64 (frequency: 500 ms) 110: Clock SUB/128 (frequency: 1 s) 111: Clock SUB/256 (frequency: 2 s) Notes: 1. Only 0 can be written, for flag clearing. 2. When the OVF flag is polled with the interval timer interrupt disabled, read the OVF bit while it is 1 at least twice 3. The overflow period is the time from when TCNT starts counting up from H'00 until overflow occurs. Rev. 3.00, 08/03, page 266 of 612 12.2.3 Reset Control/Status Register (RSTCSR) (only WDT_0) RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, and not by the WDT internal reset signal caused by overflows. Bit Bit Name Initial Value R/W 7 WOVF 0 R/(W)* Watchdog Overflow Flag Description This bit is set when TCNT overflows in watchdog timer mode. This bit cannot be set in interval timer mode, and only 0 can be written, to clear the flag. [Setting condition] Set when TCNT overflows (changed from H'FF to H'00) in watchdog timer mode [Clearing condition] Cleared by reading RSTCSR when WOVF = 1, and then writing 0 to WOVF 6 RSTE 0 R/W Reset Enable Specifies whether or not a reset signal is generated in the chip if TCNT overflows during watchdog timer operation. 0: Reset signal is not generated even if TCNT overflows (Though this LSI is not reset, TCNT and TCSR in WDT are reset) 1: Reset signal is generated if TCNT overflows 5 0 R/W Reserved This bit can be read from and written to. However, the write value should always be 0. 4 to 0 All 1 Reserved These bits are always read as 1 and cannot be modified. Note: * Only 0 can be written, to clear the flag. Rev. 3.00, 08/03, page 267 of 612 12.3 Operation 12.3.1 Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT bit in TCSR and the TME bit to 1. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs. Thus, TCNT does not overflow while the system is operating normally. When the WDT is used as a watchdog timer and the RSTE bit in RSTCSR of WDT_0 is set to 1, and if TCNT overflows without being rewritten because of a system malfunction or other error, an internal reset signal for this LSI is output for 518 system clocks. When the RST/NMI bit in TCSR of WDT_1 is set to 1, and if TCNT overflows, the internal reset signal is output for 516 system clock periods. When the RST/ NMI bit is cleared to 0, an NMI interrupt request is generated (for 515 or 516 system clock periods when the clock source is set to SUB (PSS = 1)). An internal reset request from the watchdog timer and a reset input from the RES pin are both treated as having the same vector. If a WDT internal reset request and the RES pin reset occur at the same time, the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0. An NMI request from the watchdog timer and an interrupt request from the NMI pin are both treated as having the same vector. So, avoid handling an NMI request from the watchdog timer and an interrupt request from the NMI pin at the same time. Rev. 3.00, 08/03, page 268 of 612 TCNT value Overflow H'FF Time H'00 WT/IT=1 TME=1 WOVF=1 Write H'00' to TCNT WT/IT=1 TME=1 Write H'00' to TCNT internal reset is generated Internal reset signal* 518 system clock (WDT0) 515/516 system clock (WDT1) [Legend] WT/IT: Timer mode select bit TME: Timer enable bit Note: * In the case of WDT_0, the internal reset signal is generated only when the RSTE bit is set to 1. In the case of WDT_1,either the internal reset or the NMI interrupt is generated. Figure 12.3 Watchdog Timer Mode Operation 12.3.2 Interval Timer Mode To use the WDT as an internal timer, set the WT/IT and TME bits in TCSR to 0. When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows. Therefore, an interrupt can be generated at intervals. When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested at the time the OVF bit of the TCSR is set to 1. TCNT value Overflow H'FF Overflow Overflow Overflow Time H'00 WT/IT=0 TME=1 WOVI WOVI WOVI WOVI [Legend] WOVI: Interval timer interrupt request generation Figure 12.4 Interval Timer Mode Operation Rev. 3.00, 08/03, page 269 of 612 12.3.3 Timing of Setting Overflow Flag (OVF) The OVF flag is set to 1 if TCNT overflows during interval timer operation. At the same time, an interval timer interrupt (WOVI) is requested. This timing is shown in figure 12.5. TCNT H'FF H'00 1 1 Overflow signal (internal signal) 1 OVF Figure 12.5 Timing of OVF Setting 12.3.4 Timing of Setting Watchdog Timer Overflow Flag (WOVF) With WDT_0 the WOVF bit in RSTCSR is set to 1 if TCNT overflows in watchdog timer mode. If TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal is generated for the entire chip. this timing is illustrated in figure 12.6. TCNT H'FF H'00 Overflow signal (internal signal) WOVF Internal reset signal 518 states (WDT_0) 515/516 states (WDT_1) Figure 12.6 Timing of WOVF Setting Rev. 3.00, 08/03, page 270 of 612 12.4 Interrupt Sources During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. If an NMI request has been chosen in the watchdog timer mode, an NMI request is generated when a TCNT overflow occurs. Table 12.1 WDT Interrupt Source Name Interrupt Source Interrupt Flag WOVI TCNT overflow (interval timer mode) OVF NMI TCNT overflow (watchdog timer mode) OVF 12.5 Usage Notes 12.5.1 Notes on Register Access The watchdog timer's TCNT and TCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. Writing to TCNT, TCSR, and RSTCSR These registers must be written to by a word transfer instruction. They cannot be written to by a byte transfer instruction. TCNT and TCSR both have the same write address. Therefore, the relative condition shown in figure 12.7 needs to be satisfied in order to write to TCNT or TCSR. The transfer instruction writes the lower byte data to TCNT or TCSR. The upper byte must be H'5A for writing to TCNT, and H'A5 for writing to TCSR. To write to RSTCSR, execute a word transfer instruction for address H'FF76. A byte transfer instruction cannot write to RSTCSR. The method of writing 0 to the OVF bit differs from that of writing to the RSTE bit. To write 0 to the WOVF bit, satisfy the condition shown in figure 12.7. If satisfied, the transfer instruction clears the WOVF bit to 0, but has no effect on the RSTE bit. To write to the RSTE and RSTS bits, satisfy the condition shown in figure 12.7. If satisfied, the transfer instruction writes the values in bit 6 of the lower byte into the RSTE bit, but has no effect on the WOVF bit. Rev. 3.00, 08/03, page 271 of 612 TCNT write Writing to RSTE and RSTS bits Address: H'FF74 H'FF76 15 8 H'5A 7 0 Write data TCSR write Writing 0 to WOVF bit Address: H'FF74 H'FF76 15 8 H'A5 7 0 Write data or H'00 Figure 12.7 Writing to TCNT and TCSR (example for WDT_0) Reading TCNT, TCSR, and RSTCSR (WDT_ _0) These registers are read in the same way as other registers. The read addresses are H'FF74 for TCSR and H'FF77 for RSTCSR. 12.5.2 Contention between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 12.8 shows this operation. TCNT write cycle T1 T2 Address Internal write signal TCNT input clock TCNT N M Counter write data Figure 12.8 Contention between TCNT Write and Increment Rev. 3.00, 08/03, page 272 of 612 12.5.3 Changing Value of CKS2 to CKS0 If bits CKS0 to CKS2 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must be used to stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits CKS0 to CKS2. 12.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode If the mode is switched from watchdog timer to interval timer while the WDT is operating, errors could occur in the incrementation. Software must be used to stop the watchdog timer (by clearing the TME bit to 0) before switching the mode. 12.5.5 Internal Reset in Watchdog Timer Mode This LSI is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog timer operation, however TCNT_0 and TCSR_0 of the WDT_0 are reset. TCNT, TCSR, or RSTCR cannot be written to for 132 states following an overflow. During this period, any attempt to read the WOVF flag is not acknowledged. Accordingly, wait 132 states after overflow to write 0 to the WOVF flag for clearing. 12.5.6 OVF Flag Clearing in Interval Timer Mode When the OVF flag setting conflicts with the OVF flag reading in interval timer mode, writing 0 to the OVF bit may not clear the flag even though the OVF bit has been read while it is 1. If there is a possibility that the OVF flag setting and reading will conflict, such as when the OVF flag is polled with the interval timer interrupt disabled, read the OVF bit while it is 1 at least twice before writing 0 to the OVF bit to clear the flag. Rev. 3.00, 08/03, page 273 of 612 Rev. 3.00, 08/03, page 274 of 612 Section 13 Serial Communication Interface (SCI) This LSI has three independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Serial data communication can be carried out using standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function). The SCI also supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. 13.1 Features * Choice of asynchronous or clocked synchronous serial communication mode * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. * On-chip baud rate generator allows any bit rate to be selected External clock can be selected as a transfer clock source (except for in Smart Card interface mode). * Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data) * Four interrupt sources Transmit-end, transmit-data-empty, receive-data-full, and receive error that can issue requests. The transmit-data-empty interrupt and receive data full interrupts can be used to activate the data transfer controller (DTC) (H8S/2268 Group only). * Module stop mode can be set Asynchronous Mode * Data length: 7 or 8 bits * Stop bit length: 1 or 2 bits * Parity: Even, odd, or none * Receive error detection: Parity, overrun, and framing errors * Break detection: Break can be detected by reading the RxD pin level directly in the case of a framing error SCI0025B_000020020700 Rev. 3.00, 08/03 page 275 of 612 * Average transfer rate generator (SCI_0): 720 kbps, 460.784 kbps, or 115.196 kbps can be selected at 16 MHz operation. * Transfer rate clock can be input from the TPU (SCI_0). * Communications between multi-processors are possible. Clocked Synchronous Mode * Data length: 8 bits * Receive error detection: Overrun errors detected Smart Card Interface * Automatic transmission of error signal (parity error) in receive mode * Error signal detection and automatic data retransmission in transmit mode * Direct convention and inverse convention both supported Rev. 3.00, 08/03, page 276 of 612 Bus interface Figure 13.1 shows a block diagram of the SCI_0, and figure 13.2 shows that of the SCI1 and SCI_2. Module data bus RDR SCMR TDR Internal data bus BRR SSR SCR RxD0 RSR /4 Baud rate generator SMR TSR SEMR /16 /64 Transmission/ reception control TxD0 Clock Parity generation TEI TXI RXI ERI Parity check External clock SCK0 Average transfer rate generator 10.667MHz operation 115.152kbps 460.606kbps 16MHz operation 115.196kbps 460.784kbps 720kbps TIOCA1 TCLKA TPU TIOCA2 [Legend] RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register SCR: SSR: SCMR: BRR: SEMR: Serial control register Serial status register Smart card mode register Bit rate register Serial expansion mode register Figure 13.1 Block Diagram of SCI_0 Rev. 3.00, 08/03 page 277 of 612 Bus interface Module data bus RDR BRR SCMR TDR SSR RxD TxD SCR RSR TSR SMR Baud rate generator Transmission/ reception control Parity generation /4 /16 /64 Clock Parity check External clock SCK [Legend] RSR: RDR: TSR: TDR: SMR: SCR: SSR: SCMR: BRR: Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Smart card mode register Bit rate register TEI TXI RXI ERI Figure 13.2 Block Diagram of SCI_1 or SCI_2 Rev. 3.00, 08/03, page 278 of 612 Internal data bus 13.2 Input/Output Pins Table 13.1 shows the pin configuration for each SCI channel. Table 13.1 Pin Configuration Channel Pin Name* I/O Function 0 SCK0 I/O SCI0 clock input/output 1 2 Note: 13.3 * RxD0 Input SCI0 receive data input TxD0 Output SCI0 transmit data output SCK1 I/O SCI1 clock input/output RxD1 Input SCI1 receive data input TxD1 Output SCI1 transmit data output SCK2 I/O SCI2 clock input/output RxD2 Input SCI2 receive data input TxD2 Output SCI2 transmit data output Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel designation. Register Descriptions The SCI has the following registers for each channel. For details on register addresses and register states during each process, refer to Section 24, List of Registers. The serial mode register (SMR), serial status register (SSR), and serial control register (SCR) are described separately for normal serial communication interface mode and Smart Card interface mode because their bit functions differ in part. * Receive Shift Register (RSR) * Receive Data Register (RDR) * Transmit Data Register (TDR) * Transmit Shift Register (TSR) * Serial Mode Register (SMR) * Serial Control Register (SCR) * Serial Status Register (SSR) * Smart Card Mode Register (SCMR) * Bit Rate Register (BRR) Other than the above registers, SCI_0 has the following register. * Serial Expansion Mode Register (SEMR0) Rev. 3.00, 08/03 page 279 of 612 13.3.1 Receive Shift Register (RSR) RSR is a shift register that is used to receive serial data input to the RxD pin and convert it into parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 13.3.2 Receive Data Register (RDR) RDR is an 8-bit register that stores received data. When the SCI has received one byte of serial data, it transfers the received serial data from RSR to RDR, where it is stored. After this, RSR is receive-enabled. As RSR and RDR function as a double buffer in this way, continuous receive operations are possible. After confirming that the RDRF bit in SSR is set to 1, read RDR only once. RDR cannot be written to by the CPU. RDR is initialized to H'00 by a reset, in standby mode, watch mode,subactive mode, subsleep mode or module stop mode. 13.3.3 Transmit Data Register (TDR) TDR is an 8-bit register that stores data for transmission. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered structure of TDR and TSR enables continuous serial transmission. If the next transmit data has already been written to TDR during serial transmission, the SCI transfers the written data to TSR to continue transmission. Although TDR can be read or written to by the CPU at all times, to achieve reliable serial transmission, write transmit data to TDR only once after confirming that the TDRE bit in SSR is set to 1. TDR is initialized to H'FF by a reset, in standby mode, watch mode, subactive mode, subsleep mode or module stop mode. 13.3.4 Transmit Shift Register (TSR) TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin. TSR cannot be directly accessed by the CPU. Rev. 3.00, 08/03, page 280 of 612 13.3.5 Serial Mode Register (SMR) SMR is used to set the SCI's serial transfer format and select the baud rate generator clock source. Some bit functions of SMR differ between normal serial communication interface mode and Smart Card interface mode. Normal Serial Communication Interface Mode (When SMIF in SCMR is 0) Bit Bit Name Initial Value R/W Description 7 C/A 0 R/W Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode 6 CHR 0 R/W Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length. LSB-first is fixed and the MSB (bit 7) of TDR is not transmitted in transmission. In clocked synchronous mode, a fixed data length of 8 bits is used. 5 PE 0 R/W Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. For a multiprocessor format, parity bit addition and checking are not performed regardless of the PE bit setting. 4 O/E 0 R/W Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1 bits in the receive character plus parity bit is even. 1: Selects odd parity. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. Rev. 3.00, 08/03 page 281 of 612 Bit Bit Name Initial Value R/W Description 3 STOP 0 R/W Stop Bit Length (enabled only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits In reception, only the first stop bit is checked. If the second stop bit is 0, it is treated as the start bit of the next transmit character. 2 MP 0 R/W Multiprocessor Mode (enabled only in asynchronous mode) When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode. For details, see 13.5, Multiprocessor Communication Function. 1 CKS1 0 R/W Clock Select 0 and 1 0 CKS0 0 R/W These bits select the clock source for the baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) For the relationship between the bit rate register setting and the baud rate, see section 13.3.9, Bit Rate Register (BRR). n is the decimal representation of the value of n in BRR (see section 13.3.9, Bit Rate Register (BRR)). Rev. 3.00, 08/03, page 282 of 612 Smart Card Interface Mode (When SMIF in SCMR is 1) Bit Bit Name Initial Value R/W Description 7 GM 0 R/W GSM Mode When this bit is set to 1, the SCI operates in GSM mode. In GSM mode, the timing of the TEND setting is advanced by 11.0 etu (Elementary Time Unit: the time for transfer of one bit), and clock output control mode addition is performed. For details, refer to section 13.7.8, Clock Output Control. 6 BLK 0 R/W When this bit is set to 1, the SCI operates in block transfer mode. For details on block transfer mode, refer to section 13.7.3, Block Transfer Mode. 5 PE 0 R/W Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data in transmission, and the parity bit is checked in reception. In Smart Card interface mode, this bit must be set to 1. 4 O/E 0 R/W Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity. For details on setting this bit in Smart Card interface mode, refer to section 13.7.2, Data Format (Except for Block Transfer Mode). 3 BCP1 0 R/W Basic Clock Pulse 0 and 1 2 BCP0 0 R/W These bits specify the number of basic clock periods in a 1-bit transfer interval on the Smart Card interface. 00: 32 clock (S = 32) 01: 64 clock (S = 64) 10: 372 clock (S = 372) 11: 256 clock (S = 256) For details, refer to section 13.7.4, Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode. S stands for the value of S in BRR (see section 13.3.9, Bit Rate Register (BRR)). Rev. 3.00, 08/03 page 283 of 612 Bit Bit Name Initial Value R/W Description 1 CKS1 0 R/W Clock Select 0 and 1 0 CKS0 0 R/W These bits select the clock source for the baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) For the relationship between the bit rate register setting and the baud rate, see section 13.3.9, Bit Rate Register (BRR). n is the decimal representation of the value of n in BRR (see section 13.3.9, Bit Rate Register (BRR)). Note: etu (Elementary Time Unit): Abbreviation for the transfer period for one bit. 13.3.6 Serial Control Register (SCR) SCR is a register that enables or disables SCI transfer operations and interrupt requests, and is also used to selection of the transfer clock source. For details on interrupt requests, refer to section 13.8, Interrupt Sources. Some bit functions of SCR differ between normal serial communication interface mode and Smart Card interface mode. Normal Serial Communication Interface Mode (When SMIF in SCMR is 0) Bit Bit Name Initial Value R/W Description 7 TIE 0 R/W Transmit Interrupt Enable When this bit is set to 1, the TXI interrupt request is enabled. TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0, or clearing the TIE bit to 0. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF, FER, PER, or ORER flag in SSR, then clearing the flag to 0, or clearing the RIE bit to 0. Rev. 3.00, 08/03, page 284 of 612 Bit Bit Name Initial Value R/W Description 5 TE 0 R/W Transmit Enable When this bit s set to 1, transmission is enabled. In this state, serial transmission is started when transmit data is written to TDR and the TDRE flag in SSR is cleared to 0. SMR setting must be performed to decide the transfer format before setting the TE bit to 1. When this bit is cleared to 0, the transmission operation is disabled, and the TDRE flag is fixed at 1. 4 RE 0 R/W Receive Enable When this bit is set to 1, reception is enabled. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode. SMR setting must be performed to decide the reception format before setting the RE bit to 1. Clearing the RE bit to 0 does not affect the RDRF, FER,PER, and ORER flags, which retain their states. 3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is prohibited. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. For details, refer to section 13.5, Multiprocessor Communication Function. When receive data including MPB = 0 is received, receive data transfer from RSR to RDR, receive error detection, and setting of the RERF, FER, and ORER flags in SSR, are not performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting are enabled. 2 TEIE 0 R/W Transmit End Interrupt Enable This bit is set to 1, TEI interrupt request is enabled. TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0. Rev. 3.00, 08/03 page 285 of 612 Bit Bit Name Initial Value R/W Description 1 CKE1 0 R/W Clock Enable 0 and 1 0 CKE0 0 R/W Selects the clock source and SCK pin function. Asynchronous mode 00: On-chip baud rate generator SCK pin functions as I/O port 01: On-chip baud rate generator Outputs a clock of the same frequency as the bit rate from the SCK pin. 1X: External clock Inputs a clock with a frequency 16 times the bit rate from the SCK pin. Clocked synchronous mode 0X: Internal clock (SCK pin functions as clock output) 1X: External clock (SCK pin functions as clock input) [Legend] X: Don't care Rev. 3.00, 08/03, page 286 of 612 Smart Card Interface Mode (When SMIF in SCMR is 1) Bit Bit Name Initial Value R/W Description 7 TIE 0 R/W Transmit Interrupt Enable When this bit is set to 1, TXI interrupt request is enabled. TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0, or clearing the TIE bit to 0. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF, FER, PER, or ORER flag in SSR, then clearing the flag to 0, or clearing the RIE bit to 0. 5 TE 0 R/W Transmit Enable When this bit s set to 1, transmission is enabled. In this state, serial transmission is started when transmit data is written to TDR and the TDRE flag in SSR is cleared to 0. SMR setting must be performed to decide the transfer format before setting the TE bit to 1. When this bit is cleared to 0, the transmission operation is disabled, and the TDRE flag is fixed at 1. 4 RE 0 R/W Receive Enable When this bit is set to 1, reception is enabled. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode. SMR setting must be performed to decide the reception format before setting the RE bit to 1. Clearing the RE bit to 0 does not affect the RDRF, FER,PER, and ORER flags, which retain their states. Rev. 3.00, 08/03 page 287 of 612 Bit Bit Name Initial Value R/W Description 3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) Write 0 to this bit in Smart Card interface mode. When receive data including MPB = 0 is received, receive data transfer from RSR to RDR, receive error detection, and setting of the RERF, FER, and ORER flags in SSR, are not performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting are enabled. 2 TEIE 0 R/W Transmit End Interrupt Enable Write 0 to this bit in Smart Card interface mode. TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0. 1 CKE1 0 0 CKE0 0 R/W Clock Enable 0 and 1 Enables or disables clock output from the SCK pin. The clock output can be dynamically switched in GSM mode. For details, refer to section 13.7.8, Clock Output Control. When the GM bit in SMR is 0: 00: Output disabled (SCK pin can be used as an I/O port pin) 01: Clock output 1X: Reserved When the GM bit in SMR is 1: 00: Output fixed low 01: Clock output 10: Output fixed high 11: Clock output [Legend] X: Don't care Rev. 3.00, 08/03, page 288 of 612 13.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Some bit functions of SSR differ between normal serial communication interface mode and Smart Card interface mode. Normal Serial Communication Interface Mode (When SMIF in SCMR is 0) Bit Bit Name Initial Value R/W 7 TDRE 1 R/(W)* Transmit Data Register Empty Description Displays whether TDR contains transmit data. [Setting conditions] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written to TDR [Clearing conditions] 6 RDRF 0 * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt request and writes data to TDR (H8S/2268 Group only) R/(W)* Receive Data Register Full Indicates that the received data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR [Clearing conditions] * When 0 is written to RDRF after reading RDRF = 1 * When the DTC is activated by an RXI interrupt and transferred data from RDR (H8S/2268 Group only) The RDRF flag is not affected and retains their previous values when the RE bit in SCR is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost. Rev. 3.00, 08/03 page 289 of 612 Bit Bit Name Initial Value R/W 5 ORER 0 R/(W)* Overrun Error Description Indicates that an overrun error occurred during reception, causing abnormal termination. [Setting condition] * When the next serial reception is completed while RDRF = 1 The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial reception cannot be continued while the ORER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued either. [Clearing condition] * When 0 is written to ORER after reading ORER = 1 The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 4 FER 0 R/(W)* Framing Error Indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. [Setting condition] * When the stop bit is 0 In 2 stop bit mode, only the first stop bit is checked for a value to 1; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the FER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. [Clearing condition] * When 0 is written to FER after reading FER = 1 In 2-stop-bit mode, only the first stop bit is checked. The FER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. Rev. 3.00, 08/03, page 290 of 612 Bit Bit Name Initial Value R/W 3 PER 0 R/(W)* Parity Error Description Indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. [Setting condition] * When a parity error is detected during reception If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. [Clearing condition] * When 0 is written to PER after reading PER = 1 The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2 TEND 1 R Transmit End Indicates that transmission has been ended. [Setting conditions] * When the TE bit in SCR is 0 * When TDRE = 1 at transmission of the last bit of a 1byte serial transmit character [Clearing conditions] 1 MPB 0 R * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt request and transfer transmission data to TDR (H8S/2268 Group only) Multiprocessor Bit MPB stores the multiprocessor bit in the receive data. When the RE bit in SCR is cleared to 0 its previous state is retained. 0 MPBT 0 R/W Multiprocessor Bit Transfer MPBT stores the multiprocessor bit to be added to the transmit data. Note: * Only a 0 can be written to this bit, to clear the flag. Rev. 3.00, 08/03 page 291 of 612 Smart Card Interface Mode (When SMIF in SCMR is 1) Bit Bit Name Initial Value R/W 7 TDRE 1 R/(W)* Transmit Data Register Empty Description Indicates whether TDR contains transmit data. [Setting conditions] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written to TDR [Clearing conditions] 6 RDRF 0 * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt request and writes data to TDR (H8S/2268 Group only) R/(W)* Receive Data Register Full Indicates that the received data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR [Clearing conditions] * When 0 is written to RDRF after reading RDRF = 1 * When the DTC is activated by an RXI interrupt and transferred data from RDR (H8S/2268 Group only) The RDRF flag is not affected and retains their previous values when the RE bit in SCR is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost. Rev. 3.00, 08/03, page 292 of 612 Bit Bit Name Initial Value R/W 5 ORER 0 R/(W)* Overrun Error Description Indicates that an overrun error occurred during reception, causing abnormal termination. [Setting condition] * When the next serial reception is completed while RDRF = 1 The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial cannot be continued while the ORER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. [Clearing condition] * When 0 is written to ORER after reading ORER = 1 The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 4 ERS 0 R/(W)* Error Signal Status Indicates that the status of an error, signal 1 returned from the reception side at reception [Setting condition] * When the low level of the error signal is sampled [Clearing condition] * When 0 is written to ERS after reading ERS = 1 The ERS flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 3 PER 0 R/(W)* Parity Error Indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. [Setting condition] * When a parity error is detected during reception If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. [Clearing condition] * When 0 is written to PER after reading PER = 1 The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. Rev. 3.00, 08/03 page 293 of 612 Bit Bit Name Initial Value R/W 2 TEND 1 R Description Transmit End This bit is set to 1 when no error signal has been sent back from the receiving end and the next transmit data is ready to be transferred to TDR. [Setting conditions] * When the TE bit in SCR is 0 and the ERS bit is also 0 * When the ESR bit is 0 and the TDRE bit is 1 after the specified interval following transmission of 1-byte data. The timing of bit setting differs according to the register setting as follows: When GM = 0 and BLK = 0, 2.5 etu after transmission starts When GM = 0 and BLK = 1, 1.0 etu after transmission starts When GM = 1 and BLK = 0, 1.5 etu after transmission starts When GM = 1 and BLK = 1, 1.0 etu after transmission starts [Clearing conditions] 1 MPB 0 R 0 MPBT 0 R/W * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and transfers transmission data to TDR (H8S/2268 Group only) Multiprocessor Bit This bit is not used in Smart Card interface mode. Multiprocessor Bit Transfer Write 0 to this bit in Smart Card interface mode. Note: Only 0 can be written to this bit, to clear the flag. Rev. 3.00, 08/03, page 294 of 612 13.3.8 Smart Card Mode Register (SCMR) SCMR is a register that selects Smart Card interface mode and its format. Bit Bit Name Initial Value R/W Description 7 to 4 All 1 Reserved These bits are always read as 1, and cannot be modified. 3 SDIR 0 R/W Smart Card Data Transfer Direction Selects the serial/parallel conversion format. 0: LSB-first in transfer 1: MSB-first in transfer The bit setting is valid only when the transfer data format is 8 bits. For 7-bit data, LSB-first is fixed. 2 SINV 0 R/W Smart Card Data Invert Specifies inversion of the data logic level. The SINV bit does not affect the logic level of the parity bit. To invert the parity bit, invert the O/E bit in SMR. 0: TDR contents are transmitted as they are. Receive data is stored as it is in RDR 1: TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR 1 1 Reserved This bit is always read as 1, and cannot be modified. 0 SMIF 0 R/W Smart Card Interface Mode Select This bit is set to 1 to make the SCI operate in Smart Card interface mode. 0: Normal asynchronous mode or clocked synchronous mode 1: Smart card interface mode Rev. 3.00, 08/03 page 295 of 612 13.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 13.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode, clocked synchronous mode, and Smart Card interface mode. The initial value of BRR is H'FF, and it can be read or written to by the CPU at all times. Table 13.2 The Relationships between The N Setting in BRR and Bit Rate B Communication Mode Asynchronous Mode ABCS bit 0 B= 1 B= Clocked Synchronous Mode Smart Card Interface Mode Bit Rate B= B= Error x 106 64 x 2 2n-1 x (N + 1) x 106 32 x 2 2n-1 x 106 Error (%) = { B x 64 x 2 2n-1 x (N + 1) x 106 Error (%) = { x (N + 1) B x 32 x 2 2n-1 x (N + 1) 8 x 2 2n-1 x (N + 1) x 106 Sx2 2n+1 x 106 Error (%) = { x (N + 1) B x S x 2 2n+1 x (N + 1) SMR Setting CKS1 CKS0 Clock Source 0 0 0 0 0 32 0 1 /4 1 0 1 64 1 0 /16 2 1 0 372 1 1 /64 3 1 1 256 Rev. 3.00, 08/03, page 296 of 612 -1 } x 100 x 106 Note: B: Bit rate (bit/s) N: BRR setting for baud rate generator (0 N 255) : Operating frequency (MHz) n and S: Determined by the SMR settings shown in the following tables. SMR Setting -1 } x 100 n BCP1 BCP0 S -1 } x 100 Table 13.3 shows sample N settings in BRR in normal asynchronous mode. Table 13.4 shows the maximum bit rate for each frequency in normal asynchronous mode. Table 13.6 shows sample N settings in BRR in clocked synchronous mode. Table 13.8 shows sample N settings in BRR in Smart Card interface mode. In Smart Card interface mode, S (the number of basic clock periods in a 1-bit transfer interval) can be selected. For details, refer to section 13.7.4, Receive Data Sampling Timing and Reception Margin. Tables 13.5 and 13.7 show the maximum bit rates with external clock input. When the ABCS bit in SEMR_0 of SCI_0 is set to 1 in asynchronous mode, the maximum bit rate is twice the value shown in tables 13.4 and 13.5. Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency (MHz) 2 2.097152 3 n N Error (%) n N Error (%) n N Error (%) 141 0.03 1 148 -0.04 1 174 -0.26 1 212 0.33 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16 1200 0 51 0.16 0 54 -0.70 0 63 0.00 0 77 0.16 2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16 4800 0 12 0.16 0 13 -2.48 0 15 0.00 0 19 -2.34 9600 0 6 -2.48 0 7 0.00 0 9 -2.34 19200 0 3 0.00 0 4 -2.34 31250 0 1 0.00 0 2 0.00 38400 0 1 0.00 Bit Rate (bps) n N 110 1 150 Error (%) 2.4576 Rev. 3.00, 08/03 page 297 of 612 Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency (MHz) 3.6864 4 4.9152 5 Bit Rate n (bps) N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 64 0.70 2 70 0.33 2 86 0.31 2 88 -0.25 150 1 191 0.00 1 207 0.16 2 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 1 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 -1.36 9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 19200 0 5 0.00 0 7 0.00 0 7 1.73 31250 0 3 0.00 0 4 -1.70 0 4 0.00 38400 0 2 0.00 0 3 0.00 0 3 1.73 Operating Frequency (MHz) 6 6.144 Bit Rate (bps) N N Error (%) n N 110 2 106 -0.44 2 150 2 77 0.16 300 1 155 600 1 1200 7.3728 n N Error (%) n N Error (%) 108 0.08 2 130 -0.07 2 141 0.03 2 79 0.00 2 95 0.00 2 103 0.16 0.16 1 159 0.00 1 191 0.00 1 207 0.16 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 -2.34 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 -2.34 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 0.00 0 5 2.40 0 7 0.00 38400 0 4 -2.34 0 4 0.00 0 5 0.00 Rev. 3.00, 08/03, page 298 of 612 Error (%) 8 Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3) Operating Frequency (MHz) 9.8304 10 12 12.288 Bit Rate n (bps) N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 174 -0.26 2 177 -0.25 2 212 0.03 2 217 0.08 150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00 300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00 600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00 2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00 4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00 9600 0 31 0.00 0 32 -1.36 0 38 0.16 0 39 0.00 19200 0 15 0.00 0 15 1.73 0 19 -2.34 0 19 0.00 31250 0 9 -1.70 0 9 0.00 0 11 0.00 0 11 2.40 38400 0 7 0.00 0 7 1.73 0 9 -2.34 0 9 0.00 Operating Frequency (MHz) 14 14.7456 16 17.2032 Bit Rate (bps) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 248 -0.17 3 64 0.70 3 70 0.03 3 75 0.48 150 2 181 0.16 2 191 0.00 2 207 0.16 2 223 0.00 300 2 90 0.16 2 95 0.00 2 103 0.16 2 111 0.00 600 1 181 0.16 1 191 0.00 1 207 0.16 1 223 0.00 1200 1 90 0.16 1 95 0.00 1 103 0.16 1 111 0.00 2400 0 181 0.16 0 191 0.00 0 207 0.16 0 223 0.00 4800 0 90 0.16 0 95 0.00 0 103 0.16 0 111 0.00 9600 0 45 -0.93 0 47 0.00 0 51 0.16 0 55 0.00 19200 0 22 -0.93 0 23 0.00 0 25 0.16 0 27 0.00 31250 0 13 0.00 0 14 -1.70 0 15 0.00 0 16 1.20 38400 11 0.00 0 12 0.16 0 13 0.00 Rev. 3.00, 08/03 page 299 of 612 Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (4) Operating Frequency (MHz) 18 Bit Rate n (bps) 19.6608 20 N Error (%) n N Error (%) n N Error (%) 110 3 79 -0.12 3 86 0.31 3 88 -0.25 150 2 233 0.16 2 255 0.00 2 64 0.16 300 2 116 0.16 2 127 0.00 2 129 0.16 600 1 233 0.16 1 255 0.00 1 64 0.16 1200 1 116 0.16 1 127 0.00 1 129 0.16 2400 0 233 0.16 0 255 0.00 0 64 0.16 4800 0 116 0.16 0 127 0.00 0 129 0.16 9600 0 58 -0.69 0 63 0.00 0 64 0.16 19200 0 28 1.02 0 31 0.00 0 32 -1.36 31250 0 17 0.00 0 19 -1.70 0 19 0.00 38400 0 14 -2.34 0 15 0.00 0 15 1.73 Table 13.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) (MHz) Maximum Bit Rate (kbps) n N (MHz) Maximum Bit Rate (kbps) n N 2 62.5 0 0 9.8304 307.2 0 0 2.097152 65.536 0 0 10 312.5 0 0 2.4576 76.8 0 0 12 375.0 0 0 3 93.75 0 0 12.288 384.0 0 0 3.6864 115.2 0 0 14 437.5 0 0 4 125.0 0 0 14.7456 460.8 0 0 4.9152 153.6 0 0 16 500.0 0 0 5 156.25 0 0 17.2032 537.6 0 0 6 187.5 0 0 18 562.5 0 0 6.144 192.0 0 0 19.6608 614.4 0 0 7.3728 230.4 0 0 20 625.0 0 0 8 250.0 0 0 Rev. 3.00, 08/03, page 300 of 612 Table 13.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) (MHz) External Input Clock (MHz) Maximum Bit Rate (kbps) (MHz) External Input Clock (MHz) Maximum Bit Rate (kbps) 2 0.5000 31.25 9.8304 2.4576 153.6 2.097152 0.5243 327.68 10 2.5000 156.25 2.4576 0.6144 38.4 12 3.0000 187.5 3 0.7500 46.875 12.288 3.0720 192.0 3.6864 0.9216 57.6 14 3.5000 218.75 4 1.0000 62.5 14.7456 3.6864 230.4 4.9152 1.2288 76.8 16 4.0000 250.0 5 1.2500 78.125 17.2032 4.3008 268.8 6 1.5000 93.75 18 4.5000 281.25 6.144 1.5360 96.0 19.6608 4.9152 307.2 7.3728 1.8432 115.2 20 5.0000 312.5 8 2.0000 125.0 Rev. 3.00, 08/03 page 301 of 612 Table 13.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency (MHz) 2 4 8 Bit Rate (bps) n N n N 110 3 70 250 2 124 2 500 1 249 1k 1 2.5k 10 16 20 n N n N n N 249 3 124 3 249 2 124 2 249 3 124 1 249 2 124 0 199 1 99 1 199 1 5k 0 99 0 199 1 99 10k 0 49 0 99 0 199 25k 0 19 0 39 0 50k 0 9 0 19 100k 0 4 0 250k 0 1 500k 0 0* 1M n N 124 2 249 249 2 99 2 124 1 124 1 199 1 249 0 249 1 99 1 124 79 0 99 0 159 0 199 0 39 0 49 0 79 0 99 9 0 19 0 24 0 39 0 49 0 3 0 7 0 9 0 15 0 19 0 1 0 3 0 4 0 7 0 9 0 0* 0 1 0 3 0 4 0 1 0 0* 2.5M 0 0* 5M [Legend] Blank : Cannot be set. : Can be set, but there will be a degree of error. * : Continuous transfer is not possible. Table 13.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) External Input Maximum Bit Rate (MHz) Clock (MHz) (bps) (MHz) External Input Maximum Bit Rate Clock (MHz) (bps) 2 0.3333 0.333 12 2.0000 2.000 4 0.6667 0.667 14 2.6667 2.667 6 1.0000 1.000 16 3.0000 3.000 8 1.3333 1.333 20 3.3333 3.333 10 1.6667 1.667 Rev. 3.00, 08/03, page 302 of 612 Table 13.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode) (When n = 0 and S = 372) Operating Frequency (MHz) 5.00 7.00 Bit Rate (bps) N Error (%) N 6720 0 0.00 1 7.1424 10.00 10.7136 Error (%) N Error (%) N Error (%) N Error (%) 30 1 28.75 1 0.01 1 7.14 0.00 1 30 1 25 9600 Operating Frequency (MHz) Bit Rate (bps) 13.00 14.2848 16.00 18.00 20.00 N Error (%) N Error (%) N Error (%) N Error (%) N Error (%) 6720 2 13.33 2 4.76 2 6.67 2 20.01 2 33.34 9600 1 8.99 1 0.00 1 12.01 2 15.99 2 6.66 Table 13.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) (When S = 372) (MHz) Maximum Bit Rate (bps) n N 5.00 6720 0 0 7.00 9409 0 0 7.1424 9600 0 0 10.00 13441 0 0 10.7136 14400 0 0 13.00 17473 0 0 14.2848 19200 0 0 16.00 21505 0 0 18.00 24194 0 0 20.00 26882 0 0 Rev. 3.00, 08/03 page 303 of 612 13.3.10 Serial Expansion Mode Register (SEMR_0) SEMR_0 is an 8-bit register that expands SCI_0 functions; such as setting of the basic clock, selecting of the clock source, and automatic setting of the transfer rate. Bit Bit Name Initial Value R/W Description 7 0 R/W Reserved This is a readable/writable bit, but the write value should always be 0. 6 to 4 All 0 Reserved 3 ABCS 0 R/W Asynchronous Basic Clock Select The write value should always be 0. Selects the 1-bit-interval base clock in asynchronous mode. The ABCS setting is valid in asynchronous mode (C/A in SMR = 0). 0: Operates on a basic clock with a frequency of 16-times the transfer rate. 1: Operates on a basic clock with a frequency of 8-times the transfer rate. Rev. 3.00, 08/03, page 304 of 612 Bit Bit Name Initial Value R/W Description 2 ACS2 0 R/W Asynchronous Clock Source Select 1 ACS1 0 R/W 0 ACS0 0 R/W When an average transfer rate is selected, the base clock is set automatically regardless of the ABCS value. Note that average transfer rates are not supported for operating frequencies other than 10.667 MHz and 16 MHz. The ACS0 to ACS0 settings are valid when the external clock input is selected (CKE1 in SCR = 1) in asynchronous mode (C/A in SMR = 0). 000: External clock input 001: Selects the average transfer rate 115.152 kbps only for = 10.667MHz (operates on a basic clock with a frequency of 16-times the transfer rate). 001: Selects the average transfer rate 460.606 kbps only for = 10.667MHz (operates on a basic clock with a frequency of 8-times the transfer rate). 011: Reserved 100: TPU clock input (logical ANDs TIOCA1 and TIOCA2) 101: 115.196 kbps average transfer rate (for = 6 MHz only) is selected (SCI0 operates on base clock with frequency of 16 times transfer rate) 110: 460.784 kbps average transfer rate (for = 6 MHz only) is selected (SCI0 operates on base clock with frequency of 16 times transfer rate) 111: 720 kbps average transfer rate (for = 6 MHz only) is selected (SCI0 operates on base clock with frequency of 8 times transfer rate) Figure 13.3 and 13.4 shows an example of the internal base clock when the average transfer rate is selected. Rev. 3.00, 08/03 page 305 of 612 Figure 13.3 Example of Internal Base Clock when Average Transfer Rate is Selected (1) Rev. 3.00, 08/03, page 306 of 612 1 1 2 2 4 5 1 1 2 2 8 7 10 11 12 4 5 7 8 3.6848 MHz 4 5 6 5.333 MHz 6 13 14 15 16 7 Average error with 460.6kbps = - 0.043% Average transfer rate = 3.6848 MHz/8 = 460.606 kbps 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 1 Average error with 115.2kbps = - 0.043% 1 bit = Base clock x 16* 3 3 9 Average transfer rate = 1.8424 MHz/16 = 115.152 kbps 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 1 1 bit = Base clock x 16* 1.8424 MHz 4 5 6 7 Note: The 1-bit length changes according to the base clock synchronization. 3.6848 MHz (Average) 5.333 MHz x (38/55) = 5.333 MHz 10.667 MHz/2 = Base clock 6 2.667 MHz 3 3 Average transfer rate when = 460.606 MHz 1.8424 MHz (Average) 2.667 MHz x (38/55) = 2.667 MHz 10.667 MHz/4 = Base clock Average transfer rate when = 10.667 MHz 2 2 3 4 3 4 Figure 13.4 Example of Internal Base Clock when Average Transfer Rate is Selected (2) Rev. 3.00, 08/03 page 307 of 612 1 1 3 3 4 5 4 1 1 1 1 8 13 14 15 16 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 1 3 3 4 5 4 6 7 8 9 10 11 12 13 14 15 16 7 5.76 MHz 4 5 6 6 8 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 1 bit = Base clock x 16* 3 4 8 MHz Average error with 720kbps = - 0% Average transfer rate = 5.76 MHz/8 = 720 kbps 2 3 5 Average error with 460.8kbps = - 0.004% 2 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 1 bit = Base clock x 16* 7.3725 MHz 5 6 7 8 8 MHz Average transfer rate = 7.3725 MHz/16 = 460.784 kbps 2 2 Note: The 1-bit length changes according to the base clock synchronization. 5.76 MHz (Average) 8 MHz x (18/5) = 16 MHz/2 = 8 MHz Base clock 7 Average error with 115.2kbps = - 0.004% Average transfer rate when = 720 kbps 7.3725 MHz (Average) 8 MHz x (47/51) = 16 MHz/2 = 8 MHz Base clock 6 1.8431 MHz 5 6 7 8 9 10 11 12 1 bit = Base clock x 16* 2 MHz Average transfer rate = 1.8431 MHz/16 = 115.196 kbps 2 2 Average transfer rate when = 460.784 kbps 1.8431 MHz (Average) 2 MHz x (47/51) = 16 MHz/8 = 2 MHz Base clock Average transfer rate when f = 115.196 kbps 13.4 Operation in Asynchronous Mode Figure 13.5 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by data, a parity bit, and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in reception. The SCI samples the data on the 8th pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is latched at the center of each bit. The SCI_0 samples the data on the 4th pulse of a clock with a frequency of 8 times the length of one bit when the ABCS bit in SEMR_0 is 1. 1 Serial data LSB D0 0 Idle state (mark state) 1 MSB D1 D2 D3 D4 D5 Start bit Transmit/receive data 1 bit 7 or 8 bits D6 D7 0/1 Parity bit 1 bit, or none 1 1 Stop bit 1 or 2 bits One unit of transfer data (character or frame) Figure 13.5 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) 13.4.1 Data Transfer Format Table 13.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, refer to section 13.5, Multiprocessor Communication Function. Rev. 3.00, 08/03, page 308 of 612 Table 13.10 Serial Transfer Formats (Asynchronous Mode) SMR Settings Serial Transfer Format and Frame Length CHR PE MP STOP 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 0 S 8-bit data STOP 0 0 0 1 S 8-bit data STOPSTOP 0 1 0 0 S 8-bit data P STOP 0 1 0 1 S 8-bit data P STOPSTOP 1 0 0 0 S 7-bit data STOP 1 0 0 1 S 7-bit data STOP STOP 1 1 0 0 S 7-bit data P STOP 1 1 0 1 S 7-bit data P STOPSTOP 0 -- 1 0 S 8-bit data MPB STOP 0 -- 1 1 S 8-bit data MPB STOPSTOP 1 -- 1 0 S 7-bit data MPB STOP 1 -- 1 1 S 7-bit data MPB STOPSTOP [Legend] S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit Rev. 3.00, 08/03 page 309 of 612 13.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 13.6. Thus, the reception margin in asynchronous mode is given by formula (1) below. M = { (0.5 - D - 0.5 1 )- N 2N - (L - 0.5) F} x 100 [%] ... Formula (1) Where N D L F : Ratio of bit rate to clock (N = 16) : Clock duty (D = 0.5 to 1.0) : Frame length (L = 9 to 12) : Absolute value of clock rate deviation Assuming values of F (absolute value of clock rate deviation) = 0, D (clock duty) = 0.5, and N (ratio of bit rate to clock) = 16 in formula (1), the reception margin can be given by the formula. M = {0.5 - 1/(2 x 16)} x 100 [%] = 46.875% However, this is only the computed value, and a margin of 20% to 30% should be allowed for in system design. 16 clocks 8 clocks 0 7 15 0 7 15 0 Internal basic clock Receive data (RxD) Start bit D0 Synchronization sampling timing Data sampling timing Figure 13.6 Receive Data Sampling Timing in Asynchronous Mode Rev. 3.00, 08/03, page 310 of 612 D1 13.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/A bit in SMR and the CKE0 and CKE1 bits in SCR. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When an external clock is selected, a base clock with an average transfer rate can be selected by setting bits ACS2 to ACS0 in SEMR_0. When the SCI is operated on an internal clock, the clock can be output from the SCK pin when setting CKE1 = 0 and CKE0 = 1. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 13.7. SCK TxD 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 13.7 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) 13.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. When the external clock is used in asynchronous mode, the clock must be supplied even during initialization. Rev. 3.00, 08/03 page 311 of 612 Start initialization [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. Clear TE and RE bits in SCR to 0 Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [1] When the clock is selected in asynchronous mode, it is output immediately after SCR settings are made. [2] Set the data transfer format in SMR, SCMR and SEMR_0. Set data transfer format in SMR, SCMR, and SEMR_0 [2] Set value in BRR [3] Wait No 1-bit interval elapsed? [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock or an average transfer rate clock by bits AC2 to ACS0 in SEMR_0 is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [4] <Initialization completion> Figure 13.8 Sample SCI Initialization Flowchart 13.4.5 Serial Data Transmission (Asynchronous Mode) Figure 13.9 shows an example of operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt request (TXI) is generated. Continuous transmission is possible because the TXI interrupt routine writes next transmit data to TDR before transmission of the current transmit data has been completed. 3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or multiprocessor bit (may be omitted depending on the format), and stop bit. 4. The SCI checks the TDRE flag at the timing for sending the stop bit. 5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. Rev. 3.00, 08/03, page 312 of 612 6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark state" is entered, in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. 1 Start bit 0 Data D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 Data D0 D1 Parity Stop bit bit D7 0/1 1 1 Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR and TXI interrupt request generated TDRE flag cleared to 0 in request generated TXI interrupt service routine TEI interrupt request generated 1 frame Figure 13.9 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) Rev. 3.00, 08/03 page 313 of 612 Figure 13.10 shows a sample flowchart for data transmission. Initialization [1] Start transmission Read TDRE flag in SSR [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No Yes No [3] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request, and data is written to TDR. (H8S/2268 Group only) [4] Break output at the end of serial transmission: To output a break in serial transmission, set DR for the port corresponding to the TxD pin to 0, clear DDR to 1, then clear the TE TEND = 1 Break output? [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [4] Yes Clear DR to 0 and set DDR to 1 Clear TE bit in SCR to 0 <End> Figure 13.10 Sample Serial Transmission Flowchart Rev. 3.00, 08/03, page 314 of 612 13.4.6 Serial Data Reception (Asynchronous Mode) Figure 13.11 shows an example of operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line. If a start bit is detected, the SCI performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag is still set to 1), the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 4. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 5. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Continuous reception is possible because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has been completed. 1 Start bit 0 Data D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 Data D0 D1 Parity Stop bit bit D7 0/1 0 1 Idle state (mark state) RDRF FER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine ERI interrupt request generated by framing error 1 frame Figure 13.11 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) Rev. 3.00, 08/03 page 315 of 612 Table 13.11 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 13.12 shows a sample flow chart for serial data reception. Table 13.11 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF* ORER FER PER Receive Data Receive Error Type 1 1 0 0 Lost Overrun error 0 0 1 0 Transferred to RDR Framing error 0 0 0 1 Transferred to RDR Parity error 1 1 1 0 Lost Overrun error + framing error 1 1 0 1 Lost Overrun error + parity error 0 0 1 1 Transferred to RDR Framing error + parity error 1 1 1 1 Lost Overrun error + framing error + parity error Note: * The RDRF flag retains the state it had before data reception. Rev. 3.00, 08/03, page 316 of 612 Initialization [1] Start reception [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing and break detection: [2] If a receive error occurs, read the ORER, PER, and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure Yes that the ORER, PER, and FER flags are PERFERORER = 1 all cleared to 0. Reception cannot be [3] resumed if any of these flags are set to No Error processing 1. In the case of a framing error, a break can be detected by reading the (Continued on next page) value of the input port corresponding to the RxD pin. [4] Read RDRF flag in SSR [4] SCI status check and receive data read: Read SSR and check that RDRF = 1, then read the receive data in RDR and RDRF = 1 clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. Yes Read ORER, PER, and FER flags in SSR No Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes [5] [5] Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag, read RDR, and clear the RDRF flag to 0. The RDRF flag is cleared automatically when DTC is activated by an RXI interrupt and the RDR value is read. (H8S/2268 Group only) Clear RE bit in SCR to 0 <End> Figure 13.12 Sample Serial Reception Data Flowchart (1) Rev. 3.00, 08/03 page 317 of 612 [3] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 No PER = 1 Yes Parity error processing Clear ORER, PER, and FER flags in SSR to 0 <End> Figure 13.12 Sample Serial Reception Data Flowchart (2) Rev. 3.00, 08/03, page 318 of 612 13.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is performed, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles; an ID transmission cycle that specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle; if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 13.13 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends the ID code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose IDs do not match continue to skip data until data with a 1 multiprocessor bit is again received. The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1, transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags, RDRF, FER, and ORER to 1, are inhibited until data with a 1 multiprocessor bit is received. On reception of a receive character with a 1 multiprocessor bit, the MPB bit in SSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is rendered invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode. Rev. 3.00, 08/03 page 319 of 612 Transmitting station Serial transmission line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'AA H'01 (MPB = 1) (MPB = 0) ID transmission cycle = Data transmission cycle = receiving station Data transmission to specification receiving station specified by ID [Legend] MPB: Multiprocessor bit Figure 13.13 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) 13.5.1 Multiprocessor Serial Data Transmission Figure 13.14 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode. Rev. 3.00, 08/03, page 320 of 612 Initialization [1] Start transmission Read TDRE flag in SSR [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. No TDRE = 1 Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0 No All data transmitted? [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [3] Yes Read TEND flag in SSR [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request, and data is written to TDR. (H8S/2268 Group only) [4] Break output at the end of serial transmission: To output a break in serial transmission, set the port DR to 0, clear DDR to 1, then clear the TE bit in SCR to 0. No TEND = 1 Yes No Break output? [4] Yes Clear DR to 0 and set DDR to 1 Clear TE bit in SCR to 0 <End> Figure 13.14 Sample Multiprocessor Serial Transmission Flowchart Rev. 3.00, 08/03 page 321 of 612 13.5.2 Multiprocessor Serial Data Reception Figure 13.16 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 13.15 shows an example of SCI operation for multiprocessor format reception. 1 Start bit 0 Data (ID1) MPB D0 D1 D7 1 Stop bit Start bit 1 0 Data (Data1) D0 D1 Stop MPB bit D7 0 1 1 Mark state (idle state) MPIE RDRF RDR value ID1 MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine If not this station's ID, MPIE bit is set to 1 again RXI interrupt request is not generated, and RDR retains its state (a) Data does not match station's ID 1 Start bit 0 Data (ID2) D0 D1 Stop MPB bit D7 1 1 Start bit 0 Data (Data2) D0 D1 D7 Stop MPB bit 0 1 1 Mark state (idle state) MPIE RDRF RDR value ID1 MPIE = 0 Data2 ID2 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine Matches this station's ID, so reception continues, and data is received in RXI interrupt service routine MPIE bit set to 1 again (b) Data matches station's ID Figure 13.15 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Rev. 3.00, 08/03, page 322 of 612 Initialization [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. Start reception Read MPIE bit in SCR [2] ID reception cycle: Set the MPIE bit in SCR to 1. [2] [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station's ID, clear the RDRF flag to 0. Read ORER and FER flags in SSR Yes FERORER = 1 No Read RDRF flag in SSR [3] No RDRF = 1 [4] SCI status check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. Yes Read receive data in RDR [5] Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin value. No This station's ID? Yes Read ORER and FER flags in SSR Yes FERORER = 1 No Read RDRF flag in SSR [4] No RDRF = 1 Yes Read receive data in RDR No All data received? [5] Error processing Yes Clear RE bit in SCR to 0 (Continued on next page) <End> Figure 13.16 Sample Multiprocessor Serial Reception Flowchart (1) Rev. 3.00, 08/03 page 323 of 612 [5] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 <End> Figure 13.16 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 3.00, 08/03, page 324 of 612 13.6 Operation in Clocked Synchronous Mode Figure 13.17 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received synchronous with clock pulses. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. In clocked synchronous mode, the SCI receives data in synchronous with the rising edge of the serial clock. After 8-bit data is output, the transmission line holds the MSB state. In clocked synchronous mode, no parity or multiprocessor bit is added. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication through the use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer. One unit of transfer data (character or frame) * * Synchronization clock LSB Bit 0 Serial data MSB Bit 1 Bit 2 Bit 3 Bit 4 Don't care Bit 5 Bit 6 Bit 7 Don't care Note: * High except in continuous transfer Figure 13.17 Data Format in Synchronous Communication (For LSB-First) 13.6.1 Clock Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCK pin can be selected, according to the setting of CKE0 and CKE1 bits in SCR. When the SCI is operated on an internal clock, the serial clock is output from the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. 13.6.2 SCI Initialization (Clocked Synchronous Mode) Before transmitting and receiving data, the TE and RE bits in SCR should be cleared to 0, then the SCI should be initialized as described in a sample flowchart in figure 13.18. When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. Rev. 3.00, 08/03 page 325 of 612 Start initialization [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE, to 0. Clear TE and RE bits in SCR to 0 [2] Set the data transfer format in SMR and SCMR. Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [1] Set data transfer format in SMR and SCMR [2] Set value in BRR [3] [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. Wait No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [4] <Transfer start> Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared to 0 or set to 1 simultaneously. Figure 13.18 Sample SCI Initialization Flowchart Rev. 3.00, 08/03, page 326 of 612 13.6.3 Serial Data Transmission (Clocked Synchronous Mode) Figure 13.19 shows an example of SCI operation for transmission in clocked synchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if the flag is 0, the SCI recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. Continuous transmission is possible because the TXI interrupt routine writes the next transmit data to TDR before transmission of the current transmit data has been completed. 3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock mode has been specified, and synchronized with the input clock when use of an external clock has been specified. 4. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). 5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. 6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains the output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. The SCK pin is fixed high. Figure 13.20 shows a sample flow chart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1. Make sure that the receive error flags are cleared to 0 before starting transmission. Note that clearing the RE bit to 0 does not clear the receive error flags. Transfer direction Synchronization clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt service routine TXI interrupt request generated TEI interrupt request generated 1 frame Figure 13.19 Sample SCI Transmission Operation in Clocked Synchronous Mode Rev. 3.00, 08/03 page 327 of 612 [1] Initialization Start transmission Read TDRE flag in SSR [2] No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? [3] Yes [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request and data is written to TDR. (H8S/2268 Group only) Read TEND flag in SSR No TEND = 1 Yes Clear TE bit in SCR to 0 <End> Figure 13.20 Sample Serial Transmission Flowchart Rev. 3.00, 08/03, page 328 of 612 13.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 13.21 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization synchronous with a synchronous clock input or output, starts receiving data, and stores the received data in RSR. 2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag in SSR is still set to 1), the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated, receive data is not transferred to RDR, and the RDRF flag remains to be set to 1. 3. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Continuous reception is possible because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has finished. Synchronization clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt RXI interrupt request generated ERI interrupt request generated by overrun error 1 frame Figure 13.21 Example of SCI Operation in Reception Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 13.22 shows a sample flow chart for serial data reception. An overrun error occurs or synchronous clocks are output until the RE bit is cleared to 0 when an internal clock is selected and only receive operation is possible. When a transmission and reception will be carried out in a unit of one frame, be sure to carry out a dummy transmission with only one frame by the simultaneous transmit and receive operations at the same time. Rev. 3.00, 08/03 page 329 of 612 Initialization [1] Start reception [2] Read ORER flag in SSR Yes [3] ORER = 1 No Error processing (Continued below) Read RDRF flag in SSR [4] No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes [5] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the final bit of the current frame is received, reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0 should be finished. The RDRF flag is cleared automatically when the DTC is activated by a receive data full interrupt (RXI) request and the RDR value is read. (H8S/2268 Group only) Clear RE bit in SCR to 0 <End> [3] Error processing Overrun error processing Clear ORER flag in SSR to 0 <End> Figure 13.22 Sample Serial Reception Flowchart Rev. 3.00, 08/03, page 330 of 612 13.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) Figure 13.23 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0. Then simultaneously set TE and RE to 1 with a single instruction. To switch from receive mode to simultaneous transmit and receive mode, after checking that the SCI has finished reception, clear RE to 0. Then after checking that the RDRF and receive error flags (ORER, FER, and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single instruction. Rev. 3.00, 08/03 page 331 of 612 Initialization [1] [1] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. Start transmission/reception Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 [3] Read ORER flag in SSR ORER = 1 No Read RDRF flag in SSR Yes SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial transmission/reception continuation procedure: To continue serial transmission/ reception, before the final bitof the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. Also, before the final bit of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR and clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request and data is written to TDR. Also, the RDRF flag is cleared automatically when the DTC is activated by a receive data full interrupt (RXI) request and the RDR value is read. (H8S/2268 Group Error processing [4] No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? [4] [3] [5] Yes Clear TE and RE bits in SCR to 0 <End> only) Note: When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the TE bit and RE bit to 0, then set both these bits to 1 by one instruction simultaneously. Figure 13.23 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations Rev. 3.00, 08/03, page 332 of 612 13.7 Operation in Smart Card Interface The SCI supports an IC card (Smart Card) interface that conforms to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the Smart Card interface mode is carried out by means of a register setting. 13.7.1 Pin Connection Example Figure 13.24 shows an example of connection with the Smart Card. In communication with an IC card, as both transmission and reception are carried out on a single data transmission line, the TxD pin and RxD pin should be connected to the LSI pin. The data transmission line should be pulled up to the VCC power supply with a resistor. If an IC card is not connected, and the TE and RE bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out. When the clock generated on the Smart Card interface is used by an IC card, the SCK pin output is input to the CLK pin of the IC card. This LSI port output is used as the reset signal. VCC TxD RxD SCK Rx (port) This LSI Data line Clock line Reset line I/O CLK RST IC card Connected equipment Figure 13.24 Schematic Diagram of Smart Card Interface Pin Connections 13.7.2 Data Format (Except for Block Transfer Mode) Figure 13.25 shows the transfer data format in Smart Card interface mode. * One frame consists of 8-bit data plus a parity bit in asynchronous mode. * In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of one bit) is left between the end of the parity bit and the start of the next frame. * If a parity error is detected during reception, a low error signal level is output for one etu period, 10.5 etu after the start bit. * If an error signal is sampled during transmission, the same data is retransmitted automatically after a delay of 2 etu or longer. Rev. 3.00, 08/03 page 333 of 612 When there is no parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp D6 D7 Dp Transmitting station output When a parity error occurs Ds D0 D1 D2 D3 D4 D5 DE Transmitting station output [Legend] DS: D0 to D7: Dp: DE: Receiving station output Start bit Data bits Parity bit Error signal Figure 13.25 Normal Smart Card Interface Data Format Data transfer with other types of IC cards (direct convention and inverse convention) are performed as described in the following. (Z) A Z Z A Z Z Z A A Z Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (Z) State Figure 13.26 Direct Convention (SDIR = SINV = O/E E = 0) With the direction convention type IC and the above sample start character, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. The start character data above is H'3B. For the direct convention type, clear the SDIR and SINV bits in SCMR to 0. According to Smart Card regulations, clear the O/E bit in SMR to 0 to select even parity mode. (Z) A Z Z A A A A A A Z Ds D7 D6 D5 D4 D3 D2 D1 D0 Dp (Z) State Figure 13.27 Inverse Convention (SDIR = SINV = O/E E = 1) With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to state Z, and transfer is performed in MSB-first order. The start character data for the above is H'3F. For the inverse convention type, set the SDIR and SINV bits in SCMR to 1. According to Smart Card regulations, even parity mode is the logic 0 level of the parity bit, and corresponds to state Z. In this LSI, the SINV bit inverts only data bits D0 to D7. Therefore, set the O/E bit in SMR to 1 to invert the parity bit for both transmission and reception. Rev. 3.00, 08/03, page 334 of 612 13.7.3 Block Transfer Mode Operation in block transfer mode is the same as that in the normal Smart Card interface mode, except for the following points. * In reception, though the parity check is performed, no error signal is output even if an error is detected. However, the PER bit in SSR is set to 1 and must be cleared before receiving the parity bit of the next frame. * In transmission, a guard time of at least 1 etu is left between the end of the parity bit and the start of the next frame. * In transmission, because retransmission is not performed, the TEND flag is set to 1, 11.5 etu after transmission start. * As with the normal Smart Card interface, the ERS flag indicates the error signal status, but since error signal transfer is not performed, this flag is always cleared to 0. 13.7.4 Receive Data Sampling Timing and Reception Margin In Smart Card interface mode an internal clock generated by the on-chip baud rate generator can only be used as a transmission/reception clock. In this mode, the SCI operates on a basic clock with a frequency of 32, 64, 372, or 256 times the transfer rate (fixed to 16 times in normal asynchronous mode) as determined by bits BCP1 and BCP0. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. As shown in figure 13.28, by sampling receive data at the rising-edge of the 16th, 32nd, 186th, or 128th pulse of the basic clock, data can be latched at the middle of the bit. The reception margin is given by the following formula. M = | (0.5 - | D - 0.5 | 1 ) - (L - 0.5) F - (1 + F) | x 100% N 2N Where M: Reception margin (%) N: Ratio of bit rate to clock (N = 32, 64, 372, and 256) D: Clock duty (D = 0 to 1.0) L: Frame length (L = 10) F: Absolute value of clock frequency deviation Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin formula is as follows. M = (0.5 - 1/2 x 372) x 100% = 49.866% Rev. 3.00, 08/03 page 335 of 612 372 clocks 186 clocks 0 185 185 371 0 371 0 Internal basic clock Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 13.28 Receive Data Sampling Timing in Smart Card Mode (Using Clock of 372 Times the Transfer Rate) 13.7.5 Initialization Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. 1. Clear the TE and RE bits in SCR to 0. 2. Clear the error flags ERS, PER, and ORER in SSR to 0. 3. Set the GM, BLK, O/E, BCP0, BCP1, CKS0, CKS1 bits in SMR. Set the PE bit to 1. 4. Set the SMIF, SDIR, and SINV bits in SCMR. When the SMIF bit is set to 1, the TxD and RxD pins are both switched from ports to SCI pins, and are placed in the high-impedance state. 5. Set the value corresponding to the bit rate in BRR. 6. Set the CKE0 and CKE1 bits in SCR. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0. If the CKE0 bit is set to 1, the clock is output from the SCK pin. 7. Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE bit and RE bit at the same time, except for self-diagnosis. To switch from receive mode to transmit mode, after checking that the SCI has finished reception, initialize the SCI, and set RE to 0 and TE to 1. Whether SCI has finished reception or not can be checked with the RDRF, PER, or ORER flags. To switch from transmit mode to receive mode, after checking that the SCI has finished transmission, initialize the SCI, and set TE to 0 and RE to 1. Whether SCI has finished transmission or not can be checked with the TEND flag. Rev. 3.00, 08/03, page 336 of 612 13.7.6 Serial Data Transmission (Except for Block Transfer Mode) As data transmission in Smart Card interface mode involves error signal sampling and retransmission processing, the operations are different from those in normal serial communication interface mode (except for block transfer mode). Figure 13.29 illustrates the retransfer operation when the SCI is in transmit mode. 1. If an error signal is sent back from the receiving end after transmission of one frame is complete, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The ERS bit in SSR should be cleared to 0 by the time the next parity bit is sampled. 2. The TEND bit in SSR is not set for a frame in which an error signal indicating an abnormality is received. Data is retransferred from TDR to TSR, and retransmitted automatically. 3. If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set. Transmission of one frame, including a retransfer, is judged to have been completed, and the TEND bit in SSR is set to 1. If the TIE bit in SCR is enabled at this time, a TXI interrupt request is generated. Writing transmit data to TDR transfers the next transmit data. Figure 13.31 shows a flowchart for transmission. In the H8S/2268 Group, a sequence of transmit operations can be performed automatically by specifying the DTC to be activated with a TXI interrupt source. In a transmit operation, the TDRE flag is set to 1 at the same time as the TEND flag in SSR is set, and a TXI interrupt will be generated if the TIE bit in SCR has been set to 1. If the TXI request is designated beforehand as a DTC activation source, the DTC will be activated by the TXI request, and transfer of the transmit data will be carried out. The TDRE and TEND flags are automatically cleared to 0 when data is transferred by the DTC. In the event of an error, the SCI retransmits the same data automatically. During this period, the TEND flag remains cleared to 0 and the DTC is not activated. Therefore, the SCI and DTC will automatically transmit the specified number of bytes in the event of an error, including retransmission. However, the ERS flag is not cleared automatically when an error occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of an error, and the ERS flag will be cleared. When performing transfer using the DTC, it is essential to set and enable the DTC before carrying out SCI setting. For details of the DTC setting procedures, refer to section 8, Data Transfer Controller (DTC). Rev. 3.00, 08/03 page 337 of 612 nth transfer frame Transfer frame n+1 Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Ds D0 D1 D2 D3 D4 TDRE Transfer to TSR from TDR Transfer to TSR from TDR Transfer to TSR from TDR TEND FER/ERS Figure 13.29 Retransfer Operation in SCI Transmit Mode The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag set timing is shown in figure 13.30. I/O data Ds TXI (TEND interrupt) D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Guard time 12.5etu When GM = 0 11.0etu When GM = 1 [Legend] Ds: D0 to D7: Dp: DE: Start bit Data bits Parity bit Error signal Figure 13.30 TEND Flag Generation Timing in Transmission Operation Rev. 3.00, 08/03, page 338 of 612 Start Initialization Start transmission ERS = 0? No Yes Error processing No TEND = 1? Yes Write data to TDR, and clear TDRE flag in SSR to 0 No All data transmitted ? Yes No ERS = 0? Yes Error processing No TEND = 1? Yes Clear TE bit to 0 End Figure 13.31 Example of Transmission Processing Flow Rev. 3.00, 08/03 page 339 of 612 13.7.7 Serial Data Reception (Except for Block Transfer Mode) Data reception in Smart Card interface mode uses the same operation procedure as for normal serial communication interface mode. Figure 13.32 illustrates the retransfer operation when the SCI is in receive mode. 1. If an error is found when the received parity bit is checked, the PER bit in SSR is automatically set to 1. If the RIE bit in SCR is set at this time, an ERI interrupt request is generated. The PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled. 2. The RDRF bit in SSR is not set for a frame in which an error has occurred. 3. If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1, the receive operation is judged to have been completed normally, and the RDRF flag in SSR is automatically set to 1. If the RIE bit in SCR is enabled at this time, an RXI interrupt request is generated. Figure 13.33 shows a flowchart for reception. In the H8S/2268 Group, a sequence of receive operations can be performed automatically by specifying the DTC to be activated using an RXI interrupt source. In a receive operation, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. If the RXI request is designated beforehand as a DTC activation source, the DTC will be activated by the RXI request, and the receive data will be transferred. The RDRF flag is cleared to 0 automatically when data is transferred by the DTC. If an error occurs in receive mode and the ORER or PER flag is set to 1, a transfer error interrupt (ERI) request will be generated. Hence, so the error flag must be cleared to 0. In the event of an error, the DTC is not activated and receive data is skipped. Therefore, receive data is transferred for only the specified number of bytes in the event of an error. Even when a parity error occurs in receive mode and the PER flag is set to 1, the data that has been received is transferred to RDR and can be read from there. Note: For details on receive operations in block transfer mode, refer to section 13.4, Operation in Asynchronous Mode. nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transfer frame n+1 (DE) Ds D0 D1 D2 D3 D4 RDRF PER Figure 13.32 Retransfer Operation in SCI Receive Mode Rev. 3.00, 08/03, page 340 of 612 Start Initialization Start reception ORER = 0 and PER = 0 No Yes Error processing No RDRF = 1? Yes Read RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit to 0 Figure 13.33 Example of Reception Processing Flow 13.7.8 Clock Output Control When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE0 and CKE1 in SCR. At this time, the minimum clock pulse width can be made the specified width. Figure 13.34 shows the timing for fixing the clock output level. In this example, GM is set to 1, CKE1 is cleared to 0, and the CKE0 bit is controlled. CKE0 SCK Specified pulse width Specified pulse width Figure 13.34 Timing for Fixing Clock Output Level When turning on the power or switching between Smart Card interface mode and software standby mode, the following procedures should be followed in order to maintain the clock duty. Rev. 3.00, 08/03 page 341 of 612 Powering on: To secure clock duty from power-on, the following switching procedure should be followed. 1. The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor to fix the potential. 2. Fix the SCK pin to the specified output level with the CKE1 bit in SCR. 3. Set SMR and SCMR, and switch to smart card mode operation. 4. Set the CKE0 bit in SCR to 1 to start clock output. When changing from smart card interface mode to software standby mode: 1. Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to the value for the fixed output state in software standby mode. 2. Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt transmit/receive operation. At the same time, set the CKE1 bit to the value for the fixed output state in software standby mode. 3. Write 0 to the CKE0 bit in SCR to halt the clock. 4. Wait for one serial clock period. During this interval, clock output is fixed at the specified level, with the duty preserved. 5. Make the transition to the software standby state. When returning to smart card interface mode from software standby mode: 1. Exit the software standby state. 2. Write 1 to the CKE0 bit in SCR and output the clock. Signal generation is started with the normal duty. Normal operation Software standby Normal operation Figure 13.35 Clock Halt and Restart Procedure Rev. 3.00, 08/03, page 342 of 612 13.8 Interrupt Sources 13.8.1 Interrupts in Normal Serial Communication Interface Mode Table 13.12 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC to perform data transfer. The TDRE flag is cleared to 0 automatically when data is transferred by the DTC. (H8S/2268 Group only) When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt request can activate the DTC to transfer data. The RDRF flag is cleared to 0 automatically when data is transferred by the DTC. (H8S/2268 Group only) A TEI interrupt is requested when the TEND flag is set to 1 and the TEIE bit is set to 1. If a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt has priority for acceptance. However, if the TDRE and TEND flags are cleared simultaneously by the TXI interrupt routine, the SCI cannot branch to the TEI interrupt routine later. Rev. 3.00, 08/03 page 343 of 612 Table 13.12 Interrupt Sources of Serial Communication Interface Mode 2 1 Channel Name Interrupt Source Interrupt Flag DTC Activation* Priority* 0 ERI0 Receive Error ORER, FER, PER Not possible High RXI0 Receive Data Full RDRF Possible TXI0 Transmit Data Empty TDRE Possible TEI0 Transmission End TEND Not possible ERI1 Receive Error ORER, FER, PER Not possible RXI1 Receive Data Full RDRF Possible TXI1 Transmit Data Empty TDRE Possible TEI1 Transmission End TEND Not possible ERI2 Receive Error ORER, FER, PER Not possible RXI2 Receive Data Full RDRF Possible TXI2 Transmit Data Empty TDRE Possible TEI2 Transmission End TEND Not possible 1 2 Low Notes: 1. Indicates the initial state immediately after a reset. Priorities in channels can be changed by the interrupt controller. (H8S/2268 Group only) 2. Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 344 of 612 13.8.2 Interrupts in Smart Card Interface Mode Table 13.13 shows the interrupt sources in Smart Card interface mode. The transmit end interrupt (TEI) request cannot be used in this mode. Note: In case of block transfer mode, see 13.8.1, Interrupts in Nomal Serial Communication Interface Mode. Table 13.13 Interrupt Sources in Smart Card Interface Mode Channel Name Interrupt Source Interrupt Flag DTC 2 Activation* Priority* 0 ERI0 Receive Error, detection ORER, PER, ERS Not possible High 1 2 RXI0 Receive Data Full RDRF Possible TXI0 Transmit Data Empty TEND Possible ERI1 Receive Error, detection ORER, PER, ERS Not possible RXI1 Receive Data Full RDRF Possible TXI1 Transmit Data Empty TEND Possible ERI2 Receive Error, detection ORER, PER, ERS Not possible RXI2 Receive Data Full RDRF Possible TXI2 Transmit Data Empty TEND Possible 1 Low Notes: 1. Indicates the initial state immediately after a reset. Priorities in channels can be changed by the interrupt controller. (H8S/2268 Group only) 2. Supported only by the H8S/2268 Group. 13.9 13.9.1 Usage Notes Module Stop Mode Setting SCI operation can be disabled or enabled using the module stop control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 22, Power-Down Modes. 13.9.2 Break Detection and Processing (Asynchronous mode only) When framing error (FER) detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, setting the FER flag, and possibly the PER flag. Note that as the SCI continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. Rev. 3.00, 08/03 page 345 of 612 13.9.3 Mark State and Break Detection (Asynchronous mode only) When TE is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are determined by DDR. This can be used to set the TxD pin to mark state (high level) or send a break during serial data transmission. To maintain the communication line at mark state until TE is set to 1, set both DDR and DR to 1. As TE is cleared to 0 at this point, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To send a break during serial transmission, first set PDR to 1 and DR to 0, and then clear TE to 0. When TE is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. 13.9.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0. 13.9.5 Restrictions on Use of DTC (H8S/2268 Group Only) * When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 clock cycles after TDR is updated by the DTC. Misoperation may occur if the transmit clock is input within 4 clocks after TDR is updated. (Figure 13.36) * When RDR is read by the DTC, be sure to set the activation source to the relevant SCI reception data full interrupt (RXI). SCK t TDRE LSB Serial data D0 D1 D2 D3 D4 D5 D6 D7 Note: When operating on an external clock, set t > 4 clocks. Figure 13.36 Example of Clocked Synchronous Transmission by DTC Rev. 3.00, 08/03, page 346 of 612 13.9.6 Operation in Case of Mode Transition * Transmission Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition. TSR, TDR, and SSR are reset. The output pin states in module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode depend on the port settings, and becomes high-level output after the relevant mode is cleared. If a transition is made during transmission, the data being transmitted will be undefined. When transmitting without changing the transmit mode after the relevant mode is cleared, transmission can be started by setting TE to 1 again, and performing the following sequence: SSR read -> TDR write -> TDRE clearance. To transmit with a different transmit mode after clearing the relevant mode, the procedure must be started again from initialization. Figure 13.37 shows a sample flowchart for mode transition during transmission. Port pin states are shown in figures 13.38 and 13.39. Operation should also be stopped (by clearing TE, TIE, and TEIE to 0) before making a transition from transmission by DTC transfer to module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition. To perform transmission with the DTC after the relevant mode is cleared, setting TE and TIE to 1 will set the TXI flag and start DTC transmission. (H8S/2268 Group only) * Reception Receive operation should be stopped (by clearing RE to 0) before making a module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition. RSR, RDR, and SSR are reset. If a transition is made without stopping operation, the data being received will be invalid. To continue receiving without changing the reception mode after the relevant mode is cleared, set RE to 1 before starting reception. To receive with a different receive mode, the procedure must be started again from initialization. Figure 13.40 shows a sample flowchart for mode transition during reception. Rev. 3.00, 08/03 page 347 of 612 <Transmission> No All data transmitted? [1] [1] Data being transmitted is interrupted. After exiting software standby mode, etc., normal CPU transmission is possible by setting TE to 1, reading SSR, writing TDR, and clearing TDRE to 0, but note that if the DTC has been activated, the remaining data in DTCRAM will be transmitted when TE and TIE are set to 1. (H8S/2268 Group only) [2] If TIE and TEIE are set to 1, clear them to 0 in the same way. [3] Includes module stop mode, watch mode, subactive mode, and subsleep mode. Yes Read TEND flag in SSR No TEND = 1 Yes [2] TE = 0 Transition to software standby mode, etc. [3] Exit from software standby mode, etc. Change operating mode? No Yes Initialization TE = 1 <Start of transmission> Figure 13.37 Sample Flowchart for Mode Transition during Transmission Start of transmission End of transmission Transition to software standby Exit from software standby TE bit Port input/output SCK output pin TxD output pin Port input/output High output Port Start SCI TxD output Stop Port input/output Port Figure 13.38 Asynchronous Transmission Using Internal Clock Rev. 3.00, 08/03, page 348 of 612 High output SCI TxD output Start of transmission End of transmission Transition to software standby Exit from software standby TE bit Port input/output SCK output pin TxD output pin Port input/output Last TxD bit held Marking output Port SCI TxD output Port input/output Port High output* SCI TxD output Note: * Initialized by software standby. Figure 13.39 Synchronous Transmission Using Internal Clock <Reception> Read RDRF flag in SSR RDRF = 1 No [1] [1] Receive data being received becomes invalid. [2] [2] Includes module stop mode, watch mode, subactive mode, and subsleep mode. Yes Read receive data in RDR RE = 0 Transition to software standby mode, etc. Exit from software standby mode, etc. Change operating mode? No Yes Initialization RE = 1 <Start of reception> Figure 13.40 Sample Flowchart for Mode Transition during Reception Rev. 3.00, 08/03 page 349 of 612 13.9.7 Switching from SCK Pin Function to Port Pin Function: * Problem in Operation: When switching the SCK pin function to the output port function (highlevel output) by making the following settings while DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1 (synchronous mode), low-level output occurs for one half-cycle. 1. End of serial data transmission 2. TE bit = 0 3. C/A bit = 0 ... switchover to port output 4. Occurrence of low-level output (see figure 13.41) Half-cycle low-level output SCK/port 1. End of transmission Data Bit 6 4. Low-level output Bit 7 TE 2. TE = 0 C/A 3. C/A = 0 CKE1 CKE0 Figure 13.41 Operation when Switching from SCK Pin Function to Port Pin Function * Sample Procedure for Avoiding Low-Level Output: As this sample procedure temporarily places the SCK pin in the input state, the SCK/port pin should be pulled up beforehand with an external circuit. With DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following settings in the order shown. 1. End of serial data transmission 2. TE bit = 0 3. CKE1 bit = 1 4. C/A bit = 0 ... switchover to port output 5. CKE1 bit = 0 Rev. 3.00, 08/03, page 350 of 612 High-level output SCK/port 1. End of transmission Data Bit 6 Bit 7 2. TE = 0 TE 4. C/A = 0 C/A 3. CKE1 = 1 CKE1 5. CKE1 = 0 CKE0 Figure 13.42 Operation when Switching from SCK Pin Function to Port Pin Function (Example of Preventing Low-Level Output) 13.9.8 Assignment and Selection of Registers Some serial communication interface registers are assigned to the same address as other registers. Register selection is performed by means of the IICE bit in the serial control register (SCRX). For details on register addresses, see section 24, List of Registers. Rev. 3.00, 08/03 page 351 of 612 Rev. 3.00, 08/03, page 352 of 612 Section 14 I2C Bus Interface (IIC) (Option) An I2C bus interface is available as an option. Observe the following notes when using this option. 1. For mask-ROM versions, a W is added to the part number in products in which this optional function is used. Examples: HD6432268WTE 2. The product number is identical for F-ZTAT versions. However, be sure to inform your Renesas sales representative if you will be using this option. The H8S/2268 Group has an internal I2C bus interface of two channels, while the H8S/2264 Group has that of one channel. The I2C bus interface conforms to and provides a subset of the Philips I2C bus (inter-IC bus) interface functions. The register configuration that controls the I2C bus differs partly from the Philips configuration, however. The I2C bus interface data transfer is performed using a data line (SDA) and a clock line (SCL) for each channel, which allows efficient use of connectors and the area of the PCB. 14.1 Features * Selection of I2C format or clocked synchronous serial format I2C bus format: addressing format with acknowledge bit, for master/slave operation Clocked synchronous serial format: non-addressing format without acknowledge bit, for master operation only I2C bus format * Two ways of setting slave address * Start and stop conditions generated automatically in master mode * Selection of acknowledge output levels when receiving * Automatic loading of acknowledge bit when transmitting * Wait function in master mode A wait can be inserted by driving the SCL pin low after data transfer, excluding acknowledgement. The wait can be cleared by clearing the interrupt flag. * Wait function in slave mode A wait request can be generated by driving the SCL pin low after data transfer, excluding acknowledgement. The wait request is cleared when the next transfer becomes possible. IICIC05B_000020020700 Rev. 3.00, 08/03, page 353 of 612 * Three interrupt sources Data transfer end (including transmission mode transition with I2C bus format and address reception after loss of master arbitration) Address match: when any slave address matches or the general call address is received in slave receive mode Stop condition detection * Selection of 16 internal clocks (in master mode) * Direct bus drive Two pins, P35/SCL0 and P34/SDA0, function as NMOS open-drain outputs when the bus drive function is selected. Two pins - P33/SCL1 and P32/SDA1 - function as NMOS-only outputs when the bus drive function is selected. (H8S/2268 Group only) Figure 14.1 shows a block diagram of the I2C bus interface. Figure 14.2 shows an example of I/O pin connections to external circuits. Channel I/O pins are NMOS open drains, and it is possible to apply voltages in excess of the power supply (Vcc) voltage for this LSI. Set the upper limit of voltage applied to the power supply (Vcc) power supply range +0.3 V, i.e. 5.8 V. Channel 1 (H8S/2268 Group only) I/O pins are driven solely by NMOS, so in terms of appearance they carry out the same operations as an NMOS open drain. However, the voltage which can be applied to the I/O pins depends on the voltage of the power supply (Vcc) of this LSI. Rev. 3.00, 08/03, page 354 of 612 PS ICCR SCL Clock control Noise canceler Bus state decision circuit SDA ICSR Arbitration decision circuit ICDRT Output data control circuit ICDRS Internal data bus ICMR ICDRR Noise canceler Address comparator SAR, SARX [Legend] ICCR: I2C bus control register ICMR: I2C bus mode register ICSR: I2C bus status register ICDR: I2C bus data register SAR: Slave address register SARX: Slave address register X PS: Prescaler Interrupt generator Interrupt request Figure 14.1 Block Diagram of I2C Bus Interface Rev. 3.00, 08/03, page 355 of 612 VDD VCC SCL SCL SDA SDA SCL in SDA in SCL SDA SDA out (Master) SCL in This LSI SCL out SCL out SDA in SDA in SDA out SDA out SCL in (Slave 1) SCL SDA SCL out (Slave 2) Figure 14.2 I2C Bus Interface Connections (Example: This LSI as Master) 14.2 Input/Output Pins Table 14.1 shows the pin configuration for the I2C bus interface. Table 14.1 Pin Configuration 1 Name Abbreviation* I/O Function Serial clock SCL0 I/O IIC_0 serial clock input/output SDA0 I/O IIC_0 serial data input/output Serial clock* SCL1 I/O IIC_1 serial clock input/output 2 SDA1 I/O IIC_1 serial data input/output Serial data 2 Serial data* Notes: 1. In the text, the channel subscript is omitted, and only SCL and SDA are used. 2. Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 356 of 612 14.3 Register Descriptions The I2C bus interface has the following registers. Registers ICDR and SARX and registers ICMR and SAR are allocated to the same addresses. Accessible addresses differ depending on the ICE bit in ICCR. SAR and SARX are accessed when ICE is 0, and ICMR and ICDR are accessed when ICE is 1. For details on the module stop control register, refer to section 22.1.2, Module Stop Control Registers A to D (MSTPCRA to MSTPCRD). * I2C bus data register_0 (ICDR_0) * Slave address register_0 (SAR_0) * Second slave address register_0 (SARX_0) * I2C bus mode register_0 (ICMR_0) * I2C bus control register_0 (ICCR_0) * I2C bus status register_0 (ICSR_0) * I2C bus data register_1 (ICDR_1)* * Slave address register_1 (SAR_1)* * Second slave address register_1 (SARX_1)* * I2C bus mode register_1 (ICMR_1)* * I2C bus control register_1 (ICCR_1)* * I2C bus status register_1 (ICSR_1)* * DDC switch register (DDCSWR) * Serial control register X (SCRX) Note: * Supported only by the H8S/2268 Group. 14.3.1 I2C Bus Data Register (ICDR) ICDR is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when receiving. ICDR is divided internally into a shift register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). Data transfers among the three registers are performed automatically in coordination with changes in the bus state, and affect the status of internal flags such as TDRE and RDRF. When TDRE is 1 and the transmit buffer is empty, TDRE shows that the next transmit data can be written from the CPU. When RDRF is 1, it shows that the valid receive data is stored in the receive buffer. If I2C is in transmit mode and the next data is in ICDRT (the TDRE flag is 0) following transmission/reception of one frame of data using ICDRS, data is transferred automatically from ICDRT to ICDRS. If I2C is in receive mode and no previous data remains in ICDRR (the RDRF flag is 0) following transmission/reception of one frame of data using ICDRS, data is transferred automatically from ICDRS to ICDRR. Rev. 3.00, 08/03, page 357 of 612 If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and receive data are stored differently. Transmit data should be written justified toward the MSB side when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1. ICDR can be written and read only when the ICE bit is set to 1 in ICCR. The value of ICDR is undefined after a reset. The TDRE and RDRF flags are set and cleared under the conditions shown below. Setting the TDRE and RDRF flags affects the status of the interrupt flags. Bit Bit Name Initial Value R/W Description TDRE Transmit Data Register Empty [Setting conditions] * In transmit mode, when a start condition is detected in the bus line state after a start condition is issued in 2 master mode with the I C bus format or serial format selected * When data is transferred from ICDRT to ICDRS * When a switch is made from receive mode to transmit mode after detection of a start condition [Clearing conditions] RDRF * When transmit data is written in ICDR in transmit mode * When a stop condition is detected in the bus line state 2 after a stop condition is issued with the I C bus format or serial format selected * When a stop condition is detected with the I C bus format selected * In receive mode 2 Receive Data Register Full [Setting condition] When data is transferred from ICDRS to ICDRR [Clearing condition] When ICDR (ICDRR) receive data is read in receive mode Rev. 3.00, 08/03, page 358 of 612 14.3.2 Slave Address Register (SAR) SAR selects the slave address and selects the transfer format. SAR can be written and read only when the ICE bit is cleared to 0 in ICCR. Bit Bit Name Initial Value R/W Description 7 SVA6 0 R/W Slave Address 6 to 0 6 SVA5 0 R/W Sets a slave address 5 SVA4 0 R/W 4 SVA3 0 R/W 3 SVA2 0 R/W 2 SVA1 0 R/W 1 SVA0 0 R/W 0 FS 0 R/W 14.3.3 Second Slave Address Register (SARX) Selects the transfer format together with the FSX bit in SARX. Refer to table 14.2. SARX stores the second slave address and selects the transfer format. SARX can be written and read only when the ICE bit is cleared to 0 in ICCR. Bit Bit Name Initial Value R/W Description 7 SVAX6 0 R/W Slave Address 6 to 0 6 SVAX5 0 R/W Sets the second slave address 5 SVAX4 0 R/W 4 SVAX3 0 R/W 3 SVAX2 0 R/W 2 SVAX1 0 R/W 1 SVAX0 0 R/W 0 FSX 1 R/W Selects the transfer format together with the FS bit in SAR. Refer to table 14.2. Rev. 3.00, 08/03, page 359 of 612 Table 14.2 Transfer Format SAR SARX FS FSX I C Transfer Format 0 0 SAR and SARX are used as the slave addresses with 2 the I C bus format. 0 1 Only SAR is used as the slave address with the I C bus format. 1 0 Only SARX is used as the slave address with the I C bus format. 1 1 Clock synchronous serial format (SAR and SARX are invalid) 14.3.4 2 2 2 I2C Bus Mode Register (ICMR) ICMR sets the transfer format and transfer rate. It can only be accessed when the ICE bit in ICCR is 1. Bit Bit Name Initial Value R/W Description 7 MLS 0 R/W MSB-First/LSB-First Select 0: MSB-first 1: LSB-first 2 Set this bit to 0 when the I C bus format is used. 6 WAIT 0 R/W Wait Insertion Bit 2 This bit is valid only in master mode with the I C bus format. When WAIT is set to 1, after the fall of the clock for the final data bit, the IRIC flag is set to 1 in ICCR, and a wait state begins (with SCL at the low level). When the IRIC flag is cleared to 0 in ICCR, the wait ends and the acknowledge bit is transferred. If WAIT is cleared to 0, data and acknowledge bits are transferred consecutively with no wait inserted. The IRIC flag in ICCR is set to 1 on completion of the acknowledge bit transfer, regardless of the WAIT setting. 5 CKS2 0 R/W Serial Clock Select 2 to 0 4 CKS1 0 R/W This bit is valid only in master mode. 3 CKS0 0 R/W These bits select the required transfer rate, together with the IICX 1 and IICX0 bit in SCRX. Refer table 14.3. Rev. 3.00, 08/03, page 360 of 612 Bit Bit Name Initial Value R/W Description 2 BC2 0 R/W Bit Counter 2 to 0 1 BC1 0 R/W 0 BC0 0 R/W These bits specify the number of bits to be transferred 2 next. With the I C bus format, the data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000, the setting should be made while the SCL line is low. The value returns to 000 at the end of a data transfer, including the acknowledge bit. 2 I C Bus Format Clocked Synchronous Mode 000: 9 bit 000: 8 bit 001: 2 bit 001: 1 bit 010: 3 bit 010: 2 bit 011: 4 bit 011: 3 bit 100: 5 bit 100: 4 bit 101: 6 bit 101: 5 bit 110: 7 bit 110: 6 bit 111: 8 bit 111: 7 bit Rev. 3.00, 08/03, page 361 of 612 Table 14.3 I2C Transfer Rate SCRX ICMR Bit 5 or 6 Bit 5 Bit 4 Bit 3 Transfer Rate IICX CKS2 CKS1 CKS0 Clock = 5 MHz = 8 MHz = 10 MHz = 16 MHz = 20 MHz 0 0 0 0 /28 179MHz 286kHz 357kHz 571kHz* 714kHz* 0 0 0 1 /40 125kHz 200kHz 250kHz 400kHz 500kHz* 0 0 1 0 /48 104kHz 167kHz 208kHz 333kHz 417kHz 0 0 1 1 /64 78.1kHz 125kHz 156kHz 250kHz 313kHz 0 1 0 0 /80 62.5kHz 100kHz 125kHz 200kHz 250kHz 0 1 0 1 /100 50.0kHz 80.0kHz 100kHz 160kHz 200kHz 0 1 1 0 /112 44.6kHz 71.4kHz 89.3kHz 143kHz 179kHz 0 1 1 1 /128 39.1kHz 62.5kHz 78.1kHz 125kHz 156kHz 1 0 0 0 /56 89.3kHz 143kHz 179kHz 286kHz 357kHz 1 0 0 1 /80 62.5kHz 100kHz 125kHz 200kHz 250kHz 1 0 1 0 /96 52.1kHz 83.3kHz 104kHz 167kHz 208kHz 1 0 1 1 /128 39.1kHz 62.5kHz 78.1kHz 125kHz 156kHz 1 1 0 0 /160 31.3kHz 50.0kHz 62.5kHz 100kHz 125kHz 1 1 0 1 /200 25.0kHz 40.0kHz 50.0kHz 80.0kHz 100kHz 1 1 1 0 /224 22.3kHz 35.7kHz 44.6kHz 71.4kHz 89.3kHz 1 1 1 1 /256 19.5kHz 31.3kHz 39.1kHz 62.5kHz 78.1kHz Note: * Out of the range of the I2C bus interface specification (normal mode: 100kHz in max. and high-speed mode: 400kHz in max) Rev. 3.00, 08/03, page 362 of 612 14.3.5 Serial Control Register X (SCRX) SCRX controls the IIC operating modes. Bit Bit Name Initial Value R/W Description 7 0 R/W Reserved The initial value should not be changed. 2 6 IICX1* 0 R/W I C Transfer Rate Select 1 and 0 5 IICX0 0 R/W Selects the transfer rate in master mode, together with bits CKS2 to CKS0 in ICMR. Refer to table 14.3. 4 IICE 0 R/W I C Master Enable Note:* In the H8S/2264 Group, this bit is reserved. 2 Controls CPU access to the IIC data register and control registers (ICCR, ICSR, ICDR/SARX, and ICMR/SAR). 0: CPU access to the IIC data register and control registers is disabled. 1: CPU access to the IIC data register and control registers is enabled. 3 FLSHE 0 R/W For details on this bit, refer to section 20.5.7, Serial Control Register X (SCRX). 2 to 0 All 0 R/W Reserved The initial value should not be changed. Rev. 3.00, 08/03, page 363 of 612 14.3.6 I2C Bus Control Register (ICCR) I2C bus control register (ICCR) consists of the control bits and interrupt request flags of I2C bus interface. Bit Bit Name Initial Value R/W Description 7 ICE 0 R/W I C Bus Interface Enable 2 2 When this bit is set to 1, the I C bus interface module is enabled to send/receive data and drive the bus since it is connected to the SCL and SDA pins. ICMR and ICDR can be accessed. When this bit is cleared, the module is halted and separated from the SCL and SDA pins. SAR and SARX can be accessed. 6 IEIC 0 R/W 2 I C Bus Interface Interrupt Enable When this bit is 1, interrupts are enabled by IRIC. 5 MST 0 4 TRS 0 R/W Master/Slave Select Transmit/Receive Select 00: Slave receive mode 01: Slave transmit mode 10: Master receive mode 11: Master transmit mode Both these bits will be cleared by hardware when they 2 lose in a bus contention in master mode of the I C bus format. In slave receive mode, the R/W bit in the first frame immediately after the start automatically sets these bits in receive mode or transmit mode by using hardware. The settings can be made again for the bits that were set/cleared by hardware, by reading these bits. When the TRS bit is intended to change during a transfer, the bit will not be switched until the frame transfer is completed, including acknowledgement. Rev. 3.00, 08/03, page 364 of 612 Bit Bit Name Initial Value R/W Description 3 ACKE 0 R/W Acknowledge Bit Judgement Selection 0: The value of the acknowledge bit is ignored, and continuous transfer is performed. The value of the received acknowledge bit is not indicated by the ACKB bit, which is always 0. 1: If the acknowledge bit is 1, continuous transfer is interrupted. In the H8S/2268 Group, the DTC* can be used to perform continuous transfer. The DTC* is activated when the IRTR interrupt flag is set to 1 (IRTR us one of two interrupt flags, the other being IRIC). When the ACKE bit is 0, the TDRE, IRIC, and IRTR flags are set on completion of data transmission, regardless of the acknowledge bit. When the ACKE bit is 1, the TDRE, IRIC, and IRTR flags are set on completion of data transmission when the acknowledge bit is 0, and the IRIC flag alone is set on completion of data transmission when the acknowledge bit is 1. When the DTC* is activated, the TDRE, IRIC, and IRTR flags are cleared to 0 after the specified number of data transfers have been executed. Consequently, interrupts are not generated during continuos data transfer, but if data transmission is completed with a 1 acknowledge bit when the ACKE bit is set to 1, the DTC* is not activated and an interrupt is generated, if enabled. Depending on the receiving device, the acknowledge bit may be significant, in indicating completion of processing of the received data, for instance, or may be fixed at 1 and have no significance. Note: * Supported only by the H8S/2268 Group. 2 BBSY 0 R/W Bus Busy In slave mode, reading the BBSY flag enables to confirm 2 whether the I C bus is occupied or released. The BBSY flag is set to 0 when the SDA level changes from high to low under the condition of SCl = high, assuming that the start condition has been issued. The BBSY flag is cleared to 0 when the SDA level changes from low to high under the condition of SCl = high, assuming that the start condition has been issued. Writing to the BBSY flag in slave mode is disabled. In master mode, the BBSY flag is used to issue start and stop conditions. Write 1 to BBSY and 0 to SCP to issue a start condition. Follow this procedure when also retransmitting a start condition. To issue a start/stop 2 condition, use the MOV instruction. The I C bus interface must be set in master transmit mode before the issue of a start condition. Rev. 3.00, 08/03, page 365 of 612 Bit Bit Name Initial Value R/W Description 1 IRIC 0 R/W I2C Bus Interface Interrupt Request Flag Also see table 14.4. [Setting conditions] In I2C bus format master mode * When a start condition is detected in the bus line state after a start condition is issued (when the TDRE flag is set to 1 because of first frame transmission) * When a wait is inserted between the data and acknowledge bit when WAIT = 1 * At the end of data transfer (when the TDRE or RDRF flag is set to 1) * When a slave address is received after bus arbitration is lost (when the AL flag is set to1) * When 1 is received as the acknowledge bit when the ACKE bit is 1(when the ACKB bit is set to 1) In I2C bus format slave mode * When the slave address (SVA, SVAX) matches (when the AAS and AASX flags are set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (when the TDRE or RDRF flag is set to 1) * When the general call address is detected (when the ADZ flag is set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection(when the TDRE or RDRF flag is set to 1) * When 1 is received as the acknowledge bit when the ACKE bit is 1(when the ACKB bit is set to 1) * When a stop condition is detected(when the STOP or ESTP flag is set to 1) With clocked synchronous serial format * At the end of data transfer (when the TDRE or RDRF flag is set to 1) * When a start condition is detected with serial format selected When a condition occurs in which internal flag of TDRE and RDFR is set to 1 except for the above [Clearing condition] When 0 is written in IRIC after reading IRIC = 1 * When ICDR is read/written by DTC (H8S/2268 Group only) (When TDRE or RDRF flag is cleared to 0) (AS it might not be a condition to clear, for details, see description of DTC operation next page) Rev. 3.00, 08/03, page 366 of 612 Bit Bit Name Initial Value R/W Description 0 SCP 1 R/W Start Condition/Stop Condition Prohibit bit The SCP bit controls the issue of start/stop conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP. This bit is always read as 1. If 1 is written, the data is not stored. When, with the I2C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set IRIC to 1. Although each source has a corresponding flag, caution is needed at the end of a transfer. When the TDRE or RDRF internal flag is set, the readable IRTR flag may or may not be set. In the H8S/2268 Group, even when data transfer is complete, the DTC activation request flag, IRTR, is not set until a retransmission start condition or stop condition is detected after a slave address (SVA) or general call address matched in the I2C bus format slave mode. Even when the IRIC flag and IRTR flag are set, the TDRE or RDRF internal flag may not be set. For a continuous transfer using the DTC in the H8S/2268 Group, the IRIC or IRTR flag is not cleared at the completion of the specified number of times of transfers. On the other hand, the TDRE and RDRF flags are cleared because the specified number of times of read/write operations have been complete. Table 14.4 shows the relationship between the flags and the transfer states. Rev. 3.00, 08/03, page 367 of 612 Table 14.4 Flags and Transfer States MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB State 1/0 1/0 0 0 0 0 0 0 0 0 0 Idle state (flag clearing required) 1 1 0 0 0 0 0 0 0 0 0 Start condition issuance 1 1 1 0 0 1 0 0 0 0 0 Start condition established 1 1/0 1 0 0 0 0 0 0 0 0/1 Master mode wait 1 1/0 1 0 0 1 0 0 0 0 0/1 Master mode transmit/receive end 0 0 1 0 0 0 1/0 1 1/0 1/0 0 Arbitration lost 0 0 1 0 0 0 0 0 1 0 0 SAR match by first frame in slave mode 0 0 1 0 0 0 0 0 1 1 0 General call address match 0 0 1 0 0 0 1 0 0 0 0 SARX match 0 1/0 1 0 0 0 0 0 0 0 0/1 Slave mode transmit/receive end(except after SARX match) 0 1/0 1 0 0 1 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 Slave mode transmit/receive end(after SARX match) 0 1/0 0 1/0 1/0 0 0 0 0 0 0/1 Stop condition detected 14.3.7 I2C Bus Status Register (ICSR) ICSR consists of status flags. Bit Bit Name Initial Value R/W 7 ESTP 0 R/(W)* Error Stop Condition Detection Flag Description 2 This bit is valid in I C bus format slave mode. [Setting condition] When a stop condition is detected during frame transfer. [Clearing condition] 6 STOP 0 * When 0 is written in ESTP after reading the state of 1 * When the IRIC flag is cleared to 0 R/(W)* Normal Stop Condition Detection Flag 2 This bit is valid in I C bus format slave mode. [Setting condition] When a stop condition is detected during frame transfer. [Clearing condition] Rev. 3.00, 08/03, page 368 of 612 * When 0 is written in STOP after reading STOP = 1 * When the IRIC flag is cleared to 0 Bit Bit Name Initial Value 5 IRTR 0 R/W Description 2 R/(W)* I C Bus Interface Continuous Transmission/Reception Interrupt Request Flag [Setting conditions] 2 In I C bus interface slave mode * When the TDRE or RDRF flag is set to 1 when AASX =1 2 In I C bus interface other modes * When the TDRE or RDRF flag is set to 1 [Clearing conditions] 4 AASX 0 * When 0 is written in IRTR after reading IRTR = 1 * When the IRIC flag is cleared to 0 R/(W)* Second Slave Address Recognition Flag [Setting condition] When the second slave address is detected in slave receive mode and FSX = 0 [Clearing conditions] 3 AL 0 * When 0 is written in AASX after reading AASX = 1 * When a start condition is detected * In master mode R/(W)* Arbitration Lost Flag Indicates that bus arbitration was lost in master mode. [Setting condition] * When the internal SDA and SDA pin do not match at the rise of SCL. * When the internal SCL is high at the fall of SCL. [Clearing conditions] * When 0 is written in AL after reading AL = 1 * When ICDR data is written (transmit mode) or read (receive mode) Rev. 3.00, 08/03, page 369 of 612 Bit Bit Name Initial Value R/W 2 AAS 0 R/(W)* Slave Address Recognition Flag Description [Setting condition] When the slave address or general call address is detected in slave receive mode and FS = 0. [Clearing conditions] 1 ADZ 0 * When ICDR data is written (transmit mode) or read (receive mode) * When 0 is written in AAS after reading AAS = 1 * In master mode R/(W)* General Call Address Recognition Flag 2 This bit is valid in I C bus format slave receive mode. [Setting condition] When the general call address is detected in slave receive mode and FSX = 0 or FS = 0. [Clearing conditions] 0 ACKB 0 * When ICDR data is written (transmit mode) or read (receive mode) * When 0 is written in ADZ after reading ADZ = 1 * In master mode R/(W)* Acknowledge Bit Stores acknowledge bit. 0: At reception, outputs 0 in the acknowledge output timing. At transmission, indicates that acknowledge was sent (0) from the receive device. 1: At reception, outputs 1 in the acknowledge output timing. At transmission, indicates that acknowledge was not sent (1) from the receive device. Note: Only a 0 can be written to this bit, to clear the flag. Rev. 3.00, 08/03, page 370 of 612 14.3.8 DDC Switch Register (DDCSWR) DDCSWR controls the I2C bus interface format automatic switching function and internal latch clear. Bit Bit Name 7 to 4 Initial Value All 0 R/W Description 1 R/(W)* Reserved The write value should always be 0. 2 3 CLR3 1 W I C Bus Interface Clear 3 to 0: 2 CLR2 1 W 1 CLR1 1 W 0 CLR0 1 W When bits CLR3 to CLR0 are set, a clear signal is 2 generated for the I C bus interface internal latch circuit, and the internal state is initialized. The write data for 2 these bits is not retained. To perform I C clearance, bits CLR3 to CLR0 must be written to simultaneously using an MOV instruction. Do not use a bit manipulation instruction such as BCLR. 00XX: Setting prohibited 0100: Setting prohibited 0101: IIC_0 Internal latch cleared 2 0110: IIC_1* Internal Iatch cleared 2 0111: IIC_0, IIC_1* Internal Iatch cleared 1XXX: Invalid setting [Legend] X: Don't care Notes: 1. Only 0 can be written to these bits, to clear the flag. 2. Supported only by the H8S/2268 Group. 14.4 Operation The I2C bus interface has serial and I2C bus formats. 14.4.1 I2C Bus Data Format The I2C bus formats are addressing formats and an acknowledge bit is inserted. The first frame following a start condition always consists of 8 bits. The I2C bus format is shown in figure 14.3. The serial format is a non-addressing format with no acknowledge bit. This is shown in figure 14.4. Figure 14.5 shows the I2C bus timing. Rev. 3.00, 08/03, page 371 of 612 (a) I2C bus format (FS = 0 or FSX = 0) S SLA R/W A DATA A A/A P 1 7 1 1 n 1 1 1 1 n: transfer bit count (n = 1 to 8) m: transfer frame count (m 1) m (b) I2C bus format (start condition retransmission, FS = 0 or FSX = 0) S SLA R/W A DATA A/A S SLA R/W A DATA A/A P 1 7 1 1 n1 1 1 7 1 1 n2 1 1 1 m1 1 m2 n1 and n2: transfer bit count (n1 and n2 = 1 to 8) m1 and m2: transfer frame count (m1 and m2 1) Figure 14.3 I2C Bus Data Formats (I2C Bus Formats) FS = 1 and FSX = 1 S DATA DATA P 1 8 n 1 1 m n: transfer bit count (n = 1 to 8) m: transfer frame count (m 1) Figure 14.4 I2C Bus Data Format (Serial Format) SDA 1-7 8 9 SLA R/W A SCL S 1-7 8 DATA 9 A 1-7 DATA 8 9 A/A P Figure 14.5 I2C Bus Timing [Legend] S: Start condition. The master device drives SDA from high to low while SCL is high SLA: Slave address R/W: Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0 A: Acknowledge. The receiving device drives SDA DATA:Transferred data P: Stop condition. The master device drives SDA from low to high while SCL is high Rev. 3.00, 08/03, page 372 of 612 14.4.2 Master Transmit Operation In I2C bus format master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The transmission procedure and operations synchronized with the ICDR writing are described below. 1. Set the ICE bit in ICCR to 1. Set bits MLS, WAIT, and CKS2 to CKS0 in ICMR, and bit IICX in SCRX, according to the operating mode. 2. Read the BBSY flag in ICCR to confirm that the bus is free. 3. Set bits MST and TRS to 1 in ICCR to select master transmit mode. 4. Write 1 to BBSY and 0 to SCP. This changes SDA from high to low when SCL is high, and generates the start condition. 5. Then IRIC and IRTR flags are set to 1. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. 6. Write the data (slave address + R/W) to ICDR. With the I2C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the first frame data following the start condition indicates the 7-bit slave address and transmit/receive direction. As indicating the end of the transfer, and so the IRIC flag is cleared to 0. After writing ICDR, clear IRIC continuously not to execute other interrupt handling routine. If one frame of data has been transmitted before the IRIC clearing, it can not be determine the end of transmission. The master device sequentially sends the transmission clock and the data written to ICDR using the timing shown in figure 14.6. The selected slave device (i.e. the slave device with the matching slave address) drives SDA low at the 9th transmit clock pulse and returns an acknowledge signal. 7. When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th transmit clock pulse. After one frame has been transmitted SCL is automatically fixed low in synchronization with the internal clock until the next transmit data is written. 8. Read the ACKB bit in ICSR to confirm that ACKB is cleared to 0. When the slave device has not acknowledged (ACKB bit is 1), operate the step [12] to end transmission, and retry the transmit operation. 9. Write the transmit data to ICDR. As indicating the end of the transfer, and so the IRIC flag is cleared to 0. Perform the ICDR write and the IRIC flag clearing sequentially, just as in point 6 in this flowchart. Transmission of the next frame is performed in synchronization with the internal clock. 10. When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th transmit clock pulse. After one frame has been transmitted SCL is automatically fixed low in synchronization with the internal clock until the next transmit data is written. 11. Read the ACKB bit in ICSR. Confirm that the slave device has been acknowledged (ACKB bit is 0). When there is data to be transmitted, go to the step [9] to continue next transmission. When the slave device has not acknowledged (ACKB bit is set to 1), operate the step [12] to end transmission. Rev. 3.00, 08/03, page 373 of 612 12. Clear the IRIC flag to 0. And write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition. Start condition generation SCL (master output) 1 2 3 4 5 6 7 Bit 2 Bit 1 8 9 1 2 Slave address Bit 7 SDA (master output) Bit 6 Bit 5 Bit 4 Bit 3 Slave address SDA (slave output) [5] Bit 0 R/W Bit 7 [7] Bit 6 Data 1 A IRIC IRTR ICDR Address + R/W Data 1 * [9] IRIC clearance ICDR writing prohibited Normal operation User processing [4] Write BBSY = 1 [6] ICDR write and SCP = 0 (start condition issuance) [6] IRIC clearance [9] ICDR write Note: * Data write timing in ICDR Figure 14.6 Master Transmit Mode Operation Timing Example (MLS = WAIT = 0) 14.4.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data, and returns an acknowledge signal. The slave device transmits data. The reception procedure and operations with the wait function synchronized with the ICDR read operation to receive data in sequence are shown below. 1. Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode, and set the WAIT bit in ICMR to 1. Also clear the bit in ICSR to ACKB 0 (acknowledge data setting). 2. When ICDR is read (dummy data read), reception is started, and the receive clock is output, and data received, in synchronization with the internal clock. In order to detect wait operation, set the IRIC flag in ICCR must be cleared to 0. After reading ICDR, clear IRIC continuously not to execute other interrupt handling routine. If one frame of data has been received before the IRIC clearing, it cannot be determine the end of reception. Rev. 3.00, 08/03, page 374 of 612 3. The IRIC flag is set to 1 at the fall of the 8th receive clock pulse. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. SCL is automatically fixed low in synchronization with the internal clock until the IRIC flag clearing. If the first frame is the last receive data, execute step [10] to halt reception. 4. Clear the IRIC flag to release from the Wait State. The master device outputs the 9th clock and drives SDA at the 9th receive clock pulse to return an acknowledge signal. 5. When one frame of data has been received, the IRIC flag in ICCR and the IRTR flag in ICSR are set to 1 at the rise of the 9th receive clock pulse. The master device outputs SCL clock to receive next data. 6. Read ICDR. 7. Clear the IRIC flag to detect next wait operation. Data reception process from [5] to [7] should be executed during one byte reception period after IRIC flag clearing in [4] or [9] to release wait status. 8. The IRIC flags set to 1 at the fall of 8th receive clock pulse. SCL is automatically fixed low in synchronization with the internal clock until the IRIC flag clearing. If this frame is the last receive data, execute step [10] to halt reception. 9. Clear the IRIC flag in ICCR to cancel wait operation. The master device drives SDA low at the 9th receive clock pulse and returns an acknowledge signal. 10. Data can be received continuously by repeating step [5] to [9]. 11. Set the ACKB bit in ICSR to 1 so as to return "No acknowledge" data. Also set the TRS bit in ICCR to 1 to switch from receive mode to transmit mode. 12. Clear IRIC flag to 0 to release from the Wait State. 13. When one frame of data has been received, the IRIC flag is set to 1 at the rise of the 9th receive clock pulse. 14. Clear the WAIT bit to 0 to switch from wait mode to no wait mode. Read ICDR and clear the IRIC flag to 0. Clearing of the IRIC flag should be after the WAIT = 0. If the WAIT bit is cleared to 0 after clearing the IRIC flag and then an instruction to issue a stop condition is executed, the stop condition cannot be issued because the output level of the SDA line is fixed as low. 15. Clear the BBSY bit and SCP bit to 0. This changes SDA from low to high when SCL is high, and generates the stop condition. Rev. 3.00, 08/03, page 375 of 612 Master tansmit mode SCL (master output) SDA (slave output) Master receive mode 9 1 2 A Bit 7 Bit 6 3 Bit 5 4 5 6 7 8 9 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data 1 Bit 7 [3] SDA (master output) 1 2 Bit 6 3 4 5 Bit 5 Bit 4 Bit 3 Data 2 [5] A IRIC IRTR ICDR Data 1 User processing [1] TRS cleared to 0 [2] ICDR read [2] IRIC clearance (dummy read) WAIT set to 1 ACKB cleared to 0 [4] IRIC clearance [6] ICDR read [7] IRIC clearance (Data 1) Figure 14.7 (1) Master Receive Mode Operation Timing Example (MLS = ACKB = 0, WAIT = 1) SCL (master output) 8 9 Bit 0 SDA (slave output) Data 2 SDA (master output) [8] 1 2 Bit 7 Bit 6 [5] 3 Bit 5 4 5 6 7 8 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data 3 9 1 Bit 7 [8] [5] 2 Bit 6 Data 4 A A IRIC IRTR ICDR Data 1 Data 3 Data 2 [6] ICDR read (Data 3) User processing [9] IRIC clearance [6] ICDR read (Data 2) [7] IRIC clearance [9] IRIC clearance Figure 14.7 (2) Master Receive Mode Operation Timing Example (MLS = ACKB = 0, WAIT = 1) Rev. 3.00, 08/03, page 376 of 612 [7] IRIC clearance 14.4.4 Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The reception procedure and operations in slave receive mode are described below. 1. Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR according to the operating mode. 2. When the start condition output by the master device is detected, the BBSY flag in ICCR is set to 1. 3. When the slave address matches in the first frame following the start condition, the device operates as the slave device specified by the master device. If the 8th data bit (R/W) is 0, the TRS bit in ICCR remains cleared to 0, and slave receive operation is performed. 4. At the 9th clock pulse of the receive frame, the slave device drives SDA low and returns an acknowledge signal. At the same time, the IRIC flag in ICCR is set to 1. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. If the RDRF internal flag has been cleared to 0, it is set to 1, and the receive operation continues. If the RDRF internal flag has been set to 1, the slave device drives SCL low from the fall of the receive clock until data is read into ICDR. 5. Read ICDR and clear the IRIC flag in ICCR to 0. The RDRF flag is cleared to 0. Receive operations can be performed continuously by repeating steps [4] and [5]. When SDA is changed from low to high when SCL is high, and the stop condition is detected, the BBSY flag in ICCR is cleared to 0. Rev. 3.00, 08/03, page 377 of 612 Start condition issuance SCL (master output) 1 2 3 4 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 6 7 8 Bit 2 Bit 1 Bit 0 9 1 2 Bit 7 Bit 6 SCL (slave output) SDA (master output) SDA (slave output) Slave address R/W Data 1 [4] A RDRF IRIC ICDRS ICDRR User processing Interrupt request generation Address + R/W Address + R/W [5] ICDR read [5] IRIC clearance Figure 14.8 Example of Slave Receive Mode Operation Timing (1) (MLS = ACKB = 0) Rev. 3.00, 08/03, page 378 of 612 SCL (master output) 7 8 Bit 1 Bit 0 9 1 2 Bit 7 Bit 6 3 4 5 6 7 8 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 SCL (slave output) SDA (master output) Data 1 SDA (slave output) [4] [4] Data 2 A A RDRF IRIC Interrupt request generation ICDRS Data 1 ICDRR Data 1 User processing Interrupt request generation Data 2 Data 2 [5] ICDR read [5] IRIC clearance Figure 14.9 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0) 14.4.5 Slave Transmit Operation In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. The transmission procedure and operations in slave transmit mode are described below. 1. Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR according to the operating mode. 2. When the slave address matches in the first frame following detection of the start condition, the slave device drives SDA low at the 9th clock pulse and returns an acknowledge signal. At the same time, the IRIC flag in ICCR is set to 1. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. If the 8th data bit (R/W) is 1, the TRS bit in ICCR is set to 1, and the mode changes to slave transmit mode automatically. The TDRE internal flag is set to 1. The slave device drives SCL low from the fall of the transmit clock until ICDR data is written. Rev. 3.00, 08/03, page 379 of 612 3. After clearing the IRIC flag to 0, write data to ICDR. The TDRE internal flag is cleared to 0. The written data is transferred to ICDRS, and the TDRE internal flag and the IRIC and IRTR flags are set to 1 again. After clearing the IRIC flag to 0, write the next data to ICDR. The slave device sequentially sends the data written into ICDR in accordance with the clock output by the master device at the timing shown in figure 14.10. 4. When one frame of data has been transmitted, the IRIC flag in ICCR is set to 1 at the rise of the 9th transmit clock pulse. If the TDRE internal flag has been set to 1, this slave device drives SCL low from the fall of the transmit clock until data is written to ICDR. The master device drives SDA low at the 9th clock pulse, and returns an acknowledge signal. As this acknowledge signal is stored in the ACKB bit in ICSR, this bit can be used to determine whether the transfer operation was performed normally. When the TDRE internal flag is 0, the data written into ICDR is transferred to ICDRS, transmission is started, and the TDRE internal flag and the IRIC and IRTR flags are set to 1 again. 5. To continue transmission, clear the IRIC flag to 0, then write the next data to be transmitted into ICDR. The TDRE flag is cleared to 0. Transmit operations can be performed continuously by repeating steps [4] and [5]. To end transmission, write H'FF to ICDR. When SDA is changed from low to high when SCL is high, and the stop condition is detected, the BBSY flag in ICCR is cleared to 0. Rev. 3.00, 08/03, page 380 of 612 Slave receive mode SCL (master output) 8 Slave transmit mode 9 1 2 A Bit 7 Bit 6 3 4 5 6 7 8 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 1 2 Bit 7 Bit 6 SCL (slave output) SDA (slave output) SDA (master output) R/W Data 1 [2] Data 2 A TDRE [3] IRIC Interrupt request generation ICDRT Interrupt request generation Data 1 ICDRS User processing Interrupt request generation Data 2 Data 1 [3] IRIC clearance [3] ICDR write Data 2 [3] ICDR write [5] IRIC clearance [5] ICDR write Figure 14.10 Example of Slave Transmit Mode Operation Timing (MLS = 0) Rev. 3.00, 08/03, page 381 of 612 14.4.6 IRIC Setting Timing and SCL Control The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX. If the TDRE or RDRF internal flag is set to 1, SCL is automatically held low after one frame has been transferred; this timing is synchronized with the internal clock. Figure 14.11 shows the IRIC set timing and SCL control. (a) When WAIT = 0, and FS = 0 or FSX = 0 (I2C bus format, no wait) SCL 7 8 9 1 SDA 7 8 A 1 IRIC User processing Clear IRIC Write to ICDR (transmit) or read ICDR (receive) (b) When WAIT = 1, and FS = 0 or FSX = 0 (I2C bus format, wait inserted) SCL 8 9 1 SDA 8 A 1 IRIC Clear IRIC User processing Clear Write to ICDR (transmit) IRIC or read ICDR (receive) (c) When FS = 1 and FSX = 1 (synchronous serial format) SCL 7 8 1 SDA 7 8 1 IRIC User processing Clear IRIC Write to ICDR (transmit) or read ICDR (receive) Figure 14.11 IRIC Setting Timing and SCL Control Rev. 3.00, 08/03, page 382 of 612 14.4.7 Operation Using the DTC (H8S/2268 Group Only) The I2C bus format provides for selection of the slave device and transfer direction by means of the slave address and the R/W bit, confirmation of reception with acknowledge bit, indication of the last frame, and so on. Therefore, continuous data transfer using the DTC must be carried out in conjunction CPU processing by means of interrupts. Table 14.5 shows some example of processing using the DTC. These examples assume that the number of transfer data bytes is know in slave mode. Table 14.5 Flags and Transfer States Item Master Transmit Master Receive Mode Mode Slave address + Transmission by R/W bit DTC (ICDR rite) Transmission by DTC (ICDR rite) Slave Transmit Mode Slave Receive Mode Reception by CPU (ICDR read) Reception by CPU (ICDR read) Transmission/ reception Dummy data read Processing by DTC (ICDR read) Actual data Transmission by Reception by CPU Transmission by transmission/re DTC (ICDR write) (ICDR read) DTC (ICDR write) ception Reception by CPU (ICDR read) Dummy data (HFF) write Processing by DTC (ICDR write) Last frame processing Not necessary Reception by CPU Not necessary (ICDR read) Transfer request processing after last frame processing 1st time: Clearing Not necessary by CPU 2nd time: End condition issuance by CPU Automatic clearing Not necessary on detection of end condition during transmission of dummy data (HFF) Setting of number of DTC transfer data frames Transmission: Reception: Actual Actual data count data count + 1 (+ 1 equivalent to slave address + R/W bits) Transmission: Reception: Actual Actual data count + data count 1 (+ 1 equivalent to dummy data (HFF)) Reception by CPU (ICDR read) Rev. 3.00, 08/03, page 383 of 612 14.4.8 Noise Chancellor The logic levels at the SCL and SDA pins are routed through noise chancellors before being latched internally. Figure 14.12 shows a block diagram of the noise cancelled circuit. The noise chancellor consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. If they do not agree, the previous value is held. Sampling clock C SCL or SDA input signal D C Q Latch D Q Latch Match detector Internal SCL or SDA signal System clock period Sampling clock Figure 14.12 Block Diagram of Noise Chancellor 14.4.9 Sample Flowcharts Figures 14.13 to 14.16 show sample flowcharts for using the I2C bus interface in each mode. Rev. 3.00, 08/03, page 384 of 612 Start Initialize [1] Initialization Read BBSY in ICCR [2] Test the status of the SCL and SDA lines. No BBSY = 0? Yes Set MST = 1 and TRS = 1 in ICCR [3] Select master transmit mode. Write BBSY =1 and SCP = 0 in ICCR [4] Start condition issuance Read IRIC in ICCR [5] Wait for a start condition No IRIC = 1? Yes Write transmit data in ICDR [6] Set transmit data for the first byte (slave address + R/W). (After writing ICDR, clear IRIC continuously) Clear IRIC in ICCR Read IRIC in ICCR No [7] Wait for 1 byte to be transmitted. IRIC = 1? Yes Read ACKB in ICSR No ACKB = 0? [8] Test the acknowledge bit, transferred from slave device. Yes Transmit mode? No Master receive mode Yes Write transmit data in ICDR Clear IRIC in ICCR [9] Set transmit data for the second and subsequent bytes. (After writing ICDR, clear IRIC immediately) Read IRIC in ICCR [10] Wait for 1 byte to be transmitted. No IRIC = 1? Yes Read ACKB in ICSR [11] Test for end of tranfer No End of transmission? or ACKB = 1? Yes Clear IRIC in ICCR Write BBSY = 0 and SCP = 0 in ICCR [12] Stop condition issuance End Figure 14.13 Sample Flowchart for Master Transmit Mode Rev. 3.00, 08/03, page 385 of 612 Master receive operation Set TRS = 0 in ICCR [1] Select receive mode. Set WAIT = 1 in ICMR Set ACKB = 0 in ICSR Read ICDR [2] Start receiving. The first read is a dummy read. After reading ICDR, please clear IRIC immediately. Clear IRIC in ICCR Read IRIC in ICCR No [3] Wait for 1 byte to be received. IRIC = 1? Yes Yes Last receive? No [4] Clear IRIC. (to end the wait insertion) Clear IRIC in ICCR Read IRIC in ICCR [5] Wait for 1 byte to be received. No IRIC = 1? Yes [6] Read the receive data. Read ICDR [7] Clear IRIC. Clear IRIC in ICCR Read IRIC in ICCR No [8] Wait for the next data to be received. IRIC = 1? Yes Last receive? No Clear IRIC in ICCR Set ACKB = 1 in ICSR Yes [9] Clear IRIC. (to end the wait insertion) [10] Set acknowledge data for the last reception. Set TRS = 1 in ICCR Clear IRIC = 1 in ICCR [11] Clear IRIC. (to end the wait insertion) Read IRIC in ICCR [12] Wait for 1 byte to be received. No IRIC = 1? Yes Set Wait = 0 in ICMR Read ICDR Clear IRIC in ICCR Write BBSY = 0 and SCP = 0 in ICCR [13] --------Clear IRIC. (Note: After setting WAIT = 0, IRIC should be cleared to 0.) [14] Stop condition issuance. End Figure 14.14 Sample Flowchart for Master Receive Mode Rev. 3.00, 08/03, page 386 of 612 Start Initialize Set MST = 0 and TRS = 0 in ICCR [1] Set ACKB = 0 in ICSR Read IRIC in ICCR No [2] IRIC = 1? Yes Read AAS and ADZ in ICSR AAS = 1 and ADZ = 0? No General call address processing * Description omitted Yes Read TRS in ICCR No TRS = 0? Slave transmit mode Yes Last receive? No Read ICDR Yes [3] [1] Select slave receive mode. Clear IRIC in ICCR [2] Wait for the first byte to be received (slave address). Read IRIC in ICCR [3] Start receiving. The first read is a dummy read. No [4] IRIC = 1? [4] Wait for the transfer to end. [5] Set acknowledge data for the last reception. Yes [6] Start the last reception. [7] Wait for the transfer to end. Set ACKB = 1 in ICSR [5] Read ICDR [6] [8] Read the last receive data. Clear IRIC in ICCR Read IRIC in ICCR No [7] IRIC = 1? Yes Read ICDR [8] Clear IRIC in ICCR End Figure 14.15 Sample Flowchart for Slave Receive Mode Rev. 3.00, 08/03, page 387 of 612 Slave transmit mode [1] Set transmit data for the second and subsequent bytes. Clear IRIC in ICCR Write transmit data in ICDR [1] [2] Wait for 1 byte to be transmitted. [3] Test for end of transfer. Clear IRIC in ICCR [4] Set slave receive mode. [5] Dummy read (to release the SCL line). Read IRIC in ICCR No [2] IRIC = 1? Yes Read ACKB in ICSR No [3] End of transmission (ACKB = 1)? Yes Set TRS = 0 in ICCR [4] Read ICDR [5] Clear IRIC in ICCR End Figure 14.16 Sample Flowchart for Slave Transmit Mode Rev. 3.00, 08/03, page 388 of 612 14.5 Usage Notes 1. In master mode, if an instruction to generate a start condition is immediately followed by an instruction to generate a stop condition, neither condition will be output correctly. To output consecutive start and stop conditions, after issuing the instruction that generates the start condition, read the relevant ports, check that SCL and SDA are both low, then issue the instruction that generates the stop condition. Note that SCL may not yet have gone low when BBSY is cleared to 0. 2. Either of the following two conditions will start the next transfer. Pay attention to these conditions when reading or writing to ICDR. Write access to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to ICDRS) Read access to ICDR when ICE = 1 and TRS = 0 (including automatic transfer from ICDRS to ICDRR) 3. Table 14.6 shows the timing of SCL and SDA output in synchronization with the internal clock. Timings on the bus are determined by the rise and fall times of signals affected by the bus load capacitance, Series resistance, and parallel resistance. Table 14.6 I2C Bus Timing (SCL and SDA Output) Item Symbol Output Timing Unit SCL output cycle time tSCLO 28tcyc to 256tcyc ns SCL output high pulse width tSCLHO 0.5tSCLO ns SCL output low pulse width tSCLLO 0.5tSCLO ns SDA output bus free time tBUFO 0.5tSCLO - 1tcyc ns Start condition output hold time tSTAHO 0.5tSCLO - 1tcyc ns Retransmission start condition output setup time tSTASO 1tSCLO ns Stop condition output setup time tSTOSO 0.5tSCLO + 2tcyc ns Data output setup time (master) tSDASO 1tSCLLO - 3tcyc ns 1tSCLL - 3tcyc ns 3tcyc ns Data output setup time (slave) Data output hold time tSDAHO Notes 4. SCL and SDA inputs are sampled in synchronization with the internal clock. The AC timing therefore depends on the system clock cycle tcyc, as shown in table 26.8 in section 26, Electrical Characteristics. Note that the I2C bus interface AC timing specifications will not be met with a system clock frequency of less than 5 MHz. Rev. 3.00, 08/03, page 389 of 612 5. The I2C bus interface specification for the SCL rise time tsr is under 1000 ns (300 ns for highspeed mode). In master mode, the I2C bus interface monitors the SCL line and synchronizes one bit at a time during communication. If tsr (the time for SCL to go from low to VIH) exceeds the time determined by the input clock of the I2C bus interface, the high period of SCL is extended. The SCL rise time is determined by the pull-up resistance and load capacitance of the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance and load capacitance so that the SCL rise time does not exceed the values given in the table in table 14.7. Table 14.7 Permissible SCL Rise Time (tsr) Values Time Indication 2 I C Bus Specification (Max.) = 5 MHz = 8 MHz = 10 MHz = 16 MHz = 20 MHz Normal mode 1000 ns 1000 ns 937 ns 750 ns 468 ns 375 ns High-speed mode 300 ns 300 ns 300 ns 300 ns 300 ns 300 ns Normal mode 1000 ns 1000 ns 1000 ns 1000 ns 1000 ns 875 ns High-speed mode 300 ns 300 ns 300 ns 300 ns 300 ns 300 ns tcyc IICX Indication 0 1 7.5tcyc 17.5tcyc 6. The I2C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns and 300 ns. The I2C bus interface SCL and SDA output timing is prescribed by tScyc and tcyc, as shown in table 14.6. However, because of the rise and fall times, the I2C bus interface specifications may not be satisfied at the maximum transfer rate. Table 14.8 shows output timing calculations for different operating frequencies, including the worst-case influence of rise and fall times. The values in the above table will vary depending on the settings of the IICX bit and bits CKS0 to CKS2. Depending on the frequency it may not be possible to achieve the maximum transfer rate; therefore, whether or not the I2C bus interface specifications are met must be determined in accordance with the actual setting conditions. tBUFO fails to meet the I2C bus interface specifications at any frequency. The solution is either (a) to provide coding to secure the necessary interval (approximately 1 s) between issuance of a stop condition and issuance of a start condition, or (b) to select devices whose input timing permits this output timing for use as slave devices connected to the I2C bus. tSCLLO in high-speed mode and tSTASO in standard mode fail to satisfy the I2C bus interface specifications for worst-case calculations of tSr/tSf. Possible solutions that should be investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input timing permits this output timing for use as slave devices connected to the I2C bus. Rev. 3.00, 08/03, page 390 of 612 Table 14.8 I2C Bus Timing (with Maximum Influence of tSr/tSf) Time Indication (at Maximum Transfer Rate) [ns] 2 I C Bus Item tcyc Indication tSCLHO 0.5tSCLO (-tSr) tSCLLO tBUFO 0.5tSCLO (-tSf ) 0.5tSCLO -1tcyc 0.5tSCLO -1tcyc (-tSf ) tSTASO tSTOSO 1tSCLO (-tSr ) 0.5tSCLO + 2tcyc (-tSr ) 2 tSDASO 1tSCLLO* -3tcyc (master) (-tSr ) 2 Specifi- Influence cation = = = = = (Max.) (Min.) 5 MHz 8 MHz 10 MHz 16 MHz 20 MHz -1000 4000 4000 4000 4000 4000 4000 High-speed mode -300 600 950 950 950 950 950 Standard mode 4700 4750 Standard mode ( -tSr ) tSTAHO tSr/tSf 2 tSDASO 1tSCLL* -3tcyc* (slave) (-tSr ) tSDAHO 3tcyc -250 4750 4750 1 1000* 1 4750 1 1000* 3875* 1 4750 1 1 1000* 1000*1 3900* 1 3938* 1 3950* High-speed mode -250 1300 1000* Standard mode 4700 3800* High-speed mode -300 1300 750* 825*1 850*1 888*1 900*1 Standard mode 4000 4550 4625 4650 4688 4700 High-speed mode -250 600 800 875 900 938 950 Standard mode 4700 9000 9000 9000 9000 9000 High-speed mode -300 600 2200 2200 2200 2200 2200 Standard mode 4000 4400 4250 4200 4125 4100 High-speed mode -300 600 1350 1200 1150 1075 1050 Standard mode 250 3100 3325 3400 3513 3550 High-speed mode -300 100 400 625 700 813 850 Standard mode 250 3100 3325 3400 3513 3550 High-speed mode -300 100 400 625 700 813 850 Standard mode 0 0 600 375 300 188 150 High-speed mode 0 0 600 375 300 188 150 -1000 -250 -1000 -1000 -1000 -1000 1 1 2 Notes: 1. Does not meet the I C bus interface specification. Remedial action such as the following is necessary: (a) secure a start/stop condition issuance interval; (b)adjust the rise and fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate; (d) select slave devices whose input timing permits this output timing. The values in the above table will vary depending on the settings of the IICX bit and bits CKS0 to CKS2.Depending on the frequency it may not be possible to achieve the 2 maximum transfer rate; therefore, whether or not the I C bus interface specifications are met must be determined in accordance with the actual setting conditions. 2 2. Calculated using the I C bus specification values (standard mode: 4700 ns min.; highspeed mode: 1300 ns min.). Rev. 3.00, 08/03, page 391 of 612 7. Note on ICDR Read at End of Master Reception To halt reception after completion of a receive operation in master receive mode, set the TRS bit to 1 and write 0 to BBSY and SCP in ICCR. This changes the SDA pin from low to high when the SCL pin is high, and generates the stop condition. After this, receive data can be read by means of an ICDR read, but if data remains in the buffer the ICDRS receive data will not be transferred to ICDR, and so it will not be possible to read the second byte of data. If it is necessary to read the second byte of data, issue the stop condition in master receive mode (i.e. with the TRS bit cleared to 0). When reading the receive data, first confirm that the BBSY bit in ICCR is cleared to 0, the stop condition has been generated, and the bus has been released, then read ICDR with TRS cleared to 0. Note that if the receive data (ICDR data) is read in the interval between execution of the instruction for issuance of the stop condition (writing of 0 to BBSY and SCP in ICCR) and the actual generation of the stop condition, the clock may not be output correctly in subsequent master transmission. Clearing of the MST bit after completion of master transmission/reception, or other modifications of IIC control bits to change the transmit/receive operating mode or settings, must be carried out during interval (a) in figure 14.17 (after confirming that the BBSY bit has been cleared to 0 in the ICCR register). Stop condition Start condition (a) SDA Bit 0 A SCL 8 9 Internal clock BBSY bit Master receive mode ICDR reading prohibited Execution of stop condition issuance instruction (0 written to BBSY and SCP) Confirmation of stop condition generation (0 read from BBSY) Start condition issuance Figure 14.17 Points for Attention Concerning Reading of Master Receive Data 8. Notes on Start Condition Issuance for Retransmission Depending on the timing combination with the start condition issuance and the subsequently writing data to ICDR, it may not be possible to issue the retransmission and the data transmission after retransmission condition issuance. Rev. 3.00, 08/03, page 392 of 612 After start condition issuance is done and determined the start condition, write the transmit data to ICDR, as shown below. Figure 14.18 shows the timing of start condition issuance for retransmission, and the timing for subsequently writing data to ICDR, together with the corresponding flowchart. [1] Wait for end of 1-byte transfer No IRIC = 1? [1] [2] Determine whether SCL0 is low Yes Clear IRIC in ICSR [3] Issue restart condition instruction for transmission No Start condition issuance? Other processing [4] Determine whether start condition is generated or not Yes [5] Set transmit data (slave address + R/W) Read SCL pin No SCL = Low? [2] Yes Write BBSY = 1, SCP = 0 (ICSR) [3] No IRIC = 1? [4] Note: Program so that processing from [3] to [5] is executed continuously. Yes Write transmit data to ICDR [5] Start condition (retransmission) SCL 9 SDA ACK Bit 7 Data output IRIC [5] ICDR write (next transmit data) [4] IRIC determination [3] (Restart) Start condition instruction issuance [2] Detemination of SCL = Low [1] IRIC determination Figure 14.18 Flowchart and Timing of Start Condition Instruction Issuance for Retransmission Rev. 3.00, 08/03, page 393 of 612 9. Notes on I2C Bus Interface Stop Condition Instruction Issuance If the rise time of the 9th SCL clock exceeds the specification because the bus load capacitance is large, or if there is a slave device of the type that drives SCL low to effect a wait, after rising of the 9th SCL clock, issue the stop condition after reading SCL and determining it to be low, as shown below. SCL 9th clock VIH High period secured As waveform rise is late, SCL is detected as low SDA Stop condition IRIC [1] Determination of SCL = Low [2] Stop condition instruction isuuance Figure 14.19 Timing of Stop Condition Issuance 10. Notes on Initialization of Internal State The I2C has a function for forcible initialization of its internal state if a deadlock occurs during communication. Initialization is executed by (1) setting bits CLR3 to CLR0 in the DDCSWR register. For details see section 14.3.8 DDC Switch Register (DDCSWR). * Scope of Initialization: The initialization executed by function covers the following items: TDRE and RDRF internal flags Transmit/receive sequencer and internal operating clock counter Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data output, etc.) * The following items are not initialized: Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, DDCSWR, STCR) Internal latches used t retain register read information setting/clearing flags in the ICMR,.ICCR, ICSR, and DDCSWR registers The value of the ICMR register bit counter (BC2 to BC0) Generated interrupt sources (interrupt sources transferred to the interrupt controller) Rev. 3.00, 08/03, page 394 of 612 * Notes on Initialization: Interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be taken as necessary. Basically, other register flags are not cleared either, and so flag clearing measures must be taken as necessary. When initialization is executed by the DDCSWR register, the write data for bits CLR3 to CLR0 is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be written to simultaneously using an MOV instruction. Do not use a bit manipulation instruction such as BCLR. Similarly, when clearing is required again, all the bits must be written to simultaneously in accordance with the setting. If a flag clearing setting is made during transmission/reception, the IIC module will stop transmitting/receiving at that point and the SCL and SDA pins will be released. When transmission/reception is started again, register initialization, etc., must be carried out as necessary to enable correct communication as a system. The value of the BBSY bit cannot be modified directly by this module clear function, but since the stop condition pin waveform is generated according to the state and release timing of the SCL and SDA pins, the BBSY bit may be cleared as a result. Similarly, state switching of other bits and flags may also have an effect. To prevent problems caused by these factors, the following procedure should be used when initializing the IIC state. Execute initialization of the internal state according to the setting of bits CLR3 to CLR0. Execute a stop condition issuance instruction (write 0 to BBSY and SCP) to clear the BBSY bit to 0, and wait for two transfer rate clock cycles. Re-execute initialization of the internal state according to the setting of bits CLR3 to CLR0. Initialize (re-set) the IIC registers. 11. Interrupt during Module Stop Mode When the module is stopped in the state that an interrupt is requested, the interrupt source of the CPU or activation source of the DTC* is not cleared. Be sure to enter module stop mode by disabling the interrupt beforehand. Note: * Supported only by the H8S/2268 Group. 12. Assignment and Selection of Register Addresses Some I2C bus interface registers are assigned to the same address as other registers. Register selection is performed by means of the IICE bit in the serial control register X (SCRX). For details on register addresses, see section 24, List of Registers. Rev. 3.00, 08/03, page 395 of 612 Rev. 3.00, 08/03, page 396 of 612 Section 15 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter that allows up to ten analog input channels to be selected. A block diagram of the A/D converter is shown in figure 15.1. 15.1 Features * 10-bit resolution * Ten input channels * Conversion time: 6.3 s per channel (at 20.5 MHz operation) * Two operating modes Single mode: Single-channel A/D conversion Scan mode: Continuous A/D conversion on 1 to 4 channels * Four data registers Conversion results are held in a 16-bit data register for each channel * Sample and hold function * Three methods conversion start Software 16-bit timer pulse unit (TPU or TMR) conversion start trigger External trigger signal * Interrupt request An A/D conversion end interrupt request (ADI) can be generated * Module stop mode can be set ADCMS35B_000020020700 Rev. 3.00, 08/03, page 397 of 612 Module data bus Vref 10-bit D/A AVSS Bus interface A D D R A A D D R B A D D R C A D D R D A D C S R A D C R /2 + /4 Comparator Multiplexer AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Successive approximations register AVCC Internal data bus Control circuit /8 Sample-andhold circuit AN8 AN9 AN10 AN11 /16 ADI interrupt Conversion start trigger from TPU or TMR ADTRG [Legend] ADCR: A/D control register ADCSR: A/D control/status register ADDRA: A/D data register A ADDRB: A/D data register B ADDRC: A/D data register C ADDRD: A/D data register D Figure 15.1 Block Diagram of A/D Converter Rev. 3.00, 08/03, page 398 of 612 15.2 Input/Output Pins Table 15.1 summarizes the input pins used by the A/D converter. The eight analog input pins are divided into two groups each of which consists of four channels; analog input pins 0 to 3 (AN0 to AN3) comprising group 0 and analog input pins 4 to 7 (AN4 to AN7) comprising group 1. The AVcc and AVss pins are the power supply pins for the analog block in the A/D converter. The Vref pin is the A/D conversion reference voltage pin. Table 15.1 Pin Configuration Pin Name Symbol I/O Function Analog power supply pin AVcc Input Analog block power supply and reference voltage Analog ground pin AVss Input Analog block ground and reference voltage Reference voltage pin Vref Input Reference voltage for A/D conversion Analog input pin 0 AN0 Input Group 0 analog input pins Analog input pin 1 AN1 Input Analog input pin 2 AN2 Input Analog input pin 3 AN3 Input Analog input pin 4 AN4 Input Analog input pin 5 AN5 Input Analog input pin 6 AN6 Input Analog input pin 7 AN7 Input Analog input pin 8 AN8 Input Analog input pin 9 AN9 Input A/D external trigger input pin ADTRG Input Group 1 analog input pins Analog input pins External trigger input pin for starting A/D conversion Rev. 3.00, 08/03, page 399 of 612 15.3 Register Descriptions The A/D converter has the following registers. For details on the module stop control register, refer to section 22.1.2, Module Stop Control Registers A to D (MSTPCRA to MSTPCRD). * A/D data register A (ADDRA) * A/D data register B (ADDRB) * A/D data register C (ADDRC) * A/D data register D (ADDRD) * A/D control/status register (ADCSR) * A/D control register (ADCR) 15.3.1 A/D Data Registers A to D (ADDRA to ADDRD) There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown in table 15.2. The converted 10-bit data is stored in bits 6 to 15. The lower 6 bits are always read as 0. The data bus between the CPU and the A/D converter is 8 bits wide. The upper byte can be read directly from the CPU, however the lower byte should be read via a temporary register. Therefore, when reading the ADDR, read only the upper byte, or read in word unit. Table 15.2 Analog Input Channels and Corresponding ADDR Registers Analog Input Channel CH3 = 0 CH3 = 1 A/D Data Register to be Stored Results of A/D Conversion Group 0 (CH2 = 0) Group 1 (CH2 = 1) (CH2 = 0) (CH2 = 1) AN0 AN4 Setting prohibited Setting prohibited ADDRA AN1 AN5 Setting prohibited Setting prohibited ADDRB AN2 AN6 Setting prohibited AN8 ADDRC AN3 AN7 Setting prohibited AN9 ADDRD Rev. 3.00, 08/03, page 400 of 612 15.3.2 A/D Control/Status Register (ADCSR) ADCSR controls A/D conversion operations. Bit 7 Bit Name ADF Initial Value 0 R/W Description 1 R/(W)* A/D End Flag A status flag that indicates the end of A/D conversion. [Setting conditions] * When A/D conversion ends in single mode * When A/D conversion ends on all specified channels in scan mode [Clearing conditions] 6 ADIE 0 R/W * When 0 is written after reading ADF = 1 * When the DTC is activated by an ADI interrupt and 2 ADDR is read* A/D Interrupt Enable A/D conversion end interrupt (ADI) request enabled when 1 is set 5 ADST 0 R/W A/D Start Clearing this bit to 0 stops A/D conversion, and the A/D converter enters the wait state. Setting this bit to 1 starts A/D conversion. In single mode, this bit is cleared to 0 automatically when conversion on the specified channel is complete. In scan mode, conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or a transition to power-down mode in which the A/D converter is halted, shown in table 22.1. The ADST bit can be set to 1 by software, a timer conversion start trigger, or the A/D external trigger input pin (ADTRG). 4 SCAN 0 R/W Scan Mode Selects single mode or scan mode as the A/D conversion operating mode. Only set the SCAN bit while conversion is stopped (ADST = 0). 0: Single mode 1: Scan mode Rev. 3.00, 08/03, page 401 of 612 Bit Bit Name Initial Value R/W Description 3 CH3 0 R/W Channel Select 0 to 3 2 CH2 0 R/W Select analog input channels. 1 CH1 0 R/W When SCAN = 0 When SCAN = 1 0 CH0 0 R/W 0000: AN0 0000: AN0 0001: AN1 0001: AN0 to AN1 0010: AN2 0010: AN0 to AN2 0011: AN3 0011: AN0 to AN3 0100: AN4 0100: AN4 0101: AN5 0101: AN4 to AN5 0110: AN6 0110: AN4 to AN6 0111: AN7 0111: AN4 to AN7 1000: Setting prohibited 1000: Setting prohibited 1001: Setting prohibited 1001: Setting prohibited 1010: Setting prohibited 1010: Setting prohibited 1011: Setting prohibited 1011: Setting prohibited 1100: Setting prohibited 1100: Setting prohibited 1101: Setting prohibited 1101: Setting prohibited 1110: AN8 1110: Setting prohibited 1111: AN9 1111: Setting prohibited Notes: 1. Only 0 can be written to bit 7, to clear this bit. 2. Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 402 of 612 15.3.3 A/D Control Register (ADCR) The ADCR enables A/D conversion started by an external trigger signal. Bit Bit Name Initial Value R/W Description 7 TRGS1 0 R/W Timer Trigger Select 0 and 1 6 TRGS0 0 R/W Enables the start of A/D conversion by a trigger signal. Only set bits TRGS0 and TRGS1 while conversion is stopped (ADST = 0). 00: A/D conversion start by software is enabled 01: A/D conversion start by TPU conversion start trigger is enabled 10: A/D conversion start by 8-bit timer conversion start trigger is enabled 11: A/D conversion start by external trigger pin (ADTRG) is enabled 5, 4 All 1 Reserved These bits are always read as 1 and cannot be modified. 3 CKS1 0 R/W Clock Select 0 and 1 2 CKS0 0 R/W These bits specify the A/D conversion time. The conversion time should be changed only when ADST = 0. Specify a setting that gives a value within the range shown in table 26.9 or 26.22 in section 26, Electrical Characteristics. 00: Conversion time = 530 states (max.) 01: Conversion time = 266 states (max.) 10: Conversion time = 134 states (max.) 11: Conversion time = 68 states (max.) 1, 0 All 1 Reserved These bits are always read as 1 and cannot be modified. 15.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. When changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the bit ADST to 0 in ADCSR. The ADST bit can be set at the same time as the operating mode or analog input channel is changed. Rev. 3.00, 08/03, page 403 of 612 15.4.1 Single Mode In single mode, A/D conversion is to be performed only once on the specified single channel. The operations are as follows. 1. A/D conversion is started when the ADST bit is set to 1, according to software, timer conversion start trigger, or external trigger input. 2. When A/D conversion is completed, the result is transferred to the corresponding A/D data register to the channel. 3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 4. The ADST bit remains set to 1 during A/D conversion. When A/D conversion ends, the ADST bit is automatically cleared to 0 and the A/D converter enters the wait state. Set* ADIE A/D conversion start Set* Set* ADST Clear* Clear* ADF State of channel 0 (AN0) Idle State of channel 1 (AN1) Idle State of channel 2 (AN2) Idle State of channel 3 (AN3) Idle A/D conversion 1 A/D conversion 2 Idle ADDRA Read conversion result* A/D conversion result 1 ADDRB Read conversion result* A/D conversion result 2 ADDRC ADDRD Note: Vertical arrows indicate instructions executed by software. Figure 15.2 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) Rev. 3.00, 08/03, page 404 of 612 15.4.2 Scan Mode In scan mode, A/D conversion is to be performed sequentially on the specified channels (four channels maximum). The operations are as follows. 1. When the ADST bit is set to 1 by software, TPU, timer conversion start trigger, or external trigger, input, A/D conversion starts on the first channel in the group (AN0 when CH3 and CH2 = 00, AN4 when CH3 and CH2 = 01, or AN8 when CH3 and CH2 = 10). 2. When A/D conversion for each channel is completed, the result is sequentially transferred to the A/D data register corresponding to each channel. 3. When conversion of all the selected channels is completed, the ADF flag is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. Conversion of the first channel in the group starts again. 4. Steps [2] to [3] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the A/D converter enters the wait state. Contimuous A/D conversion Clear*1 Set*1 ADST Clear*1 ADF State of channel 0 (AN0) A/D conversion time Idle A/D conversion 1 State of channel 1 (AN1) Idle State of channel 2 (AN2) Idle Idle Idle A/D conversion 2 A/D conversion 5 *2 Idle Idle A/D conversion 3 State of channel 3 (AN3) ADDRA Idle A/D conversion 4 Idle A/D conversion result 1 ADDRB A/D conversion result 2 A/D conversion result 2 ADDRC A/D conversion result 3 ADDRD Note: 1. Vertical arrows indicate instructions executed by software. 2. Data currently being converted is ignored. Figure 15.3 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected) Rev. 3.00, 08/03, page 405 of 612 15.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) has passed after the ADST bit is set to 1, then starts conversion. Figure 15.2 shows the A/D conversion timing. Table 15.3 shows the A/D conversion time. As indicated in figure 15.4, the A/D conversion time (tCONV) includes tD and the input sampling time (tSPL). The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 15.3. In scan mode, the values given in table 15.3 apply to the first conversion time. The values given in table 15.4 apply to the second and subsequent conversions. (1) Address (2) Write signal Input sampling timing ADF tD tSPL tCONV [Legend] (1): ADCSR write cycle (2): ADCSR address A/D conversion start delay tD: tSPL: Input sampling time tCONV: A/D conversion time Figure 15.4 A/D Conversion Timing Rev. 3.00, 08/03, page 406 of 612 Table 15.3 A/D Conversion Time (Single Mode) CKS1 = 0 CKS0 = 0 Symbol Min Typ Max Item CKS1 = 1 CKS0 = 1 CKS0 = 0 CKS0 = 1 Min Typ Max Min Typ Max Min Typ Max A/D conversion tD start delay 18 33 10 17 6 9 4 5 Input sampling tSPL time 127 63 31 15 A/D conversion tCONV time 515 266 131 134 67 68 Note: * 530 259 All values represent the number of states. Table 15.4 A/D Conversion Time (Scan Mode) CKS1 CKS0 Conversion Time (State) 0 0 512 (Fixed) 1 256 (Fixed) 0 128 (Fixed) 1 64 (Fixed) 1 15.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS0 and TRGS1 bits are set to 11 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as when the bit ADST has been set to 1 by software. Figure 15.5 shows the timing. ADTRG Internal trigger signal ADST A/D conversion Figure 15.5 External Trigger Input Timing Rev. 3.00, 08/03, page 407 of 612 15.5 Interrupt Source The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. Setting the ADIE bit to 1 enables ADI interrupt requests while the bit ADF in ADCSR is set to 1 after A/D conversion is completed. In the H8S/2268 Group, the DTC* can be activated by an ADI interrupt. Having the converted data read by the DTC* in response to an ADI interrupt enables continuous conversion without imposing a load on software. Table 15.5 A/D Converter Interrupt Source Name Interrupt Source Interrupt Source Flag DTC Activation* ADI A/D conversion completed ADF Possible Note: 15.6 * Supported only by the H8S/2268 Group. A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. * Resolution The number of A/D converter digital output codes * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 15.6). * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'000) to B'0000000001 (H'001) (see figure 15.7). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see figure 15.7). * Nonlinearity error The error with respect to the ideal A/D conversion characteristic between zero voltage and fullscale voltage. Does not include offset error, full-scale error, or quantization error (see figure 15.7). * Absolute accuracy The deviation between the digital value and the analog input value. Includes offset error, fullscale error, quantization error, and nonlinearity error. Rev. 3.00, 08/03, page 408 of 612 Digital output 111 Ideal A/D conversion characteristic 110 101 100 011 010 Quantization error 001 000 1 2 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 15.6 A/D Conversion Accuracy Definitions (1) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Offset error FS Analog input voltage Figure 15.7 A/D Conversion Accuracy Definitions (2) Rev. 3.00, 08/03, page 409 of 612 15.7 15.7.1 Usage Notes Module Stop Mode Setting Operation of the A/D converter can be disabled or enabled using the module stop control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 22, Power-Down Modes. 15.7.2 Permissible Signal Source Impedance This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 k, charging may be insufficient and it may not be possible to guarantee A/D conversion accuracy. However, for A/D conversion in single mode with a large capacitance provided externally, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. However, as a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/s or greater) (see figure 15.8). When converting a high-speed analog signal, a low-impedance buffer should be inserted. 15.7.3 Influences on Absolute Accuracy Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute accuracy. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board (i.e., acting as antennas). This LSI Sensor input Sensor output impedance to 5 k Low-pass filter C to 0.1mF A/D converter equivalent circuit 10 k Cin = 15 pF Figure 15.8 Example of Analog Input Circuit Rev. 3.00, 08/03, page 410 of 612 20 pF 15.7.4 Range of Analog Power Supply and Other Pin Settings If the conditions below are not met, the reliability of the device may be adversely affected. * Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVss ANn AVcc. * Relationship between AVcc, AVss and Vcc, Vss Set AVss = Vss as the relationship between AVcc, AVss and Vcc, Vss. If the A/D converter is not used, the AVcc and AVss pins must not be left open. * Vref range The reference voltage input from the Vref pin should be set to AVcc or less. 15.7.5 Notes on Board Design In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input signals (AN0 to AN9), and analog power supply (AVcc) by the analog ground (AVss). Also, the analog ground (AVss) should be connected at one point to a stable digital ground (Vss) on the board. 15.7.6 Notes on Noise Countermeasures A protection circuit should be connected in order to prevent damage due to abnormal voltage, such as an excessive surge at the analog input pins (AN0 to AN9), between AVcc and AVss, as shown in figure 15.9. Also, the bypass capacitors connected to AVcc and the filter capacitor connected to AN0 to AN9 must be connected to AVss. If a filter capacitor is connected, the input currents at the analog input pins (AN0 to AN9) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding circuit constants. Rev. 3.00, 08/03, page 411 of 612 AVCC Vref Rin*2 *1 100 *1 AN0 to AN9 0.1 F AVSS Notes: Values are reference values. 1. 10 F 0.01 F 2. Rin: Input impedance Figure 15.9 Example of Analog Input Protection Circuit Table 15.6 Analog Pin Specifications Item Min Max Unit Analog input capacitance 20 pF Permissible signal source impedance 5 k 10 k AN0 to AN9 To A/D converter 20 pF Note: Values are reference values. Figure 15.10 Analog Input Pin Equivalent Circuit Rev. 3.00, 08/03, page 412 of 612 Section 16 D/A Converter The H8S/2268 Group includes a D/A converter, while the H8S/2264 Group does not. 16.1 Features * 8-bit resolution * Two output channels * Conversion time: 10 s, maximum (when load capacitance is 20 pF) * Output voltage: 0 V to Vref * D/A output retaining function in software standby mode * Module stop mode can be set Internal data bus Module data bus Bus interface Vref AVCC DA1 8-bit D/A D A D R 0 D A D R 1 D A C R DA0 AVSS Control circuit [Legend] DACR: D/A control register DADR0: D/A data register 0 DADR1: D/A data register 1 Figure 16.1 Block Diagram of D/A Converter DAC0004B_000020020700 Rev. 3.00, 08/03, page 413 of 612 16.2 Input/Output Pins Table 16.1 shows the pin configuration for the D/A converter. Table 16.1 Pin Configuration Pin Name Symbol I/O Function Analog power supply pin AVCC Input Analog block power supply Analog ground pin AVSS Input Analog block ground and reference voltage Analog output pin 0 DA0 Output Channel 0 analog output pin Analog output pin 1 DA1 Output Channel 1 analog output pin Reference voltage pin Vref Input Reference voltage for analog block 16.3 Register Description The D/A converter has the following registers. For details on the module stop control register, refer to section 22.1.2, Module Stop Control Registers A to D (MSTPCRA to MSTPCRD). * D/A data register 0 (DADR0) * D/A data register 1 (DADR1) * D/A control register (DACR) 16.3.1 D/A Data Registers 0 and 1 (DADR0 and DADR1) DADR0 and DADR1 are 8-bit readable/writable registers that store data for D/A conversion. When analog output is permitted, D/A data register contents are converted and output to analog output pins. Rev. 3.00, 08/03, page 414 of 612 16.3.2 D/A Control Register (DACR) DACR controls D/A converter operation. Bit Bit Name Initial Value R/W Description 7 DAOE1 0 R/W D/A Output Enable 1 Controls D/A conversion and analog output 0: Analog output DA1 is disabled 1: D/A conversion for channel 1 and analog output DA1 are enabled 6 DAOE0 0 R/W D/A Output Enable 0 Controls D/A conversion and analog output 0: Analog output DA0 is disabled 1: D/A conversion for channel 0 and analog output DA0 are enabled 5 DAE 0 R/W D/A Enable Controls D/A conversion in conjunction with the DAOE0 and DAOE1 bits. When the DAE bit is cleared to 0, D/A conversion for channels 0 and 1 are controlled individually. When DAE is set to 1, D/A conversion for channels 0 and 1 are controlled as one. Conversion result output is controlled by the DAOE0 and DAOE1 bits. For details, see table 16.2. 4 to 0 All 1 Reserved These bits are always read as 1 and cannot be modified. Table 16.2 D/A Conversion Control Bit 5 Bit 7 Bit 6 DAE DAOE1 DAOE0 Description 0 0 0 Disables D/A Conversion 1 Enables D/A Conversion for channel 0 1 0 Enables D/A Conversion for channel 1 1 Enables D/A Conversion for channels 0 and 1 0 Disables D/A Conversion 1 Enables D/A Conversion for channels 0 and 1 1 0 1 0 1 Rev. 3.00, 08/03, page 415 of 612 16.4 Operation Two channels of the D/A converter can perform conversion individually. When the DAOE bit in DACR is set to 1, D/A conversion is enabled and the conversion results are output. An example of D/A conversion of channel 0 is shown below. The operation timing is shown in figure 16.2. 1. Write conversion data to DADR0. 2. When the DAOE0 bit in DACR is set to 1, D/A conversion starts. After the interval of tDCONV, the conversion results are output from the analog output pin DA0. The conversion results are output continuously until DADR0 is modified or DAOE0 bit is cleared to 0. The output value is calculated by the following formula: (DADR contents)/256 x Vref 3. Conversion starts immediately after DADR0 is modified. After the interval of tDCONV, conversion results are output. 4. When the DAOE bit is cleared to 0, analog output is disabled. DADR0 write cycle DACR write cycle DADR0 write cycle DACR write cycle ADRES Conversion data (1) DADR0 Conversion data (2) DAOE0 Conversion result (2) Conversion result (1) DA0 High impedance state tDCONV tDCONV [Legend] tDCONV: D/A conversion time Figure 16.2 D/A Converter Operation Example Rev. 3.00, 08/03, page 416 of 612 16.5 16.5.1 Usage Notes Analog Power Supply Current in Software Standby Mode If this LSI enters software standby mode while D/A conversion is enabled, D/A output is retained and the analog power supply current is equivalent to that during D/A conversion. To reduce analog power supply current in software standby mode, clear the DAOE0, DAOE1 and DAE bits to 0 to disable D/A output. 16.5.2 Setting for Module Stop Mode It is possible to enable/disable the D/A converter operation using the module stop control register, the D/A converter does not operate by the initial value of the register. The register can be accessed by releasing the module stop mode. For more details, see section 22, Power-Down Modes. Rev. 3.00, 08/03, page 417 of 612 Rev. 3.00, 08/03, page 418 of 612 Section 17 LCD Controller/Driver The H8S/2268 has an on-chip segment type LCD control circuit, LCD driver, and power supply circuit, enabling it to directly drive an LCD panel. 17.1 Features Features of the LCD controller/driver are given below. * Display capacity Duty Cycle Internal Driver Static 40 SEG 1/2 40 SEG 1/3 40 SEG 1/4 40 SEG * LCD RAM capacity 8 bits x 20 bytes (160 bits) Byte or word access to LCD RAM * The segment output pins can be used as ports. H8S/2268 Group: SEG40 to SEG1 pins can be used as ports in groups of eight. H8S/2264 Group: SEG24 to SEG1 pins can be used as ports in groups of eight. * Common output pins not used because of the duty cycle can be used for common doublebuffering (parallel connection). With 1/2 duty, parallel connection of COM1 to COM2, and of COM3 to COM4, can be used In static mode, parallel connection of COM1 to COM2, COM3, and COM4 can be used * Choice of 11 frame frequencies * A or B waveform selectable by software * Built-in power supply split-resistance * Display possible in operating modes other than standby mode and module stop mode * Display possible during low-voltage operation by built-in triple step-up voltage circuit (supported only by the H8S/2268 Group) * Module stop mode As the initial setting, LCD operation is halted. Access to registers and LCD RAM is enabled by clearing module stop mode. LCDSG00B_000020030700 Rev. 3.00, 08/03, page 419 of 612 Figure 17.1 shows a block diagram of the LCD controller/driver. VCC M /16 to /2048 V1 V2 V3 VSS CL2 Common data latch SUB Internal data bus LCD drive power supply (Built-in step-up voltage circuit*) Common driver COM4 SEG40 SEG39 SEG38 SEG37 SEG36 LPCR LCR LCR2 Display timing generator COM1 40-bit shift register CL1 Segment driver LCD RAM 20 bytes SEG1 SEGn, DO [Legend] LPCR: LCD port control register LCR: LCD control register LCR2: LCD control register 2 Note: * Supported only by the H8S/2268 Group. Figure 17.1 Block Diagram of LCD Controller/Driver Rev. 3.00, 08/03, page 420 of 612 17.2 Input/Output Pins Table 17.1 shows the LCD controller/driver pin configuration. Table 17.1 Pin Configuration Name Abbreviation I/O Function Segment output pins SEG40 to SEG1 Output LCD segment drive pins (H8S/2268 Group) All pins are multiplexed as port pins (setting programmable) (H8S/2264 Group) SEG24 to SEG1 pins are multiplexed as port pins (setting programmable) Common output pins COM4 to COM1 LCD power supply pins V1, V2, V3 Output LCD common drive pins Pins can be used in parallel with static or 1/2 duty Used when a bypass capacitor is connected externally, and when an external power supply circuit is used V3 pin is LCD input reference power supply when triple step-up voltage circuit is used*. Capacitance pins for LCD step-up voltage* C1, C2 Capacitance pins for step-up voltage LCD drive power supply Note:* Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 421 of 612 17.3 Register Descriptions The LCD controller/driver has the following registers. * LCD port control register (LPCR) * LCD control register (LCR) * LCD control register 2 (LCR2) * LCDRAM 17.3.1 LCD Port Control Register (LPCR) LPCR selects the duty cycle, LCD driver, and pin functions. Bit Bit Name Initial Value R/W Description 7 DTS1 0 R/W Duty Cycle Select 1 and 0 6 DTS0 0 R/W Common Function Select 5 CMX 0 R/W The combination of DTS1 and DTS0 selects static, 1/2, 1/3, or 1/4 duty. CMX specifies whether or not the same waveform is to be output from multiple pins to increase the common drive power when not all common pins are used because of the duty setting. 4 0 Reserved This bit is always read as 0 and should only be written with 0. 3 SGS3 0 R/W Segment Driver Select 3 to 0 2 SGS2 0 R/W Bits 3 to 0 select the segment drivers to be used. 1 SGS1 0 R/W For details, see tables 17.3 and 17.4. 0 SGS0 0 R/W Rev. 3.00, 08/03, page 422 of 612 Table 17.2 Duty Cycle and Common Function Selection Bit 7: DTS1 Bit 6: DTS0 Bit 5: CMX Duty Cycle Common Drivers Notes 0 0 0 Static COM1 COM4, COM3, and COM2 can be used as ports (Initial value) COM4 to COM1 COM4, COM3, and COM2 output the same waveform as COM1 COM2 to COM1 COM4 and COM3 can be used as ports COM4 to COM1 COM4 outputs the same waveform as COM3, and COM2 outputs the same waveform as COM1 COM3 to COM1 COM4 can be used as a port* COM4 to COM1 Do not use COM4 COM4 to COM1 1 1 0 1/2 duty 1 1 0 0 1/3 duty 1 1 X 1/4 duty [Legend] X: Don't care Note: COM4 to COM1 function as ports when the setting of SGS3 to SGS0 is 0000. * Cannot be used as a port when the SUPS bit in LCR2 is 1 in the H8S/2268 Group. Set the SUPS bit to 0 when using as a port. Table 17.3 Segment Driver Selection (1) (H8S/2268 Group) Function of Pins SEG40 to SEG1 Bit 3: Bit 2: Bit 1: Bit 0: SEG40 to SGS3 SGS2 SGS1 SGS0 SEG33 SEG32 to SEG25 SEG24 to SEG17 SEG16 to SEG9 SEG8 to SEG1 0 0 0 1 1 1 X 0 0 Port Port Port Port Port 1 SEG Port Port Port Port 0 SEG SEG Port Port Port 1 SEG SEG SEG Port Port 0 SEG SEG SEG SEG Port 1 SEG SEG SEG SEG SEG 1 X Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited X X Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited [Legend] X: Don't care Note: * COM4 to COM1 also function as ports when the setting of SGS3 to SGS0 is 0000. Rev. 3.00, 08/03, page 423 of 612 Table 17.4 Segment Driver Selection (2) (H8S/2264 Group) Function of Pins SEG40 to SEG1 Bit 3: SGS3 Bit 2: SGS2 Bit 1: SGS1 Bit 0: SGS0 SEG40 to SEG25 SEG24 to SEG17 SEG16 to SEG9 SEG8 to SEG1 0 0 0 0 Port Port Port 1 Setting prohibited Setting prohibited Setting prohibited Setting prohibited 0 SEG Port Port Port 1 SEG SEG Port Port 0 SEG SEG SEG Port 1 SEG SEG SEG SEG 1 X Setting prohibited Setting prohibited Setting prohibited Setting prohibited X X Setting prohibited Setting prohibited Setting prohibited Setting prohibited 1 1 1 0 X [Legend] X: Don't care Note: * COM4 to COM1 also function as ports when the setting of SGS3 to SGS0 is 0000. 17.3.2 LCD Control Register (LCR) LCR performs LCD power supply split-resistance connection control and display data control, and selects the frame frequency. Bit Bit Name Initial Value R/W Description 7 1 R/W LCD Disable Bit This bit is always read as 1. The write value should always be 0. 6 PSW 0 R/W LCD Power Supply Split-Resistance Connection Control Bit 6 can be used to disconnect the LCD power supply split-resistance from VCC when LCD display is not required in a power-down mode, or when an external power supply is used. When the ACT bit is cleared to 0, and also in standby mode, the LCD power supply splitresistance is disconnected from VCC regardless of the setting of this bit. 0: LCD power supply split-resistance is disconnected from VCC 1: LCD power supply split-resistance is connected to VCC Rev. 3.00, 08/03, page 424 of 612 Bit Bit Name Initial Value R/W 5 ACT 0 R/W Description Display Function Activate Bit 5 specifies whether or not the LCD controller/driver is used. Clearing this bit to 0 halts operation of the LCD controller/driver. The LCD drive power supply ladder resistance is also turned off, regardless of the setting of the PSW bit. However, register contents are retained. 0: LCD controller/driver operation halted 1: LCD controller/driver operation enabled 4 DISP 0 R/W Display Data Control Bit 4 specifies whether the LCD RAM contents are displayed or blank data is displayed regardless of the LCD RAM contents. 0: Blank data is displayed 1: LCD RAM data is displayed 3 CKS3 0 R/W Frame Frequency Select 3 to 0 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Bits 3 to 0 select the operating clock and the frame frequency. In subactive mode, watch mode, and subsleep mode, the system clock () is halted, and therefore display operations are not performed if one of the clocks from /16 to /2048 is selected. If LCD display is required in these modes, SUB, SUB/2, or SUB/4 must be selected as the operating clock. For details, see table 17.5. Note: * 0 should be written to bit 7 after the other bits have been set. Rev. 3.00, 08/03, page 425 of 612 Table 17.5 Frame Frequency Selection Bit 3: CKS3 0 1 Bit 2: CKS2 X 0 Bit 1: CKS1 Operating Clock 0 SUB 128 Hz* 1 SUB/2 64 Hz* 1 X SUB/4 0 0 0 1 1 Frame Frequency* Bit 0: CKS0 0 1 = 20 MHz 2 1 = 2 MHz 2 128 Hz* 2 64 Hz* 2 32 Hz* 2 32 Hz* /16 488 Hz 1 /32 244 Hz 0 /64 122 Hz 1 /128 610 Hz 61 Hz 0 /256 305 Hz 30.5 Hz 1 /512 152.6 Hz 0 /1024 76.3 Hz 1 /2048 38.1 Hz 2 [Legend] X: Don't care Notes: 1. When 1/3 duty is selected, the frame frequency is 4/3 times the value shown. 2. This is the frame frequency when SUB = 32.768 kHz. 17.3.3 LCD Control Register 2 (LCR2) LCR2 controls switching between the A waveform and B waveform, selects clock for step-up voltage circuit, selects power supply, and selects the duty ratio for charge/discharge pulse that controls to separate power supply divider resistance from power supply circuit. Bit Bit Name Initial Value R/W Description 7 LCDAB 0 R/W A Waveform/B Waveform Switching Control Bit 7 specifies whether the A waveform or B waveform is used as the LCD drive waveform. 0: Drive using A waveform 1: Drive using B waveform 6 1 Reserved These bits are always read as 1 and cannot be modified. Rev. 3.00, 08/03, page 426 of 612 Bit Bit Name Initial Value R/W Description 5 HCKS 0 R/W (H8S/2268 Group) Triple Step-Up Voltage Circuit Clock Select This bit selects a clock used for triple step-up voltage circuit. This bit selects a clock which divides a clock specified by the LCD operating control register (LCR) by 4 or 8 as step-up voltage circuit clock. 0: A clock, which divides a LCD operating clock by 4, is selected as step-up voltage circuit clock 1: A clock, which divides a LCD operating clock by 8, is selected as step-up voltage circuit clock (H8S/2264 Group) Reserved 0 should be written to this bit. 4 SUPS 0 R/W (H8S/2268 Group) Drive Power Select Triple Step-up Voltage Circuit Control The triple step-up voltage circuit stops operation when Vcc is selected as drive power. The triple step-up voltage circuit starts operation when LCD input reference voltage (VLCD3) is selected as drive power. 0: Drive power is Vcc, triple step-up voltage circuit halts 1: Drive power is triple step-up voltage of the LCD input reference voltage (VLCD3), triple step-up voltage circuit operates (H8S/2264 Group) Reserved 0 should be written to this bit. Rev. 3.00, 08/03, page 427 of 612 Bit Bit Name Initial Value R/W Description 3 CDS3 0 R/W Selection of Duty Ratio for Charge/Discharge Pulse 2 CDS2 0 R/W 1 CDS1 0 R/W 0 CDS0 0 R/W Duty ratio is selected during the power supply divider resistance is connected to power supply circuit. When the duty ratio of 0 is selected, the power supply divider resistance is fixed to the state that the resistance is separated from the power supply circuit. Therefore, supply the power to pins V1, V2, and V3 from the external circuit. The charge/discharge pulses have the waveform shown in figure 17.2. The duty ratio is represented by TC/TW . 0000: duty ratio = 1 (stack at high) 0001: duty ratio = 1/8 0010: duty ratio = 2/8 0011: duty ratio = 3/8 0100: duty ratio = 4/8 0101: duty ratio = 5/8 0110: duty ratio = 6/8 0111: duty ratio = 0 (stack at low) 10XX: duty ratio = 1/16 11XX: duty ratio = 1/32 [Legend] X: Don't care 1 TW COM1 Tc Tdc Tc Tdc Figure 17.2 A Waveform 1/2 Duty 1/2 Vias Rev. 3.00, 08/03, page 428 of 612 The relationships between the LCD operating clock and step-up voltage clock, and between bits CKS3 to CKS0 in LCD control register (LCR) and bit HCKS in LCD control register 2 (LCR2) are shown below. LCR Step-up Bit 3 Bit 2 Bit 1 Bit 0 CKS3 CKS2 CKS1 CKS0 0 X 0 0 0 X 0 1 LCR2 Voltage Circuit HCKS* LCD clock clock* = 20 MHz = 2 MHz = 20 MHz = 2 MHz 0 SUB SUB/4 128 Hz Bit 5 0 SUB/2 1 X 0 SUB/4 0 0 0 0 /16 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 0 /128 1 0 1 1 1 1 0 0 1 1 1 0 1 244 Hz 122 Hz 61 Hz 305 Hz /512 152.6 Hz 76.3 Hz 4096 /1024 8192 /2048 38.1 Hz 16384 31.3 kHz 15.6 kHz 7.81 kHz 3.91 kHz 39.1 kHz 19.5 kHz 1.95 kHz 9.77 kHz 977 kHz 30.5 Hz 2048 1 1 610 Hz /256 1 0 488 Hz 1024 1 1 512 1 1 1024 Hz 256 /64 1 1 64 /32 1 0 32 Hz 128 1 1 2048 Hz SUB/32 1 1 4096 Hz 64 Hz SUB/16 1 X 8192 Hz SUB/8 1 0 Frame frequency Step-Up Voltage Circuit clock frequency* 4.88 kHz 2.44 kHz 1.22 kHz [Legend] X: Don't care Note: * Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 429 of 612 17.4 Operation 17.4.1 Settings up to LCD Display To perform LCD display, the hardware and software related items described below must first be determined. 1. Hardware Settings A. Using 1/2 duty When 1/2 duty is used, interconnect pins V2 and V3 as shown in figure 17.3. VCC V1 V2 V3 VSS Figure 17.3 Handling of LCD Drive Power Supply when Using 1/2 Duty B. Large-panel display As the impedance of the built-in power supply split-resistance is large, it may not be suitable for driving a large panel. If the display lacks sharpness when using a large panel, refer to section 17.4.6, Boosting the LCD Drive Power Supply. When static or 1/2 duty is selected, the common output drive capability can be increased. Set CMX to 1 when selecting the duty cycle. In this mode, with a static duty cycle pins COM4 to COM1 output the same waveform, and with 1/2 duty the COM1 waveform is output from pins COM2 and COM1, and the COM2 waveform is output from pins COM4 and COM3. C. LCD drive power supply setting With the H8S/2268 and 2264, there are two ways of providing LCD power: by using the on-chip power supply circuit, or by using an external power supply circuit. When an external power supply circuit is used for the LCD drive power supply, connect the external power supply to the V1 pin. 2. Software Settings A. Duty selection Any of four duty cyclesstatic, 1/2 duty, 1/3 duty, or 1/4 dutycan be selected with bits DTS1 and DTS0. Rev. 3.00, 08/03, page 430 of 612 B. Segment selection The segment drivers to be used can be selected with bits SGS3 to SGS0. 3. Frame frequency selection The frame frequency can be selected by setting bits CKS3 to CKS0. The frame frequency should be selected in accordance with the LCD panel specification. For the clock selection method in watch mode, subactive mode, and subsleep mode, see section 17.4.4, Operation in Power-Down Modes. A. A or B waveform selection Either the A or B waveform can be selected as the LCD waveform to be used by means of LCDAB. B. LCD drive power supply selection When an external power supply circuit is used, turn the LCD drive power supply off with the PSW bit. 17.4.2 Relationship between LCD RAM and Display The relationship between the LCD RAM and the display segments differs according to the duty cycle. LCD RAM maps for the different duty cycles are shown in figures 17.4 to 17.7. After setting the registers required for display, data is written to the part corresponding to the duty using the same kind of instruction as for ordinary RAM, and display is started automatically when turned on. Word- or byte-access instructions can be used for RAM setting. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FC40 SEG2 SEG2 SEG2 SEG2 SEG1 SEG1 SEG1 SEG1 H'FC53 SEG40 SEG40 SEG40 SEG40 SEG39 SEG39 SEG39 SEG39 COM4 COM3 COM2 COM1 COM4 COM3 COM2 COM1 Figure 17.4 LCD RAM Map (1/4 Duty) Rev. 3.00, 08/03, page 431 of 612 Bit 6 Bit 5 Bit 4 Bit 2 Bit 1 Bit 0 H'FC40 Bit 7 SEG2 SEG2 SEG2 Bit 3 SEG1 SEG1 SEG1 H'FC53 SEG40 SEG40 SEG40 SEG39 SEG39 SEG39 COM3 COM2 COM1 COM3 COM2 COM1 Space not used for display Figure 17.5 LCD RAM Map (1/3 Duty) H'FC40 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SEG4 SEG4 SEG3 SEG3 SEG2 SEG2 SEG1 SEG1 Display space H'FC49 SEG40 SEG40 SEG39 SEG39 SEG38 SEG38 SEG37 SEG37 Space not used for display H'FC53 COM2 COM1 COM2 COM1 COM2 COM1 COM2 COM1 Figure 17.6 LCD RAM Map (1/2 Duty) Rev. 3.00, 08/03, page 432 of 612 H'FC40 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 Display space H'FC44 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 Space not used for display H'FC53 COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 Figure 17.7 LCD RAM Map (Static Mode) Rev. 3.00, 08/03, page 433 of 612 1 frame 1 frame M M Data Data COM1 V1 V2 V3 VSS COM1 V1 V2 V3 VSS COM2 V1 V2 V3 VSS COM2 V1 V2 V3 VSS COM3 V1 V2 V3 VSS COM3 V1 V2 V3 VSS COM4 V1 V2 V3 VSS SEGn V1 V2 V3 VSS SEGn V1 V2 V3 VSS (a) Waveform with 1/4 duty (b) Waveform with 1/3 duty 1 frame 1 frame M M Data Data COM1 COM2 V1 V2,V3 VSS COM1 V1 V2,V3 VSS SEGn V1 V2,V3 VSS SEGn V1 VSS V1 VSS (d) Waveform with static output (c) Waveform with 1/2 duty Figure 17.8 Output Waveforms for Each Duty Cycle (A Waveform) Rev. 3.00, 08/03, page 434 of 612 1 frame 1 frame 1 frame 1 frame 1 frame M M Data Data 1 frame 1 frame 1 frame COM1 V1 V2 V3 VSS COM1 V1 V2 V3 VSS COM2 V1 V2 V3 VSS COM2 V1 V2 V3 VSS COM3 V1 V2 V3 VSS COM3 V1 V2 V3 VSS COM4 V1 V2 V3 VSS SEGn V1 V2 V3 VSS SEGn V1 V2 V3 VSS (a) Waveform with 1/4 duty 1 frame 1 frame 1 frame (b) Waveform with 1/3 duty 1 frame 1 frame M M Data Data V1 V2,V3 VSS COM1 COM2 V1 V2,V3 VSS SEGn SEGn V1 V2,V3 VSS COM1 1 frame 1 frame 1 frame V1 VSS V1 VSS (d) Waveform with static output (c) Waveform with 1/2 duty Figure 17.9 Output Waveforms for Each Duty Cycle (B Waveform) Rev. 3.00, 08/03, page 435 of 612 Table 17.6 Output Levels Data 0 0 1 1 M 0 1 0 1 Common output V1 VSS V1 VSS Segment output V1 VSS VSS V1 Common output V2, V3 V2, V3 V1 VSS Segment output V1 VSS VSS V1 Static 1/2 duty 1/3 duty 1/4 duty 17.4.3 Common output V3 V2 V1 VSS Segment output V2 V3 VSS V1 Common output V3 V2 V1 VSS Segment output V2 V3 VSS V1 Triple Step-Up Voltage Circuit (Supported Only by the H8S/2268 Group) The H8S/2268 Group incorporates a triple step-up voltage circuit. Triple voltage of liquid crystal input reference voltage (VLCD3) input from V3 pin can be used for the LCD driver. Before enabling the step-up voltage circuit, duty cycle (1/3 duty or 1/4 duty), LCD driver or I/O pin function, and display data and frame frequency should be selected. Around 0.1-F capacitor should be connected between C1 and C2, and voltage specified in section 25.2.6, LCD Characteristics should be applied to V3 pin. After above settings, by selecting the step-up voltage circuit clock in LCD control register 2 (LCR2) and setting SUPS to 1, the triple step-up voltage circuit operates, voltage double of VLCD3 is generated for V2 pin, and voltage triple of VLCD3 is generated for V1pin. Notes: 1. The triple step-up voltage circuit should only be used as LCD drive power of the H8S/2268 Group. To drive large panel, power supply capacitance may be insufficient. In this case, Vcc should be used as power supply or external power supply circuit should be used. 2. When the triple step-up voltage circuit is used, do not specify static or 1/2 duty as duty cycle. 3. Do not use capacitance with polarity such as electrolytic capacitor as capacitance to be connected between C1 and C2. Rev. 3.00, 08/03, page 436 of 612 C1 C C2 V1 C V2 C V3 C Note: C: 0.1F (typ.) (0.05 to 0.2F) Figure 17.10 Connection when Triple Step-Up Voltage Circuit Used (Supported Only by the H8S/2268 Group) 17.4.4 Operation in Power-Down Modes In the H8S/2268 and 2264, the LCD controller/driver can be operated even in the power-down modes. The operating state of the LCD controller/driver in the power-down modes is summarized in table 17.7. In subactive mode, watch mode, and subsleep mode, the system clock oscillator stops, and therefore, unless SUB, SUB/2, or SUB/4 has been selected by bits CKS3 to CKS0, the clock will not be supplied and display will halt. Since there is a possibility that a direct current will be applied to the LCD panel in this case, it is essential to ensure that SUB, SUB/2, or SUB/4 is selected. In the software standby mode the segment output and common output pins switch to I/O port status. In this case if a port's DDR or PCR bit is set to 1, a DC voltage could be applied to the LCD panel. Therefore, DDR and PCR must never be set to 1 for ports being used for segment output or common output. Rev. 3.00, 08/03, page 437 of 612 Table 17.7 Power-Down Modes and Display Operation Software Hardware Reset Active Sleep Watch Subactive Subsleep Standby standby Module Stop Runs Runs Runs Stops Stops Stops Stops Stops Stops*4 w Runs Runs Runs Runs Runs Runs Stops*1 Stops Stops*4 ACT = 0 Stops Stops Stops Stops Stops Stops Stops*2 Stops*2 Stops ACT = 1 Stops Functions Functions Functions Functions*3 Functions*3 Stops*2 Stops*2 Stops Mode Clock Display operation *3 Notes: 1. The subclock oscillator does not stop, but clock supply is halted. 2. The LCD drive power supply is turned off regardless of the setting of the PSW bit. 3. Display operation is performed only if SUB, SUB/2, or SUB/4 is selected as the operating clock. 4. The clock supplied to the LCD stops. 17.4.5 Low-Power LCD Drive The simplest way to achieve low-power operation for an LCD power supply circuit is to use an internal division resistor. However, since the values of the internal resistors are fixed, a constant current continually flows from Vcc to Vss of the internal resistor. Since the quantity of the current is independent of the dissipation current of an LCD panel, power is wasted in using a low-power LCD. This LSI incorporates a function that eliminates wastage of power. By using this function, a power supply circuit that is most suitable for the power of a given LCD panel can be obtained. * Principle As shown in figure 17.11, external capacitors are connected to V1, V2, and V3 of the LCD power supply terminals. The capacitors connected to V1, V2, and V3 are repeatedly charged and discharged to retain required voltage levels in the cycles shown in figure 17.11. In this case, the charged voltages are equivalent to V1, V2, and V3, respectively. (In 1/3 bias operation, for example, the V2 voltage is two thirds of the V1 voltage and the V3 voltage is one third of the V1 voltage.) Power is supplied to the LCD panel by the electric charges that are accumulated in these capacitors. The capacitances of the capacitors and the charge-discharge period are determined by the quantity of power which the LCD panel requires. The charge-discharge period can be determined by software. Rev. 3.00, 08/03, page 438 of 612 * Example of Operation (1/3 bias operation) During charging period Tc in figure 17.11, the voltages that are divided by the internal division resistors are applied to the V1, V2, and V3 terminals (the V2 voltage is two thirds of the V1 voltage and the V3 voltage is one third of the V1 voltage), and these voltages charge external capacitors C1, C2, and C3. Even during this period, the LCD panel is being driven. In the subsequent discharge period Tdc, the charge operation stops. The LCD panel is now driven by discharge of the charges accumulated in the respective capacitors. At this point in time, the respective voltages fall slightly as the capacitors are discharged. Attention must be paid so that the operation of the LCD panel is not affected, by selecting the proper charging period and the capacitance of the capacitors. The capacitors connected to the V1, V2, and V3 terminals are repeatedly charged and discharged in the cycles shown in figure 17.11 and retain required voltages, keeping the LCD panel in operation. The capacitance of the capacitors and a charge-discharge period is determined by the quantity of power in which the LCD panel requires. In addition, the charge-discharge period can be selected by CDS3 to 0. In actuality, the capacitance of the capacitors and the charge-discharge period must be determined through experiment, on the basis of the power dissipation specifications of the LCD panel. This method, however, permits the most proper current value to be selected, compared with a case in which a DC current continually flows in the internal resistors. Charging period Tc V1 potential V1 V2 potential C1 V2 C2 V3 C3 V1x2/3 V3 potential V1x1/3 Discharging period Tdc Voltage drop Vd1 associated with discharging due to LCD panel driving Vd2 Vd3 Power supply voltage fluctuation in 1/3 bias system Figure 17.11 Example of Low-Power-Consumption LCD Drive Operation Rev. 3.00, 08/03, page 439 of 612 17.4.6 Boosting the LCD Drive Power Supply When a large panel is driven, the on-chip power supply capacity may be insufficient. In this case, the power supply impedance must be reduced. This can be done by connecting bypass capacitors of around 0.1 to 0.3 F to pins V1 to V3, as shown in figure 17.12, or by adding a split-resistance externally. VCC VR V1 R This LSI R = several k to several M V2 R C = 0.1 to 0.3 F V3 R VSS Figure 17.12 Connection of External Split-Resistance Rev. 3.00, 08/03, page 440 of 612 Section 18 DTMF Generation Circuit The H8S/2268 Group contains a Dual-Tone Multi-Frequency generation circuit to generate DTMF signals. It is not contained in the H8S/2264 Group. 1 2 3 A R1(697Hz) 4 5 6 B R2(770Hz) 7 8 9 C R3(852Hz) * 0 # D R4(941Hz) C1(1,209Hz) C2(1,336Hz) C3(1,477Hz) C4(1,633Hz) The DTMF signal consists of two types of sine waveforms and is used to access a switch device. The function of the DTMF signal is shown in the frequency matrix in figure 18.1. The DTMF generation circuit produces the frequencies corresponding to the numbers and symbols in the figure. Figure 18.1 DTMF Frequencies 18.1 Features * Generating DTMF frequency sine waveform from the system clock () The system clock (2.0 to 20.4 MHz, with 400 kHz stops) is divided to produce a 400-kHz clock signal. This clock signal is then supplied to the feedback loop, comprised of a variant program divider and sine waveform counter to generate a DTMF frequency sine waveform. * Producing low distortion, stable sine waveforms Sine waveforms signals are output from the high-precision resistor rudder-type D/A converter. In addition, one cycle is divided into 32, resulting in low-distortion stable signal waveforms. * Synthesis or single waveform output selectable Synthesized row and column output, row output, or column output are selectable. * Module stop mode can be set. Figure 18.2 shows the block diagram for the DTMF generation circuit. DTMF000B_000020020700 Rev. 3.00, 08/03, page 441 of 612 DTLR (2.0 to 20.4MHz, with 400kHz steps) 400kHz Clock counter Variant program divider Sine waveform counterD/A TONED Feed back Internal data bus Row DTCR AVCC Column Sine waveform counter D/A Variant progam divider Feedback Symbol explanationl DTLR : DTMF Load Register DTCR : DTMF Control Register Figure 18.2 DTMF Generation Circuit Diagram 18.2 Input/Output Pins Table 18.1 shows the pin configuration of the DTMF generation circuit. Table 18.1 Pin Configuration Name Abbreviation Analog power supply pin AVcc Input Power supply of analog section DTMF signal output TONED Output DTMF signal output pin Rev. 3.00, 08/03, page 442 of 612 Input/Output Function 18.3 Register Descriptions The DTMF generation circuit contains the following resisters: * DTMF control register (DTCR) * DTMF load register (DTLR) 18.3.1 DTMF Control Register (DTCR) The DTCR controls the DTMF generation circuit operation, column and row outputs, and selects the output frequency. Bit Bit Name Initial Value R/W Description 7 DTEN 0 R/W This bit controls DTMF generation 0: Halts the DTMF generation circuit. 1: Operates DTMF generation circuit. 6 - 1 - 5 CLOE 0 R/W Reserved This bit is always read as 1 and cannot be modified. This bit controls Column section outputs 0: Inhibits DTMF signal output on Column section (hiimpedance) 1: Enables DTMF signal output on Column section. 4 RWOE 0 R/W This bit controls Column section outputs 0: Inhibits DTMF signal output on Row section (hiimpedance) 1: Enables DTMF signal output on Row section. 3 CLF1 0 R/W DTMF signal output frequency on Column section 1 and 0 2 CLF0 0 R/W Selects Column DTMF signal frequency from C1 to C4. 00: Column DTMF signal output frequency: 1209 Hz (C1) 01: Column DTMF signal output frequency: 1336 Hz (C2) 10: Column DTMF signal output frequency: 1447 Hz (C3) 11: Column DTMF signal output frequency: 1633 Hz (C4) 1 RWF1 0 R/W DTMF signal output frequency on Row section: 1, 0 0 RWF0 0 R/W Selects Column DTMF signal frequency from R1 to R4. 00: Row DTMF signal output frequency: 697 Hz (R1) 01: Row DTMF signal output frequency: 770 Hz (R2) 10: Row DTMF signal output frequency: 852 Hz (R3) 11: Row DTMF signal output frequency: 941 Hz (R4) Rev. 3.00, 08/03, page 443 of 612 18.3.2 DTMF Load Register (DTLR) The DTLR sets the system clock division ratio for the DTMF generation circuit. Bit Bit Name Initial Value R/W Description 7, 6 - All 1 - Reserved These bits are always read as 1 and cannot be modified. 5 DTL5 0 R/W Main clock division ratio 5 to 0 4 DTL4 0 R/W 3 DTL3 0 R/W 2 DTL2 0 R/W 1 DTL1 0 R/W These bits set the system clock division ratio to produce 400-kHz clock signals to be supplied to the DTMF generation circuit. The division ratio determines the counter value of 6b'000101 to 6b'110011(D'5 to D'51) according to the range 2.0 to 20.4 MHz. 0 DTL0 0 R/W 000000: Setting prohibited 000001: Setting prohibited 000010: Setting prohibited 000011: Setting prohibited 000100: Setting prohibited 000101: Division ratio (5) main clock frequency (2.0 MHz) 000110: Division ratio (6) main clock frequency (2.4 MHz) 000111: Division ratio (7) main clock frequency (2.8 MHz) : : 110001: Division ratio (49) main clock frequency (19.6 MHz) 110010: Division ratio (50) main clock frequency (20.0 MHz) 110011: Division ratio (51) main clock frequency (20.4 MHz) 110100: Setting prohibited : : 111111: Setting prohibited Note: The correct values should be set in DTL0 to DTL5. If these bit settings do not match the system clock, correct DTMF signal output frequency cannot be obtained. Additionally, correct operation is not guaranteed if the DTL0 to DTL5 settings are other than 5 to 51 (division ratio 5 to 51). Rev. 3.00, 08/03, page 444 of 612 18.4 Operation 18.4.1 Output Waveform The DTMF generation circuit provides synthesized row and column groups output waveforms or sine waveforms (DTCR signal) of row or column group from TONED pin. These signals are produced in the high-precision resistor rudder-type D/A converter. The output frequency is set in DTCR. Figure 18.3 shows the TONED pin output equivalent circuit. Figure 18.4 shows a single output waveform of column or row group alone. One cycle of the output waveform is divided into 32, resulting in low-distortion stable signal waveforms. control AVCC Output control AVSS Row TONED Column Figure 18.3 TONED Pin Output Equivalent Circuit AVCC 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425 26272829 303132 AVSS Time slot Figure 18.4 TONED Pin Output Waveform (Row or Column Group Alone) Table 18.2 shows DTMF generation circuit output signal and typical signal frequencies, and frequency deviation between the two. Rev. 3.00, 08/03, page 445 of 612 Table 18.2 Frequency Deviation Between DTMF Output Signals And Typical Signals Symbol Typical Signal (Hz) DTMF Signal Output (Hz) Frequency Deviation (%) R1 697 694.44 -0.37 R2 770 769.23 -0.10 R3 852 851.06 -0.11 R4 941 938.97 -0.22 C1 1209 1212.12 0.26 C2 1336 1333.33 -0.20 C3 1477 1481.48 0.30 C4 1633 1639.34 0.39 18.4.2 Operation Flow The operating procedure for the DTMF generation circuit is as follows: 1. Set the system clock division ratio for the DTLR based on the frequency of the connected system clock. (2.0 to 20.4 MHz, with 400 kHz stops) 2. Set the frequencies of the Row (R1 to R4) and Column (C1 to C4) sections based on CLF0, CLF1, RWF0 and RWF1 of the DTCR. 3. Select the outputs of the Row and Column based on CLOE and RWOE of the DTCR, and set DTEN to 1 to operate the DTMF generation circuit. With the above setting, the set DTMF signal is output from the TONED pin. Rev. 3.00, 08/03, page 446 of 612 18.5 Application Circuit Example An application example of the DTMF generation circuit is shown in figure 18.5. 24k 19 TONED DTMF 2k HA16808ANT LSI 20 AVCC 100k 360k Pxx Vref1 +0.47 11 MUTE 2SC458 Note: The numeriic values on the right end of the signal lines indicate the HA16808ANT pin numbers. Figure 18.5 Example of HA16808ANT Connection 18.6 Usage Notes 1. Setting the module stop mode It is possible to enable/disable the DTMF operation using the module stop control register. The DTMF does not operate by the initial value of the register. The register can be accessed by releasing the module stop mode. For more details, see section 22, Power-Down Modes. 2. DTLR setting and system clock When using the DTMF generation circuit, note the following: The DTLR must be set so as to accommodate the system clock. If the DTLR setting does not match the system clock, correct DTMF signal output frequency cannot be obtained. 3. Relationship between AVcc, AVss and Vcc, Vss Set AVss = Vss as the relationship between AVcc, AVss and Vcc, Vss. If the DTMF generation circuit is not used, the AVcc and AVss pins must not be left open. Note: If the conditions above are not met, the reliability of the device may be adversely affected. Rev. 3.00, 08/03, page 447 of 612 Rev. 3.00, 08/03, page 448 of 612 Section 19 RAM The H8S/2268 Group and the H8S/2264 Group have on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. Product Classification RAM Size RAM Address Flash memory H8S/2268F version H8S/2266F 16 kbytes HFFB000 to HFFEFBF, HFFFFC0 to HFFFFFF H8S/2265F 8 kbytes HFFD000 to HFFEFBF, HFFFFC0 to HFFFFFF 4 kbytes HFFE000 to HFFEFBF, HFFFFC0 to HFFFFFF Masked ROM H8S/2268 version H8S/2266 16 kbytes HFFB000 to HFFEFBF, HFFFFC0 to HFFFFFF 8 kbytes HFFD000 to HFFEFBF, HFFFFC0 to HFFFFFF H8S/2265 4 kbytes HFFE000 to HFFEFBF, HFFFFC0 to HFFFFFF H8S/2264 4 kbytes HFFE000 to HFFEFBF, HFFFFC0 to HFFFFFF H8S/2262 2 kbytes HFFE800 to HFFEFBF, HFFFFC0 to HFFFFFF Rev. 3.00, 08/03, page 449 of 612 Rev. 3.00, 08/03, page 450 of 612 Section 20 ROM The features of the flash memory are summarized below. The block diagram of the flash memory is shown in figure 20.1. 20.1 Features * Size Product Type ROM Size ROM Address H8S/2268F 256 kbytes H000000 to H03FFFF H8S/2266F 128 kbytes H000000 to H01FFFF H8S/2265F 128 kbytes H000000 to H01FFFF * Programming/erase methods The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units. The flash memory of the H8S/2268 is configured as follows: 64 kbytes x 3 blocks, 32 kbytes x 1 block, and 4 kbytes x 8 blocks. The flash memory of the H8S/2266 and H8S/2265 is configured as follows: 64 kbytes x 1 block, 32 kbytes x 1 block, and 4 kbytes x 8 blocks. To erase the entire flash memory, each block must be erased in turn. * Reprogramming capability The flash memory can be reprogrammed for 100 times. * Two programming modes Boot mode User program mode On-board programming/erasing can be done in boot mode, in which the boot program built into the chip is started to erase or program of the entire flash memory. In normal user program mode, individual blocks can be erased or programmed. * Automatic bit rate adjustment For data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match the transfer bit rate of the host. * Programming/erasing protection There are three protect modes, hardware, software, and error protect, which allow protected status to be designated for flash memory program/erase operations. * Programmer mode Flash memory can be programmed/erased in programmer mode using a PROM programmer, as well as in on-board programming mode. ROMF253B_000020030700 Rev. 3.00, 08/03, page 451 of 612 * Emulation function for flash memory in RAM The real-time emulation for programming of flash memory is possible by overlapping the flash memory to a part of RAM. Internal address bus Module bus Internal data bus (16 bits) FLMCR1 FLMCR2 EBR1 Bus interface/controller Operating mode FWE pin Mode pin EBR2 RAMER FLPWCR Flash memory [Legend] FLMCR1: FLMCR2: EBR1: EBR2: RAMER: FLPWCR: Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register Flash memory power control register Figure 20.1 Block Diagram of Flash Memory 20.2 Mode Transitions When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, this LSI enters an operating mode as shown in figure 20.2. In user mode, flash memory can be read but not programmed or erased. The boot, user program and programmer modes are provided as modes to write and erase the flash memory. The differences between boot mode and user program mode are shown in table 20.1. Figure 20.3 shows the operation flow for boot mode and figure 20.4 shows that for user program mode. Rev. 3.00, 08/03, page 452 of 612 MD1 = 1, MD2 = 1, FWE = 0*1 Reset state RES = 0 RES = 0 User mode MD1 = 1, MD2 = 1, FWE = 1 FWE = 1 RES = 0 FWE = 0 User program mode *2 MD1 = 0 MD2 = 1, FWE = 1 RES = 0 Programmer mode *1 Boot mode On-board programming mode Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. 1. RAM emulation possible 2. MD1 = 0, MD2 = 0, P14 = 0, P16 = 0, P70 = 1 Figure 20.2 Flash Memory State Transitions Table 20.1 Differences between Boot Mode and User Program Mode Boot Mode User Program Mode Total erase Yes Yes Block erase No Yes Programming control program* Program/program-verify Program/program-verify/erase/ erase-verify/emulation Note: * To be provided by the user, in accordance with the recommended algorithm. Rev. 3.00, 08/03, page 453 of 612 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in this LSI (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication. The boot program required for flash memory erasing is automatically transferred to the RAM boot program area. Host Host Programming control program New application program New application program This LSI This LSI SCI Boot program Flash memory RAM SCI Boot program RAM Flash memory Boot program area Application program (old version) Application program (old version) 3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, total flash memory erasure is performed, without regard to blocks. Programming control program 4. Writing new application program The programming control program transferred from the host to RAM is executed, and the new application program in the host is written into the flash memory. Host Host New application program This LSI This LSI SCI Boot program Flash memory RAM Flash memory Boot program area Flash memory preprogramming erase Programming control program SCI Boot program RAM Boot program area New application program Programming control program Program execution state Figure 20.3 Boot Mode Rev. 3.00, 08/03, page 454 of 612 1. Initial state The FWE assessment program that confirms that user program mode has been entered, and the program that will transfer the programming/erase control program from flash memory to on-chip RAM should be written into the flash memory by the user beforehand. The programming/erase control program should be prepared in the host or in the flash memory. 2. Programming/erase control program transfer When user program mode is entered, user software confirms this fact, executes transfer program in the flash memory, and transfers the programming/erase control program to RAM. Host Host Programming/ erase control program New application program New application program This LSI This LSI SCI Boot program Flash memory SCI Boot program Flash memory RAM RAM FWE assessment program FWE assessment program Transfer program Transfer program Programming/ erase control program Application program (old version) Application program (old version) 3. Flash memory initialization The programming/erase program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units. 4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks. Host Host New application program This LSI This LSI SCI Boot program Flash memory RAM FWE assessment program Flash memory RAM FWE assessment program Transfer program Transfer program Programming/ erase control program Flash memory erase SCI Boot program Programming/ erase control program New application program Program execution state Figure 20.4 User Program Mode (Example) Rev. 3.00, 08/03, page 455 of 612 20.3 Block Configuration Figure 20.5 shows the block configuration of 256-kbyte flash memory of the H8S/2268. Figure 20.6 shows the block configuration of 128-kbyte flash memory of the H8S/2266 and H8S/2265. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The flash memory of the H8S/2268 is divided into 4 kbytes (8 blocks), 32 kbytes (1 block), and 64 kbytes (3 blocks). The flash memory of the H8S/2266 and H8S/2265 is divided into 4 kbytes (8 blocks), 32 kbytes (1 block), and 64 kbytes (1 block). Erasing is performed in these units. Programming is performed in 128-byte units starting from an address with lower eight bits H'00 or H'80. Rev. 3.00, 08/03, page 456 of 612 EB0 Erase unit 4 kbytes H'000000 H'000001 H'000002 Programming unit: 128 bytes EB1 Erase unit 4 kbytes H'001000 H'001001 H'001002 Programming unit: 128 bytes H'00007F H'000FFF H'001FFF EB2 Erase unit 4 kbytes H'002000 H'002001 H'002002 Programming unit: 128 bytes EB3 Erase unit 4 kbytes H'003000 H'003001 H'003002 Programming unit: 128 bytes H'004002 Programming unit: 128 bytes EB4 Erase unit 4 kbytes H'00107F H'00207F H'002FFF H'00307F H'003FFF H'004000 H'004001 H'00407F H'004FFF EB5 Erase unit 4 kbytes H'005000 H'005001 H'005002 Programming unit: 128 bytes EB6 Erase unit 4 kbytes H'006000 H'006001 H'006002 Programming unit: 128 bytes H'00507F H'005FFF H'00607F H'006FFF EB7 Erase unit 4 kbytes H'007000 H'007001 H'007002 Programming unit: 128 bytes EB8 Erase unit 32 kbytes H'008000 H'008001 H'008002 Programming unit: 128 bytes EB9 Erase unit 64 kbytes H'010000 H'010001 H'010002 Programming unit: 128 bytes H'01007F EB10 Erase unit 64 kbytes H'020000 H'020001 H'020002 Programming unit: 128 bytes H'02007F H'030002 Programming unit: 128 bytes EB11 Erase unit 64 kbytes H'00707F H'007FFF H'00807F H'00FFFF H'01FFFF H'02FFFF H'030000 H'030001 H'03007F H'03FFFF Figure 20.5 Flash Memory Block Configuration (H8S/2268) Rev. 3.00, 08/03, page 457 of 612 EB0 Erase unit 4 kbytes H'000000 H'000001 H'000002 Programming unit: 128 bytes EB1 Erase unit 4 kbytes H'001000 H'001001 H'001002 Programming unit: 128 bytes H'00007F H'000FFF H'001FFF EB2 Erase unit 4 kbytes H'002000 H'002001 H'002002 Programming unit: 128 bytes EB3 Erase unit 4 kbytes H'003000 H'003001 H'003002 Programming unit: 128 bytes H'004002 Programming unit: 128 bytes EB4 Erase unit 4 kbytes H'00107F H'00207F H'002FFF H'00307F H'003FFF H'004000 H'004001 H'00407F H'004FFF EB5 Erase unit 4 kbytes H'005000 H'005001 H'005002 Programming unit: 128 bytes EB6 Erase unit 4 kbytes H'006000 H'006001 H'006002 Programming unit: 128 bytes H'00507F H'005FFF H'00607F H'006FFF EB7 Erase unit 4 kbytes H'007000 H'007001 H'007002 Programming unit: 128 bytes EB8 Erase unit 32 kbytes H'008000 H'008001 H'008002 Programming unit: 128 bytes EB9 Erase unit 64 kbytes H'010000 H'010001 H'010002 Programming unit: 128 bytes H'00707F H'007FFF H'00807F H'00FFFF H'01007F H'01FFFF Figure 20.6 Flash Memory Block Configuration (H8S/2266 and H8S/2265) Rev. 3.00, 08/03, page 458 of 612 20.4 Input/Output Pins The flash memory is controlled by means of the pins shown in table 20.2. Table 20.2 Pin Configuration Pin Name I/O Function RES Input Reset FWE Input Flash program/erase protection by hardware MD2 Input Sets this LSI's operating mode MD1 Input Sets this LSI's operating mode P70 Input Sets MCU operating mode in programmer mode P16 Input Sets MCU operating mode in programmer mode P14 Input Sets MCU operating mode in programmer mode TxD0 Output Serial transmit data output RxD0 Input Serial receive data input 20.5 Register Descriptions The flash memory has the following registers. * Flash memory control register 1 (FLMCR1) * Flash memory control register 2 (FLMCR2) * Erase block register 1 (EBR1) * Erase block register 2 (EBR2) * RAM emulation register (RAMER) * Flash memory power control register (FLPWCR) * Serial control register X (SCRX) The registers described above are not present in the masked ROM version. If a register described above is read in the masked ROM version, an undefined value will be returned. Rev. 3.00, 08/03, page 459 of 612 20.5.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to section 20.8, Flash Memory Programming/Erasing. Bit Bit Name Initial Value R/W Description 7 FWE R Flash Write Enable Bit Reflects the input level at the FWE pin. It is set to 1 when a low level is input to the FWE pin, and cleared to 0 when a high level is input. When this bit is cleared to 0, the flash memory changes to hardware protect mode. 6 SWE1 0 R/W Software Write Enable Bit When this bit is set to 1, flash memory programming/erasing is enabled. When this bit is cleared to 0, bits 5 to 0 in FLMCR1 register and all EBR1 and EBR2 bits cannot be set. [Setting condition] When FWE = 1. 5 ESU1 0 R/W Erase Setup Bit When this bit is set to 1, the flash memory changes to the erase setup state. When it is cleared to 0, the erase setup state is cancelled. Set this bit to 1 before setting the E1 bit in FLMCR1. [Setting condition] When FWE = 1 and SWE1 = 1 4 PSU1 0 R/W Program Setup Bit When this bit is set to 1, the flash memory changes to the program setup state. When it is cleared to 0, the program setup state is cancelled. Set this bit to 1 before setting the P1 bit in FLMCR1. [Setting condition] When FWE = 1 and SWE1 = 1 3 EV1 0 R/W Erase-Verify When this bit is set to 1, the flash memory changes to erase-verify mode. When it is cleared to 0, erase-verify mode is cancelled. [Setting condition] When FWE = 1 and SWE1 = 1 Rev. 3.00, 08/03, page 460 of 612 Bit Bit Name Initial Value R/W 2 PV1 0 R/W Description Program-Verify When this bit is set to 1, the flash memory changes to program-verify mode. When it is cleared to 0, programverify mode is cancelled. [Setting condition] When FWE = 1 and SWE1 = 1 1 E1 0 R/W Erase When this bit is set to 1, and while the SWE1 and ESU1 bits are 1, the flash memory changes to erase mode. When it is cleared to 0, erase mode is cancelled. [Setting condition] When FWE = 1, SWE1 = 1, and ESU1 = 1 0 P1 0 R/W Program When this bit is set to 1, and while the SWE1 and PSU1 bits are 1, the flash memory changes to program mode. When it is cleared to 0, program mode is cancelled. When FWE = 1, SWE1 = 1, and PSU1 = 1 20.5.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a read-only register, and should not be written to. Bit Bit Name Initial Value R/W Description 7 FLER 0 R Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-protection state. See section 20.9.3, Error Protection, for details. 6 to 0 All 0 R Reserved These bits are always read as 0. Rev. 3.00, 08/03, page 461 of 612 20.5.3 Erase Block Register 1 (EBR1) EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE1 bit in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 and EBR2 to be automatically cleared to 0. Bit Bit Name Initial Value R/W Description 7 EB7 0 R/W When this bit is set to 1, 4 kbytes of EB7 (H'007000 to H'007FFF) will be erased. 6 EB6 0 R/W When this bit is set to 1, 4 kbytes of EB6 (H'006000 to H'006FFF) will be erased. 5 EB5 0 R/W When this bit is set to 1, 4 kbytes of EB5 (H'005000 to H'005FFF) will be erased. 4 EB4 0 R/W When this bit is set to 1, 4 kbytes of EB4 (H'004000 to H'004FFF) will be erased. 3 EB3 0 R/W When this bit is set to 1, 4 kbytes of EB3 (H'003000 to H'003FFF) will be erased. 2 EB2 0 R/W When this bit is set to 1, 4 kbytes of EB2 (H'002000 to H'002FFF) will be erased. 1 EB1 0 R/W When this bit is set to 1, 4 kbytes of EB1 (H'001000 to H'001FFF) will be erased. 0 EB0 0 R/W When this bit is set to 1, 4 kbytes of EB0 (H'000000 to H'000FFF) will be erased. Rev. 3.00, 08/03, page 462 of 612 20.5.4 Erase Block Register 2 (EBR2) EBR2 specifies the flash memory erase area block. EBR2 is initialized to H'00 when the SWE1 bit in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 and EBR2 to be automatically cleared to 0. Bit Bit Name Initial Value R/W Description 7 to 4 All 0 R/W Reserved These bits are always read as 0. Only 0 should be written to these bits. 3 EB11* 0 R/W When this bit is set to 1, 64 kbytes of EB11 (H'030000 to H'03FFFF) will be erased. 2 EB10* 0 R/W When this bit is set to 1, 64 kbytes of EB10 (H'020000 to H'02FFFF) will be erased. 1 EB9 0 R/W When this bit is set to 1, 64 kbytes of EB9 (H'010000 to H'01FFFF) will be erased. 0 EB8 0 R/W When this bit is set to 1, 32 kbytes of EB8 (H'008000 to H'00FFFF) will be erased. Note: 20.5.5 * These bits are reserved bits in the H8S/2266 and H8S/2265. Only 0 should be written to these bits. RAM Emulation Register (RAMER) RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory programming. RAMER settings should be made in user mode or user program mode. To ensure correct operation of the emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified. Normal execution of an access immediately after register modification is not guaranteed. Bit Bit Name Initial Value R/W Description 7 to 5 All 0 R Reserved These bits are always read as 0. 4 0 R/W Reserved 3 RAMS 0 R/W RAM Select Only 0 should be written to this bit. Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, the flash memory is overlapped with part of RAM, and all flash memory block are program/erase-protected. Rev. 3.00, 08/03, page 463 of 612 Bit Bit Name Initial Value R/W Description 2 RAM2 0 R/W Flash Memory Area Selection 1 RAM1 0 R/W 0 RAM0 0 R/W When the RAMS bit is set to 1, one of the following flash memory areas is selected to overlap the RAM area. The areas correspond with 4-kbyte erase blocks. 000: H'000000 to H'000FFF (EB0) 001: H'001000 to H'001FFF (EB1) 010: H'002000 to H'002FFF (EB2) 011: H'003000 to H'003FFF (EB3) 100: H'004000 to H'004FFF (EB4) 101: H'005000 to H'005FFF (EB5) 110: H'006000 to H'006FFF (EB6) 111: H'007000 to H'007FFF (EB7) 20.5.6 Flash Memory Power Control Register (FLPWCR) FLPWCR enables/disables transition to power-down modes for the flash memory when this LSI enters sub-active mode. Bit Bit Name Initial Value R/W Description 7 PDWND 0 R/W Power Down Disable Enables/disables transition to power-down modes for the flash memory when this LSI enters sub-active mode. 0: Transition to power-down modes for the flash memory enabled. 1: Transition to power-down modes for the flash memory disabled. 6 to 0 All 0 R Reserved These bits are always read as 0. Rev. 3.00, 08/03, page 464 of 612 20.5.7 Serial Control Register X (SCRX) SCRX performs register access control. Bit Bit Name Initial Value R/W Description 7 0 R/W Reserved Only 0 should be written to this bit. 2 6 IICX1 0 R/W I C Transfer Select 1, 0 5 IICX0 0 R/W For details, see section 14.3.5, Serial Control Register X (SCRX). 4 IICE 0 R/W I C Master Enable 2 For details, see section 14.3.5, Serial Control Register X (SCRX). 3 FLSHE 0 R/W Flash Memory Control Register Enable Controls for the CPU accessing to the control registers (FLMCR1, FLMCR2, EBR1, EBR2) of the flash memory. When this bit is set to 1, the flash memory control registers can be read/written to. When this bit is cleared to 0, the flash memory control registers are not selected. At this time, the contents of the flash memory control registers are retained. 0: Area at H'FFFFA8 to H'FFFFAC not selected for the flash memory control registers. 1: Area at H'FFFFA8 to H'FFFFAC selected for the flash memory control registers. 2 to 0 All 0 R/W Reserved Only 0 should be written to these bits. Rev. 3.00, 08/03, page 465 of 612 20.6 On-Board Programming Modes When pins are set to on-board programming mode, program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 20.3. For a diagram of the transitions to the various flash memory modes, see figure 20.2. Table 20.3 Setting On-Board Programming Modes FWE MD2 MD1 Mode Setting 1 1 0 Boot Mode 1 1 1 User program mode 0 1 1 User mode 20.6.1 Boot Mode Table 20.4 shows the boot mode operations between reset end and branching to the programming control program. 1. When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. Prepare a programming control program in accordance with the description in section 20.8, Flash Memory Programming/Erasing. In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. Boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased. 2. SCI_0 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. 3. When the boot program is initiated, the chip measures the low-level period of asynchronous SCI communication data (H'00) transmitted continuously from the host. The chip then calculates the bit rate of transmission from the host, and adjusts the SCI_0 bit rate to match that of the host. The reset should end with the RxD pin high. The RxD and TxD pins should be pulled up on the board if necessary. After the reset is complete, it takes approximately 100 states before the chip is ready to measure the low-level period. 4. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the completion of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the chip. If reception could not be performed normally, initiate boot mode again by a reset. Depending on the host's transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between the bit rates of the host and the chip. To operate the SCI properly, set the host's transfer bit rate and system clock frequency of this LSI within the ranges listed in table 20.5. Rev. 3.00, 08/03, page 466 of 612 5. In boot mode, a part of the on-chip RAM area is used by the boot program. The area H'FFC000 to H'FFDFFF is the area to which the programming control program is transferred from the host. In the H8S/2266 and H8S/2265, the RAM in this area is enabled only in boot mode. The boot program area cannot be used until the execution state in boot mode switches to the programming control program. 6. Before branching to the programming control program, the chip terminates transfer operations by SCI_0 (by clearing the RE and TE bits in SCR to 0), however the adjusted bit rate value remains set in BRR. Therefore, the programming control program can still use it for transfer of write data or verify data with the host. The TxD pin is high. The contents of the CPU general registers are undefined immediately after branching to the programming control program. These registers must be initialized at the beginning of the programming control program, as the stack pointer (SP), in particular, is used implicitly in subroutine calls, etc. 7. Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting the FWE pin and mode pins, and executing reset release*. Boot mode is also cleared when a WDT overflow occurs. 8. All interrupts are disabled during programming or erasing of the flash memory. Note: * The input signals on the FWE and mode pins must satisfy the mode programming setup time (tMDS = 200 ns) at the reset release timing. Rev. 3.00, 08/03, page 467 of 612 Table 20.4 Boot Mode Operation Item Boot mode start Host Operation Processing Contents Communications Contents LSI Operation Processing Contents Branches to boot program at reset-start. Boot program initiation Bit rate adjustment Continuously transmits data H'00 at specified bit rate. Transmits data H'55 when data H'00 is received error-free. H'00, H'00 ...... H'00 * Measures low-level period of receive data H'00. * Calculates bit rate and sets it in BRR of SCI_0. * Transmits data H'00 to host as adjustment end indication. H'00 H'55 H'AA Transmits data H'AA to host when data H'55 is received. Receives data H'AA. Transfer of programming control program Transmits number of bytes (N) of programming control program to be transferred as 2-byte data (low-order byte following high-order byte) Transmits 1-byte of programming control program (repeated for N times) High-order byte and low-order byte Echobacks the 2-byte data received. Echoback H'XX Echoback Flash memory erase Boot program erase error Receives data H'AA. H'FF H'AA Echobacks received data to host and also transfers it to RAM (repeated for N times) Checks flash memory data, erases all flash memory blocks in case of written data existing, and transmits data H'AA to host. (If erase could not be done, transmits data H'FF to host and aborts operation.) Branches to programming control program transferred to on-chip RAM and starts execution. Table 20.5 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate System Clock Frequency Range of this LSI 19,200 bps 8 to 20.5 MHz 9,600 bps 4 to 20.5 MHz 4,800 bps 2 to 20.5 MHz Rev. 3.00, 08/03, page 468 of 612 20.6.2 Programming/Erasing in User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must prepare onboard means for controlling FWE, on-board means of supplying programming data, and branching conditions. The flash memory must contain the user program/erase control program or a program that provides the user program/erase control program from external memory. As the flash memory itself cannot be read during programming/erasing, transfer the user program/erase control program to on-chip RAM, as in boot mode. Figure 20.7 shows a sample procedure for programming/erasing in user program mode. Prepare a user program/erase control program in accordance with the description in section 20.7, Flash Memory Programming/Erasing. Reset-start No Program/erase? Yes Transfer user program/erase control program to RAM Branch to flash memory application program Branch to user program/erase control program in RAM Execute user program/erase control program (flash memory rewrite) Branch to flash memory application program Figure 20.7 Programming/Erasing Flowchart Example in User Program Mode Rev. 3.00, 08/03, page 469 of 612 20.7 Flash Memory Emulation in RAM A setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. Emulation can be performed in user mode or user program mode. Figure 20.8 shows an example of emulation of real-time flash memory programming. 1. Set RAMER to overlap part of RAM onto the area for which real-time programming is required. 2. Emulation is performed using the overlapping RAM. 3. After the program data has been confirmed, the RAMS bit is cleared, thus releasing the RAM overlap. 4. The data written in the overlapping RAM is written into the flash memory space. Start of emulation program Set RAMER Write tuning data to overlap RAM Execute application program No Tuning OK? Yes Clear RAMER Write to flash memory emulation block End of emulation program Figure 20.8 Flowchart for Flash Memory Emulation in RAM Rev. 3.00, 08/03, page 470 of 612 An example in which flash memory block area EB0 is overlapped is shown in figure 20.9. 1. The RAM area to be overlapped is fixed at a 4-kbyte area in the range H'FFD000 to H'FFDFFF. In the H8S/2265, the RAM in this area is enabled only in RAM emulation mode. 2. The flash memory area to be overlapped is selected by RAMER from a 4-kbyte area of the EB0 to EB7 blocks. 3. The overlapped RAM area can be accessed from both the flash memory addresses and RAM addresses. 4. When the RAMS bit in RAMER is set to 1, program/erase protection is enabled for all flash memory blocks (emulation protection). In this state, setting the P1 or E1 bit in FLMCR1 to 1 does not cause a transition to program mode or erase mode. 5. A RAM area cannot be erased by execution of software in accordance with the erase algorithm. 6. Block area EB0 contains the vector table. When performing RAM emulation, the vector table is needed in the overlap RAM. H'000000 Flash memory (EB0) Flash memory (EB0) (EB1) On-chip RAM (Shadow of H'FFD000 to H'FFDFFF) (EB2) Flash memory (EB2) (EB3) (EB3) On-chip RAM (4 kbytes) On-chip RAM (4 kbytes) Normal memory map RAM overlap memory map H'001000 H'002000 H'003000 H'FFD000 H'FFDFFF Figure 20.9 Example of RAM Overlap Operation Rev. 3.00, 08/03, page 471 of 612 20.8 Flash Memory Programming/Erasing A software method using the CPU is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify mode. The programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing. Flash memory programming and erasing should be performed in accordance with the descriptions in section 20.8.1, Program/Program-Verify and section 20.8.2, Erase/Erase-Verify, respectively. 20.8.1 Program/Program-Verify When writing data or programs to the flash memory, the program/program-verify flowchart shown in figure 20.10 should be followed. Performing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting the chip to voltage stress or sacrificing program data reliability. 1. Programming must be done to an empty address. Do not reprogram an address to which programming has already been performed. 2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be performed even if writing fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. 3. Prepare the following data storage areas in RAM: A 128-byte programming data area, a 128byte reprogramming data area, and a 128-byte additional-programming data area. Perform reprogramming data computation and additional programming data computation according to figure 20.10. 4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data area to the flash memory. The program address and 128-byte data are latched in the flash memory. The lower 8 bits of the start address in the flash memory destination area must be H'00 or H'80. 5. The time during which the P1 bit is set to 1 is the programming time. Figure 20.10 shows the allowable programming times. 6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc. Set a value greater than (tspsu + tsp200 + tcp + tcpsu) s as the WDT overflow period. 7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 2 bits are b'00. Verify data can be read in words from the address to which a dummy write was performed. 8. The maximum number of repetitions of the program/program-verify sequence of the same bit is (N). Rev. 3.00, 08/03, page 472 of 612 Write pulse application subroutine Start of programming Sub-Routine Write Pulse START Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. Set SWE1 bit in FLMCR1 WDT enable Wait (tsswe) 1s Set PSU1 bit in FLMCR1 Store 128-byte program data in program data area and reprogram data area Wait (tspsu) 50s Set P1 bit in FLMCR1 Start of programming Wait tsp10 or 30 or 200 *5 *4 n= 1 m= 0 Clear P1 bit in FLMCR1 Write 128-byte data in RAM reprogram data area consecutively to flash memory End of programming *1 Sub-Routine-Call Wait (tcp) 5s Apply Write pulse tsp30 or 200 Clear PSU1 bit in FLMCR1 Set PV1 bit in FLMCR1 See Note 6 for pulse width Wait (tspv) 4s Wait (tcpsu) 5s H'FF dummy write to verify address Disable WDT nn+1 tspvr = Wait 2s End Sub Read verify data *2 Write data = verify data? No Increment address Note 6: Write Pulse Width Number of Writes n Write Time (tsp30/tsp200) s 30 * 30 * 30 * 30 * 30 * 30 * 1 2 3 4 5 6 7 8 9 10 11 12 13 No 6n? Yes Additional-programming data computation Transfer additional-programming data to additional-programming data area 200 200 200 200 200 200 200 *4 *3 Reprogram data computation Transfer reprogram data to reprogram data area No 998 999 1000 m=1 Yes *4 128-byte data verification completed? Yes Clear PV1 bit in FLMCR1 200 200 200 Reprogram Wait (tcpv) s Note: * Use a 10 s write pulse for additional programming. No 6 n? Yes Successively write 128-byte data from additional1 programming data area in RAM to flash memory * RAM Program data storage area (128 bytes) Sub-Routine-Call Apply Write Pulse (Additional programming) Reprogram data storage area (128 bytes) No m= 0 ? Additional-programming data storage area (128 bytes) No n 1000? Yes Clear SWE1 bit in FLMCR1 Yes Clear SWE1 bit in FLMCR1 Wait (tcswe) 100s Wait (tcswe) 100s End of programming Programming failure Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. 2. Verify data is read in 16-bit (word) units. 3. Reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program data area and the verify data). Bits for which the reprogram data is 0 are programmed in the next reprogramming loop. Therefore, even bits for which programming has been completed will be subjected to programming once again if the result of the subsequent verify operation is NG. 4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM. The contents of the reprogram data area and additional data area are modified as programming proceeds. 5. A write pulse of 30 s or 200 s is applied according to the progress of the programming operation. See Note 6 for details of the pulse widths. When writing of additional-programming data is executed, a 10 s write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied. Additional-Programming Data Computation Table Reprogram Data Computation Table Original Data Verify Data Reprogram Data (D) 0 (V) 0 (X) 1 0 1 0 1 0 1 1 1 1 Comments Reprogram Data (X') Verify Data Additional(V) Programming Data (Y) Programming completed 0 0 0 Programming incomplete; reprogram 0 1 1 1 0 1 1 1 1 Still in erased state; no action Comments Additional programming to be executed Additional programming not to be executed Additional programming not to be executed Additional programming not to be executed Figure 20.10 Program/Program-Verify Flowchart Rev. 3.00, 08/03, page 473 of 612 20.8.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 20.11 should be followed. 1. Prewriting (setting erase block data to all 0) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block register 1 and 2 (EBR1 and EBR2). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E1 bit is set to 1 is the flash memory erase time. 4. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc. Set a value greater than (tsesu + tse + tce + tcesu) ms as the WDT overflow period. 5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two bits are b'00. Verify data can be read in words from the address to which a dummy write was performed. 6. If the read data is not erased successfully, set erase mode again, and repeat the erase/eraseverify sequence as before. The maximum number of repetitions of the erase/erase-verify sequence is (N). 20.8.3 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including the NMI interrupt, are disabled while flash memory is being programmed or erased, or while the boot program is executing, for the following three reasons: 1. Interrupt during programming/erasing may cause a violation of the programming or erasing algorithm, with the result that normal operation cannot be assured. 2. If interrupt exception handling starts before the vector address is written or during programming/erasing, a correct vector cannot be fetched and the CPU malfunctions. 3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be carried out. Rev. 3.00, 08/03, page 474 of 612 Erase start *1 Erasing should be done to a block SWE1 bit in FLMCR1 1 tsswe: Wait 1 s n=1 *3 Set EBR1 (2) Enable WDT ESU1 bit in FLMCR1 1 tsesu: Wait 100 s E1 bit in FLMCR1 1 start erasing tse: Wait 10 ms E1 bit in FLMCR1 0 stop erasing tce: Wait 10 s ESU1 bit in FLMCR1 0 tcesu: Wait 10 s Disable WDT EV1 bit in FLMCR1 1 tsev: Wait 20 s Set block start address as verify address H'FF dummy write to verify address tsevr: Wait 2 s nn+1 Read verify data Verify data = all 1? Increment address *2 No Yes No Last address of block? Yes EV1 bit in FLMCR1 0 EV1 bit in FLMCR1 0 tcev: Wait 4 s tcev: Wait 4 s All erase block erased? n 100? *4 No No Yes Yes SWE1 bit in FLMCR1 0 SWE1 bit in FLMCR1 0 tcswe: Wait 100 s tcswe: Wait 100 s End of erasing Erase failure Notes: 1. Pre-writing (all erase block data are cleared to 0) is not necessary. 2. Verify data is read out in 16 bit size (word access). 3. Erasing block register (EBR) can be set about 1 bit at a time. Do not specify 2 bits or more. 4. Erasing is performed block by block. when multiple blocks must be erased, erase each lock one by one. Figure 20.11 Erase/Erase-Verify Flowchart Rev. 3.00, 08/03, page 475 of 612 20.9 Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 20.9.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset or standby mode. Flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), erase block register 1 (EBR1), and erase block register 2 (EBR2) are initialized. In a reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the RES pulse width specified in the AC Characteristics section. 20.9.2 Software Protection Software protection can be implemented against programming/erasing of all flash memory blocks by clearing the SWE1 bit in FLMCR1. When software protection is in effect, setting the P1 or E1 bit in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase block register 1 and 2 (EBR1 and EBR2), erase protection can be set for individual blocks. When EBR1 and EBR2 are set to H'00, erase protection is set for all blocks. By setting bit RAMS in RAMER, programming/erase protection is set for all blocks. 20.9.3 Error Protection In error protection, an error is detected when CPU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. When the following errors are detected during programming/erasing of flash memory, the FLER bit in FLMCR2 is set to 1, and the error protection state is entered. * When the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) * Immediately after exception handling (excluding a reset) during programming/erasing * When a SLEEP instruction is executed during programming/erasing * When the CPU loses the bus during programming/erasing The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, however program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P1 or E1 bit. However, PV1 and EV1 bit setting is enabled, and a Rev. 3.00, 08/03, page 476 of 612 transition can be made to verify mode. Error protection can be cleared only by a reset or in hardware standby. 20.10 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI input, are disabled when flash memory is being programmed or erased (when the P1 or E1 bit is set in FLMCR1), and while the boot program is executing in boot mode*1, to give priority to the program or erase operation. There are three reasons for this: 1. Interrupt during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. 2. In the interrupt exception handling sequence during programming or erasing, the vector would not be read correctly*2, possibly resulting in CPU runaway. 3. If an interrupt occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. Notes: 1. Interrupt requests must be disabled inside and outside the CPU until the programming control program has completed programming. 2. The vector may not be read correctly in this case for the following two reasons: * If flash memory is read while being programmed or erased (while the P1 or E1 bit is set in FLMCR1), correct read data will not be obtained (undetermined values will be returned). * If the interrupt entry in the vector table has not been programmed yet, interrupt exception handling will not be executed correctly. 20.11 Programmer Mode In programmer mode, a PROM programmer can be used to perform programming/erasing via a socket adapter, just as for a discrete flash memory. Use a PROM programmer which supports the Renesas 256-kbyte flash memory on-chip microcomputer device type (FZTAT256V3A). The socket adapter pin correspondence diagram is shown in figure 20.12. Rev. 3.00, 08/03, page 477 of 612 This LSI Pin No. Socket Adapter (Conversion to 40-Pin Arrangement) HN27C4096HG (40-Pin) Pin No. Pin Name A0 21 A0 A1 22 A1 15 A2 23 A2 13 A3 24 A3 11 A4 25 A4 10 A5 26 A5 9 A6 27 A6 8 A7 28 A7 7 A8 29 A8 6 A9 31 A9 5 A10 32 A10 4 A11 33 A11 3 A12 34 A12 2 A13 35 A13 1 A14 36 A14 100 A15 37 A15 99 A16 38 A16 98 A17 39 A17 97 A18 10 A18 25 D0 19 I/O0 24 D1 18 I/O1 23 D2 17 I/O2 22 D3 16 I/O3 21 D4 15 I/O4 20 D5 14 I/O5 19 D6 13 I/O6 18 D7 12 I/O7 26 CE 2 CE 28 OE 20 OE 27 WE 3 WE 66 FWE 4 FWE 1, 40 VCC 12, 30, 53, 54, 58, VCC 11, 30 VSS FP-100B,TFP-100B, TFP-100G Pin Name 17 16 60, 61, 62, 75 14, 29, 38, 40,42, VSS 5, 6, 7 NC 8 A20 9 A19 56, 64, 67 59 RES 63 XTAL 65 EXTAL Other than the above N.C.(OPEN) Power-on reset circuit Oscillator circuit Legend FWE: I/O0 to 7: A20 to 0: OE: CE: WE: Flash write enable Data input/output Address input Output enable Chip enable Write enable Note: This drawing indicates pin correspondences and does not show the entire circuitry of the socket adapter. Figure 20.12 Socket Adapter Pin Correspondence Diagram Rev. 3.00, 08/03, page 478 of 612 20.12 Power-Down States for Flash Memory In user mode, the flash memory will operate in either of the following states: * Normal operating mode The flash memory can be read and written to at high speed. * Power-down state The flash memory can be read when part of the power circuit is halted and the LSI operates by subclocks. * Standby mode All flash memory circuits are halted. Table 20.6 shows the correspondence between the operating modes of the H8S/2268 Group and the flash memory. When the flash memory returns to its normal operating state from standby mode, a period to stabilize the power supply circuits that were stopped is needed. When the flash memory returns to its normal operating state, bits STS2 to STS0 in SBYCR must be set to provide a wait time of at least 100 s, even when the external clock is being used. Table 20.6 Flash Memory Operating States LSI Operating State Flash Memory Operating State Active mode Normal operating mode Sleep mode Normal operating mode Watch mode Standby mode Standby mode Sub-active mode PDWND = 0: Power-down mode (read only) Sub-sleep mode PDWND = 1: Normal operating mode (read only) 20.13 Flash Memory Programming and Erasing Precautions Precautions concerning the use of on-board programming mode, the RAM emulation function, and programmer mode are summarized below. Use the specified voltages and timing for programming and erasing: Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports the Renesas 256-kbyte flash memory on-chip microcomputer device type (FZTAT256V3A). Do not select the HN27C4096 setting for the PROM programmer, and only use the specified socket adapter. Failure to observe these points may result in damage to the device. Rev. 3.00, 08/03, page 479 of 612 Powering on and off (see figures 20.13 to 20.15): Do not apply a high level to the FWE pin until VCC has stabilized. Also, drive the FWE pin low before turning off VCC. When applying or disconnecting VCC power, fix the FWE pin low and place the flash memory in the hardware protection state. The power-on and power-off timing requirements should also be satisfied in the event of a power failure and subsequent recovery. FWE application/disconnection (see figures 20.13 to 20.15): FWE application should be carried out when MCU operation is in a stable condition. If MCU operation is not stable, fix the FWE pin low and set the protection state. The following points must be observed concerning FWE application and disconnection to prevent unintentional programming or erasing of flash memory: * Apply FWE when the VCC voltage has stabilized within its rated voltage range. * In boot mode, apply and disconnect FWE during a reset. * In user program mode, FWE can be switched between high and low level regardless of the reset state. FWE input can also be switched during execution of a program in flash memory. * Do not apply FWE if program runaway has occurred. * Disconnect FWE only when the SWE1, ESU1, PSU1, EV1, PV1, P1, and E1 bits in FLMCR1 are cleared. Make sure that the SWE1, ESU1, PSU1, EV1, PV1, P1, and E1 bits are not set by mistake when applying or disconnecting FWE. Do not apply a constant high level to the FWE pin: Apply a high level to the FWE pin only when programming or erasing flash memory. A system configuration in which a high level is constantly applied to the FWE pin should be avoided. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. Use the recommended algorithm when programming and erasing flash memory: The recommended algorithm enables programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program data reliability. When setting the P1 or E1 bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against program runaway, etc. Do not set or clear the SWE1 bit during execution of a program in flash memory: Wait for at least 100 s after clearing the SWE1 bit before executing a program or reading data in flash memory. When the SWE1 bit is set, data in flash memory can be rewritten. Access flash memory only for verify operations (verification during programming/erasing). Also, do not clear the SWE1 bit Rev. 3.00, 08/03, page 480 of 612 during programming, erasing, or verifying. Similarly, when using the RAM emulation function while a high level is being input to the FWE pin, the SWE1 bit must be cleared before executing a program or reading data in flash memory. However, the RAM area overlapping flash memory space can be read and written to regardless of whether the SWE1 bit is set or cleared. Do not use interrupts while flash memory is being programmed or erased: All interrupt requests, including NMI, should be disabled during FWE application to give priority to program/erase operations. Do not perform additional programming. Erase the memory before reprogramming: In onboard programming, perform only one programming operation on a 128-byte programming unit block. In programmer mode, too, perform only one programming operation on a 128-byte programming unit block. Programming should be carried out with the entire programming unit block erased. Before programming, check that the chip is correctly mounted in the PROM programmer: Overcurrent damage to the device can result if the index marks on the PROM programmer socket, socket adapter, and chip are not correctly aligned. Do not touch the socket adapter or chip during programming: Touching either of these can cause contact faults and write errors. Reset the flash memory before turning on the power: To reset the flash memory during oscillation stabilization period, the reset signal must be input for at least 100 s. Apply the reset signal while SWE1 is low to reset the flash memory during its operation: The reset signal is applied at least 100 s after the SWE1 bit has been cleared. Rev. 3.00, 08/03, page 481 of 612 Programming/ erasing t Wait time: sswe possible Wait time: 100s min 0s tOSC1 VCC tMDS*3 FWE min 0s MD2, MD1*1 tMDS*3 RES SWE1 set SWE1 cleared SWE1bit Period during which flash memory access is prohibited (tsswe: Wait time after setting SWE1 bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1. Except when switching modes, the level of the mode pins (MD2, MD1) must be fixed until power-off by pulling the pins up or down. 2. See section 25.2.8, Flash Memory Characteristics. 3. Mode programming setup time tMDS (min) = 200ns. Figure 20.13 Power-On/Off Timing (Boot Mode) Rev. 3.00, 08/03, page 482 of 612 Programming/ erasing Wait time: tsswe possible Wait time: 100s tOSC1 min 0s VCC FWE MD2,MD1*1 tMDS*3 RES SWE1 set SWE1 cleared SWE1 bit Period during which flash memory access is prohibited (tsswe: Wait time after setting SWE1 bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1. Except when switching modes, the level of the mode pins (MD2, MD1) must be fixed until power-off by pulling the pins up or down. 2. See section 25.2.8, Flash Memory Characteristics. 3. Mode programming setup time tMDS (min) = 200ns. Figure 20.14 Power-On/Off Timing (User Program Mode) Rev. 3.00, 08/03, page 483 of 612 *4 Programming/ erasing possible Wait time: tsswe Wait time: tsswe Programming/ erasing possible Wait time: tsswe Programming/ erasing possible Programming/ erasing possible Wait time: tsswe *4 *4 tOSC1 VCC min 0s FWE tMDS 2 tMDS* MD2,MD1 tMDS tRESW RES SWE1 cleared SWE1 set SWE1 bit Mode 1 change* Boot mode Mode 1 User * mode change User program mode User mode User program mode Period during which flash memory access is prohibited (tsswe: Wait time after setting SWE1 bit)*3 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1. When entering boot mode or making a transition from boot mode to another mode, mode switching must be carried out by means of RES input. 2. When making a transition from boot mode to another mode, a mode programming setup time tMDS (min) of 200 ns is necessary with respect to RES clearance timing. 3. See section 25.2.8, Flash Memory Characteristics. 4. Wait time: 100s. Figure 20.15 Mode Transition Timing (Example: Boot Mode User Mode User Program Mode) Rev. 3.00, 08/03, page 484 of 612 20.14 Note on Switching from F-ZTAT Version to Masked ROM Version The masked ROM version does not have the internal registers for flash memory control that are provided in the F-ZTAT version. Table 20.7 lists the registers that are present in the F-ZTAT version but not in the masked ROM version. If a register listed in table 20.7 is read in the masked ROM version, an undefined value will be returned. Therefore, if application software developed on the F-ZTAT version is switched to a masked ROM version product, it must be modified to ensure that the registers in table 20.7 have no effect. Table 20.7 Registers Present in F-ZTAT Version but Absent in Masked ROM Version Register Abbreviation Address Flash memory control register 1 FLMCR1 H'FFA8 Flash memory control register 2 FLMCR2 H'FFA9 Erase block register 1 EBR1 H'FFAA Erase block register 2 EBR2 H'FFAB RAM emulation register RAMER H'FEDB Flash memory power control register FLPWCR H'FFAC Serial control register X (Only bit 3) SCRX H'FDB4 Rev. 3.00, 08/03, page 485 of 612 Rev. 3.00, 08/03, page 486 of 612 Section 21 Clock Pulse Generator This LSI has an on-chip clock pulse generator that generates the system clock (), the bus master clock, and internal clocks. The clock pulse generator consists of an oscillator, duty adjustment circuit, clock selection circuit, medium-speed clock divider, bus master clock selection circuit, subclock oscillator, and wave formation circuit. A block diagram of the clock pulse generator is shown in figure 21.1. LPWRCR SCKCR RFCUT EXTAL XTAL System clock oscillator SCK2 to SCK0 Duty adjustment circuit Mediumspeed clock divider Clock selection circuit SUB OSC1 Subclock oscillator OSC2 Waveform Generation Circuit /2 to /32 Bus master clock selection circuit Internal clock Internal clock to peripheral modules Bus master clock to CPU and DTC WDT_1, TMR4, LCD count clock Legend: LPWRCR: Low-power control register SCKCR: System clock control register Figure 21.1 Block Diagram of Clock Pulse Generator Frequency changes are performed by software by settings in the low-power control register (LPWRCR) and system clock control register (SCKCR). CPG0501B_000020020700 Rev. 3.00, 08/03, page 487 of 612 21.1 Register Descriptions The on-chip clock pulse generator has the following registers. * System clock control register (SCKCR) * Low-power control register (LPWRCR) 21.1.1 System Clock Control Register (SCKCR) SCKCR performs medium-speed mode control. Bit Bit Name Initial Value R/W Description 7, 6 All 0 R/W Reserved These are readable/writable bits, but the write value should always be 0. 5, 4 All 0 Reserved These bits are always read as 0.Writing is invalid. 3 0 R/W Reserved This is a readable/writable bit, but the write value should always be 0. 2 SCK2 0 R/W System Clock Select 2 to 0 1 SCK1 0 R/W These bits select the bus master clock. 0 SCK0 0 R/W 000: High-speed mode 001: Medium-speed clock is /2 010: Medium-speed clock is /4 011: Medium-speed clock is /8 100: Medium-speed clock is /16 101: Medium-speed clock is /32 11X: Setting prohibited [Legend] X: Don't care Rev. 3.00, 08/03, page 488 of 612 21.1.2 Low-Power Control Register (LPWRCR) LPWRCR performs down-mode control, selects sampling frequency for eliminating noise, performs subclock generation control, and specifies multiplication factor. Bit Bit Name Initial Value R/W Description 7 DTON 0 R/W Direct Transition ON Flag 0: When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts to sleep mode, software standby mode, or watch mode. When the SLEEP instruction is executed in sub-active mode, operation shifts to sub-sleep mode or watch mode. 1: When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts directly to sub-active mode, or shifts to sleep mode or software standby mode. When the SLEEP instruction is executed in sub-active mode, operation shifts directly to high-speed mode, or shifts to sub-sleep mode. 6 LSON 0 R/W Low Speed ON Fag 0: When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts to sleep mode, software standby mode, or watch mode*. When the SLEEP instruction is executed in sub-active mode, operation shifts to watch mode* or shifts directly to high-speed mode. Operation shifts to high-speed mode when watch mode is cancelled. 1: When the SLEEP instruction is executed in high-speed mode, operation shifts to watch mode or sub-active mode. When the SLEEP instruction is executed in sub-active mode, operation shifts to sub-sleep mode or watch mode. Operation shifts to sub-active mode when watch mode is cancelled. Rev. 3.00, 08/03, page 489 of 612 Bit Bit Name Initial Value R/W 5 NESEL 0 R/W Description Noise Elimination Sampling Frequency Select This bit selects the sampling frequency of the subclock (SUB) generated by the subclock oscillator is sampled by the clock () generated by the system clock oscillator Set 0 when is 5 MHz or higher. Set 1 when is 2.1 MHz or lower. Any value can be set when is 2.1 to 5 MHz. 0: Sampling using 1/32 x 1: Sampling using 1/4 x 4 SUBSTP 0 R/W Subclock Enable This bit enables/disables subclock generation. This bit should be set to 1 when subclock is not used. 0: Enables subclock generation. 1: Disables subclock generation. 3 RFCUT 0 R/W Oscillation Circuit Feedback Resistance Control Bit Selects whether or not built-in feedback resistance and duty adjustment circuit of the system clock generator are used when an external clock is input. Do not access when the crystal resonator is used. After setting this bit in the external clock input state, enter software standby mode, watch mode, or subactive mode. When software standby mode, watch mode, or subactive mode is entered, switch whether or not built-in feedback resistance and duty adjustment circuit are used. 0: Built-in feedback resistance and duty adjustment circuit of the system clock generator used. 1: Built-in feedback resistance and duty adjustment circuit of the system clock generator not used. 2 0 R/W Reserved This is a readable/writable bit, but the write value should always be 0. Rev. 3.00, 08/03, page 490 of 612 Bit Bit Name Initial Value R/W Description 1 STC1 0 R/W Multiplication factor setting 0 STC0 0 R/W Specifies multiplication factor of the PLL circuit built in the evaluation chip. The specified multiplication factor becomes valid software standby mode, watch mode, or subactive mode is entered. These bits should be set to 11 in this LSI. Since the value becomes STC1 = STC0 = 0 after a reset, set STC1 = STC0 = 1. 00: x 1 01: x 2 (setting prohibited) 10: x 4 (setting prohibited) 11: PLL is bypass Note: 21.2 * When watch mode or subactive mode is entered, set high-speed mode. System Clock Oscillator System clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 21.2.1 Connecting a Crystal Resonator A crystal resonator can be connected as shown in the example in figure 21.2. Select the damping resistance Rd according to table 21.1. An AT-cut parallel-resonance crystal should be used. CL1 EXTAL XTAL CL2 Rd Note: CL1 = CL2 = 10 to 22pF CL1 and CL2 are reference values including the floating capacitance of the board. Figure 21.2 Connection of Crystal Resonator (Example) Table 21.1 Damping Resistance Value Frequency (MHz) 2 4 6 8 10 12 16 20 Rd () 1k 500 300 200 100 0 0 0 Rev. 3.00, 08/03, page 491 of 612 Figure 21.3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown in table 21.2. CL L XTAL Rs C0 EXTAL AT-cut parallel-resonance type Figure 21.3 Crystal Resonator Equivalent Circuit Table 21.2 Crystal Resonator Characteristics Frequency (MHz) 2 4 6 8 10 12 16 20 RS max () 500 120 100 80 60 60 50 40 C0 max (pF) 7 7 7 7 7 7 7 7 21.2.2 External Clock Input An external clock signal can be input as shown in the examples in figure 21.4. If the XTAL pin is left open, ensure that stray capacitance does not exceed 10 pF. When complementary clock is input to the XTAL pin, the external clock input should be fixed high in standby mode, subactive mode, subsleep mode, or watch mode. External clock input EXTAL XTAL Open (a) XTAL pin left open EXTAL External clock input XTAL (b) Complementary clock input at XTAL pin Figure 21.4 External Clock Input (Examples) Table 21.3 shows the input conditions for the external clock. Table 21.4 shows the input conditions for the external clock when duty adjustment circuit is not used. Rev. 3.00, 08/03, page 492 of 612 Table 21.3 External Clock Input Conditions VCC = 2.7 V to 5.5 V V CC = 4.0 V to 5.5 V Min Max Min Max Unit Test Conditions External clock input low tEXL pulse width 30 20 ns Figure 21.5 External clock input high pulse width tEXH 30 20 ns External clock rise time tEXr 7 5 ns External clock fall time 7 5 ns Item Symbol tEXf Table 21.4 External Clock Input Conditions (Duty Adjustment Circuit not Used) VCC = 2.7 V to 5.5 V VCC = 4.0 V to 5.5 V Min Max Min Max Unit Test Conditions External clock input low tEXL pulse width 37 25 ns Figure 21.5 External clock input high pulse width tEXH 37 25 ns External clock rise time tEXr 7 5 ns External clock fall time 7 5 ns Item Symbol tEXf Note: When duty adjustment circuit is not used, maximum operating frequency is lowered according to the input waveform. (Example: When tEXL = tEXH = 50 ns, tEXr = tEXf = 10 ns, clock cycle time = 120 ns, and maximum operating frequency = 8.3 MHz) tEXH tEXL VCC x 0.5 EXTAL tEXr tEXf Figure 21.5 External Clock Input Timing Rev. 3.00, 08/03, page 493 of 612 21.2.3 Notes on Switching External Clock When two or more external clocks (e.g.: 10 MHz and 2 MHz) are used as the system clock, input clock should be switched in software standby mode. An example of external clock switching circuit is shown in figure 21.6. An example of external clock switching timing is shown in figure 21.7. This LSI External clock switch request Control circuit External interrupt signal Port output External interrupt External clock 1 External clock 2 Selector External clock switch signal EXTAL Figure 21.6 External Clock Switching Circuit (Examples) External clock 1 External clock 2 Operation Clock switching request SLEEP instruction execution Interrupt exception handling (5) (1) Port output (2) External clock switching circuit (3) EXTAL Internal clock o standby mode External interrupt 200ns or more Active (external clock2) (4) Software standby mode Active (external clock1) (1) Port output (clock switching) (2) Transition to software standby mode (3) External clock switchover (4) External interrupt generation (An interrupt should be input 200 ns or more after transition to software standby mode.) (5) Interrupt exception handling Figure 21.7 External Clock Switching Timing (Examples) Rev. 3.00, 08/03, page 494 of 612 21.3 Duty Adjustment Circuit The duty adjustment circuit is valid when oscillation frequency is more than 5 MHz. The duty adjustment circuit adjusts clock output fr/m the system clock oscillator to generate the system clock (). 21.4 Medium-Speed Clock Divider The medium-speed clock divider divides the system clock to generate /2, /4, /8, /16, and /32. 21.5 Bus Master Clock Selection Circuit The bus master clock selection circuit selects the clock supplied to the bus master by setting the bits SCK2 to SCK0 in SCKCR. The bus master clock can be selected from system clock (), or medium-speed clocks (/2, /4, /8, /16, /32). 21.6 Subclock Oscillator 21.6.1 Connecting 32.768-kHz Crystal Resonator To supply a clock to the subclock divider, connect a 32.768-kHz crystal resonator, as shown in Figure 21.8. Figure 21.9 shows the equivalence circuit for a 32.768kHz oscillator. C1 OSC1 C2 OSC2 C1 = C2 = 15pF (typ) Note: C1 and C2 are reference values including the floating capacitance of the boad. Figure 21.8 Example Connection of 32.768-kHz Crystal Resonator Rev. 3.00, 08/03, page 495 of 612 Ls Cs Rs OSC1 OSC2 Co Co = 1.5pF (typ.) Rs = 14k (typ.) fw = 32.768kHz Type name = C001R (SEIKO EPSON) Figure 21.9 Equivalence Circuit for 32.768-kHz Crystal Resonator 21.6.2 Handling Pins when Subclock not Required If no subclock is required, connect the OSC1 pin to Vss and leave OSC2 open, as shown in figure 21.10. Set the SUBSTP bit of LPWRCR to 1. OSC1 OSC2 Open Note: Set the SUBSTP bit in LPWRCR to 1. Figure 21.10 Pin Handling When Subclock Not Required 21.7 Subclock Waveform Generation Circuit To eliminate noise from the subclock input to OSCI, the subclock is sampled using the dividing clock . The sampling frequency is set using the NESEL bit of LPWRCR. For details, see Section 21.1.2, Low Power Control Register (LPWRCR). No sampling is performed in sub-active mode, sub-sleep mode, or watch mode. Rev. 3.00, 08/03, page 496 of 612 21.8 Usage Notes 21.8.1 Note on Crystal Resonator As various characteristics related to the crystal resonator are closely linked to the user's board design, thorough evaluation is necessary on the user's part, using the resonator connection examples shown in this section as a guide. As the resonator circuit ratings will depend on the floating capacitance of the resonator and the mounting circuit, the ratings should be determined in consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the maximum rating is not applied to the oscillator pin. 21.8.2 Note on Board Design When designing the board, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Make wires as short as possible. Other signal lines should be routed away from the oscillator circuit, as shown in figure 21.11. This is to prevent induction from interfering with correct oscillation. Signal A Signal B Avoid C2 This LSI XTAL, OSC2 EXTAL, OSC1 C1 Figure 21.11 Note on Board Design of Oscillator Circuit 21.8.3 Note on Using a Crystal Resonator When a microcomputer runs, internal power supply potential will fluctuate synchronized with the system clock. In addition, according to the individual characteristics of crystal resonator, there is a case where the amplitude of the oscillation waveform will not be grown sufficiently immediately after oscillation stabilization period, thus the oscillation waveform is easily affected by the fluctuation of the power supply voltage. In this condition, oscillation waveform will be unstable, resulting in the system clock instability and malfunction of the microcomputer. If a malfunction occurs, the setting of the standby timer select 2 to 0 (STS2 to STS0) bits in the standby control register (SBYCR) must be set so as for the standby time to be longer. For example, if a malfunction occurs when the standby time is set to 8192 states, the operation should be confirmed by setting the standby time to 16384 states or longer. Rev. 3.00, 08/03, page 497 of 612 In addition, if a malfunction similar to at state transition occurs at reset, the RES pin hold time must be set longer. Rev. 3.00, 08/03, page 498 of 612 Section 22 Power-Down Modes In addition to the normal program execution state, the H8S/2268 Group and the H8S/2264 Group have nine power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip peripheral modules, and so on. The H8S/2268 Group and the H8S/2264 Group operating modes are as follows: 1. High-speed mode 2. Medium-speed mode 3. Subactive mode 4. Sleep mode 5. Subsleep mode 6. Watch mode 7. Module stop mode 8. Software standby mode 9. Hardware standby mode 2. to 9. are low power dissipation states. Sleep mode and sub-sleep mode are CPU states, mediumspeed mode is a CPU and bus master state, sub-active mode is a CPU and bus master and internal peripheral function state, and module stop mode is an internal peripheral function (including bus masters other than the CPU) state. Some of these states can be combined. After a reset, the LSI is in high-speed mode with modules other than the DTC in module stop mode. Table 22.1 shows the internal state of the LSI in the respective modes. Table 22.2 shows the conditions for shifting between the low power dissipation modes. Figure 22.1 is a mode transition diagram. Table 22.1 LSI Internal States in Each Mode Function HighSpeed System clock pulse Functiongenerator ing Subclock pulse generator MediumSpeed Sleep Module Stop Functioning Functioning Functioning Function- Function- Function- Functioning/halted ing/halted ing/halted ing/halted Watch Subactive Software Subsleep Standby Hardware Standby Halted Halted Halted Halted Halted Functioning Functioning Functioning Function- Halted ing/halted Rev. 3.00, 08/03, page 499 of 612 HighSpeed Function CPU MediumSpeed Sleep Instructions Function- Medium- Halted ing speed operation Module Stop Watch Software Hardware Subsleep Standby Standby Halted Halted Retained Retained Undefined RAM Function- Function- Function- Function- Retained Function- Retained ing ing ing (DTC) ing ing *2 Retained Retained I/O Function- Function- Function- Function- Retained Function- Function- Halted ing ing ing ing ing ing External NMI interrupts IRQn WKPn Function- Function- Function- Function- Function- Function- Function- Function- Halted ing ing ing ing ing ing ing ing 2 Function- Medium- Function- Function- Halted Subclock Halted Halted Halted ing speed ing ing/halted (retained) operation (retained) (retained) (reset) operation (retained) DTC*2 Function- Medium- Function- Function- Halted Halted Halted Halted Halted ing speed ing ing/halted (retained) (retained) (retained) (retained) (reset) operation (retained) TMR_4*2 Halted Function- Function- Function- Function- Subclock Subclock Subclock Halted ing ing ing ing/halted operation operation operation (retained) (reset) 1 1 1 * * (retained) * Registers Peripheral PBC* functions LCD Notes: Retained Function- Halted ing Subactive Subclock Halted operation Retained High impedance WDT_1 Function- Function- Function- Function- Subclock Subclock Subclock Halted Halted ing ing ing ing operation operation operation (retained) (reset) 1 1 1 * * * WDT_0 Function- Function- Function- Function- Halted Subclock Subclock Halted Halted ing ing ing ing (retained) operation operation (retained) (reset) TMR_0 TMR_1 TMR_2*2 TMR_3*2 Function- Function- Function- Function- Halted Subclock Subclock Halted Halted ing ing ing ing/halted (retained) operation operation (retained) (reset) (retained) TPU SCI IIC DTMF*2 D/A*2 Function- Function- Function- Function- Halted Halted Halted Halted Halted ing ing ing ing/halted (retained) (retained) (retained) (retained) (reset) (retained) A/D Function- Function- Function- Function- Halted ing ing ing ing/halted (reset) (reset) Halted (reset) Halted (reset) Halted (reset) Halted (reset) "Halted (retained)" means that internal register values are retained. The internal state is "operation suspended." "Halted (reset)" means that internal register values and internal states are initialized. In module stop mode, only modules for which a stop setting has been made are halted (reset or retained). 2 1. When the TMR_4* , WDT_1, or LCD is operated in watch, subactive, or subsleep mode, use the subclock. 2. Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 500 of 612 Program-halted state STBY pin = Low Reset state STBY pin = High RES pin = Low Program execution state Hardware standby mode RES pin = High SSBY= 0, LSON= 0 SLEEP instruction High-speed mode (main clock) Sleep mode (main clock) Any interrupt *3 SCK2 to SCK0= 0 SCK2 to SCK0 0 Medium-speed mode (main clock) SLEEP instruction External interrupt *4 SLEEP instruction SSBY = 1, PSS = 1 DTON = 1, LSON = 1 Clock switching exception processing SLEEP instruction Interrupt *1 LSON bit = 1 Sub-active mode (subclock) Software standby mode SLEEP instruction Interrupt *1 LSON bit = 0 SLEEP instruction SSBY = 1, PSS = 1 DTON = 1, LSON = 0 After the oscillation settling time (STS2 to 0), clock switching exception processing SSBY= 1, PSS= 0, LSON= 0 SLEEP instruction Interrupt *2 : Transition after exception processing SSBY= 1, PSS= 1, DTON= 0 Watch mode (subclock) SSBY= 0, PSS= 1, LSON= 1 Sub-sleep mode (subclock) : Low power dissipation mode Notes: 1. H8S/2268 Group: NMI, IRQ0, IRQ1, IRQ3 to IRQ5, WKP0 to WKP7, WDT1 interrupt, and TMR4 interrupt H8S/2264 Group: NMI, IRQ0, IRQ1, IRQ3, IRQ4, WKP0 to WKP7, and WDT1 interrupt 2. H8S/2268 Group: NMI, IRQ0, IRQ1, IRQ3 to IRQ5, WKP0 to WKP7, WDT0 interrupt, WDT1 interrupt, and TMR0 to TMR4 interrupts H8S/2264 Group: NMI, IRQ0, IRQ1, IRQ3, IRQ4, WKP0 to WKP7, WDT0 interrupt, WDT1 interrupt, TMR0 interrupt, and TMR1 interrupt 3. All interrupts 4. H8S/2268 Group: NMI, IRQ0, IRQ1, IRQ3 to IRQ5, WKP0 to WKP7 H8S/2264 Group: NMI, IRQ0, IRQ1, IRQ3, IRQ4, WKP0 to WKP7 * When a transition is made between modes by means of an interrupt, the transition cannot be made on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the interrupt request. * From any state except hardware standby mode, a transition to the reset state occurs when RES is driven Low. * From any state, a transition to hardware standby mode occurs when STBY is driven low. * Always select high-speed mode before making a transition to watch mode or sub-active mode. Figure 22.1 Mode Transition Diagram Rev. 3.00, 08/03, page 501 of 612 Table 22.2 Low Power Dissipation Mode Transition Conditions Status of Control Bit at Transition Pre-Transition State SSBY PSS State After Transition State After Transition Back from Low Power Mode Invoked by Invoked by SLEEP LSON DTON Instruction Interrupt High-speed/ 0 Medium-speed 0 X 0 X Sleep High-speed/Medium-speed X 1 X 1 0 0 X Software standby High-speed/Medium-speed 1 0 1 X 1 1 0 0 Watch High-speed 1 1 1 0 Watch Sub-active 1 1 0 1 1 1 1 1 Sub-active 0 0 X X 0 1 0 X 0 1 1 X Sub-sleep Sub-active 1 0 X X 1 1 0 0 Watch High-speed 1 1 1 0 Watch Sub-active 1 1 0 1 High-speed 1 1 1 1 Sub-active [Legend] X: Don't care : Do not set. Rev. 3.00, 08/03, page 502 of 612 22.1 Register Description The following registers relates to the power-down modes. For details on system clock control register (SCKCR), refer to section 21.1.1, System Clock Control Register (SCKCR). For details on low power control register (LPWRCR), refer to section 21.1.2, Low Power Control Register (LPWRCR). For details on timer control status register (TCSR), refer to section 12.2.2, Timer Control/Status Register (TCSR). * Standby control register (SBYCR) * Module stop control register A (MSTPCRA) * Module stop control register B (MSTPCRB) * Module stop control register C (MSTPCRC) * Module stop control register D (MSTPCRD) * Low power control register (LPWRCR) * System clock control register (SCKCR) * Timer control status register (TCSR) 22.1.1 Standby Control Register (SBYCR) SBYCR performs power-down mode control. Bit Bit Name Initial Value R/W Description 7 SSBY 0 R/W Software Standby Specifies transition destination when the SLEEP instruction is executed. 0: Shifts to sleep mode when the SLEEP instruction is executed in high-speed mode or medium-speed mode. Shifts to sub-sleep mode when the SLEEP instruction is executed in sub-active mode. 1: Shifts to software standby mode, sub-active mode, and watch mode when the SLEEP instruction is executed in high-speed mode or medium-speed mode. Shifts to watch mode or high-speed mode when the SLEEP instruction is executed in sub-active mode. Note that the value of the SSBY bit does not change even when software standby mode is canceled and making normal operation mode transition by executing an external interrupt. To clear this bit, 0 should be written to. Rev. 3.00, 08/03, page 503 of 612 Bit Bit Name Initial Value R/W Description 6 STS2 0 R/W Standby Timer Select 2 to 0 5 STS1 0 R/W 4 STS0 0 R/W These bits select the MCU wait time for clock settling to cancel software standby mode, watch mode, or subactive mode. With a crystal resonator (Table 22.3), select a wait time of 8 ms (oscillation settling time) or more, depending on the operating frequency. With an external clock, there are no specific wait requirements. 000: Standby time = 8192 states 001: Standby time = 16384 states 010: Standby time = 32768 states 011: Standby time = 65536 states 100: Standby time = 131072 states 101: Standby time = 262144 states 110: Standby time = 2048 states 111: Standby time = Reserved 3 1 R/W Reserved This is a readable/writable bit, but the write value should always be 1. 2 to 0 All 0 Reserved These bits are always read as 0 and cannot be modified. Rev. 3.00, 08/03, page 504 of 612 22.1.2 Module Stop Control Registers A to D (MSTPCRA to MSTPCRD) MSTPCR performs module stop mode control. When bits in MSTPCR registers are set to 1, module stop mode is set. When cleared to 0, module stop mode is cleared. MSTPCRA Bit 7 Bit Name Initial Value R/W 1 R/W 2 MSTPA7* 0 Target Module 6 MSTPA6* 0 R/W Data transfer controller (DTC) 5 MSTPA5 1 R/W 16-bit timer pulse unit (TPU) 4 MSTPA4 8-bit timer (TMR_0, TMR_1) 3 1 R/W 1 MSTPA3* 1 R/W 1 2 MSTPA2* 1 R/W 1 MSTPA1 1 R/W A/D converter MSTPA0* 1 R/W 8-bit timer (TMR_2, TMR_3) 0 2 MSTPCRB Bit Bit Name Initial Value R/W Target Module 7 MSTPB7 1 R/W Serial communication interface 0 (SCI_0) 6 MSTPB6 1 R/W Serial communication interface 1 (SCI_1) 5 MSTPB5* 1 R/W 4 MSTPB4 R/W 1 1 2 R/W 1 R/W 1 R/W 1 R/W 3 MSTPB3* 1 2 MSTPB2* 1 1 0 MSTPB1* 1 MSTPB0* 1 2 2 2 2 I C bus interface 0 (I C_0) (optional) I C bus interface 1 (I C_1) (optional) Rev. 3.00, 08/03, page 505 of 612 MSTPCRC Bit Bit Name 7 MSTPC7 Initial Value R/W Target Module Serial communication interface 2 (SCI_2) 1 R/W 6 1 MSTPC6* 1 R/W 5 MSTPC5* 1 2 R/W D/A converter 2 R/W PC break controller (PBC) 1 R/W 2 R/W 1 R/W 1 R/W 4 3 2 1 0 MSTPC4* 1 MSTPC3* 1 MSTPC2* 1 MSTPC1* 1 MSTPC0* 1 DTMF generation circuit MSTPCRD Bit Bit Name Initial Value 1 R/W 7 MSTPD7* 1 R/W 6 MSTPD6 5 4 3 2 Target Module 1 R/W LCD controller/driver 2 MSTPD5* 1 R/W 8-bit reload timer (TMR_4) 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W MSTPD4* 1 MSTPD3* 1 MSTPD2* 1 1 MSTPD1* 1 0 MSTPD0* 1 Notes: 1. Bit MSTPA7 can be read/written to. This bit is initialized to 0. Only 1 should be written to. Bits MSTPA3, MSTPA2, MSTPB5, MSTPB2 to MSTPB0, MSTPC6, MSTPC3, MSTPC1, MSTPC0, MSTPD7, MSTPD4 to MSTPD0 can be read/written to. These bits are initialized to 1. Only 1 should be written to. 2. With the H8S/2264 Group, only 1 should be written to. Rev. 3.00, 08/03, page 506 of 612 22.2 Medium-Speed Mode In high-speed mode, when the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode changes to medium-speed mode as soon as the current bus cycle ends. In medium-speed mode, the CPU operates on the operating clock (/2, /4, /8, /16, or /32) specified by the SCK2 to SCK0 bits. The bus masters other than the CPU (DTC*) also operate in medium-speed mode. On-chip peripheral modules other than the bus masters always operate on the high-speed clock (). In medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. For example, if /4 is selected as the operating clock, on-chip memory is accessed in 4 states, and internal I/O registers in 8 states. Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle. If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, and LSON bit in LPWRCR is cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored. When the SLEEP instruction is executed with the SSBY bit = 1, LPWRCR LSON bit = 0, and TCSR (WDT_1) PSS bit = 0, operation shifts to the software standby mode. When software standby mode is cleared by an external interrupt, medium-speed mode is restored. When the RES pin is set low and medium-speed mode is cancelled, operation shifts to the reset state. The same applies in the case of a reset caused by overflow of the watchdog timer. When the STBY pin is driven low, a transition is made to hardware standby mode. Figure 22.2 shows the timing for transition to and clearance of medium-speed mode. Note: * Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 507 of 612 Medium-speed mode Internal clock , peripheral module clock Bus master clock Internal address bus SBYCR SBYCR Internal write signal Figure 22.2 Medium-Speed Mode Transition and Clearance Timing 22.3 Sleep Mode 22.3.1 Sleep Mode When the SLEEP instruction is executed while the SBYCR SSBY bit = 0 and the LPWRCR LSON bit = 0, the CPU enters the sleep mode. In sleep mode, CPU operation stops but the contents of the CPU's internal registers are retained. Other peripheral modules do not stop. 22.3.2 Exiting Sleep Mode Sleep mode is exited by any interrupt, or signals at the RES, or STBY pins. * Exiting Sleep Mode by Interrupts When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the CPU. * Exiting Sleep Mode by RES pin Setting the RES pin level low selects the reset state. After the stipulated reset input duration, driving the RES pin high starts the CPU performing reset exception processing. * Exiting Sleep Mode by STBY Pin When the STBY pin level is driven low, a transition is made to hardware standby mode. Rev. 3.00, 08/03, page 508 of 612 22.4 Software Standby Mode 22.4.1 Software Standby Mode A transition is made to software standby mode when the SLEEP instruction is executed while the SBYCR SSBY bit = 1 and the LPWRCR LSON bit = 0, and the TCSR (WDT_1) PSS bit = 0. In this mode, the CPU, on-chip peripheral modules, and oscillator all stop. However, the contents of the CPU's internal registers, RAM data, and the states of on-chip peripheral modules other than the A/D converter, and the states of I/O ports are retained. In this mode the oscillator stops, and therefore power dissipation is significantly reduced. 22.4.2 Clearing Software Standby Mode Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0, IRQ1, IRQ3, IRQ4 , IRQ5*, WKP0 to WKP7), or by means of the RES pin or STBY pin. * Clearing with an interrupt When an NMI, or IRQ0, IRQ1, IRQ3, IRQ4, IRQ5*, or WKP0 to WKP7 interrupt request signal is input, clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SYSCR, stable clocks are supplied to the entire chip, software standby mode is cleared, and interrupt exception handling is started. When clearing software standby mode with an IRQ0, IRQ1, IRQ3, IRQ4, IRQ5*, or WKP0 to WKP7 interrupt, set the corresponding enable bit/pin function switching bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0, IRQ1, IRQ3, IRQ4, IRQ5*, or WKP0 to WKP7 is generated. Software standby mode cannot be cleared if the interrupt has been masked on the CPU side or has been designated as a DTC activation source. * Clearing with the RES pin When the RES pin is driven low, clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the entire chip. Note that the RES pin must be held low until clock oscillation settles. When the RES pin goes high, the CPU begins reset exception handling. * Clearing with the STBY pin When the STBY pin is driven low, a transition is made to hardware standby mode. Note: * Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 509 of 612 22.4.3 Oscillation Settling Time after Clearing Software Standby Mode Bits STS2 to STS0 in SBYCR should be set as described below. * Using a Crystal Oscillator Set bits STS2 to STS0 so that the standby time is at least 8 ms (the oscillation settling time). Table 22.3 shows the standby times for different operating frequencies and settings of bits STS2 to STS0. * Using an External Clock Any value can be set. Normally, minimum time is recommended. Table 22.3 Oscillation Settling Time Settings STS2 STS1 STS0 Standby Time 20 MHz 16 MHz 13 MHz 10 MHz 8 MHz 6 MHz 4 MHz 2 MHz Unit 0 0 0 8192 states 0.41 0.51 0.63 0.82 1.0 1.4 2.0 4.1 ms 1 16384 states 0.82 1.0 1.3 1.6 2.0 2.7 4.1 8.2 0 32768 states 1.6 2.0 2.5 3.3 4.1 5.5 8.2 16.4 1 65536 states 3.3 4.1 5.0 6.6 8.2 10.9 16.4 32.8 0 131072 states 6.6 8.2 10.1 13.1 16.4 21.8 32.8 65.5 1 262144 states 13.1 16.4 20.2 26.2 32.8 43.7 65.5 131.1 0 2048 states 0.10 0.13 0.16 0.20 0.26 0.34 0.51 1.0 1 Reserved 1 1 0 1 Shading: Recommended time setting 22.4.4 Software Standby Mode Application Example Figure 22.3 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge on the NMI pin. Rev. 3.00, 08/03, page 510 of 612 Oscillator Internal clock NMI NMIEG SSBY NMI exception Software standby mode handling (power-down mode) NMIEG=1 SSBY=1 SLEEP instruction Oscillation settling time tOSC2 NMI exception handling Figure 22.3 Software Standby Mode Application Example 22.5 Hardware Standby Mode 22.5.1 Hardware Standby Mode When the STBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip RAM data is retained. I/O ports are set to the high-impedance state. Do not change the state of the mode pins (MD2,MD1) during hardware standby mode. 22.5.2 Clearing Hardware Standby Mode Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY pin is driven high while the RES pin is low, the reset state is set and clock oscillation is started. Ensure that the RES pin is held low until the clock oscillator settles (at least tosc1 msthe oscillation settling timewhen using a crystal/ceramic oscillator). When the RES pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state. Rev. 3.00, 08/03, page 511 of 612 22.5.3 Hardware Standby Mode Timing Figure 22.4 shows an example of hardware standby mode timing. When the STBY pin is driven low after the RES pin has been driven low, a transition is made to hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high, waiting for the oscillation settling time, then changing the RES pin from low to high. Oscillator RES STBY Oscillation settling time tosc1 Reset exception handling Figure 22.4 Hardware Standby Mode Timing 22.6 Module Stop Mode Module stop mode can be set for individual on-chip peripheral modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module starts operating at the end of the bus cycle. In module stop mode, the internal states of modules other than the A/D converter are retained. After reset clearance, all modules other than DTC* are in module stop mode. When an on-chip peripheral module is in module stop mode, read/write access to its registers is disabled. Since the operations of the bus controller and I/O port are stopped when sleep mode is entered at the all-module stop state (MSTPCR=H'FFFFFFFF), power consumption can further be reduced. Note: * Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 512 of 612 22.7 Watch Mode 22.7.1 Transition to Watch Mode CPU operation makes a transition to watch mode when the SLEEP instruction is executed in highspeed mode or sub-active mode with SBYCR SSBY=1, LPWRCR DTON = 0, and TCSR (WDT_1) PSS = 1. In watch mode, the CPU is stopped and peripheral modules other than WDT_1, TMR_4*, and LCD are also stopped. The contents of the CPU's internal registers, the data in internal RAM, and the statuses of the internal peripheral modules (excluding the A/D converter) and I/O ports are retained. To make a transition to watch mode, bits SCK2 to SCK0 in SCKCR must be set to 0. Note: * Supported only by the H8S/2268 Group. 22.7.2 Exiting Watch Mode Watch mode is exited by any interrupt (WOVI1 interrupt, OVI4 to OVI7 interrupts*, NMI pin, or IRQ0, IRQ1, IRQ3, IRQ4, IRQ5*, or WKP0 to WKP7), or signals at the RES, or STBY pins. * Exiting Watch Mode by Interrupts When an interrupt occurs, watch mode is exited and a transition is made to high-speed mode or medium-speed mode when the LPWRCR LSON bit = 0 or to sub-active mode when the LSON bit = 1. When a transition is made to high-speed mode, a stable clock is supplied to all LSI circuits and interrupt exception processing starts after the time set in SBYCR STS2 to STS0 has elapsed. In the case of IRQ0, IRQ1, IRQ3, IRQ4, IRQ5*, and WKP0 to WKP7 interrupts, no transition is made from watch mode if the corresponding enable bit/pin function switching bit has been cleared to 0, and, in the case of interrupts from the internal peripheral modules, the interrupt enable register has been set to disable the reception of that interrupt, or is masked by the CPU. See section 22.4.3, Oscillation Settling Time after Clearing Software Standby Mode, for how to set the oscillation settling time when making a transition from watch mode to high-speed mode. * Exiting Watch Mode by RES pins For exiting watch mode by the RES pins, see section 22.4.2, Clearing Software Standby Mode. * Exiting Watch Mode by STBY pin When the STBY pin level is driven low, a transition is made to hardware standby mode. Note: * Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 513 of 612 22.8 Sub-Sleep Mode 22.8.1 Transition to Sub-Sleep Mode When the SLEEP instruction is executed with the SBYCR SSBY bit = 0, LPWRCR LSON bit = 1, and TCSR (WDT_1) PSS bit = 1, CPU operation shifts to sub-sleep mode. In sub-sleep mode, the CPU is stopped. Peripheral modules other than TMR_0, TMR1, TMR2 to TMR_4*, WDT_0, WDT_1, and LCD are also stopped. The contents of the CPU's internal registers, the data in internal RAM, and the statuses of the internal peripheral modules (excluding the A/D converter) and I/O ports are retained. Note: * Supported only by the H8S/2268 Group. 22.8.2 Exiting Sub-Sleep Mode Sub-sleep mode is exited by an interrupt (interrupts from internal peripheral modules, NMI pin, or IRQ0, IRQ1, IRQ3, IRQ4, IRQ5*, or WKP0 to WKP7), or signals at the RES or STBY pins. * Exiting Sub-Sleep Mode by Interrupts When an interrupt occurs, sub-sleep mode is exited and interrupt exception processing starts. In the case of IRQ0, IRQ1, IRQ3, IRQ4, IRQ5*, and WKP0 to WKP7 interrupts, sub-sleep mode is not cancelled if the corresponding enable bit/pin function switching bit has been cleared to 0, and, in the case of interrupts from the internal peripheral modules, the interrupt enable register has been set to disable the reception of that interrupt, or is masked by the CPU. * Exiting Sub-Sleep Mode by RES For exiting sub-sleep mode by the RES pins, see section 22.4.2, Clearing Software Standby Mode. * Exiting Sub-Sleep Mode by STBY Pin When the STBY pin level is driven low, a transition is made to hardware standby mode. Note: * Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 514 of 612 22.9 Sub-Active Mode 22.9.1 Transition to Sub-Active Mode When the SLEEP instruction is executed in high-speed mode with the SBYCR SSBY bit = 1, LPWRCR DTON bit = 1, LSON bit = 1, and TCSR (WDT_1) PSS bit = 1, CPU operation shifts to sub-active mode. When an interrupt occurs in watch mode, and if the LSON bit of LPWRCR is 1, a transition is made to sub-active mode. And if an interrupt occurs in sub-sleep mode, a transition is made to sub-active mode. In sub-active mode, the CPU operates at low speed on the subclock, and the program is executed step by step. Peripheral modules other than PBC*, TMR_0, TMR_1, TMR_2 to TMR_4*, WDT_0, WDT_1, and LCD are also stopped. When operating the CPU in sub-active mode, the SCKCR SCK2 to SCK0 bits must be set to 0. Note: * Supported only by the H8S/2268 Group. 22.9.2 Exiting Sub-Active Mode Sub-active mode is exited by the SLEEP instruction or the RES or STBY pins. * Exiting Sub-Active Mode by SLEEP Instruction When the SLEEP instruction is executed with the SBYCR SSBY bit = 1, LPWRCR DTON bit = 0, and TCSR (WDT_1) PSS bit = 1, the CPU exits sub-active mode and a transition is made to watch mode. When the SLEEP instruction is executed with the SBYCR SSBY bit = 0, LPWRCR LSON bit = 1, and TCSR (WDT_1) PSS bit = 1, a transition is made to sub-sleep mode. Finally, when the SLEEP instruction is executed with the SBYCR SSBY bit = 1, LPWRCR DTON bit = 1, LSON bit = 0, and TCSR (WDT_1) PSS bit = 1, a direct transition is made to high-speed mode (SCK0 to SCK2 all 0). * Exiting Sub-Active Mode by RES Pins For exiting sub-active mode by the RES pins, see section 22.4.2, Clearing Software Standby Mode. * Exiting Sub-Active Mode by STBY Pin When the STBY pin level is driven low, a transition is made to hardware standby mode. Rev. 3.00, 08/03, page 515 of 612 22.10 Direct Transitions There are three modes, high-speed, medium-speed, and sub-active, in which the CPU executes programs. When a direct transition is made, there is no interruption of program execution when shifting between high-speed and sub-active modes. Direct transitions are enabled by setting the LPWRCR DTON bit to 1, then executing the SLEEP instruction. After a transition, direct transition interrupt exception processing starts. 22.10.1 Direct Transitions from High-Speed Mode to Sub-Active Mode Execute the SLEEP instruction in high-speed mode when the SBYCR SSBY bit = 1, LPWRCR LSON bit = 1, and DTON bit = 1, and TSCR (WDT_1) PSS bit = 1 to make a transition to subactive mode. 22.10.2 Direct Transitions from Sub-Active Mode to High-Speed Mode Execute the SLEEP instruction in sub-active mode when the SBYCR SSBY bit = 1, LPWRCR LSON bit = 0, and DTON bit = 1, and TSCR (WDT_1) PSS bit = 1 to make a direct transition to high-speed mode after the time set in SBYCR STS2 to STS0 has elapsed. 22.11 Usage Notes 22.11.1 I/O Port Status In software standby mode and watch mode, I/O port states are retained. Therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. 22.11.2 Current Dissipation during Oscillation Settling Wait Period Current dissipation increases during the oscillation settling wait period. 22.11.3 DTC Module Stop (Supported only by the H8S/2268 Group) Depending on the operating status of the DTC, the MSTPA6 bit may not be set to 1. Setting of the DTC module stop mode should be carried out only when the respective module is not activated. For details, refer to section 8, Data Transfer Controller (DTC). Rev. 3.00, 08/03, page 516 of 612 22.11.4 On-Chip Peripheral Module Interrupt * Module stop mode Relevant interrupt operations cannot be performed in module stop mode. Consequently, if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DTC* activation source. Interrupts should therefore be disabled before entering module stop mode. Note: Supported only by the H8S/2268 Group. * Subactive mode / Watch mode On-chip peripheral modules (DTC*, TPU, IIC) that stop operation in subactive mode cannot clear interrupts in subactive mode. Therefore, if subactive mode is entered when an interrupt is requested, CPU interrupt factors cannot be cleared. Interrupts should therefore before executing the SLEEP instruction and entering subactive or watch mode. Note: * Supported only by the H8S/2268 Group. 22.11.5 Writing to MSTPCR MSTPCR should only be written to by the CPU. 22.11.6 Entering Subactive / Watch Mode and DTC Module Stop (Supported only by H8S/2268 Group) To enter subactive or watch mode, set DTC to module stop (write 1 to the MSTPA6 bit) and reading the MSTPA6 bit as 1 before transiting mode. After transiting from subactive mode to active mode, clear module stop. When DTC activation factor occurs in subactive mode, DTC is activated when module stop is cleared after active mode is entered. Rev. 3.00, 08/03, page 517 of 612 Rev. 3.00, 08/03, page 518 of 612 Section 23 Power Supply Circuit This LSI has an internal power step-down circuit built into it. Using this circuit allows the internal power supply to be fixed at approximately 3.0 V without relaying on the power supply voltage connected to the external Vcc terminal. This means that, when used at an external power supply higher than 3.0 V, the current consumption value can be suppressed to largely the same value as that when used at approximately 3.0 V. If the external voltage is 3.0 V or less, the internal voltage will be largely consistent with the external voltage. 23.1 When Internal Power Step-Down Circuit is Used As shown in figure 23.1, an external power supply should be connected to the Vcc pin, using the shortest possible wiring, with a capacitance (H8S/2268 Group: 0.1 F/0.2 F and H8S/2264 Group: 0.2 F) between CVcc and Vss. Adding this external circuit makes the internal step-down circuit valid. Applying a power supply exceeding the absolute maximum rated value of 4.3 V to the CVcc terminal can permanently damage the LSI, so the power supply should not be connected to the CVcc terminal. The external power supply voltage connected to Vcc and the GND potential connected to Vss serve as the references for the input/output levels of the external circuit. For example, a "High" port input/output level will be the Vcc reference, and a "Low" level will be the Vss reference. The analog power supplies of the A/D converter, D/A converter*, and DTMF generation circuit* do not affect the internal step-down circuit. Note: * Supported only by the H8S/2268 Group. Vcc Vcc 2.7 to 5.5V (Vcc = 3.0 to 5.5V for the F-ZTAT version) Step-down voltage circuit CVcc Internal logic Internal power supply Stabilized capacitance (H8S/2268 Group: 0.1 F/0.2 F and H8S/2264 Group: 0.2 F) Vss Figure 23.1 Power Supply Connections when Internal Power Supply Step-Down Circuit is Used PSCKT20A_000020020700 Rev. 3.00, 08/03, page 519 of 612 Rev. 3.00, 08/03, page 520 of 612 Section 24 List of Registers This section gives information on the on-chip I/O registers and is configured as described below. 1. Register Addresses (by functional module, in address order) * Descriptions by functional module, in ascending order of addresses * When registers consist of 16 bits, the addresses of the MSBs are given. * Data bus width is given. * The number of access states are given. 2. Register Bits * Bit configurations of the registers are described in the same order as the Register Addresses (by functional module, in ascending order of addresses). * Reserved bits are indicated by in the bit name. * When registers consist of 16 or 32 bits, bits are described from the MSB side. 3. Register States in Each Operating Mode * Register states are described in the same order as the Register Addresses (by functional module, in ascending order of addresses). * The register states described are for the basic operating modes. If there is a specific reset for an on-chip module, refer to the section on that on-chip module. Rev. 3.00, 08/03, page 521 of 612 24.1 Register Addresses (by function module, in address order) The data bus width indicates the numbers of bits by which the register is accessed. The number of access states indicates the number of states based on the specified reference clock. Register Name 4 DTC mode register A* 4 DTC source address register* 4 DTC mode register B* Abbreviation Bit No. Address* Module Data Width MRA 8 H'EBC0 to DTC 16/32* SAR MRB DTC destination address 4 register* 4 DTC transfer count register A* 4 24 1 2 1 2 1 2 1 2 16/32* 16/32* 16/32* CRA 16 DTC 16/32* LPCR 8 LCD control register LCR LCD control register 2 LCD RAM DTMF load register* 1 2 DTC LCD port control register 4 DTC 2 24 16 DTMF control register* DTC Access State DAR CRB 4 H'EFBF 8 DTC transfer count register B* Module stop control register D 1 DTC 16/32* 1 H'FC30 LCD 8/16 4 8 H'FC31 LCD 8/16 4 LCR2 8 H'FC32 LCD 8/16 4 8 H'FC40 to LCD H'FC53 8/16 4 MSTPCRD 8 H'FC60 SYSTEM 8 4 DTCR 8 H'FC68 DTMF 8 4 DTLR 8 H'FC69 DTMF 8 4 4 TCR_4 8 H'FC70 TMR_4 8/16 4 4 TCR_5 8 H'FC71 TMR_4 8/16 4 4 TCR_6 8 H'FC72 TMR_4 8/16 4 Timer control register_7* 4 TCR_7 8 H'FC73 TMR_4 8/16 4 Timer counter 4/Timer reload 4 register 4* TCNT_4(R)/ 8 TLR_4(W) H'FC74 TMR_4 8/16 4 Timer counter 5/Timer reload 4 register 5* TCNT_5(R)/ 8 TLR_5(W) H'FC75 TMR_4 8/16 4 Timer counter 6/Timer reload 4 register 6* TCNT_6(R)/ 8 TLR_6(W) H'FC76 TMR_4 8/16 4 Timer counter 7/Timer reload 4 register 7* TCNT_7(R)/ 8 TLR_7(W) H'FC77 TMR_4 8/16 4 Port H data direction register PHDDR 8 H'FC80 PORT 8 4 Port J data direction register PJDDR 8 H'FC81 PORT 8 4 Port K data direction register PKDDR 8 H'FC82 PORT 8 4 Timer control register_4* Timer control register_5* Timer control register_6* Rev. 3.00, 08/03, page 522 of 612 Register Name Port L data direction register Abbreviation Bit No. Address* 1 Data Module Width Access State PLDDR 8 H'FC83 PORT 8 4 4 PMDDR 8 H'FC84 PORT 8 4 4 Port N data direction register* PNDDR 8 H'FC85 PORT 8 4 Port H data register PHDR 8 H'FC88 PORT 8 4 Port J data register PJDR 8 H'FC89 PORT 8 4 Port K data register PKDR 8 H'FC8A PORT 8 4 PLDR 8 H'FC8B PORT 8 4 Port M data direction register* Port L data register 4 PMDR 8 H'FC8C PORT 8 4 Port N data register* 4 PNDR 8 H'FC8D PORT 8 4 Port H register PORTH 8 H'FC90 PORT 8 4 Port J register PORTJ 8 H'FC91 PORT 8 4 Port K register PORTK 8 H'FC92 PORT 8 4 Port M data register* Port L register PORTL 8 H'FC93 PORT 8 4 4 PORTM 8 H'FC94 PORT 8 4 4 PORTN 8 H'FC95 PORT 8 4 Port J pull-up MOS control register PJPCR 8 H'FC99 PORT 8 4 Wakeup control register 8 H'FC9F PORT 8 4 Wakeup interrupt request register IWPR 8 H'FCA0 INT 8 4 Interrupt enable register Port M register* Port N register* WPCR IENR1 8 H'FCA1 INT 8 4 4 DADR_0 8 H'FDAC D/A 8 2 4 DADR_1 8 H'FDAD D/A 8 2 4 D/A control register* DACR 8 H'FDAE D/A 8 2 Serial control register X SCRX 8 H'FDB4 IIC, FLASH 8 2 DDCSWR 8 H'FDB5 IIC 8 2 TCR_2 8 H'FDC0 TMR_2 8 2 D/A data register_0* D/A data register_1* DDC switch register 4 Timer control register_2* 4 Timer control register_3* TCR_3 8 H'FDC1 TMR_3 8 2 4 TCSR_2 8 H'FDC2 TMR_2 8 2 4 Timer control/status register_2* Timer control/status register_3* TCSR_3 8 H'FDC3 TMR_3 8 2 4 TCORA_2 8 H'FDC4 TMR_2 8/16 2 4 TCORA_3 8 H'FDC5 TMR_3 8/16 2 4 TCORB_2 8 H'FDC6 TMR_2 8/16 2 4 TCORB_3 8 H'FDC7 TMR_3 8/16 2 Time constant register A_2* Time constant register A_3* Time constant register B_2* Time constant register B_3* Rev. 3.00, 08/03, page 523 of 612 Abbreviation Bit No. 1 Data Module Width Access State 4 TCNT_2 8 H'FDC8 TMR_2 8/16 2 4 Timer counter_3* TCNT_3 8 H'FDC9 TMR_3 8/16 2 Serial mode register_2 SMR_2 8 H'FDD0 SCI_2 8 2 Bit rate register_2 BRR_2 8 H'FDD1 SCI_2 8 2 Serial control register_2 SCR_2 8 H'FDD2 SCI_2 8 2 Transmit data register_2 TDR_2 8 H'FDD3 SCI_2 8 2 Serial status register_2 SSR_2 8 H'FDD4 SCI_2 8 2 Register Name Timer counter_2* Address* Receive data register_2 RDR_2 8 H'FDD5 SCI_2 8 2 Smart card mode register_2 SCMR_2 8 H'FDD6 SCI_2 8 2 Standby control register SBYCR 8 H'FDE4 SYSTEM 8 2 System control register SYSCR 8 H'FDE5 SYSTEM 8 2 System clock control register SCKCR 8 H'FDE6 SYSTEM 8 2 Mode control register MDCR 8 H'FDE7 SYSTEM 8 2 Module stop control register A MSTPCRA 8 H'FDE8 SYSTEM 8 2 Module stop control register B MSTPCRB 8 H'FDE9 SYSTEM 8 2 Module stop control register C MSTPCRC 8 H'FDEA SYSTEM 8 2 Low power control register LPWRCR 8 H'FDEC SYSTEM 8 2 8 H'FDF8 SCI_0 8 2 Serial expansion mode register_0 SEMR_0 4 BARA 32 H'FE00 PBC 8/16 2 4 Break address register A* Break address register B* BARB 32 H'FE04 PBC 8/16 2 4 BCRA 8 H'FE08 PBC 8/16 2 4 Break control register B* BCRB 8 H'FE09 PBC 8/16 2 IRQ sense control register H ISCRH 8 H'FE12 INT 8 2 Break control register A* IRQ sense control register L ISCRL 8 H'FE13 INT 8 2 IRQ enable register IER 8 H'FE14 INT 8 2 ISR 8 H'FE15 INT 8 2 DTCER 8 H'FE16 to DTC H'FE1B, H'FE1E 8 2 DTC vector register* DTVECR 8 H'FE1F DTC 8 2 Port 1 data direction register P1DDR 8 H'FE30 PORT 8 2 Port 3 data direction register P3DDR 8 H'FE32 PORT 8 2 Port 7 data direction register P7DDR 8 H'FE36 PORT 8 2 IRQ status register 4 DTC enable register* 4 Rev. 3.00, 08/03, page 524 of 612 Register Name Abbreviation Bit No. 1 Data Module Width Access State Port F data direction register PFDDR 8 H'FE3E PORT 8 2 Port 3 open drain control register P3ODR 8 H'FE46 PORT 8 2 Timer start register TSTR 8 H'FEB0 TPU 8 2 Timer synchro register Address* TSYR 8 H'FEB1 TPU 8 2 4 IPRA 8 H'FEC0 INT 8 2 4 IPRB 8 H'FEC1 INT 8 2 4 IPRC 8 H'FEC2 INT 8 2 4 IPRD 8 H'FEC3 INT 8 2 4 IPRE 8 H'FEC4 INT 8 2 4 IPRF 8 H'FEC5 INT 8 2 4 IPRG 8 H'FEC6 INT 8 2 Interrupt priority register A* Interrupt priority register B* Interrupt priority register C* Interrupt priority register D* Interrupt priority register E* Interrupt priority register F* Interrupt priority register G* 4 Interrupt priority register I* IPRI 8 H'FEC8 INT 8 2 4 IPRJ 8 H'FEC9 INT 8 2 4 IPRK 8 H'FECA INT 8 2 4 INT 8 2 Interrupt priority register J* Interrupt priority register K* Interrupt priority register L* IPRL 8 H'FECB 4 IPRM 8 H'FECC INT 8 2 4 IPRO 8 H'FECE INT 8 2 RAM emulation register* RAMER 8 H'FEDB FLASH 8 2 Port 1 data register P1DR 8 H'FF00 PORT 8 2 Port 3 data register P3DR 8 H'FF02 PORT 8 2 Port 7 data register P7DR 8 H'FF06 PORT 8 2 PFDR 8 H'FF0E PORT 8 2 TCR_0 8 H'FF10 TPU_0 8 2 TMDR_0 8 H'FF11 TPU_0 8 2 TIORH_0 8 H'FF12 TPU_0 8 2 TIORL_0 8 H'FF13 TPU_0 8 2 8 H'FF14 TPU_0 8 2 TSR_0 8 H'FF15 TPU_0 8 2 Interrupt priority register M* Interrupt priority register O* 4 Port F data register 4 Timer control register_0* 4 Timer mode register_0* 4 Timer I/O control register H_0* 4 Timer I/O control register L_0* 4 Timer interrupt enable register_0* TIER_0 4 Timer status register_0* 4 Timer counter_0* TCNT_0 16 H'FF16 TPU_0 16 2 4 TGRA_0 16 H'FF18 TPU_0 16 2 4 TGRB_0 16 H'FF1A TPU_0 16 2 4 TGRC_0 16 H'FF1C TPU_0 16 2 Timer general register A_0* Timer general register B_0* Timer general register C_0* Rev. 3.00, 08/03, page 525 of 612 Abbreviation Bit No. Data Module Width Access State Timer general register D_0* TGRD_0 16 H'FF1E TPU_0 16 2 Timer control register_1 TCR_1 8 H'FF20 TPU_1 8 2 Timer mode register_1 TMDR_1 8 H'FF21 TPU_1 8 2 Timer I/O control register_1 TIOR_1 8 H'FF22 TPU_1 8 2 Timer interrupt enable register_1 TIER_1 8 H'FF24 TPU_1 8 2 Timer status register_1 TSR_1 8 H'FF25 TPU_1 8 2 Timer counter_1 TCNT_1 16 H'FF26 TPU_1 16 2 Timer general register A_1 TGRA_1 16 H'FF28 TPU_1 16 2 Timer general register B_1 TGRB_1 16 H'FF2A TPU_1 16 2 Timer control register_2 TCR_2 8 H'FF30 TPU_2 8 2 Timer mode register_2 TMDR_2 8 H'FF31 TPU_2 8 2 Timer I/O control register_2 TIOR_2 8 H'FF32 TPU_2 8 2 Timer interrupt enable register_2 TIER_2 8 H'FF34 TPU_2 8 2 Timer status register_2 TSR_2 8 H'FF35 TPU_2 8 2 Timer counter_2 TCNT_2 16 H'FF36 TPU_2 16 2 Timer general register A_2 TGRA_2 16 H'FF38 TPU_2 16 2 Timer general register B_2 TGRB_2 16 H'FF3A TPU_2 16 2 Timer control register_0 TCR_0 8 H'FF68 TMR_0 8 2 Timer control register_1 TCR_1 8 H'FF69 TMR_1 8 2 Timer control/status register_0 TCSR_0 8 H'FF6A TMR_0 8 2 Timer control/status register_1 TCSR_1 8 H'FF6B TMR_1 8 2 Time constant register A_0 TCORA_0 8 H'FF6C TMR_0 8/16 2 Time constant register A_1 TCORA_1 8 H'FF6D TMR_1 8/16 2 Time constant register B_0 TCORB_0 8 H'FF6E TMR_0 8/16 2 Time constant register B_1 TCORB_1 8 H'FF6F TMR_1 8/16 2 Timer counter_0 TCNT_0 8 H'FF70 TMR_0 8/16 2 Timer counter_1 TCNT_1 8 H'FF71 TMR_1 8/16 2 Timer control/status register_0 TCSR_0 8 H'FF74(W) WDT_0 H'FF74(R) 16 2 Timer counter_0 TCNT_0 8 H'FF74(W) WDT_0 H'FF75(R) 16 2 Reset control/status register RSTCSR 8 H'FF76(W) WDT_0 H'FF77(R) 16 2 Register Name 4 Rev. 3.00, 08/03, page 526 of 612 Address* 1 Register Name Abbreviation Bit No. 1 Serial mode register_0 SMR_0 8 H'FF78* 2 I C bus control register_0 ICCR_0 Bit rate register_0 BRR_0 2 Address* 8 8 Data Module Width Access State 3 SCI_0 8 2 3 IIC_0 8 2 3 SCI_0 8 2 3 H'FF78* H'FF79* I C bus status register_0 ICSR_0 8 H'FF79* IIC_0 8 2 Serial control register_0 SCR_0 8 H'FF7A SCI_0 8 2 Transmit data register_0 TDR_0 8 H'FF7B SCI_0 8 2 Serial status register_0 SSR_0 8 H'FF7C SCI_0 8 2 Receive data register_0 RDR_0 8 H'FF7D Smart card mode register_0 SCMR_0 8 H'FF7E* 2 ICDR_0/ SARX_0 8 I C bus mode register_0/Slave address register_0 2 ICMR_0/ SAR_0 Serial mode register_1 I C bus data register_0/Second slave address register_0 2 4 I C bus control register_1* Bit rate register_1 2 SCI_0 8 2 3 SCI_0 8 2 H'FF7E* 3 IIC_0 8 2 8 H'FF7F IIC_0 8 2 SMR_1 8 H'FF80* 3 SCI_1 8 2 ICCR_1 8 H'FF80* 3 IIC_1 8 2 3 SCI_1 8 2 3 BRR_1 4 8 H'FF81* I C bus status register_1* ICSR_1 8 H'FF81* IIC_1 8 2 Serial control register_1 SCR_1 8 H'FF82 SCI_1 8 2 Transmit data register_1 TDR_1 8 H'FF83 SCI_1 8 2 Serial status register_1 SSR_1 8 H'FF84 SCI_1 8 2 Receive data register_1 RDR_1 8 H'FF85 Smart card mode register_1 SCI_1 8 2 3 3 SCMR_1 8 H'FF86* SCI_1 8 2 2 ICDR_1/ SARX_1 8 H'FF86* IIC_1 8 2 I C bus mode register_1/Slave 4 address register_1* 2 ICMR_1/ SAR_1 8 H'FF87 IIC_1 8 2 A/D data register AH ADDRAH 8 H'FF90 A/D 8 2 A/D data register AL ADDRAL 8 H'FF91 A/D 8 2 A/D data register BH ADDRBH 8 H'FF92 A/D 8 2 A/D data register BL ADDRBL 8 H'FF93 A/D 8 2 A/D data register CH ADDRCH 8 H'FF94 A/D 8 2 A/D data register CL ADDRCL 8 H'FF95 A/D 8 2 A/D data register DH ADDRDH 8 H'FF96 A/D 8 2 I C bus data register_1/Second 4 slave address register_1* Rev. 3.00, 08/03, page 527 of 612 Register Name Abbreviation Data 1 Bit No. Address* Module Width Access State A/D data register DL ADDRDL 8 H'FF97 2 A/D control/status register ADCSR 8 H'FF98 A/D 8 2 A/D control register ADCR 8 H'FF99 A/D 8 2 Timer control/status register_1 TCSR_1 8 H'FFA2(W) WDT_1 H'FFA2(R) 16 2 Timer counter_1 TCNT_1 8 H'FFA2(W) WDT_1 H'FFA3(R) 16 2 4 FLMCR1 8 H'FFA8 FLASH 8 2 4 FLMCR2 8 H'FFA9 FLASH 8 2 4 EBR1 8 H'FFAA FLASH 8 2 4 Erase block register 2* EBR2 8 H'FFAB FLASH 8 2 Flash memory power control 4 register* FLPWCR 8 H'FFAC FLASH 8 2 Port 1 register PORT1 8 H'FFB0 PORT 8 2 Flash memory control register 1* Flash memory control register 2* Erase block register 1* A/D 8 Port 3 register PORT3 8 H'FFB2 PORT 8 2 Port 4 register PORT4 8 H'FFB3 PORT 8 2 Port 7 register PORT7 8 H'FFB6 PORT 8 2 Port 9 register PORT9 8 H'FFB8 PORT 8 2 Port F register PORTF 8 H'FFBE PORT 8 2 Notes: 1. Lower 16 bits of the address. 2. Allocated on the on-chip RAM. 32-bit bus when DTC accesses as register information, and 16-bit in other cases. 4 3. Part of registers SCI_0 and SCI_1 and part of registers IIC_0 and IIC_1* are allocated to the same address. Use the IICE bit of the serial control register X (SCRX) to select the register. 4. Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 528 of 612 24.2 Register Bits Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module SM1 SM0 DM1 DM0 MD1 MD0 DTS Sz DTC CHNE DISEL - - - - - - LPCR DTS1 DTS0 CMX - SGS3 SGS2 SGS1 SGS0 LCR - PSW ACT CKS3 CKS2 CKS1 CKS0 LCR2 LCDAB - HCKS* CDS3 CDS2 CDS1 CDS0 LCD RAM Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MSTPCRD MSTPD7 MSTPD6 MSTPD5 MSTPD4 MSTPD3 MSTPD2 MSTPD1 MSTPD0 SYSTEM DTEN - CLOE RWOE CLF1 CLF0 RWF1 RWF0 DTMF DTL1 DTL0 MRA* SAR* 1 1 MRB*1 1 DAR* 1 CRA* CRB*1 DTCR* 1 DISP 2 SUPS* 2 - - DTL5 DTL4 DTL3 DTL2 1 ARSL OVF OVIE - - CKS2 CKS1 CKS0 TCR_5*1 ARSL OVF OVIE - - CKS2 CKS1 CKS0 TCR_6* 1 ARSL OVF OVIE - - CKS2 CKS1 CKS0 TCR_7* 1 ARSL OVF OVIE - - CKS2 CKS1 CKS0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PHDDR - - - - PH3DDR PH2DDR PH1DDR PH0DDR PJDDR PJ7DDR PJ6DDR PJ5DDR PJ4DDR PJ3DDR PJ2DDR PJ1DDR PJ0DDR DTLR* 1 TCR_4* TCNT_4(R)/ TLR_4(W)* TMR_4 1 TCNT_5(R)/ TLR_5(W)* LCD 1 TCNT_6(R)/ TLR_6(W)*1 TCNT_7(R)/ TLR_7(W)* 1 PORT Rev. 3.00, 08/03, page 529 of 612 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PKDDR PK6DDR PK5DDR PK4DDR PK3DDR PK2DDR PK1DDR PK0DDR PORT PK7DDR PLDDR PL7DDR PL6DDR PL5DDR PL4DDR PL3DDR PL2DDR PL1DDR PL0DDR 1 PM7DDR PM6DDR PM5DDR PM4DDR PM3DDR PM2DDR PM1DDR PM0DDR 1 PN7DDR PN6DDR PN5DDR PN4DDR PN3DDR PN2DDR PN1DDR PN0DDR PHDR - - - - PH3DR PH2DR PH1DR PH0DR PJDR PJ7DR PJ6DR PJ5DR PJ4DR PJ3DR PJ2DR PJ1DR PJ0DR PKDR PK7DR PK6DR PK5DR PK4DR PK3DR PK2DR PK1DR PK0DR PMDDR* PNDDR* PLDR PL7DR PL6DR PL5DR PL4DR PL3DR PL2DR PL1DR PL0DR 1 PM7DR PM6DR PM5DR PM4DR PM3DR PM2DR PM1DR PM0DR 1 PMDR* PNDR* PN7DR PN6DR PN5DR PN4DR PN3DR PN2DR PN1DR PN0DR PORTH PH7 - - - PH3 PH2 PH1 PH0 PORTJ PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PORTK PK7 PK6 PK5 PK4 PK3 PK2 PK1 PK0 PORTL PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 1 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0 1 PN7 PN6 PN5 PN4 PN3 PN2 PN1 PN0 PJ7PCR PJ6PCR PJ5PCR PJ4PCR PJ3PCR PJ2PCR PJ1PCR PJ0PCR PORTM* PORTN* PJPCR WPCR WPC7 WPC6 WPC5 WPC4 WPC3 WPC2 WPC1 WPC0 IWPR IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 INT IENWP - - - - - - - DADR_0* 1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DADR_1* 1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DAOE1 DAOE0 DAE - - - - - - - - IIC, FLASH IENR1 DACR* 1 SCRX - IICX1* 2 IICX0 IICE FLSHE* 1 D/A - - - - CLR3 CLR2 CLR1 CLR0 IIC 1 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMR_2 TCR_3*1 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMR_3 CMFB CMFA OVF - OS3 OS2 OS1 OS0 TMR_2 DDCSWR TCR_2* TCSR_2*1 CMFB CMFA OVF - OS3 OS2 OS1 OS0 TMR_3 TCORA_2* 1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TMR_2 TCORA_3* 1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TMR_3 TCORB_2* 1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TMR_2 TCORB_3* 1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TMR_3 TCSR_3* 1 Rev. 3.00, 08/03, page 530 of 612 Register Name Bit 7 TCNT_2* 1 TCNT_3* 1 Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TMR_2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TMR_3 SMR_2 C/A CHR PE O/E STOP MP CKS1 CKS0 SCI_2 SMR_2 GM BLK PE O/E BCP1 BCP0 CKS1 CKS0 BRR_2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCR_2 TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDR_2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SSR_2 TDRE RDRF ORER FER PER TEND MPB MPBT SSR_2 TDRE RDRF ORER ERS PER TEND MPB MPBT RDR_2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCMR_2 - - - - SDIR SINV - SMIF SBYCR SSBY STS2 STS1 STS0 - - - - SYSCR - - INTM1 INTM0 NMIEG - - - SCKCR - - - - - SCK2 SCK1 SCK0 MDCR - - - - - MDS2 MDS1 - MSTPCRA MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 MSTPCRB MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 SYSTEM MSTPCRC MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 LPWRCR DTON LSON NESEL SUBSTP RFCUT - STC1 STC0 SEMR0 - - - - ABCS ACS2 ACS1 ACS0 SCI_0 1 - - - - - - - - PBC BAA23 BAA22 BAA21 BAA20 BAA19 BAA18 BAA17 BAA16 BAA15 BAA14 BAA13 BAA12 BAA11 BAA10 BAA9 BAA8 BAA7 BAA6 BAA5 BAA4 BAA3 BAA2 BAA1 BAA0 - - - - - - - - BAB23 BAB22 BAB21 BAB20 BAB19 BAB18 BAB17 BAB16 BAB15 BAB14 BAB13 BAB12 BAB11 BAB10 BAB9 BAB8 BARA* BARB* 1 BAB7 BAB6 BAB5 BAB4 BAB3 BAB2 BAB1 BAB0 BCRA* 1 CMFA CDA BAMRA2 BAMRA1 BAMRA0 CSELA1 CSELA0 BIEA BCRB* 1 CMFB CDB BAMRB2 BAMRB1 BAMRB0 CSELB0 BIEB ISCRH - - - - IRQ5SCB* IRQ5SCA* IRQ4SCB IRQ4SCA ISCRL IRQ3SCB IRQ3SCA - IER - - ISR - - 2 - IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA 2 IRQ4E IRQ3E - IRQ1E IRQ0E 2 IRQ4F IRQ3F - IRQ1F IRQ0F IRQ5E* IRQ5F* CSELB1 2 INT Rev. 3.00, 08/03, page 531 of 612 Register Name Bit 7 DTCER* 1 DTVECR* 1 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0 DTC SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR P3DDR - - P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR P7DDR P77DDR P76DDR P75DDR P74DDR P73DDR P72DDR P71DDR P70DDR PFDDR - - - - PF3DDR - - - P3ODR - - P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR TSTR - - - - - CST2 CST1 CST0*2 TSYR - - - - - SYNC2 SYNC1 SYNC0* IPRA* 1 - IPR6 IPR5 IPR4 - IPR2 IPR1 IPR0 IPRB* 1 - IPR6 IPR5 IPR4 - IPR2 IPR1 IPR0 IPRC* 1 - - - - - IPR2 IPR1 IPR0 IPRD* 1 - IPR6 IPR5 IPR4 - - - - 1 - IPR6 IPR5 IPR4 - IPR2 IPR1 IPR0 1 - IPR6 IPR5 IPR4 - IPR2 IPR1 IPR0 1 - IPR6 IPR5 IPR4 - - - - IPR5 IPR4 - IPR2 IPR1 IPR0 IPRE* IPRF* IPRG* PORT TPU 2 INT - IPR6 1 - - - - - IPR2 IPR1 IPR0 IPRK*1 - IPR6 IPR5 IPR4 - IPR2 IPR1 IPR0 1 - IPR6 IPR5 IPR4 - IPR2 IPR1 IPR0 - IPR6 IPR5 IPR4 - IPR2 IPR1 IPR0 - IPR6 IPR5 IPR4 - - - - - - - - RAMS RAM2 RAM1 RAM0 FLASH P1DR P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR PORT P3DR - - P35DR P34DR P33DR P32DR P31DR P30DR IPRI* 1 IPRJ* IPRL* IPRM* IPRO* 1 1 RAMER* 1 P7DR P77DR P76DR P75DR P74DR P73DR P72DR P71DR P70DR PFDR - - - - PF3DR - - - CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TCR_0*1 TMDR_0* - - BFB BFA MD3 MD2 MD1 MD0 1 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 1 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 TTGE - - TCIEV TGIED TGIEC TGIEB TGIEA - - - TCFV TGFD TGFC TGFB TGFA 1 TIORH_0* TIORL_0* TIER_0* TSR_0* 1 1 Rev. 3.00, 08/03, page 532 of 612 TPU_0 Register Name Bit 7 TCNT_0* 1 1 TGRA_0* 1 TGRB_0* TGRC_0* 1 TGRD_0* 1 Bit15 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TPU_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TCR_1 - CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_1 - - - - MD3 MD2 MD1 MD0 TIOR_1 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TTGE - TCIEU* TCIEV - - TGIEB TGIEA 2 TCFV - - TGFB TGFA TIER_1 2 TSR_1 TCFD* - TCFU* TCNT_1 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TCR_2 - CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_2 - - - - MD3 MD2 MD1 MD0 TIOR_2 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TTGE - TCIEU* TCIEV - - TGIEB TGIEA 2 TGRA_1 TGRB_1 TIER_2 2 2 TSR_2 TCFD* - TCFU* TCFV - - TGFB TGFA TCNT_2 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TGRA_2 TGRB_2 TCR_0 2 TPU_1 TPU_2 TMR_0 Rev. 3.00, 08/03, page 533 of 612 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TCR_1 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMR_1 TCSR_0 CMFB CMFA OVF ADTE OS3 OS2 OS1 OS0 TMR_0 TCSR_1 CMFB CMFA OVF - OS3 OS2 OS1 OS0 TMR_1 TCORA_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TMR_0 TCORA_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TMR_1 TCORB_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TMR_0 TCORB_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TMR_1 TCNT_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TMR_0 TCNT_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TMR_1 WDT_0 TCSR_0 OVF WT/IT TME - - CKS2 CKS1 CKS0 TCNT_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RSTCSR WOVF RSTE - - - - - - SMR_0 C/A CHR PE O/E STOP MP CKS1 CKS0 SMR_0 GM BLK PE O/E BCP1 BCP0 CKS1 CKS0 ICCR_0 ICE IEIC MST TRS ACKE BBSY IRIC SCP IIC_0 BRR_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCI_0 ICSR_0 ESTP STOP IRTR AASX AL AAS ADZ ACKB IIC_0 SCR_0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 SCI_0 TDR_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SSR_0 TDRE RDRF ORER FER PER TEND MPB MPBT SSR_0 TDRE RDRF ORER ERS PER TEND MPB MPBT RDR_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCMR_0 - - - - SDIR SINV - SMIF ICDR_0/ ICDR7/ ICDR6/ ICDR5/ ICDR4/ ICDR3/ ICDR2/ ICDR1/ ICDR0/FSX SARX_0 SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 ICMR_0/ MLS/SVA6 WAIT/SVA5 CKS2/SVA4 CKS1/SVA3 CKS0/SVA2 BC2/SVA1 BC1/SVA0 BC0/FS C/A CHR PE O/E STOP MP CKS1 CKS0 GM BLK PE O/E BCP1 BCP0 CKS1 CKS0 ICE IEIC MST TRS ACKE BBSY IRIC SCP IIC_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCI_1 SCI_0 IIC_0 SAR_0 SMR_1 SMR_1 ICCR_1* 1 BRR_1 ICSR_1* 1 SCI_1 ESTP STOP IRTR AASX AL AAS ADZ ACKB IIC_1 SCR_1 TIE RIE TE RE MPIE TEIE CKE1 CKE0 SCI_1 TDR_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Rev. 3.00, 08/03, page 534 of 612 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module SSR_1 TDRE RDRF ORER FER PER TEND MPB MPBT SCI_1 SSR_1 TDRE RDRF ORER ERS PER TEND MPB MPBT RDR_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCMR_1 - - - - SDIR SINV - SMIF ICDR_1/ ICDR7/ ICDR6/ ICDR5/ ICDR4/ ICDR3/ ICDR2/ ICDR1/ ICDR0/FSX SARX_1*1 SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 ICMR_1/ MLS/SVA6 WAIT/SVA5 CKS2/SVA4 CKS1/SVA3 CKS0/SVA2 BC2/SVA1 BC1/SVA0 BC0/FS ADDRAH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADDRAL AD1 AD0 - - - - - - ADDRBH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADDRBL AD1 AD0 - - - - - - ADDRCH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADDRCL AD1 AD0 - - - - - - ADDRDH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADDRDL AD1 AD0 - - - - - - ADCSR ADF ADIE ADST SCAN CH3 CH2 CH1 CH0 ADCR TRGS1 TRGS0 - - CKS1 CKS0 - - TCSR_1 OVF WT/IT TME PSS RST/NMI CKS2 CKS1 CKS0 IIC_1 SAR_1*1 TCNT_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 FLMCR1* 1 FWE SWE1 ESU1 PSU1 EV1 PV1 E1 P1 FLMCR2* 1 FLER - - - - - - - EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 - - - - EB11 EB10 EB9 EB8 PDWND - - - - - - - PORT1 P17 P16 P15 P14 P13 P12 P11 P10 PORT3 - - P35 P34 P33 P32 P31 P30 PORT4 P47 P46 P45 P44 P43 P42 P41 P40 PORT7 P77 P76 P75 P74 P73 P72 P71 P70 PORT9 P97 P96 - - - - - - PORTF - - - - PF3 - - - EBR1* 1 EBR2* 1 FLPWCR* 1 A/D WDT_1 FLASH PORT Notes: 1. Supported only by the H8S/2268 Group. 2. Reserved in the H8S/2264 Group. Rev. 3.00, 08/03, page 535 of 612 24.3 Register States in Each Operating Mode Register Name Reset High -speed Mediumspeed Sleep Module Stop Watch Subactive Software Subsleep Standby Hardware Standby Module MRA* - - - - - - - - - - SAR* - - - - - - - - - - MRB* - - - - - - - - - - DAR* - - - - - - - - - - CRA* - - - - - - - - - - CRB* - - - - - - - - - - LPCR Initialized - - - - - - - - Initialized LCR Initialized - - - - - - - - Initialized LCR2 Initialized - - - - - - - - Initialized LCD RAM - - - - - - - - - - MSTPCRD Initialized - - - - - - - - Initialized SYSTEM DTCR* Initialized - - - - - - - - Initialized DTMF DTLR* Initialized - - - - - - - - Initialized TCR_4* Initialized - - - - - - - - Initialized TCR_5* Initialized - - - - - - - - Initialized TCR_6* Initialized - - - - - - - - Initialized TCR_7* Initialized - - - - - - - - Initialized TCNT_4/ Initialized - - - - - - - - Initialized Initialized - - - - - - - - Initialized Initialized - - - - - - - - Initialized Initialized - - - - - - - - Initialized PHDDR Initialized - - - - - - - - Initialized PJDDR Initialized - - - - - - - - Initialized PKDDR Initialized - - - - - - - - Initialized PLDDR Initialized - - - - - - - - Initialized PMDDR* Initialized - - - - - - - - Initialized PNDDR* Initialized - - - - - - - - Initialized PHDR Initialized - - - - - - - - Initialized PJDR Initialized - - - - - - - - Initialized DTC LCD TMR_4 TLR_4* TCNT_5/ TLR_5* TCNT_6/ TLR_6* TCNT_7/ TLR_7* Rev. 3.00, 08/03, page 536 of 612 PORT Register Name Reset High -speed Mediumspeed Sleep Module Stop Watch Subactive Software Subsleep Standby Hardware Standby Module PKDR Initialized - - - - - - - - Initialized PLDR Initialized - - - - - - - - Initialized PMDR* Initialized - - - - - - - - Initialized PNDR* Initialized - - - - - - - - Initialized PORTH Initialized - - - - - - - - Initialized PORTJ Initialized - - - - - - - - Initialized PORTK Initialized - - - - - - - - Initialized PORTL Initialized - - - - - - - - Initialized PORTM* Initialized - - - - - - - - Initialized PORTN* Initialized - - - - - - - - Initialized PJPCR Initialized - - - - - - - - Initialized WPCR Initialized - - - - - - - - Initialized IWPR Initialized - - - - - - - - Initialized IENR1 Initialized - - - - - - - - Initialized DADR_0* Initialized - - - - - - - - Initialized DADR_1* Initialized - - - - - - - - Initialized DACR Initialized - - - - - - - - Initialized SCRX Initialized - - - - - - - - Initialized IIC, FLASH DDCSWR Initialized - - - - - - - - Initialized IIC TCR_2* Initialized - - - - - - - - Initialized TMR_2 TCR_3* Initialized - - - - - - - - Initialized TMR_3 TCSR_2* Initialized - - - - - - - - Initialized TMR_2 TCSR_3* Initialized - - - - - - - - Initialized TMR_3 TCORA_2* Initialized - - - - - - - - Initialized TMR_2 TCORA_3* Initialized - - - - - - - - Initialized TMR_3 TCORB_2* Initialized - - - - - - - - Initialized TMR_2 TCORB_3* Initialized - - - - - - - - Initialized TMR_3 TCNT_2* Initialized - - - - - - - - Initialized TMR_2 TCNT_3* Initialized - - - - - - - - Initialized TMR_3 SMR_2 Initialized - - - - - - - - Initialized SCI_2 BRR_2 Initialized - - - - - - - - Initialized SCR_2 Initialized - - - - - - - - Initialized TDR_2 Initialized - - - Initialized Initialized Initialized Initialized Initialized Initialized SSR_2 Initialized - - - Initialized Initialized Initialized Initialized Initialized Initialized PORT INT D/A Rev. 3.00, 08/03, page 537 of 612 Register Name Reset High -speed Mediumspeed Sleep Module Stop Watch Software Subsleep Standby Hardware Standby Module RDR_2 Initialized - - - Initialized Initialized Initialized Initialized Initialized Initialized SCMR_2 Initialized - - - SBYCR Initialized - - - - - - - - Initialized - - - - - Initialized SYSCR Initialized - - - - - - - - Initialized SCKCR Initialized - - - - - - - - Initialized MDCR Initialized - - - - - - - - Initialized MSTPCRA Initialized - - - - - - - - Initialized MSTPCRB Initialized - - - - - - - - Initialized MSTPCRC Initialized - - - - - - - - Initialized LPWRCR Initialized - - - - - - - - Initialized SEMR_0 Initialized - - - - - - - - Initialized SCI_0 BARA* Initialized - - - - - - - - Initialized PBC BARB* Initialized - - - - - - - - Initialized BCRA* Initialized - - - - - - - - Initialized BCRB* Initialized - - - - - - - - Initialized ISCRH Initialized - - - - - - - - Initialized ISCRL Initialized - - - - - - - - Initialized IER Initialized - - - - - - - - Initialized ISR Initialized - - - - - - - - Initialized DTCER* Initialized - - - - - - - - Initialized DTVECR* Initialized - - - - - - - - Initialized P1DDR Initialized - - - - - - - - Initialized P3DDR Initialized - - - - - - - - Initialized P7DDR Initialized - - - - - - - - Initialized PFDDR Initialized - - - - - - - - Initialized P3ODR Initialized - - - - - - - - Initialized TSTR Initialized - - - - - - - - Initialized TSYR Initialized - - - - - - - - Initialized IPRA* Initialized - - - - - - - - Initialized IPRB* Initialized - - - - - - - - Initialized IPRC* Initialized - - - - - - - - Initialized IPRD* Initialized - - - - - - - - Initialized IPRE* Initialized - - - - - - - - Initialized IPRF* Initialized - - - - - - - - Initialized Rev. 3.00, 08/03, page 538 of 612 Subactive SCI_2 SYSTEM INT DTC PORT TPU INT Register Name Reset High -speed Mediumspeed Sleep Module Stop Watch Subactive Software Subsleep Standby Hardware Standby Module IPRG* Initialized - - - - - - - - Initialized IPRI* Initialized - - - - - - - - Initialized IPRJ* Initialized - - - - - - - - Initialized IPRK* Initialized - - - - - - - - Initialized IPRL* Initialized - - - - - - - - Initialized IPRM* Initialized - - - - - - - - Initialized IPRO* Initialized - - - - - - - - Initialized RAMER* Initialized - - - - - - - - Initialized FLASH P1DR Initialized - - - - - - - - Initialized PORT P3DR Initialized - - - - - - - - Initialized P7DR Initialized - - - - - - - - Initialized PFDR Initialized - - - - - - - - Initialized TCR_0* Initialized - - - - - - - - Initialized TMDR_0* Initialized - - - - - - - - Initialized TIORH_0* Initialized - - - - - - - - Initialized TIORL_0* Initialized - - - - - - - - Initialized TIER_0* Initialized - - - - - - - - Initialized TSR_0* Initialized - - - - - - - - Initialized TCNT_0* Initialized - - - - - - - - Initialized TGRA_0* Initialized - - - - - - - - Initialized TGRB_0* Initialized - - - - - - - - Initialized TGRC_0* Initialized - - - - - - - - Initialized TGRD_0* Initialized - - - - - - - - Initialized TCR_1 Initialized - - - - - - - - Initialized TMDR_1 Initialized - - - - - - - - Initialized TIOR_1 Initialized - - - - - - - - Initialized TIER_1 Initialized - - - - - - - - Initialized TSR_1 Initialized - - - - - - - - Initialized TCNT_1 Initialized - - - - - - - - Initialized TGRA_1 Initialized - - - - - - - - Initialized TGRB_1 Initialized - - - - - - - - Initialized TCR_2 Initialized - - - - - - - - Initialized TMDR_2 Initialized - - - - - - - - Initialized TIOR_2 Initialized - - - - - - - - Initialized INT TPU_0 TPU_1 TPU_2 Rev. 3.00, 08/03, page 539 of 612 Register Name Reset High -speed Mediumspeed Sleep Module Stop Watch Software Subactive Subsleep Standby Hardware Standby Module TIER_2 Initialized - - - - - - - - Initialized TPU_2 TSR_2 Initialized - - - - - - - - Initialized TCNT_2 Initialized - - - - - - - - Initialized TGRA_2 Initialized - - - - - - - - Initialized TGRB_2 Initialized - - - - - - - - Initialized TCR_0 Initialized - - - - - - - - Initialized TMR_0 TCR_1 Initialized - - - - - - - - Initialized TMR_1 TCSR_0 Initialized - - - - - - - - Initialized TMR_0 TCSR_1 Initialized - - - - - - - - Initialized TMR_1 TCORA_0 Initialized - - - - - - - - Initialized TMR_0 TCORA_1 Initialized - - - - - - - - Initialized TMR_1 TCORB_0 Initialized - - - - - - - - Initialized TMR_0 TCORB_1 Initialized - - - - - - - - Initialized TMR_1 TCNT_0 Initialized - - - - - - - - Initialized TMR_0 TCNT_1 Initialized - - - - - - - - Initialized TMR_1 TCSR_0 Initialized - - - - - - - - Initialized WDT_0 TCNT_0 Initialized - - - - - - - - Initialized RSTCSR Initialized - - - - - - - - Initialized SMR_0 Initialized - - - - - - - - Initialized SCI_0 ICCR_0 Initialized - - - - - - - - Initialized IIC_0 BRR_0 Initialized - - - - - - - - Initialized SCI_0 ICSR_0 Initialized - - - - - - - - Initialized IIC_0 SCR_0 Initialized - - - - - - - - Initialized SCI_0 TDR_0 Initialized - - - Initialized Initialized Initialized Initialized Initialized Initialized SSR_0 Initialized - - - Initialized Initialized Initialized Initialized Initialized Initialized RDR_0 Initialized - - - Initialized Initialized Initialized Initialized Initialized Initialized SCMR_0 Initialized - - - - - - - - Initialized ICDR_0/ Initialized - - - - - - - - Initialized Initialized - - - - - - - - Initialized SMR_1 Initialized - - - - - - - - Initialized SCI_1 ICCR_1* Initialized - - - - - - - - Initialized IIC_1 BRR_1 Initialized - - - - - - - - Initialized SCI_1 IIC_0 SARX_0 ICMR_0/ SAR_0 Rev. 3.00, 08/03, page 540 of 612 Register Name Reset High -speed Mediumspeed Sleep Module Stop Watch Software Hardware Subactive Subsleep Standby Standby Module ICSR_1* Initialized - - - - - - - - Initialized IIC_1 SCR_1 Initialized - - - - - - - - Initialized SCI_1 TDR_1 Initialized - - - Initialized Initialized Initialized Initialized Initialized Initialized SSR_1 Initialized - - - Initialized Initialized Initialized Initialized Initialized Initialized RDR_1 Initialized - - - Initialized Initialized Initialized Initialized Initialized Initialized SCMR_1 Initialized - - - - - - - - Initialized ICDR_1/ Initialized - - - - - - - - Initialized Initialized - - - - - - - - Initialized ADDRAH Initialized - - - Initialized Initialized Initialized Initialized Initialized Initialized ADDRAL Initialized - - - Initialized Initialized Initialized Initialized Initialized Initialized ADDRBH Initialized - - - Initialized Initialized Initialized Initialized Initialized Initialized ADDRBL Initialized - - - Initialized Initialized Initialized Initialized Initialized Initialized ADDRCH Initialized - - - Initialized Initialized Initialized Initialized Initialized Initialized ADDRCL Initialized - - - Initialized Initialized Initialized Initialized Initialized Initialized ADDRDH Initialized - - - Initialized Initialized Initialized Initialized Initialized Initialized ADDRDL Initialized - - - Initialized Initialized Initialized Initialized Initialized Initialized ADCSR Initialized - - - Initialized Initialized Initialized Initialized Initialized Initialized ADCR Initialized - - - Initialized Initialized Initialized Initialized Initialized Initialized TCSR_1 Initialized - - - - - - - - Initialized TCNT_1 Initialized - - - - - - - - Initialized FLMCR1* Initialized - - - - - - - Initialized Initialized FLMCR2* Initialized - - - - - - - Initialized Initialized EBR1* Initialized - - - - - - - Initialized Initialized EBR2* Initialized - - - - - - - Initialized Initialized FLPWCR* Initialized - - - - - - - Initialized Initialized PORT1 Initialized - - - - - - - - Initialized PORT3 Initialized - - - - - - - - Initialized PORT4 Initialized - - - - - - - - Initialized PORT7 Initialized - - - - - - - - Initialized PORT9 Initialized - - - - - - - - Initialized PORTF Initialized - - - - - - - - Initialized IIC_1 SARX_1* ICMR_1/ SAR_1* Notes: - * A/D WDT_1 FLASH PORT is not initialized. Supported only by the H8S/2268 Group. Rev. 3.00, 08/03, page 541 of 612 Rev. 3.00, 08/03, page 542 of 612 Section 25 Electrical Characteristics 25.1 Power Supply Voltage and Operating Frequency Range Power supply voltage and operating frequency ranges (shaded areas) are shown in figure 25.1. Condition A (F-ZTAT version): Vcc = 3.0 to 5.5 V, AVcc = 2.7 to 5.5 V, Vref = 2.7 V to AVcc, Vss = AVss = 0 V, = 32.768 kHz, 2 to 13.5 MHz, Ta = -20 to +75 (regular specification), Ta = -40 to + 85 (wide range specification) Condition B (masked ROM version): Vcc = 2.7 to 5.5 V, AVcc = 2.7 to 5.5 V, Vref = 2.7 V to AVcc, Vss = AVss = 0 V, = 32.768 kHz, 2 to 13.5 MHz, Ta = -20 to +75 (regular specification), Condition C (F-ZTAT version): Ta = -40 to + 85 (wide range specification) Vcc = 4.0 to 5.5 V, AVcc = 4.0 to 5.5 V, Vref = 4.0 V to AVcc, Vss = AVss = 0 V, = 32.768 kHz, 10 to 20.5 MHz, Ta = -20 to +75 (regular specification), Ta = -40 to + 85 (wide range specification) Condition D (masked ROM version): Vcc = 4.0 to 5.5 V, AVcc = 4.0 to 5.5 V, Vref = 4.0 V to AVcc, Vss = AVss = 0 V, = 32.768 kHz, 10 to 20.5 MHz, Ta = -20 to +75 (regular specification), Ta = -40 to +85 (wide range specification) (1) Power supply voltage and range of oscillation frequency (condition A) f (kHz) f (MHz) System clock 32.768 20.5 Sub clock 13.5 2.0 0 2.7 3.0 4.0 5.5 Vcc (V) Active (high-speed/medium-speed) mode Sleep mode 0 2.7 3.0 AII operating modes 4.0 5.5 Vcc (V) 4.0 5.5 Vcc (V) (2) Power supply voltage and range of oscillation frequency (condition B) f (MHz) 20.5 System clock f (kHz) 32.768 Sub clock 0 2.7 3.0 AII operating modes 13.5 2.0 0 2.7 3.0 4.0 5.5 Vcc (V) Active (high-speed/medium-speed) mode Sleep mode Figure 25.1 Power Supply Voltage and Operating Ranges (1) Rev. 3.00, 08/03, page 543 of 612 (3) Power supply voltage and range of oscillation frequency (condition C and D) f (MHz) f (kHz) System clock 20.5 32.768 Sub clock 13.5 10.0 2.0 0 2.7 3.0 4.0 5.5 Vcc (V) Active (high-speed/medium-speed) mode Sleep mode 0 2.7 3.0 AII operating modes (4) Power supply voltage and range of instruction execution (condition A) t (ns) t (s) System clock 48.8 30.5 4.0 5.5 Vcc (V) 4.0 5.5 Vcc (V) 4.0 5.5 Vcc (V) 4.0 5.5 Vcc (V) Sub clock 74 500 0 2.7 3.0 4.0 5.5 Vcc (V) Active (high-speed/medium-speed) mode 0 2.7 3.0 Subactive mode (5) Power supply voltage and range of instruction execution (condition B) t (ns) t (s) System clock 48.8 30.5 Sub clock 74 500 0 2.7 3.0 4.0 5.5 Vcc (V) Active (high-speed/medium-speed) mode 0 2.7 3.0 Subactive mode (6) Power supply voltage and range of instruction execution (condition C and D) t (ns) t (s) System clock 48.8 30.5 Sub clock 74 100 500 0 2.7 3.0 4.0 5.5 Vcc (V) Active (high-speed/medium-speed) mode 0 2.7 3.0 Subactive mode Figure 25.1 Power Supply Voltage and Operating Ranges (2) Rev. 3.00, 08/03, page 544 of 612 25.2 Electrical Characteristics of H8S/2268 Group 25.2.1 Absolute Maximum Ratings Table 25.1 lists the absolute maximum ratings. Table 25.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC -0.3 to +7.0 V CVCC -0.3 to +4.3 V Input voltage (except port 4, 9, PH7) Vin -0.3 to VCC +0.3 V Input voltage (port 4, 9, PH7) Vin -0.3 to AVCC +0.3 V Reference voltage Vref -0.3 to AVCC +0.3 V Analog power supply voltage AVCC -0.3 to +7.0 V Analog input voltage VAN -0.3 to AVCC +0.3 V Operating temperature Topr Regular specifications: -20 to +75* C Wide-range specifications: -40 to +85* C -55 to +125 C Storage temperature Caution: Note: * Tstg Permanent damage to the chip may result if absolute maximum rating are exceeded. Operating temperature range for flash memory programming/erasing is Ta = -20 to +75C. Rev. 3.00, 08/03, page 545 of 612 25.2.2 DC Characteristics Table 25.2 lists the DC characteristics. Table 25.3 lists the permissible output currents. Table 25.4 lists the bus drive characteristics. Table 25.2 DC Characteristics (1) Condition A (F-ZTAT version): VCC = 3.0 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C 1 to +85C (wide-range specifications)* Condition B (Masked-ROM version): VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C 1 to +85C (wide-range specifications)* Item Schmitt trigger input voltage Input high voltage Symbol Min. Typ. Max. Unit VCC x 0.2 V VCC x 0.8 V VCC x 0.05 V Vcc = 4.0 to 5.5 V VCC x 0.04 V Vcc = 2.7 to 4.0 V VCC x 0.9 VCC + 0.3 V VCC x 0.8 VCC + 0.3 V VCC x 0.8 AVCC + 0.3 V - 0.3 VCC x 0.1 V - 0.3 VCC x 0.2 V VCC - 0.5 V IOH = - 200 A VCC - 1.0 V IOH = - 1 mA P34 and P35*2 VCC - 2.7 V IOH = - 100 A VCC = 4.0 to 5.5 V PH0 to PH3, Port J to N VCC - 0.5 V IOH = - 200 A VCC - 1.0 V IOH = - 1 mA VCC = 4.0 to 5.5 V IRQ0, IRQ1, IRQ3 to IRQ5, WKP0 to WKP7 VT RES, STBY,NMI, FWE, MD2, MD1 VIH - VT+ + VT - VT EXTAL, Port 1, 3, 7, F, J to N, PH0 to PH3 Port 4, 9, PH7 Input low voltage RES, STBY, FWE, MD2, MD1 VIL NMI, EXTAL, Port 1, 3, 4, 7, 9, F, H, J to N Output high voltage All output pins except P34 and P35, PH0 to PH3, and Port J to N Rev. 3.00, 08/03, page 546 of 612 VOH - Test Conditions Item Output low voltage Symbol 3 All output pins* VOL Port 7 Min. Typ. Max. Unit Test Conditions 0.4 V IOL = - 0.8 mA 1.0 V IOL = 5 mA IOL = 10 mA, VCC = 4.0 to 5.5 V Input leakage current RES | lin | 1.0 A STBY, NMI, FWE, MD2, MD1 1.0 A Port 4, 9 1.0 A Vin = 0.5 to AVCC0.5 V PH7 1.0 A Vin = 0.5 to AVCC0.5 V Vin = 0.5 to VCC0.5 V Three-state leakage current (off state) Port 1, 3, 7, Port F, J to N, PH0 to PH3 | lTSI | 1.0 A Vin = 0.5 to AVCC0.5 V Input pull-up MOS current Port J -lP 10 300 A Vin = 0 V Notes: 1. If the A/D and D/A converters and DTMF generation circuit are not used, do not leave the AVCC, Vref , and AVSS pins open. Apply a voltage 2.0 V to 5.5 V to the AVCC and Vref pins by connecting them to VCC, for instance. Set Vref AVCC. 2. P35/SCK1/SCL0 and P34/SDA0 are NMOS push/pull outputs. To output high level signal from SCL0 and SDA0 (ICE = 1), pull-up resistance must be connected externally. P35/SCK1 and P34 (ICE = 0) are driven high by NMOS. To output high when VCC = 4.0V or less, pull-up resistance should be connected externally. 3. When ICE = 0. To output low when bus drive function is selected is determined in table 25.4, Bus Drive Characteristics. Rev. 3.00, 08/03, page 547 of 612 Table 25.2 DC Characteristics (2) Condition C (F-ZTAT version): VCC = 4.0V to 5.5 V, AVCC = 4.0V to 5.5V, Vref = 4.0V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to 1 +85C (wide-range specifications)* Condition D (Masked-ROM version): VCC = 4.0V to 5.5 V, AVCC = 4.0V to 5.5V, Vref = 4.0 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C 1 to +85C (wide-range specifications)* Item Schmitt trigger input voltage Input high voltage Symbol Min. Typ. Max. Unit VT- VCC x 0.2 V VCC x 0.8 V VCC x 0.05 V VCC x 0.9 VCC + 0.3 V VCC x 0.8 VCC + 0.3 V VCC x 0.8 VCC + 0.3 V - 0.3 VCC x 0.1 V - 0.3 VCC x 0.2 V VCC - 0.5 V IOH = - 200 A VCC - 1.0 V IOH = - 1 mA P34 and P35*2 VCC - 2.7 V IOH = - 100 A PH0 to PH3, Port J to N VCC - 0.5 V IOH = - 200 A VCC - 1.0 V IOH = - 1 mA 0.4 V IOL = 0.8 mA 1.0 V IOL = 10 mA Vin = 0.5 to VCC0.5 V IRQ0, IRQ1, IRQ3 to IRQ5, WKP0 to WKP7 RES, STBY,NMI, FWE, MD2, MD1 VT+ + VT - VT VIH EXTAL, Port 1, 3, 7, F, J to N, PH0 to PH3 Port 4, 9, PH7 Input low voltage RES, STBY,FWE, MD2, MD1 VIL NMI, EXTAL, Port 1, 3, 4, 7, 9, F, H, J to N Output high voltage All output pins except P34 and P35, PH0 to PH3, and Port J to N Output low voltage All output pins*3 Input leakage current RES VOH VOL Port 7 1.0 A STBY, NMI, FWE, MD2, MD1 1.0 A Port 4, 9 1.0 A Vin = 0.5 to AVCC0.5 V PH7 1.0 A Vin = 0.5 to AVCC0.5 V Rev. 3.00, 08/03, page 548 of 612 | lin | - Test Conditions Item Symbol Min. Typ. Max. Unit Test Conditions Three-state leakage current (off state) Port 1, 3, 7, Port F, J to N, PH0 to PH3 | lTSI | 1.0 A Vin = 0.5 to AVCC0.5 V Input pull-up MOS current Port J -lP 50 300 A Vin = 0 V Notes: 1. If the A/D and D/A converters and DTMF generation circuit are not used, do not leave the AVCC, Vref , and AVSS pins open. Apply a voltage 4.0 V to 5.5 V to the AVCC and Vref pins by connecting them to VCC, for instance. Set Vref AVCC. 2. P35/SCK1/SCL0 and P34/SDA0 are NMOS push/pull outputs. To output high level signal from SCL0 and SDA0 (ICE = 1), pull-up resistance must be connected externally. P35/SCK1 and P34 (ICE = 0) are driven high by NMOS. 3. When ICE = 0. To output low when bus drive function is selected is determined in table 25.4, Bus Drive Characteristics. Rev. 3.00, 08/03, page 549 of 612 Table 25.2 DC Characteristics (3) Condition A (F-ZTAT version): VCC = 3.0 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C 1 to +85C (wide-range specifications)* Item Input capacitance Symbol Min. Typ. Max. Unit Test Conditions 30 pF Vin = 0 V NMI 30 pF f = 1 MHz P32 to P35 20 pF Ta = 25C All input pins except RES, NMI, P32 to P35 15 pF 18 VCC = 3.0 V 30 VCC = 5.5 V mA f = 13.5 MHz Sleep mode 13 VCC = 3.0 V 22 VCC = 5.5 V mA f = 13.5 MHz All modules stopped 10 mA f = 13.5 MHz, VCC = 3.0 V (reference values) Medium-speed mode (/32) 12 mA f = 13.5 MHz, VCC = 3.0 V (reference values) Subactive mode 60 110 A Using 32.768 kHz crystal resonator RES Current Normal operation consumption*2 Cin ICC*4 Vcc = 3.0 V (LCD lighting) Subsleep mode 50 90 A Using 32.768 kHz crystal resonator Vcc = 3.0 V (LCD lighting) Watch mode 4 25 A Using 32.768 kHz crystal resonator Vcc = 3.0 V (LCD and TMR4 not used, WDT_1 operates) Rev. 3.00, 08/03, page 550 of 612 Item Symbol Min. 3 Current Standby mode* consumption*2 4 ICC* Analog power supply current During A/D conversion, D/A conversion, DTMF output AlCC Waiting for A/D conversion, D/A conversion, DTMF stopped Reference current During A/D conversion, D/A conversion AlCC Waiting for A/D conversion, D/A conversion RAM standby voltage VRAM Typ. Max. Unit Test Conditions 0.5 Vcc = 3.0 V 10 Vcc = 5.5 V A Ta 50C 50 Vcc = 5.5 V 32.768 kHz not used 50C < Ta 32.768 kHz not used 1.0 2.4 mA 0.01 5.0 A 1.0 2.2 mA 0.01 5.0 A 2.0 V Notes: 1. If the A/D and D/A converters and DTMF generation circuit are not used, do not leave the AVCC, Vref , and AVSS pins open. Apply a voltage 2.0 to 5.5 V to the AVCC and Vref pins by connecting them to VCC, for instance. Set Vref AVCC. 2. Current consumption values are for VIH min. = VCC - 0.2 V, VIL max. = 0.2 V with all output pins unloaded and the on-chip pull-up resistors in the off state. 3. The values are for VRAM VCC < 3.0 V, VIH min. = VCC - 0.2, and VIL max. = 0.2 V. 4. ICC depends on VCC and f as follows (reference): ICC max. = 4.0 (mA) + 0.64 (mA/V) x Vcc + 0.75 (mA/MHz) x f + 0.15 (mA/(MHz * V)) x VCC x f (normal operation) ICC max. = 3.0 (mA) + 0.60 (mA/V) x Vcc + 0.60 (mA/MHz) x f + 0.10 (mA/(MHz * V)) VCC x f (sleep mode) Rev. 3.00, 08/03, page 551 of 612 Table 25.2 DC Characteristics (4) Preliminary Condition B (Masked-ROM version): VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C 1 to +85C (wide-range specifications)* Item Input capacitance Symbol Min. Typ. Max. Unit Test Conditions Cin 30 pF Vin = 0 V NMI 30 pF f = 1 MHz P32 to P35 20 pF Ta = 25C All input pins except RES, NMI, P32 to P35 15 pF TBD VCC = 3.0V TBD mA VCC = 5.5V f = 13.5 MHz Sleep mode TBD VCC = 3.0V TBD mA VCC = 5.5V f = 13.5 MHz All modules stopped TBD mA f = 13.5 MHz, VCC = 3.0 V (reference values) Medium-speed mode (/32) TBD mA f = 13.5 MHz, VCC = 3.0 V (reference values) Subactive mode TBD TBD A Using 32.768 kHz crystal resonator RES Current Normal consumption*2 operation ICC*4 VCC = 3.0 V (LCD lighting) Subsleep mode TBD TBD A Using 32.768 kHz crystal resonator Vcc = 3.0 V (LCD lighting) Watch mode TBD TBD A Using 32.768 kHz crystal resonator VCC = 3.0 V (LCD and TMR4 not used, WDT_1 operates) Standby mode*3 Rev. 3.00, 08/03, page 552 of 612 TBD TBD A Vcc = 3.0 V Vcc = 5.5 V Ta 50C 50C < Ta TBD Vcc = 5.5 V 32.768 kHz not used 32.768 kHz not used Item Analog power supply current During A/D conversion, D/A conversion, DTMF output Symbol Min. Typ. Max. Unit AlCC TBD TBD mA TBD TBD A TBD TBD mA TBD TBD A 2.0 V Waiting for A/D conversion, D/A conversion, DTMF stopped Reference current During A/D conversion, D/A conversion AlCC Waiting for A/D conversion, D/A conversion RAM standby voltage VRAM Test Conditions Notes: 1. If the A/D and D/A converters and DTMF generation circuit are not used, do not leave the AVCC, Vref , and AVSS pins open. Apply a voltage 2.0 to 5.5 V to the AVCC and Vref pins by connecting them to VCC, for instance. Set Vref AVCC. 2. Current consumption values are for VIH min. = VCC - 0.2 V, VIL max. = 0.2 V with all output pins unloaded and the on-chip pull-up resistors in the off state. 3. The values are for VRAM VCC < 2.7 V, VIH min. = VCC - 0.2, and VIL max. = 0.2 V. 4. ICC depends on VCC and f as follows (reference): ICC max. = TBD (mA) + TBD (mA/V) x Vcc + TBD (mA/MHz) x f + TBD (mA/(MHz * V)) x VCC x f (normal operation) ICC max. = TBD (mA) + TBD (mA/V) x Vcc + TBD (mA/MHz) x f + TBD (mA/(MHz * V)) VCC x f (sleep mode) Rev. 3.00, 08/03, page 553 of 612 Table 25.2 DC Characteristics (5) Condition C (F-ZTAT version): VCC = 4.0V to 5.5 V, AVCC = 4.0V to 5.5V, Vref = 4.0V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to 1 +85C (wide-range specifications)* Item Input capacitance Symbol Min. Typ. Max. Unit Test Conditions 30 pF Vin = 0 V NMI 30 pF f = 1 MHz P32 to P35 20 pF Ta = 25C All input pins except RES, NMI, P32 to P35 15 pF 30 40 mA VCC = 5.0 V VCC = 5.5 V f = 20.5 MHz Sleep mode 22 30 mA VCC = 5.0 V VCC = 5.5 V f = 20.5 MHz All modules stopped 15 mA f = 20.5 MHz, VCC = 5.0 V (reference values) Medium-speed mode (/32) 19 mA f = 20.5 MHz, VCC = 5.0 V (reference values) Subactive mode 70 120 A Using 32.768 kHz crystal resonator RES Current Normal consumption*2 operation Cin ICC*4 Vcc = 5.0 V (LCD lighting) Subsleep mode 60 100 A Using 32.768 kHz crystal resonator Vcc = 5.0 V (LCD lighting) Watch mode 5 30 A Using 32.768 kHz crystal resonator Vcc = 5.0 V (LCD and TMR4 not used, WDT_1 operates) Standby mode*3 Rev. 3.00, 08/03, page 554 of 612 1.0 10 A Vcc = 5.0 V Vcc = 5.5 V Ta 50C 50C < Ta 50 Vcc = 5.5 V 32.768 kHz not used 32.768 kHz not used Item Analog power supply current Symbol Min. During A/D conversion, D/A conversion, DTMF output AlCC Waiting for A/D conversion, D/A conversion, DTMF stopped Reference current During A/D conversion, D/A conversion AlCC Waiting for A/D conversion, D/A conversion RAM standby voltage VRAM Typ. Max. Unit 1.5 2.5 mA 0.01 5.0 A 1.5 2.2 mA 0.01 5.0 A 2.0 V Test Conditions Notes: 1. If the A/D and D/A converters and DTMF generation circuit are not used, do not leave the AVCC, Vref , and AVSS pins open. Apply a voltage 4.0 to 5.5 V to the AVCC and Vref pins by connecting them to VCC, for instance. Set Vref AVCC. 2. Current consumption values are for VIH min. = VCC - 0.2 V, VIL max. = 0.2 V with all output pins unloaded and the on-chip pull-up resistors in the off state. 3. The values are for VRAM VCC < 4.0 V, VIH min. = VCC - 0.2, and VIL max. = 0.2 V. 4. ICC depends on VCC and f as follows (reference): ICC max. = 4.0 (mA) + 0.64 (mA/V) x Vcc+ 0.75 (mA/MHz) x f + 0.15 (mA/(MHz * V)) x VCC x f (normal operation) ICC max. = 3.0 (mA) + 0.60 (mA/V) x Vcc+ 0.60 (mA/MHz) x f + 0.10 (mA/(MHz * V)) VCC x f (sleep mode) Rev. 3.00, 08/03, page 555 of 612 Table 25.2 DC Characteristics (6) Preliminary Condition D (Masked-ROM version): VCC = 4.0V to 5.5 V, AVCC = 4.0V to 5.5V, Vref = 4.0 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C 1 to +85C (wide-range specifications)* Item Input capacitance Symbol Min. Typ. Max. Unit Test Conditions Cin 30 pF Vin = 0 V NMI 30 pF f = 1 MHz P32 to P35 20 pF Ta = 25C All input pins except RES, NMI, P32 to P35 15 pF TBD TBD mA VCC = 5.0 V VCC = 5.5 V f = 20.5 MHz Sleep mode TBD TBD mA VCC = 5.0 V VCC = 5.5 V f = 20.5 MHz All modules stopped TBD mA f = 20.5 MHz, VCC = 5.0 V (reference values) Medium-speed mode (/32) TBD mA f = 20.5 MHz, VCC = 5.0 V (reference values) Subactive mode TBD TBD A Using 32.768 kHz crystal resonator RES Current Normal operation consumption*2 ICC*4 Vcc = 5.0 V (LCD lighting) Subsleep mode TBD TBD A Using 32.768 kHz crystal resonator Vcc = 5.0 V (LCD lighting) Watch mode TBD TBD A Using 32.768 kHz crystal resonator Vcc = 5.0 V (LCD and TMR4 not used, WDT_1 operates) Standby mode*3 Rev. 3.00, 08/03, page 556 of 612 TBD TBD A Vcc = 5.0 V Vcc = 5.5 V Ta 50C 50C < Ta TBD Vcc = 5.5 V 32.768 kHz not used 32.768 kHz not used Item Analog power supply current During A/D conversion, D/A conversion, DTMF output Symbol Min. Typ. Max. Unit AlCC TBD TBD mA TBD TBD A TBD TBD mA TBD TBD A 2.0 V Waiting for A/D conversion, D/A conversion, DTMF stopped Reference current During A/D conversion, D/A conversion AlCC Waiting for A/D conversion, D/A conversion RAM standby voltage VRAM Test Conditions Notes: 1. If the A/D and D/A converters and DTMF generation circuit are not used, do not leave the AVCC, Vref , and AVSS pins open. Apply a voltage 4.0 to 5.5 V to the AVCC and Vref pins by connecting them to VCC, for instance. Set Vref AVCC. 2. Current consumption values are for VIH min. = VCC - 0.2 V, VIL max. = 0.2 V with all output pins unloaded and the on-chip pull-up resistors in the off state. 3. The values are for VRAM VCC < 4.0 V, VIH min. = VCC - 0.2, and VIL max. = 0.2 V. 4. ICC depends on VCC and f as follows (reference): ICC max. = TBD (mA) + TBD (mA/V) x Vcc + TBD (mA/MHz) x f + TBD (mA/(MHz * V)) x VCC x f (normal operation) ICC max. = TBD (mA) + TBD (mA/V) x Vcc + TBD (mA/MHz) x f + TBD (mA/(MHz * V)) VCC x f (sleep mode) Rev. 3.00, 08/03, page 557 of 612 Table 25.3 Permissible Output Currents Condition A (F-ZTAT version): VCC = 3.0 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition B (Masked-ROM version): VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition C (F-ZTAT version): VCC = 4.0V to 5.5 V, AVCC = 4.0V to 5.5V, Vref = 4.0V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition D (Masked-ROM version): VCC = 4.0V to 5.5 V, AVCC = 4.0V to 5.5V, Vref = 4.0V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Permissible output low current (per pin) Permissible output low current (total) Symbol Min. Typ. Max. Unit IOL 10 mA SCL1, SCL0, SDA1, SDA0 10 mA Output pins except port 7, SCL1, SCL0, SDA1, SDA0 1.0 mA Port 7 Total of port 7 IOL Total of all output pins including port 7 30 mA 60 mA Permissible output All output pins high current (per pin) -IOH 1.0 mA Permissible output high current (total) -IOH 30 mA Total of all output pins Note: To protect chip reliability, do not exceed the output current values in table 25.3. Rev. 3.00, 08/03, page 558 of 612 Table 25.4 Bus Drive Characteristics (1) Condition A (F-ZTAT version): VCC = 3.0 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C 1 to +85C (wide-range specifications)* , Target pins: SCL1, SCL0, SDA1, SDA0 Condition B (Masked-ROM version): VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C 1 to +85C (wide-range specifications)* , Target pins: SCL1, SCL0, SDA1, SDA0 Item Symbol Schmitt trigger input voltage VT + VT + - VT - VT Min. Typ. Max. Unit VCC x 0.3 V VCC x 0.7 0.4 VCC= 4.0 to 5.5 V VCC x 0.05 VCC=2.7 to 4.0 V Input high voltage VIH VCC x 0.7 VCC + 0.5 V Input low voltage VIL -0.5 VCC x 0.3 V Output low voltage VOL 0.5 V 0.4 Test Conditions IOL=8 mA, VCC=4.0 to 5.5 V IOL=3mA Input capacitance CIN 20 pF VIN=0 V, f=1 MHz, Ta=25C Three-state leakage current (off state) | lSTI | 1.0 A VIN=0.5 to VCC-0.5 SDL, SDA output fall time tOf 20 + 0.1Cb 250 ns Note: If the A/D and D/A converters and DTMF generation circuit are not used, do not leave the AVCC, Vref , and AVSS pins open. Apply a voltage 2.0 V to 5.5 V to the AVCC and Vref pins by connecting them to VCC, for instance. Set Vref AVCC Rev. 3.00, 08/03, page 559 of 612 Table 25.4 Bus Drive Characteristics (2) Condition C (F-ZTAT version): VCC = 4.0V to 5.5 V, AVCC = 4.0V to 5.5V, Vref = 4.0V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to 1 +85C (wide-range specifications)* , Target pins: SCL1, SCL0, SDA1, SDA0 Condition D (Masked-ROM version): VCC = 4.0V to 5.5 V, AVCC = 4.0V to 5.5V, Vref = 4.0V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C 1 to +85C (wide-range specifications)* , Target pins: SCL1, SCL0, SDA1, SDA0 Item Symbol Schmitt trigger input voltage VT Min. Typ. Max. Unit VCC x 0.3 V VCC x 0.7 VT - VT 0.4 Input high voltage VIH VCC x 0.7 VCC + 0.5 V Input low voltage VIL -0.5 VCC x 0.3 V Output low voltage VOL 0.5 V 0.4 + VT + - Test Conditions IOL=8 mA IOL=3 mA Input capacitance Cin 20 pF VIN=0 V, f=1 MHz, Ta=25C Three-state leakage current (off state) | lSTI | 1.0 A VIN=0.5 to VCC-0.5 SDL, SDA output fall time tOf 20 + 0.1Cb 250 ns Note: 25.2.3 If the A/D and D/A converters and DTMF generation circuit are not used, do not leave the AVCC, Vref , and AVSS pins open. Apply a voltage 4.0 V to 5.5 V to the AVCC and Vref pins by connecting them to VCC, for instance. Set Vref AVCC AC Characteristics Figure 25.2 show, the test conditions for the AC characteristics. 5V RL LSI output pin C RH C=30pF: RL= 2.4k RH=12 Input/output timing measurement levels * Low level : 0.8V * High level : 2.0V Figure 25.2 Output Load Circuit Rev. 3.00, 08/03, page 560 of 612 Clock Timing: Table 25.5 lists the clock timing. Table 25.5 Clock Timing Condition A (F-ZTAT version): VCC = 3.0 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 32.768 kHz, 2 to 13.5 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition B (Masked-ROM version): VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 32.768 kHz, 2 to 13.5 MHz,Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition C (F-ZTAT version): VCC = 4.0V to 5.5 V, AVCC = 4.0V to 5.5V, Vref = 4.0V to AVCC, VSS = AVSS = 0 V, = 32.768 kHz, 10 to 20.5 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition D (Masked-ROM version): VCC = 4.0V to 5.5 V, AVCC = 4.0V to 5.5V, Vref = 4.0V to AVCC, VSS = AVSS = 0 V, = 32.768 kHz, 10 to 20.5 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition A and B Condition C and D 13.5 MHz 20.5 MHz Test Conditions Item Symbol Min. Typ. Max. Min. Typ. Max. Unit Clock cycle time tcyc 74 500 48.8 100 ns Clock oscillator settling time at reset (crystal) tOSC1 20 10 ms Figure 25.4 Clock oscillator settling time in software standby (crystal) tOSC2 8 8 ms Figure 22.3 External clock settling delay time tDEXT 500 500 s Figure 25.4 Sub clock oscillator settling time tOSC3 2 2 s Sub clock oscillator frequency fSUB 32.768 32.768 Sub clock (SUB) cycle time tSUB 30.5 30.5 kHz s Rev. 3.00, 08/03, page 561 of 612 Control Signal Timing: Table 25.6 lists the control signal timing. Table 25.6 Control Signal Timing Condition A (F-ZTAT version): VCC = 3.0 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 32.768 kHz, 2 to 13.5 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition B (Masked-ROM version): VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 32.768 kHz, 2 to 13.5 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition C (F-ZTAT version): VCC = 4.0V to 5.5 V, AVCC = 4.0V to 5.5V, Vref = 4.0V to AVCC, VSS = AVSS = 0 V, = 32.768 kHz, 10 to 20.5 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition D (Masked-ROM version): VCC = 4.0V to 5.5 V, AVCC = 4.0V to 5.5V, Vref = 4.0V to AVCC, VSS = AVSS = 0 V, = 32.768 kHz, 10 to 20.5 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Symbol Min. Max. Unit Test Conditions RES pulse width tRESW 20 tcyc Figure 25.5 NMI pulse width (exiting software standby mode) tNMIW 200 ns Figure 25.6 IRQ pulse width (exiting software standby mode) tIRQW 200 ns Rev. 3.00, 08/03, page 562 of 612 Timing of On-Chip Peripheral Modules: Table 25.7 lists the timing of on-chip peripheral modules. Table 25.8 lists the I2C bus timing. Table 25.7 Timing of On-Chip Peripheral Modules Condition A (F-ZTAT version): VCC = 3.0 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 32.768 kHz, 2 to 13.5 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition B (Masked-ROM version): VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 32.768 kHz, 2 to 13.5 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition C (F-ZTAT version): VCC = 4.0V to 5.5 V, AVCC = 4.0V to 5.5V, Vref = 4.0V to AVCC, VSS = AVSS = 0 V, = 32.768 kHz, 10 to 20.5 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition D (Masked-ROM version): VCC = 4.0V to 5.5 V, AVCC = 4.0V to 5.5V, Vref = 4.0V to AVCC, VSS = AVSS = 0 V, = 32.768 kHz, 10 to 20.5 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition A, B Item Condition C, D Symbol Min. Max. Min. Max. Unit Test Conditions tCyC Figure 25.7 tCyC Figure 25.8 Timer clock pulse width Single edge tTCKWH 1.5 1.5 Both edges tTCKWL 2.5 2.5 TMR_0 to Timer clock TMR_3 pulse width Single edge tTMCWH 1.5 1.5 Both edges tTMCWL 2.5 2.5 tTMCWH 1.5 1.5 tCyC Asynchronous tSCyC 4 tCyC Synchronous 6 TPU TMR_4 Timer clock pulse width tTMCWL SCI Input clock cycle Input clock pulse width tSCKW 0.4 0.6 0.4 0.6 tScyC Input clock rise time tSCKf 1.5 1.5 tCyC Input clock fall time tSCKf 1.5 1.5 Transmit data delay time tTXD 75 50 ns Receive data setup time (synchronous) tRXS 75 50 ns Receive data hold time (synchronous) tRXH 75 50 ns Figure 25.9 Figure 25.10 Rev. 3.00, 08/03, page 563 of 612 Table 25.8 I2C Bus Timing Conditions: VCC = 2.7 V to 5.5 V, VSS = 0 V, = 5 MHz to maximum operating frequency Ta = -20C to +75C (regular specifications), Ta = -40C to +80C (wide-range specifications) Symbol Min. SCL input cycle time tSCL 12tcyc ns SCL input high pulse width tSCLH 3tcyc ns SCL input low pulse width tSCLL 5tcyc ns SCL, SDA input rise time tSr 7.5tcyc* ns SCL, SDA input fall time tSf 300 ns SCL, SDA input spike pulse elimination time tSP 1tcyc ns SDA input bus free time tBUF 5tcyc ns Start condition input hold time tSTAH 3tcyc ns Retransmission start condition input setup time tSTAS 3tcyc ns Stop condition input setup time tSTOS 3tcyc ns Data input setup time tSDAS 0.5tcyc ns Data input hold time tSDAH 0 ns SCL, SDA load capacitance Cb 400 pF Note: * Typ. Max. Test Unit Conditions Remarks Item Figure 25.11 2 tSr can be set to 7.5 tcyc or 17.5 tcyc according to the clock used for the I C module. For details, see section 14.5 Usage Notes. Rev. 3.00, 08/03, page 564 of 612 25.2.4 A/D Conversion Characteristics Table 25.9 lists the A/D conversion characteristics. Table 25.9 A/D Conversion Characteristics Condition A (F-ZTAT version): VCC = 3.0 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 2 to 13.5 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition B (Masked-ROM version): VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 2 to 13.5 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition C (F-ZTAT version): VCC = 4.0V to 5.5 V, AVCC = 4.0V to 5.5V, Vref = 4.0V to AVCC, VSS = AVSS = 0 V, = 10 to 20.5 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition D (Masked-ROM version): VCC = 4.0V to 5.5 V, AVCC = 4.0V to 5.5V, Vref = 4.0V to AVCC, VSS = AVSS = 0 V, = 10 to 20.5 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition A, B Condition C, D 13.5 MHz 20.5 MHz Item Min. Typ. Max. Min. Typ. Max. Unit Resolution 10 10 10 10 10 10 bits Conversion time 9.6 6.3 s Analog input capacitance 20 20 pF Permissible signal-source impedance 5 5 k Nonlinearity error 6.0 3.0 LSB Offset error 4.0 2.0 LSB Full-scale error 4.0 2.0 LSB Quantization error 0.5 0.5 LSB Absolute accuracy 8.0 4.0 LSB Rev. 3.00, 08/03, page 565 of 612 25.2.5 D/A Conversion Characteristics Table 25.10 lists the D/A conversion characteristics. Table 25.10 D/A Conversion Characteristics Condition A (F-ZTAT version): VCC = 3.0 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 2 to 13.5 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition B (Masked-ROM version): VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 2 to 13.5 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition C (F-ZTAT version): VCC = 4.0V to 5.5 V, AVCC = 4.0V to 5.5V, Vref = 4.0V to AVCC, VSS = AVSS = 0 V, = 10 to 20.5 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition D (Masked-ROM version): VCC = 4.0V to 5.5 V, AVCC = 4.0V to 5.5V, Vref = 4.0V to AVCC, VSS = AVSS = 0 V, = 10 to 20.5 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition A, B, C, D Item Min. Typ. Max. Unit Resolution 8 8 8 bits Conversion time 10 s Load capacitance: 20 pF Absolute accuracy 2.0 3.0 LSB Load resistance: 2 M 2.0 LSB Load resistance: 4 M Rev. 3.00, 08/03, page 566 of 612 Test Conditions 25.2.6 LCD Characteristics Table 25.11 lists the LCD characteristics. Table 25.11 LCD Characteristics Condition A (F-ZTAT version): VCC = 3.0 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 32.768 kHz, 2 to 13.5 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition B (Masked-ROM version): VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 32.768 kHz, 2 to 13.5 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition C (F-ZTAT version): VCC = 4.0V to 5.5 V, AVCC = 4.0V to 5.5V, Vref = 4.0V to AVCC, VSS = AVSS = 0 V, = 32.768 kHz, 10 to 20.5 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition D (Masked-ROM version): VCC = 4.0V to 5.5 V, AVCC = 4.0V to 5.5V, Vref = 4.0V to AVCC, VSS = AVSS = 0 V, = 32.768 kHz, 10 to 20.5 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Applicable Test Condition A, B Condition C, D Standard Value Standard Value Item Symbol Pins Conditions Min. Segment driver step- VDS SEG1 to ID = 2A down voltage Typ. Max. Min. Typ. Max. Unit Notes 0.6 0.6 V * ID = 2A 0.3 0.3 V *1 Between 40 360 1000 40 360 1000 k 1 SEG40 Common driver step- VDC down voltage COM1 to COM4 LCD power supply RLCD division resistor V1 and VSS LCD voltage (step-up VLCD V1 3.0* VCC 4.0 VCC V VLCD3 V3 1.0 1.67 1.83 V VLCD2 V2 2x V 4 2 * voltage circuit not used) LCD input reference voltage (using step-up 3 voltage circuit)* LCD voltage (using step- No load 3 up voltage circuit)* VLCD3 VLCD1 V1 3x Reference value VLCD3 Rev. 3.00, 08/03, page 567 of 612 Applicable Test Condition A, B Condition C, D Standard Value Standard Value Item Symbol Pins Conditions Min. LCD input reference ILCD3 V3 No load, power supply current frame (using step-up voltage frequency: circuit)*3 64 Hz, Typ. Max. Min. Typ. Max. Unit Notes 2.0 A Reference value VLCD3 = 1.67 V Notes: 1. Voltage step-down between power supply pins V1, V2, V3, and VSS and segment pins. 2. If the LCD voltage is provided by an external power supply, the following relationship must be maintained: VCC V1 V2 V3 VSS. 3. The step-up voltage circuit should be used with 1/3 duty or 1/4 duty. 4. When the step-up voltage circuit is not used, the lowest value is V1 = 3.0 V. Use the step-up voltage circuit when V1 < 3.0 V. Rev. 3.00, 08/03, page 568 of 612 25.2.7 DTMF Characteristics Table 25.12 lists the DTMF characteristics. Table 25.12 DTMF Characteristics Condition A (F-ZTAT version): VCC = 3.0 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 2 to 13.2 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition B (Masked-ROM version): VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 2 to 13.2 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition C (F-ZTAT version): VCC = 4.0V to 5.5 V, AVCC = 2.7 V*1 to 5.5V, Vref = 2.7 V*1 to AVCC, VSS = AVSS = 0 V, = 10 to 20.4 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition D (Masked-ROM version): VCC = 4.0V to 5.5 V, AVCC = 2.7 V*1 to 5.5V, Vref = 2.7 V*1 to AVCC, VSS = AVSS = 0 V, = 10 to 20.4 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Standard Value Item Symbol Applicable Pins Test Conditions Min. Typ. Max. Unit DTMF output voltage VOR TONED AVcc- 750 924 mVrms Figure 25.12*2 770 945 mVrms Figure 25.12* 3 7 % Figure 25.12 2.5 dB Figure 25.12 (Row side) Notes GND=2.7V RL=100k DTMF output voltage VOC TONED (Column side) AVcc- 2 GND=2.7V RL=100k DTMF output distortion % TONED DISDT AVccGND=2.7V RL=100k DTMF output ratio dBCR TONED AVccGND=2.7V RL=100k Notes: 1. When AVcc = 2.7 to 4.0 V, and Vref = 2.7 to 4.0 V, DTMF is only available. 2. VOR and Vcc are output voltages when a single waveform is output. Rev. 3.00, 08/03, page 569 of 612 25.2.8 Flash Memory Characteristics Table 25.13 shows the flash memory characteristics. Table 25.13 Flash Memory Characteristics Conditions:VCC = 3.0 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = -25C to +75C (Programming/erasing operating temperature range: regular specification) Item Symbol Min. Programming time*1*2*4 tp Erase time*1*3*5 tE Count of rewriting Max. Unit 30 200 100 Test Condition ms/ 128 bytes 1200 ms/block 100* 10000* Times 6 NWEC Typ. 7 Data retention time TDRP* 10 Year Programming Wait time after SWE1 bit setting*1 tsswe 1 1 s tspsu 50 50 s tsp10 8 10 12 s tsp30 28 30 32 s 6n1 1000 n 7 8 1 Wait time after PSU1 bit setting* 1, 4 Wait time after P1 bit setting* * tsp200 198 200 202 s Wait time after P1 bit clear*1 tcp 5 5 s Wait time after PSU1 bit clear*1 tcpsu 4 4 s tspv 2 2 s Wait time after H'FF dummy write*1 tspvr 2 2 s 100 100 s s 1 Wait time after PV1 bit setting* 1 Erase Wait time after PV1 bit clear* tcpv Wait time after SWE1 bit clear tcswe Maximum programming count*1*4 N1 6*4 Times 4 N2 994* Times Wait time after SWE1 bit setting*1 tsswe 1 1 s Wait time after ESU1 bit setting*1 tsesu 100 100 s Wait time after E1 bit setting* * tse 10 10 100 ms Wait time after E1 bit clear*1 tce 10 10 s Wait time after ESU1 bit clear* tcesu 10 10 s Wait time after EV1 bit setting*1 tsev 20 20 s tsevr 2 2 s Wait time after EV1 bit clear* tcev 4 4 s Wait time after SWE1 bit clear tcswe 100 100 s N 100 Times 1 5 1 1 Wait time after H'FF dummy write* 1 1 5 Maximum erase count* * Rev. 3.00, 08/03, page 570 of 612 Notes: 1. Make each time setting in accordance with the program or erase algorithm. 2. Programming time per 128 bytes (Shows the total period for which the P1 bit in the flash memory control register (FLMCR1) is set. It does not include the programming verification time.) 3. Block erase time (Shows the total period for which the E1 bit in FLMCR1 is set. It does not include the erase verification time.) 4. The maximum programming time value (tp(max.)): tP(max.) = Wait time after P1 bit setting (tsp) x maximum programming count (N) (tsp30 + tsp10) x 6 + (tsp200) x 994 5. For the maximum erase time (tE(max.)), the following relationship applies between the wait time after E1 bit setting (tse) and the maximum erase count (N): tE(max.) = Wait time after E1 bit setting (tse) x maximum erase count (N) 6. The minimum times that all characteristics after rewriting are guaranteed. (A range between 1 and minimum value is guaranteed.) 7. The reference value at 25C. (Normally, it is a reference that rewriting is enabled up to this value.) 8. Data hold characteristics when rewriting is performed within the range of specifications including minimum value. 25.3 Electrical Characteristics of H8S/2264 Group 25.3.1 Absolute Maximum Ratings Table 25.14 lists the absolute maximum ratings. Table 25.14 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC -0.3 to +7.0 V CVCC -0.3 to +4.3 V Input voltage (except ports 4 and 9) Vin -0.3 to VCC +0.3 V Input voltage (ports 4 and 9) Vin -0.3 to AVCC +0.3 V Reference voltage Vref -0.3 to AVCC +0.3 V Analog power supply voltage AVCC -0.3 to +7.0 V Analog input voltage VAN -0.3 to AVCC +0.3 V Operating temperature Topr Regular specifications: -20 to +75 C Wide-range specifications: -40 to +85 C -55 to +125 C Storage temperature Caution: Tstg Permanent damage to the chip may result if absolute maximum rating are exceeded. Rev. 3.00, 08/03, page 571 of 612 25.3.2 DC Characteristics Table 25.15 lists the DC characteristics. Table 25.16 lists the permissible output currents. Table 25.17 lists the bus drive characteristics. Table 25.15 DC Characteristics (1) Condition B (Masked-ROM version): VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)*1 Item Schmitt trigger input voltage Input high voltage Input low voltage Symbol Max. Unit Test Conditions V VCC x 0.8 V V Vcc = 4.0 to 5.5 V Vcc = 2.7 to 4.0 V VCC x 0.04 V VCC x 0.9 VCC + 0.3 V EXTAL, Port 1, 3, 7, F, H, J to L VCC x 0.8 VCC + 0.3 V Port 4, 9 VCC x 0.8 AVCC + 0.3 V - 0.3 VCC x 0.1 V - 0.3 VCC x 0.2 V VCC - 0.5 V IOH = - 200 A VCC - 1.0 V IOH = - 1 mA VCC - 2.7 V IOH = - 100 A VCC = 4.0 to 5.5 V 0.4 V IOL = 0.8 mA 1.0 V IOL = 5 mA RES, STBY, NMI, FEW, MD2, MD1 RES, STBY, FEW, MD2, MD1 VIH VIL All output pins except P34 and P35 VOH 2 P34 and P35* Output low voltage Typ. VCC x 0.2 IRQ0, IRQ1, IRQ3, VT + IRQ4, WKP0 to VT WKP7 VT+ - VT- VCC x 0.05 NMI, EXTAL, Port 1, 3, 4, 7, 9, F, H, J to L Output high voltage Min. - All output pins*3 VOL Port 7 IOL = 10 mA, VCC = 4.0 to 5.5 V Input leakage current RES 1.0 A STBY, NMI, FEW, MD2, MD1 1.0 A Port 4, 9 1.0 A Vin = 0.5 to AVCC- 0.5 V PH7 1.0 A Vin = 0.5 to VCC- 0.5 V Rev. 3.00, 08/03, page 572 of 612 | lin | Vin = 0.5 to VCC- 0.5 V Item Symbol Min. Typ. Max. Unit Test Conditions Three-state Port 1, 3, 7, leakage current Port F, J to L, (off state) PH0 to PH3 | lTSI | 1.0 A Vin = 0.5 to VCC- 0.5 V Input pull-up MOS current -lP 10 300 A Vin = 0 V Port J Notes: 1. If the A/D converter is not used, do not leave the AVCC, Vref , and AVSS pins open. Apply a voltage 2.0 V to 5.5 V to the AVCC and Vref pins by connecting them to VCC, for instance. Set Vref AVCC. 2. P35/SCK1/SCL0 and P34/SDA0 are NMOS push/pull outputs. To output high level signal from SCL0 and SDA0 (ICE = 1), pull-up resistors must be connected externally. P35/SCK1 and P34 (ICE = 0) are driven high by NMOS. To output high when VCC = 4.0V or less, pull-up resistors should be connected externally. 3. When ICE = 0. The output low level when bus drive function is selected is indicated in table 25.17, Bus Drive Characteristics. Table 25.15 DC Characteristics (2) Condition D (Masked-ROM version): VCC = 4.0V to 5.5 V, AVCC = 4.0V to 5.5V, Vref = 4.0 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)*1 Item Schmitt trigger input voltage Input high voltage Input low voltage Symbol Max. Unit V VCC x 0.8 V V RES, STBY,NMI, FWE, MD2, MD1 VCC x 0.9 VCC + 0.3 V EXTAL, Port 1, 3, 7, F, H, J to L VCC x 0.8 VCC + 0.3 V Port 4, 9 VCC x 0.8 AVCC + 0.3 V - 0.3 VCC x 0.1 V - 0.3 VCC x 0.2 V RES, STBY,FWE, MD2, MD1 VIH VIL All output pins except P34 and P35 VOH P34 and P35*2 Output low voltage Typ. IRQ0, IRQ1, IRQ3, VT VCC x 0.2 + IRQ4, WKP0 to VT WKP7 VT+ - VT- VCC x 0.05 NMI, EXTAL, Port 1, 3, 4, 7, 9, F, H, J to L Output high voltage Min. - 3 All output pins* Port 7 VOL Test Conditions VCC - 0.5 V IOH = - 200 A VCC - 1.0 V IOH = - 1 mA VCC - 2.7 V IOH = - 100 A 0.4 V IOL = 0.8 mA 1.0 V IOL = 10 mA Rev. 3.00, 08/03, page 573 of 612 Item Input leakage current Symbol Min. Typ. Max. Unit Test Conditions | lin | 1.0 A Vin = 0.5 to VCC- 0.5 V STBY, NMI, FWE, MD2, MD1 1.0 A Port 4, 9 1.0 A Vin = 0.5 to AVCC- 0.5 V RES PH7 Three-state Port 1, 3, 7, Port F, | lTSI | leakage current J to L, PH0 to PH3 (off state) Input pull-up MOS current Port J -lP 1.0 A Vin = 0.5 to VCC- 0.5 V 1.0 A Vin = 0.5 to VCC- 0.5 V 50 300 A Vin = 0 V Notes: 1. If the A/D converter is not used, do not leave the AVCC, Vref , and AVSS pins open. Apply a voltage 4.0 V to 5.5 V to the AVCC and Vref pins by connecting them to VCC, for instance. Set Vref AVCC. 2. P35/SCK1/SCL0 and P34/SDA0 are NMOS push/pull outputs. To output high level signal from SCL0 and SDA0 (ICE = 1), pull-up resistors must be connected externally. P35/SCK1 and P34 (ICE = 0) are driven high by NMOS. 3. When ICE = 0. The output low level when bus drive function is selected is indicated in table 25.17, Bus Drive Characteristics. Rev. 3.00, 08/03, page 574 of 612 Table 25.15 DC Characteristics (3) Condition B (Masked-ROM version): VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C 1 to +85C (wide-range specifications)* Item Input capacitance Symbol Min. Typ. Max. Unit Test Conditions Cin 30 pF Vin = 0 V NMI 30 pF f = 1 MHz P34 and P35 20 pF Ta = 25C All input pins except RES, NMI, P34, and P35 15 pF 11 VCC = 3.0 V 18 VCC = 5.5 V mA f = 13.5 MHz Sleep mode 7 VCC = 3.0 V 12.5 VCC = 5.5 V mA f = 13.5 MHz All modules stopped 7 mA f = 13.5 MHz, VCC = 3.0 V (reference values) Mediumspeed mode (/32) 6 mA f = 13.5 MHz, VCC = 3.0 V (reference values) Subactive mode 20 40 A Using 32.768 kHz crystal resonator RES Current Normal consumption*2 operation ICC*4 Vcc = 3.0 V (LCD lighting) Subsleep mode 8 25 A Using 32.768 kHz crystal resonator Vcc = 3.0 V (LCD lighting) Watch mode 2.5 8 A Ta 50C Using 32.768 kHz crystal resonator Vcc = 3.0 V (LCD not used, WDT_1 operates) 10 50C < Ta, using 32.768 kHz crystal resonator, Vcc = 3.0 V (LCD not used, WDT_1 operates) Rev. 3.00, 08/03, page 575 of 612 Item Symbol Standby Current consumption*2 mode*3 4 ICC* Min. Typ. Max. Unit Test Conditions 0.5 Vcc = 3.0 V 5 Vcc = 5.5 V A 20 Vcc = 5.5 V Analog power supply current During A/D conversion Reference current During A/D conversion AlCC Waiting for A/D conversion AlCC Waiting for A/D conversion RAM standby voltage VRAM Ta 50C 32.768 kHz not used 50C < Ta 32.768 kHz not used 0.3 Vcc = 3.0 V 1.5 Vcc = 5.5 V mA 0.01 5.0 A 0.4 Vcc = 3.0 V 1.0 Vcc = 5.5V mA 0.01 5.0 A 2.0 V Notes: 1. If the A/D converter is not used, do not leave the AVCC, Vref , and AVSS pins open. Apply a voltage 2.0 to 5.5 V to the AVCC and Vref pins by connecting them to VCC, for instance. Set Vref AVCC. 2. Current consumption values are for VIH min. = VCC - 0.2 V, VIL max. = 0.2 V with all output pins unloaded and the on-chip pull-up resistors in the off state. 3. The values are for VRAM VCC < 2.7 V, VIH min. = VCC - 0.2, and VIL max. = 0.2 V. 4. ICC depends on VCC and f as follows (reference): ICC max. = 3.0 (mA) + 1.24 (mA/V) x (Vcc - 2.7 (V)) + 1.00 (mA/MHz) x (f - 2.0 (MHz)) (normal operation) ICC max. = 2.0 (mA) + 1.12 (mA/V) x (Vcc - 2.7 (V)) + 0.64 (mA/MHz) x (f - 2.0 (MHz)) (sleep mode) Rev. 3.00, 08/03, page 576 of 612 Table 25.15 DC Characteristics (4) Condition D (Masked-ROM version): VCC = 4.0V to 5.5 V, AVCC = 4.0V to 5.5V, Vref = 4.0 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C 1 to +85C (wide-range specifications)* Item Input capacitance Symbol Min. Typ. Max. Unit Test Conditions Cin 30 pF Vin = 0 V NMI 30 pF f = 1 MHz P34 and P35 20 pF Ta = 25C All input pins except RES, NMI, P34, and P35 15 pF 18 VCC = 5.0 V 25 VCC = 5.5 V mA f = 20.5 MHz Sleep mode 12 VCC = 5.0 V 17 VCC = 5.5 V mA f = 20.5 MHz All modules stopped 11 mA f = 20.5 MHz, VCC = 5.0V (reference values) Mediumspeed mode (/32) 10 mA f = 20.5 MHz, VCC = 5.0V (reference values) Subactive mode 20 40 A Using 32.768 kHz crystal resonator RES Current Normal consumption*2 operation ICC*4 Vcc = 5.0 V (LCD lighting) Subsleep mode 8 25 A Using 32.768 kHz crystal resonator Vcc = 5.0 V (LCD lighting) Watch mode 3 10 A Ta 50C Using 32.768 kHz crystal resonator Vcc = 5.0 V (LCD not used, WDT_1 operates) Rev. 3.00, 08/03, page 577 of 612 Item Symbol Watch mode Current consumption*2 4 ICC* Standby mode*3 Analog power supply current Reference current During A/D conversion AlCC Waiting for A/D conversion During A/D conversion AlCC Waiting for A/D conversion RAM standby voltage VRAM Min. Typ. Max. Unit Test Conditions 12 A 50C < Ta, using 32.768 kHz crystal resonator, Vcc = 5.0 V (LCD not used, WDT_1 operates) 0.5 Vcc = 5.0 V 5 Vcc = 5.5 V A Ta 50C 20 Vcc = 5.5 V 32.768 kHz not used 50C < Ta 32.768 kHz not used 0.8 Vcc = 5.0 V 1.6 Vcc = 5.5 V mA 0.01 5.0 A 0.6 Vcc = 5.0 V 1.0 Vcc = 5.5 V mA 0.01 5.0 A 2.0 V Notes: 1. If the A/D converter is not used, do not leave the AVCC, Vref , and AVSS pins open. Apply a voltage 4.0 to 5.5 V to the AVCC and Vref pins by connecting them to VCC, for instance. Set Vref AVCC. 2. Current consumption values are for VIH min. = VCC - 0.2 V, VIL max. = 0.2 V with all output pins unloaded and the on-chip pull-up resistors in the off state. 3. The values are for VRAM VCC < 4.0 V, VIH min. = VCC - 0.2, and VIL max. = 0.2 V. 4. ICC depends on VCC and f as follows (reference): ICC max. = 3.0 (mA) + 1.24 (mA/V) x (Vcc - 2.7 (V)) + 1.00 (mA/MHz) x (f - 2.0 (MHz)) (normal operation) ICC max. = 2.0 (mA) + 1.12 (mA/V) x (Vcc - 2.7 (V)) + 0.64 (mA/MHz) x (f - 2.0 (MHz)) (sleep mode) Rev. 3.00, 08/03, page 578 of 612 Table 25.16 Permissible Output Currents Condition B (Masked-ROM version): VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition D (Masked-ROM version): VCC = 4.0V to 5.5 V, AVCC = 4.0V to 5.5V, Vref = 4.0V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Permissible output low current (per pin) Permissible output low current (total) Symbol Min. Typ. Max. Unit IOL 10 SCL0, SDA0 10 mA Output pins except port 7, SCL0, SDA0 1.0 mA 30 mA 60 mA Port 7 Total of port 7 IOL Total of all output pins including port 7 mA Permissible output high current (per pin) All output pins -IOH 1.0 mA Permissible output high current (total) Total of all output pins -IOH 30 mA Note: To protect chip reliability, do not exceed the output current values in table 25.16. Rev. 3.00, 08/03, page 579 of 612 Table 25.17 Bus Drive Characteristics (1) Condition B (Masked-ROM version): VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)*, Target pins: SCL0, SDA0 Item Symbol Schmitt trigger input voltage - VT + VT + - VT - VT Min. Typ. Max. Unit VCC x 0.3 V VCC x 0.7 0.4 VCC = 4.5 to 5.5 V VCC x 0.05 VCC = 2.7 to 4.5 V Input high voltage VIH VCC x 0.7 VCC + 0.5 V Input low voltage VIL -0.5 VCC x 0.3 V Output low voltage VOL 0.5 0.4 V Test Conditions IOL = 8 mA, VCC = 4.5 to 5.5 V IOL=3 mA Input capacitance CIN 20 pF VIN = 0 V, f = 1 MHz, Ta = 25C Three-state leakage current (off state) | lTSI | 1.0 A VIN = 0.5 to VCC0.5 SDL, SDA output fall time tOf 20 + 0.1Cb 250 ns Note: * If the A/D converter is not used, do not leave the AVCC, Vref , and AVSS pins open. Apply a voltage 2.7 V to 5.5 V to the AVCC and Vref pins by connecting them to VCC, for instance. Set Vref AVCC. Rev. 3.00, 08/03, page 580 of 612 Table 25.17 Bus Drive Characteristics (2) Condition D (Masked-ROM version): VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, Vref = 4.0 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = - 40C to +85C (wide-range specifications)*, Target pins: SCL0, SDA0 Item Symbol Schmitt trigger input voltage - VT + VT + - VT - VT Min. Typ. Max. Unit VCC x 0.3 V VCC x 0.7 0.4 VCC = 4.5 to 5.5 V VCC x 0.05 VCC = 4.0 to 4.5 V Input high voltage VIH VCC x 0.7 VCC + 0.5 V Input low voltage VIL -0.5 VCC x 0.3 V Output low voltage VOL 0.5 0.4 V Test Conditions IOL = 8mA IOL = 3mA Input capacitance Cin 20 pF VIN = 0 V, f = 1 MHz, Ta = 25C Three-state leakage current (off state) | lTSI | 1.0 A VIN = 0.5 to VCC0.5 SDL, SDA output fall time tOf 20 + 0.1Cb 250 ns Note: 25.3.3 * If the A/D converter is not used, do not leave the AVCC, Vref , and AVSS pins open. Apply a voltage 4.0 V to 5.5 V to the AVCC and Vref pins by connecting them to VCC, for instance. Set Vref AVCC. AC Characteristics Figure 25.3 shows the test conditions for the AC characteristics. 5V RL LSI output pin C RH C=30pF: RL= 2.4k RH=12 Input/output timing measurement levels * Low level : 0.8V * High level : 2.0V Figure 25.3 Output Load Circuit Rev. 3.00, 08/03, page 581 of 612 Clock Timing: Table 25.18 lists the clock timing. Table 25.18 Clock Timing Condition B (Masked-ROM version): VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 32.768 kHz, 2 to 13.5 MHz,Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition D (Masked-ROM version): VCC = 4.0V to 5.5 V, AVCC = 4.0V to 5.5V, Vref = 4.0V to AVCC, VSS = AVSS = 0 V, = 32.768 kHz, 10 to 20.5 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition B Condition D 13.5 MHz 20.5 MHz Item Test Symbol Min. Typ. Max. Min. Typ. Max. Unit Conditions Clock cycle time tcyc 74 500 48.8 Clock oscillator settling time at reset (crystal) tOSC1 20 10 Clock oscillator settling time in software standby (crystal) tOSC2 8 External clock settling time tDEXT 500 Sub clock oscillator settling time tOSC3 Sub clock oscillator frequency fSUB Sub clock (SUB) cycle time tSUB 100 ns ms Figure 25.4 8 ms Figure 22.3 500 s Figure 25.4 2 2 s 32.7 68 32.7 68 kHz 30.5 30.5 s Control Signal Timing: Table 25.19 lists the control signal timing. Table 25.19 Control Signal Timing Condition B (Masked-ROM version): VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 32.768 kHz, 2 to 13.5 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition D (Masked-ROM version): VCC = 4.0V to 5.5 V, AVCC = 4.0V to 5.5V, Vref = 4.0V to AVCC, VSS = AVSS = 0 V, = 32.768 kHz, 10 to 20.5 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Symbol Min. Max. Unit RES pulse width tRESW Test Conditions 20 tcyc Figure 25.5 NMI pulse width (exitingsoftware standby mode) tNMIW 200 ns Figure 25.6 IRQ pulse width (exitingsoftware standby mode) tIRQW 200 ns Rev. 3.00, 08/03, page 582 of 612 Timing of On-Chip Peripheral Modules: Table 25.20 lists the timing of on-chip peripheral modules. Table 25.21 lists the I2C bus timing. Table 25.20 Timing of On-Chip Peripheral Modules Condition B (Masked-ROM version): VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 32.768 kHz, 2 to 13.5 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition D (Masked-ROM version): VCC = 4.0V to 5.5 V, AVCC = 4.0V to 5.5V, Vref = 4.0V to AVCC, VSS = AVSS = 0 V, = 32.768 kHz, 10 to 20.5 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition B Condition D Symbol Min. Max. Min. Test Max. Unit Conditions tTCKWH 1.5 1.5 Both edges Item TPU Timer clock pulse width Single edge tTCKWL 2.5 2.5 TMR_0, Timer clock TMR_1 pulse width Single edge tTMCWH 1.5 1.5 Both edges tTMCWL 2.5 2.5 SCI Asynchronous tScyc 4 4 Synchronous 6 6 Input clock cycle tcyc Figure 25.7 tcyc Figure 25.8 tcyc Figure 25.9 Input clock pulse width tSCKW 0.4 0.6 0.4 0.6 tScyc Input clock rise time tSCKr 1.5 1.5 tcyc Input clock fall time tSCKf 1.5 1.5 Transmit data delay time tTXD 75 50 ns Receive data setup time (synchronous) tRXS 75 50 ns Receive data hold time (synchronous) tRXH 75 50 ns Figure 25.10 Rev. 3.00, 08/03, page 583 of 612 Table 25.21 I2C Bus Timing Conditions: VCC = 2.7 V to 5.5 V, VSS = 0 V, = 5 MHz to maximum operating frequency, Ta = -20C to +75C (regular specifications), Ta = -40C to +80C (wide-range specifications) Symbol Min. SCL input cycle time tSCL 12tcyc ns SCL input high pulse width tSCLH 3tcyc ns SCL input low pulse width tSCLL 5tcyc ns SCL, SDA input rise time tSr 7.5tcyc* ns SCL, SDA input fall time tSf 300 ns SCL, SDA input spike pulse elimination time tSP 1tcyc ns SDA input bus free time tBUF 5tcyc ns Start condition input hold time tSTAH 3tcyc ns Retransmission start condition input setup time tSTAS 3tcyc ns Stop condition input setup time tSTOS 3tcyc ns Data input setup time tSDAS 0.5tcyc ns Data input hold time tSDAH 0 ns SCL, SDA load capacitance Cb 400 pF Note: * Typ. Max. Test Unit Conditions Remarks Item Figure 25.11 2 tSr can be set to 7.5 tcyc or 17.5 tcyc according to the clock used for the I C module. For details, see section 14.5, Usage Notes. Rev. 3.00, 08/03, page 584 of 612 25.3.4 A/D Conversion Characteristics Table 25.22 lists the A/D conversion characteristics. Table 25.22 A/D Conversion Characteristics Condition B (Masked-ROM version): VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 2 to 13.5 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition D (Masked-ROM version): VCC = 4.0V to 5.5 V, AVCC = 4.0V to 5.5V, Vref = 4.0V to AVCC, VSS = AVSS = 0 V, = 10 to 20.5 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition B Condition D 13.5 MHz 20.5 MHz Item Min. Typ. Max. Min. Typ. Max. Unit Resolution 10 10 10 10 10 10 bits Conversion time 9.6 6.3 s Analog input capacitance 20 20 pF Permissible signal-source impedance 5 5 k Nonlinearity error 6.0 3.0 LSB Offset error 4.0 2.0 LSB Full-scale error 4.0 2.0 LSB Quantization error 0.5 0.5 LSB Absolute accuracy 8.0 4.0 LSB Rev. 3.00, 08/03, page 585 of 612 25.3.5 LCD Characteristics Table 25.23 lists the LCD characteristics. Table 25.23 LCD Characteristics Condition B (Masked-ROM version): VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 32.768 kHz, 2 to 13.5 MHz, Ta = -20C to +75C Condition D (Masked-ROM version): VCC = 4.0V to 5.5 V, AVCC = 4.0V to 5.5V, Vref = 4.0V to AVCC, VSS = AVSS = 0 V, = 32.768 kHz, 10 to 20.5 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition B Item Condition D Standard Value Standard Value Applicable Test Symbol Pins Conditions Min. Typ. Max. Min. Typ. Max. Unit Notes Segment driver step-down voltage VDS SEG1 to SEG40 ID = 2A 0.6 0.6 V *1 Common driver step-down voltage VDC COM1 to COM4 ID = 2A 0.3 0.3 V *1 LCD power supply division resistor RLCD 360 800 150 360 800 k LCD voltage VLCD VCC 4.0 VCC V Between V1 150 and VSS V1 3.0 *2 Notes: 1. Voltage step-down between power supply pins V1, V2, V3, and VSS and segment pins. 2. If the LCD voltage is provided by an external power supply, the following relationship must be maintained: VCC V1 V2 V3 VSS. Rev. 3.00, 08/03, page 586 of 612 25.4 Operation Timing Operation timings are shown below. 25.4.1 Oscillator Settling Timing Figure 25.4 shows the oscillator settling timing. EXTAL tDEXT tDEXT Vcc STBY tOSC1 tOSC1 RES Internal clock Figure 25.4 Oscillator Settling Timing 25.4.2 Control Signal Timings Control signal timings are shown below. * Reset Input Timing Figure 25.5 shows the reset input timing. * Interrupt Input Timing Figure 25.6 shows the NMI, IRQ interrupt reset input timing. RES tRESW Figure 25.5 Reset Input Timing Rev. 3.00, 08/03, page 587 of 612 NMI tNMIW IRQ tIRQW Figure 25.6 Interrupt Input Timing 25.4.3 Timing of On-Chip Peripheral Modules Figures 25.7 to 25.12 show timing of on-chip peripheral modules. TCLKA to TCLKC, TCLKD* tTCKWL tTCKWH Note: * Supported only by the H8S/2268 Group. Figure 25.7 TPU Clock Input Timing TMCI01, TMCI23*, TMCI4* tTMCWL tTMCWH Note: * Supported only by the H8S/2268 Group. Figure 25.8 8-Bit Timer Clock Input Timing tSCKW tSCKr tSCKf SCK0 to SCK2 tScyc Figure 25.9 SCK Clock Input Timing Rev. 3.00, 08/03, page 588 of 612 SCK0 to SCK2 tTXD TxD0 to TxD2 (transmit data) tRXS tRXH RxD0 to RxD2 (receive data) Figure 25.10 SCI Input/Output Timing (Clock Synchronous Mode) SDA0 to SDA1*2 VIH VIL tBUF tSTAH tSCLH tSTAS tSP tSTOS SCL0 to SCL1*2 P*1 S*1 tsf tSCLL Sr*1 tSr tSCL Notes: 1. 2. tSDAS tSDAH S, P, and Sr indicate the following conditions. S : Start condition P : Stop condition Sr : Retransmission start condition Supported only by the H8S/2268 Group. Figure 25.11 I2C Bus Interface Input/Output Timing (Option) RL = 100k TONED GND Figure 25.12 TONED Load Circuit (Supported only by the H8S/2268 Group) Rev. 3.00, 08/03, page 589 of 612 25.5 Usage Note The F-ZTAT and masked ROM versions both satisfy the electrical characteristics shown in this manual, but actual electrical characteristic values, operating margins, noise margins, and other properties may vary due to differences in manufacturing process, on-chip ROM, layout patterns, and so on. When system evaluation testing is carried out using the F-ZTAT version, the same evaluation testing should also be conducted for the masked ROM version when changing over to that version. When combination of the F-ZTAT version of the H8S/2268 Group and the masked ROM version of the H8S/2264 Group is used, the following condition should be satisfied. * Stabilization capacitance between the CVCC pin and ground = 0.2 F * Vcc = AVcc Rev. 3.00, 08/03, page 590 of 612 Appendix A I/O Port States in Each Pin State A.1 I/O Port State in Each Pin State of H8S/2268 Group Port Name Reset Hardware Standby Software Mode Standby Mode Watch Mode Program Execution State Sleep Mode Subsleep Mode Port 1 T Keep Keep I/O port T Port 3 T T Keep Keep I/O port Port 4 T T T T I/O port Port 7 T T Keep Keep I/O port P97/DA1 P96/DA0 T T [DAOEn = 1] Keep [DAOEn = 0] T [DAOEn = 1] Keep [DAOEn = 0] T Input port Port F T T Keep Keep I/O port PH7 T T T T Input port PH3 to PH0 T T [Common output] [Common output] [Common output] Port COM4 to COM1 COM4 to COM1 [Otherwise] [Otherwise] [Otherwise] Keep Keep I/O port Port J Port K Port L Port M T T T T T T T T [Segment output] [Segment output] [Segment output] Port SEG8 to SEG1 SEG8 to SEG1 [Otherwise] [Otherwise] [Otherwise] Keep Keep I/O port [Segment output] [Segment output] [Segment output] Port SEG16 to SEG9 SEG16 to SEG9 [Otherwise] [Otherwise] [Otherwise] Keep Keep I/O port [Segment output] [Segment output] [Segment output] Port SEG24 to SEG17 SEG24 to SEG17 [Otherwise] [Otherwise] [Otherwise] Keep Keep I/O port [Segment output] [Segment output] [Segment output] Port SEG32 to SEG25 SEG32 to SEG25 [Otherwise] [Otherwise] [Otherwise] Keep Keep I/O port Rev. 3.00, 08/03, page 591 of 612 Port Name Reset Hardware Standby Software Mode Standby Mode Port N T A.2 T Watch Mode Program Execution State Sleep Mode [Segment output] [Segment output] [Segment output] Port SEG40 to SEG33 SEG40 to SEG33 [Otherwise] [Otherwise] [Otherwise] Keep Keep I/O port I/O Port State in Each Pin State of H8S/2264 Group Port Name Reset Hardware Standby Software Mode Standby Mode Watch Mode Program Execution State Sleep Mode Subsleep Mode Port 1 T T Keep Keep I/O port Port 3 T T Keep Keep I/O port Port 4 T T T T Input port Port 7 T T Keep Keep I/O port Port 9 T T T T Input port Port F T T Keep Keep I/O port PH7 T T T T Input port PH3 to PH0 T T [Common output] [Common output] [Common output] Port COM4 to COM1 COM4 to COM1 [Otherwise] [Otherwise] [Otherwise] Keep Keep I/O port Port J Port K Port L T T T T T T Rev. 3.00, 08/03, page 592 of 612 [Segment output] [Segment output] [Segment output] Port SEG8 to SEG1 SEG8 to SEG1 [Otherwise] [Otherwise] [Otherwise] Keep Keep I/O port [Segment output] [Segment output] [Segment output] Port SEG16 to SEG9 SEG16 to SEG9 [Otherwise] [Otherwise] [Otherwise] Keep Keep I/O port [Segment output] [Segment output] [Segment output] Port SEG24 to SEG17 SEG24 to SEG17 [Otherwise] [Otherwise] [Otherwise] Keep Keep I/O port Port Name Reset SEG40 to SEG25 T Hardware Standby Software Mode Standby Mode Watch Mode Program Execution State Sleep Mode Subsleep Mode T [Segment output] [Segment output] SEG40 to SEG25 SEG40 to SEG25 [Otherwise] [Otherwise] T T T [Legend] H: High level T: High-impedance Keep: Input port becomes high-impedance, output port retains state Port: Determined by port setting (input is high-impedance) Rev. 3.00, 08/03, page 593 of 612 Appendix B Product Codes * H8S/2268 Group Product Type H8S/2268 MaskedROM version Standard product Package (Renesas Package Code) Operating Voltage Product Code Mark Code HD6432268 HD6432268(A**)TE 100-pin TQFP 2.7 V to 5.5 V (TFP-100B) HD6432268(A**)TF 100-pin TQFP (TFP-100G) HD6432268(A**)FA 100-pin QFP (FP-100B) HD6432268(F**)TE 100-pin TQFP 4.0 V to 5.5 V (TFP-100B) HD6432268(F**)TF 100-pin TQFP (TFP-100G) HD6432268(F**)FA 100-pin QFP (FP-100B) Version with HD6432268W on-chip I2C bus interface HD6432268W(A**)TE 100-pin TQFP 2.7 V to 5.5 V (TFP-100B) HD6432268W(A**)TF 100-pin TQFP (TFP-100G) HD6432268W(A**)FA 100-pin QFP (FP-100B) HD6432268W(F**)TE 100-pin TQFP 4.0 V to 5.5 V (TFP-100B) HD6432268W(F**)TF 100-pin TQFP (TFP-100G) HD6432268W(F**)FA 100-pin QFP (FP-100B) Rev. 3.00, 08/03, page 594 of 612 Product Type H8S/2268 F-ZTAT version H8S/2266 MaskedROM version Standard product Standard product Package (Renesas Package Code) Operating Voltage Product Code Mark Code HD64F2268 HD64F2268TE13 100-pin TQFP 3.0 V to 5.5 V (TFP-100B) HD64F2268TF13 100-pin TQFP (TFP-100G) HD64F2268FA13 100-pin QFP (FP-100B) HD64F2268TE20 100-pin TQFP 4.0 V to 5.5 V (TFP-100B) HD64F2268TF20 100-pin TQFP (TFP-100G) HD64F2268FA20 100-pin QFP (FP-100B) HD6432266(A**)TE 100-pin TQFP 2.7 V to 5.5 V (TFP-100B) HD6432266(A**)TF 100-pin TQFP (TFP-100G) HD6432266(A**)FA 100-pin QFP (FP-100B) HD6432266(F**)TE 100-pin TQFP 4.0 V to 5.5 V (TFP-100B) HD6432266(F**)TF 100-pin TQFP (TFP-100G) HD6432266(F**)FA 100-pin QFP (FP-100B) HD6432266 Version with HD6432266W on-chip I2C bus interface HD6432266W(A**)TE 100-pin TQFP 2.7 V to 5.5 V (TFP-100B) HD6432266W(A**)TF 100-pin TQFP (TFP-100G) HD6432266W(A**)FA 100-pin QFP (FP-100B) HD6432266W(F**)TE 100-pin TQFP 4.0 V to 5.5 V (TFP-100B) HD6432266W(F**)TF 100-pin TQFP (TFP-100G) HD6432266W(F**)FA 100-pin QFP (FP-100B) Rev. 3.00, 08/03, page 595 of 612 Product Type H8S/2266 F-ZTAT version H8S/2265 MaskedROM version Standard product Standard product Package (Renesas Package Code) Operating Voltage Product Code Mark Code HD64F2266 HD64F2266TE13 100-pin TQFP 3.0 V to 5.5 V (TFP-100B) HD64F2266TF13 100-pin TQFP (TFP-100G) HD64F2266FA13 100-pin QFP (FP-100B) HD64F2266TE20 100-pin TQFP 4.0 V to 5.5 V (TFP-100B) HD64F2266TF20 100-pin TQFP (TFP-100G) HD64F2266FA20 100-pin QFP (FP-100B) HD6432265(A**)TE 100-pin TQFP 2.7 V to 5.5 V (TFP-100B) HD6432265(A**)TF 100-pin TQFP (TFP-100G) HD6432265(A**)FA 100-pin QFP (FP-100B) HD6432265(F**)TE 100-pin TQFP 4.0 V to 5.5 V (TFP-100B) HD6432265(F**)TF 100-pin TQFP (TFP-100G) HD6432265(F**)FA 100-pin QFP (FP-100B) HD6432265 Version with HD6432265W on-chip I2C bus interface HD6432265W(A**)TE 100-pin TQFP 2.7 V to 5.5 V (TFP-100B) HD6432265W(A**)TF 100-pin TQFP (TFP-100G) HD6432265W(A**)FA 100-pin QFP (FP-100B) HD6432265W(F**)TE 100-pin TQFP 4.0 V to 5.5 V (TFP-100B) HD6432265W(F**)TF 100-pin TQFP (TFP-100G) HD6432265W(F**)FA 100-pin QFP (FP-100B) Rev. 3.00, 08/03, page 596 of 612 Product Type H8S/2265 F-ZTAT version Standard product Package (Renesas Package Code) Operating Voltage Product Code Mark Code HD64F2265 HD64F2265TE13 100-pin TQFP 3.0 V to 5.5 V (TFP-100B) HD64F2265TF13 100-pin TQFP (TFP-100G) HD64F2265FA13 100-pin QFP (FP-100B) HD64F2265TE20 100-pin TQFP 4.0 V to 5.5 V (TFP-100B) HD64F2265TF20 100-pin TQFP (TFP-100G) HD64F2265FA20 100-pin QFP (FP-100B) [Legend] (A**), (F**): ROM code Note: Some products above are in the developing or planning stage. Please contact Renesas agency to confirm the present state of each product. Rev. 3.00, 08/03, page 597 of 612 * H8S/2264 Group Product Type H8S/2264 MaskedROM version Standard product Package (Renesas Package Code) Operating Voltage Product Code Mark Code HD6432264 HD6432264(A**)TE 100-pin TQFP 2.7 V to 5.5 V (TFP-100B) HD6432264(A**)TF 100-pin TQFP (TFP-100G) HD6432264(A**)FA 100-pin QFP (FP-100B) HD6432264(F**)TE 100-pin TQFP 4.0 V to 5.5 V (TFP-100B) HD6432264(F**)TF 100-pin TQFP (TFP-100G) HD6432264(F**)FA 100-pin QFP (FP-100B) Version with HD6432264W on-chip I2C bus interface HD6432264W(A**)TE 100-pin TQFP 2.7 V to 5.5 V (TFP-100B) HD6432264W(A**)TF 100-pin TQFP (TFP-100G) HD6432264W(A**)FA 100-pin QFP (FP-100B) HD6432264W(F**)TE 100-pin TQFP 4.0 V to 5.5 V (TFP-100B) HD6432264W(F**)TF 100-pin TQFP (TFP-100G) HD6432264W(F**)FA 100-pin QFP (FP-100B) H8S/2262 MaskedROM version Standard product Rev. 3.00, 08/03, page 598 of 612 HD6432262 HD6432262(A**)TE 100-pin TQFP 2.7 V to 5.5 V (TFP-100B) HD6432262(A**)TF 100-pin TQFP (TFP-100G) HD6432262(A**)FA 100-pin QFP (FP-100B) HD6432262(F**)TE 100-pin TQFP 4.0 V to 5.5 V (TFP-100B) HD6432262(F**)TF 100-pin TQFP (TFP-100G) HD6432262(F**)FA 100-pin QFP (FP-100B) Product Type H8S/2262 MaskedROM version Product Code Version with HD6432262W on-chip I2C bus interface Mark Code Package (Renesas Package Code) Operating Voltage HD6432262W(A**)TE 100-pin TQFP 2.7 V to 5.5 V (TFP-100B) HD6432262W(A**)TF 100-pin TQFP (TFP-100G) HD6432262W(A**)FA 100-pin QFP (FP-100B) HD6432262W(F**)TE 100-pin TQFP 4.0 V to 5.5 V (TFP-100B) HD6432262W(F**)TF 100-pin TQFP (TFP-100G) HD6432262W(F**)FA 100-pin QFP (FP-100B) [Legend] (A**), (F**): ROM code Note: Some products above are in the developing or planning stage. Please contact Renesas agency to confirm the present state of each product. Rev. 3.00, 08/03, page 599 of 612 Appendix C Package Dimensions The package dimensions that are shown in the Renesas Semiconductor Packages Data Book have priority. Unit: mm 16.0 0.2 14 75 51 50 0.5 16.0 0.2 76 100 0.10 *Dimension including the plating thickness Base material dimension 0.10 0.10 1.0 1.00 0.08 M *0.17 0.05 0.15 0.04 25 1.20 Max 26 1 *0.22 0.05 0.20 0.04 1.0 0 - 8 0.5 0.1 Package Code JEDEC JEITA Mass (reference value) Figure C.1 TFP-100B Package Dimensions Rev. 3.00, 08/03, page 600 of 612 TFP-100B -- Conforms 0.5 g Unit: mm 14.0 0.2 12 75 51 50 0.4 14.0 0.2 76 100 26 0.10 *Dimension including the plating thickness Base material dimension 0.15 0.04 1.20 Max 1.2 1.00 0.07 M *0.17 0.05 25 0.10 0.10 1 *0.18 0.05 0.16 0.04 1.0 0 - 8 0.5 0.1 Package Code JEDEC JEITA Mass (reference value) TFP-100G -- Conforms 0.4 g Figure C.2 TFP-100G Package Dimensions Rev. 3.00, 08/03, page 601 of 612 Unit: mm 16.0 0.3 14 75 51 50 100 26 0.5 16.0 0.3 76 0.10 *Dimension including the plating thickness Base material dimension 0.12 +0.13 -0.12 0.15 0.04 *0.17 0.05 3.05 Max 0.08 M 1.0 2.70 25 1 *0.22 0.05 0.20 0.04 1.0 0 - 8 0.5 0.2 Package Code JEDEC JEITA Mass (reference value) Figure C.3 FP-100B Package Dimensions Rev. 3.00, 08/03, page 602 of 612 FP-100B -- Conforms 1.2 g Main Revisions and Additions in this Edition Item Section 1 Overview Page Revisions (See Manual for Details) All The product lineup of the flash memory version (H8S/2264F) and the oscillation stabilization time shortened (H8S/2264R, H8S/2264RW, H8S/2262R, and H8S/2262RW) of the H8S/2264 Group deleted. 2 * On-chip memory 1.1 Overview H8S/2264 Group: * ROM On-chip memory Model ROM RAM 128 kbytes 4 kbytes 128 kbytes 4 kbytes HD6432262 64 kbytes 2 kbytes HD6432262W 64 kbytes 2 kbytes Masked ROM HD6432264 version HD6432264W * General I/O ports 2 * General I/O ports I/O pins: 67 (supported only by the H8S/2268 Group) 51 (supported only by the H8S/2264 Group) Figure 1.2 Internal Block Diagram of H8S/2264 Group 4 Figure 1.4 Pin 6 Arrangement of H8S/2264 Group PH5 and PH4/ pins for port H deleted. Pin arrangement amended. NC* NC* V3 83 84 85 Note: * The NC pin should be open. 1.4 Pin Functions 7 Connect this pin to Vss via a capacitor (H8S/2268 Group: 0.1 F/0.2 F and H8S/2264 Group: 0.2 F) for voltage stabilization. Power supply Clock Description of CVcc pin amended. 7 Description of pin deleted. Section 3 MCU Operating 47 Modes Power-on reset circuit enabled mode deleted in operating mode 7. 3.4 Address Map Product type names of H8S/2264R and H8S/2262R deleted. 50 Figure 3.1 Address Map (2) Rev. 3.00, 08/03, page 603 of 612 Item Page Revisions (See Manual for Details) Section 9 I/O Ports 130 Description of port H amended. Before modification: Table 9.1 H8S/2264 Group Port Functions (2) Description Port and Other Functions Name General input port PH7 General I/O port also functioning as output pin and LCD common output pins PH5 PH4/ PH3/COM4 PH2/COM3 PH1/COM2 PH0/COM1 After modification: Description Port and Other Functions Name General input port PH7 General I/O port also functioning as LCD common output pins PH3/COM4 PH2/COM3 PH1/COM2 PH0/COM1 9.7.1 Port H Data Direction Register (PHDDR) 148 9.7.2 Port H Data Register 148 (PHDR) 9.7.3 Port H Register (PORTH) 149 Bits 5 and 4 are amended to reserved bits. Bit Bit Name Initial Value R/W 7 to 4 Undefined Bits 5 and 4 are amended to reserved bits. Bit Bit Name Initial Value R/W 7 to 4 Undefined Bits 5 and 4 are amended to reserved bits. 1 * is amended to *. Bit Bit Name Initial Value R/W 6 to 4 Undefined Note: * Determined by the states of pins PH7 and PH3 to PH0. Rev. 3.00, 08/03, page 604 of 612 Item Page Revisions (See Manual for Details) 9.7.4 Pin Functions 149 Amended. 150, 151 Setting value for SGS3 to SGS0 of H8S/2264 Group amended. 154 Setting value for SGS3 to SGS0 amended. 157 Setting value for SGS3 to SGS0 amended. 159 Setting value for SGS3 to SGS0 amended. 165 Deleted. 174 Description of B'1111 is amended to "Setting prohibited." * PH7/TONED/TMCI4 (H8S/2268 Group) * PH7 (H8S/2264 Group) * PH3/COM4 to PH0/COM1 9.8.6 Pin Functions * PJn/WKPn/SEGn+1 9.9.4 Pin Functions * PKn/SEGn+9 9.10.4 Pin Functions * PLn/SEGn+17 Section 10 16-Bit Timer Pulse Unit (TPU) 10.1 Features * Operation with Cascaded Connection (H8S/2264 Group only) 10.3.1 Timer Control Register (TCR) Table 10.6 TPSC0 to TPSC2 (Channel 1) 10.5.4 Operation with Cascaded Connection (H8S/2264 Group Only) Section 12 Watchdog Timer (WDT) Description in revision 2.0 deleted. 261 Amended. * 12.1 Features Selectable from 16 counter input clocks for WDT_1 Figure 12.3 Block Diagram of WDT_1 for H8S/2264 Group 12.2.2 Timer Control/Status Register (TCSR) Selectable from eight counter input clocks for WDT_0 Figure in revision 2.0 deleted. 266 * TCSR_1 Bits CKS2 to CKS0: Clock selection when PSS = 1 added. Rev. 3.00, 08/03, page 605 of 612 Item Page Table 12.1 Clock Selection When PSS = 1 Section 17 LCD Controller/Driver Revisions (See Manual for Details) Table in revision 2.0 deleted. 419 Amended. * 17.1 Features The segment output pins can be used as ports. H8S/2264 Group: SEG24 to SEG1 pins can be used as ports in groups of eight. Table 17.4 Segment Driver Selection (2) (H8S/2264 Group) 424 Section 20 ROM 451 to Since the flash memory version of the H8S/2264 Group is 486 deleted, product type names and description of the H8S/2264 Group are deleted. Section 21 Clock Pulse Generator Changed. Figure in revision 2.0 deleted. Figure 21.2 Block Diagram of Clock Pulse Generator (H8S/2264 Group) 21.1.2 System Clock Control Register 2 (SCKCR2) (Supported only by the H8S/2264 Group) Description in revision 2.0 deleted. Table 21.2 Clock Selection Table in revision 2.0 deleted. 21.2.2 Connecting a Ceramic Resonator Description in revision 2.0 deleted. Table 21.3 External Clock 493 Input Conditions Vcc value amended. VCC = 2.7 V to 5.5 V Item Section 22 Power-Down Modes 504 22.1.1 Standby Control Register (SBYCR) 22.4.3 Oscillation Settling Time after Clearing Software Standby Mode Oscillation Settling Time Shortened (H8S/2264R and H8S/2262R): Rev. 3.00, 08/03, page 606 of 612 Symbol Min Max Description of bits STS2 to STS0 deleted: (Oscillation settling time shortened: H8S/2264R and H8S/2262R) Description in revision 2.0 deleted. Item Page Section 23 Power-On Reset Circuit Section 23 Power Supply Circuit Description in revision 2.0 deleted. 519 Section 24 List of Registers 24.2 Register Bits Section 25 Electrical Characteristics Revisions (See Manual for Details) Description of capacitance added. Description of system clock control register 2 (SCKCR2) in revision 2.0 deleted. 529 Bits 5 and 4 in PHDDR are amended to "-." 530 Bits 5 and 4 in PHDR and PORTH are amended to "-". 571 to Changed. 586 25.3 Electrical Characteristics of H8S/2264 Group 25.4 Operation Timing Figure in revision 2.0 deleted. Figure 25.4 Output Clock Timing Appendix 592 PH5 and PH4 pins deleted. A.2 I/O Port State in Each Pin State of H8S/2264 Group Appendix B Product Codes 594 to Description of "(regular oscillation)" deleted. 599 Product codes of HD64F2264, HD64F2264R, HD6432264R, HD6432264RW, HD6432262R, and HD6432262RW deleted. Rev. 3.00, 08/03, page 607 of 612 Rev. 3.00, 08/03, page 608 of 612 Index 16-bit timer pulse unit (TPU) ................. 165 Buffer operation.................................. 202 Buffer operation timing ...................... 220 Counter operation ............................... 195 Free-running count operation.............. 196 Input capture function......................... 199 Input capture signal timing ................. 218 Output compare output timing ............ 217 Periodic count operation ..................... 196 Phase counting mode .......................... 210 PWM modes ....................................... 205 Synchronous operation ....................... 200 TCNT count timing............................. 217 Toggle output...................................... 198 Waveform output by compare match.. 198 8-bit reload timer .................................... 253 Automatic reload timer operation ....... 258 Interval timer operation ...................... 257 8-bit timers.............................................. 233 16-bit count mode ............................... 247 Cascaded connection........................... 247 Compare-match count mode ............... 247 Pulse output ........................................ 243 TCNT incrementation timing.............. 244 Toggle output...................................... 250 A/D converter ......................................... 397 A/D converter activation..................... 216 Analog input channel .......................... 400 Conversion time.................................. 406 External trigger ................................... 407 Scan mode........................................... 405 Single mode ........................................ 404 Address map ............................................. 49 Address space ........................................... 18 Addressing modes..................................... 38 Absolute address................................... 39 Immediate ............................................. 40 Memory indirect ................................... 40 Program-counter relative....................... 40 Register direct ....................................... 39 Register indirect .................................... 39 Register indirect with displacement ...... 39 Register indirect with post-increment ... 39 Register indirect with pre-decrement .... 39 Bcc ............................................................ 35 Break address ............................................ 91 Break condition......................................... 93 Bus arbitration......................................... 101 Bus cycle................................................... 99 Bus masters ............................................. 101 Clock pulse generator.............................. 487 Condition field .......................................... 37 Condition-code register............................. 22 D/A converter.......................................... 413 Data direction register (DDR)................. 125 Data register (DR)................................... 125 Data transfer controller ........................... 103 Activated by software ......................... 119 Block transfer mode ............................ 116 Chain transfer...................................... 117 DTC vector table................................. 110 Normal mode ...................................... 114 Register information ........................... 110 Repeat mode........................................ 115 Software activation ..................... 118, 123 Vector number for the software activation interrupt.............................. 109 DTMF generation circuit ........................ 441 Effective address ................................. 38, 41 Effective address extension....................... 37 Exception handling ................................... 51 Interrupts ............................................... 55 Reset exception handling ...................... 53 Stack status............................................ 57 Rev. 3.00, 08/03, page 609 of 612 Traces ................................................... 55 Trap instruction..................................... 56 Exception Vector Table ............................ 52 Extended control register .......................... 21 Flash memory ......................................... 451 Boot mode........................................... 466 Emulation............................................ 470 Erase/erase-verify ............................... 474 Erasing units ....................................... 456 Error protection................................... 476 Hardware protection ........................... 476 Program/program-verify ..................... 472 Software protection............................. 476 User program mode ............................ 469 TGI...................................................... 215 TXI...................................................... 344 WOVI.................................................. 271 Interrupt control modes............................. 79 Interrupt controller .................................... 59 Interrupt exception handling vector table................................................ 75 Interrupt mask bit ...................................... 22 LCD controller/driver ............................. 419 Common drivers.................................. 423 Duty cycle ........................................... 419 LCD display ........................................ 430 LCD RAM .......................................... 431 Segment driver .................................... 424 General register......................................... 24 Memory cycle ........................................... 99 I2C bus interface ..................................... 353 I2C bus format..................................... 371 Noise cancelers ................................... 384 Serial format ....................................... 371 Input pull-up MOS function ................... 125 Instruction set............................................ 27 Arithmetic operations instructions........ 30 Bit Manipulation instructions ............... 33 Block data transfer instructions ............ 37 Branch instructions ............................... 35 Data transfer instructions ...................... 29 Logic operations instructions................ 32 Shift instructions................................... 32 System control instructions................... 36 Interrupt ADI ..................................................... 408 CMIA.................................................. 248 CMIB .................................................. 248 ERI...................................................... 344 NMI .................................................... 271 OVI ..................................................... 248 RXI ..................................................... 344 SWDTEND......................................... 118 TCI...................................................... 215 TEI...................................................... 344 On-board programming........................... 466 Operating mode selection.......................... 47 Operation field .......................................... 37 Rev. 3.00, 08/03, page 610 of 612 PC break controller ................................... 91 Power-down modes................................. 499 Direct transitions ................................. 516 Hardware standby mode...................... 511 Medium-speed mode........................... 507 Module stop mode............................... 512 Sleep mode.......................................... 508 Software standby mode ....................... 509 Sub-active mode.................................. 515 Sub-sleep mode ................................... 514 Watch mode ........................................ 513 Program counter........................................ 21 Program/erase protection ........................ 476 Programmer mode................................... 477 Register ADCR ......................... 403, 528, 535, 541 ADCSR ....................... 401, 528, 535, 541 ADDR ......................... 400, 527, 535, 541 BARA ........................... 92, 524, 531, 538 BARB............................ 93, 524, 531, 538 BCRA ........................... 93, 524, 531, 538 BCRB............................ 94, 524, 531, 538 BRR ............................ 296, 527, 534, 540 CRA ............................ 108, 522, 529, 536 CRB ............................ 108, 522, 529, 536 DACR ......................... 415, 523, 530, 537 DADR......................... 414, 523, 530, 537 DAR............................ 107, 522, 529, 536 DDCSWR ................... 371, 523, 530, 537 DTCER ....................... 108, 524, 532, 538 DTCR.......................... 443, 522, 529, 536 DTLR.......................... 444, 522, 529, 536 DTVECR .................... 109, 524, 532, 538 EBR1 .......................... 462, 528, 535, 541 EBR2 .......................... 463, 528, 535, 541 FLMCR1..................... 460, 528, 535, 541 FLMCR2..................... 461, 528, 535, 541 FLPWCR .................... 464, 528, 535, 541 ICCR........................... 364, 527, 534, 540 ICDR........................... 357, 527, 534, 540 ICMR .......................... 360, 527, 534, 540 ICSR ........................... 368, 527, 534, 540 IENR1........................... 71, 523, 530, 537 IER................................ 66, 524, 531, 538 IPR................................ 65, 525, 532, 538 ISCR ............................. 67, 524, 531, 538 ISR ................................ 69, 524, 531, 538 IWPR ............................ 71, 523, 530, 537 LCD RAM .................. 431, 522, 529, 536 LCR ............................ 424, 522, 529, 536 LCR2 .......................... 426, 522, 529, 536 LPCR .......................... 422, 522, 529, 536 LPWRCR.................... 489, 524, 531, 538 MDCR .......................... 48, 524, 531, 538 MRA ........................... 106, 522, 529, 536 MRB ........................... 107, 522, 529, 536 MSTPCR .................... 505, 531, 536, 538 P1DDR........................ 131, 524, 532, 538 P1DR .......................... 131, 525, 532, 539 P3DDR........................ 136, 524, 532, 538 P3DR .......................... 137, 525, 532, 539 P3ODR........................ 138, 525, 532, 538 P7DDR........................ 142, 524, 532, 538 P7DR........................... 142, 525, 532, 539 PFDDR........................ 146, 525, 532, 538 PFDR .......................... 146, 525, 532, 539 PHDDR ....................... 148, 522, 529, 536 PHDR.......................... 148, 523, 530, 536 PJDDR ........................ 152, 522, 529, 536 PJDR ........................... 152, 523, 530, 536 PJPCR ......................... 153, 523, 530, 537 PKDDR ....................... 156, 522, 530, 536 PKDR.......................... 156, 523, 530, 537 PLDDR ....................... 158, 523, 530, 536 PLDR .......................... 158, 523, 530, 537 PMDDR ...................... 160, 523, 530, 536 PMDR ......................... 160, 523, 530, 537 PNDDR ....................... 162, 523, 530, 536 PNDR.......................... 162, 523, 530, 537 PORT1 ........................ 132, 528, 535, 541 PORT3 ........................ 137, 528, 535, 541 PORT4 ........................ 141, 528, 535, 541 PORT7 ........................ 143, 528, 535, 541 PORT9 ........................ 145, 528, 535, 541 PORTF ........................ 147, 528, 535, 541 PORTH ....................... 149, 523, 530, 537 PORTJ......................... 153, 523, 530, 537 PORTK ....................... 157, 523, 530, 537 PORTL........................ 159, 523, 530, 537 PORTM....................... 161, 523, 530, 537 PORTN ....................... 163, 523, 530, 537 RAMER ...................... 463, 525, 532, 539 RDR ............................ 280, 527, 534, 540 RSR..................................................... 280 RSTCSR...................... 267, 526, 534, 540 SAR............................. 107, 522, 529, 536 SARX.......................... 359, 527, 534, 540 SBYCR ....................... 503, 524, 531, 538 SCKCR ....................... 488, 524, 531, 538 SCMR ......................... 295, 527, 534, 540 SCR............................. 284, 527, 534, 540 SCRX .......................... 363, 523, 530, 537 SEMR.......................... 304, 524, 531, 538 SMR ............................ 281, 527, 534, 540 SSR ............................. 289, 527, 534, 540 SYSCR.......................... 63, 524, 531, 538 Rev. 3.00, 08/03, page 611 of 612 TCNT......................... 191, 263, 525, 526, .................................... 533, 534, 539, 540 TCORA....................... 236, 526, 534, 540 TCORB....................... 236, 526, 534, 540 TCR ........................... 172, 237, 525, 526, .................................... 532, 533, 539, 540 TCSR .......................... 239, 526, 534, 540 TDR ............................ 280, 527, 534, 540 TGR ............................ 191, 525, 533, 539 TIER ........................... 186, 525, 532, 539 TIOR........................... 177, 525, 532, 539 TMDR......................... 175, 525, 532, 539 TSR............................. 187, 525, 532, 539 TSTR .......................... 192, 525, 532, 538 TSYR .......................... 193, 525, 532, 538 WPCR......................... 154, 523, 530, 537 Register field............................................. 37 Reset ......................................................... 53 Rev. 3.00, 08/03, page 612 of 612 Serial communication interface (SCI)..... 275 Asynchronous mode............................ 308 Bit rate................................................. 296 Break................................................... 346 Clocked synchronous mode ................ 325 Framing error ...................................... 315 Mark state............................................ 346 Multiprocessor communication function ............................................... 319 Overrun error ...................................... 315 Parity error .......................................... 315 Smart card ............................................... 275 Smart card interface ................................ 333 Stack pointer ............................................. 20 Watchdog timer....................................... 261 Interval timer mode............................. 269 Overflow ............................................. 270 Watchdog timer mode......................... 268 H8S/2268 Group, H8S/2264 Group Hardware Manual Publication Date: 1st Edition, April 2001 Rev.3.00, Aug 28, 2003 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Technical Documentation & Information Department Renesas Kodaira Semiconductor Co., Ltd. 2001, 2003 Renesas Technology Corp. All rights reserved. Printed in Japan. H8S/2268Group, H8S/2264Group Hardware Manual REJ09B0071-0300Z (ADE-602-240B)