MOTOROLA me SEMICONDV RR ee TECHNICAL DATA MC68s802 Microprocessor With Clock and Optional RAM The MC6802 is a monolithic 8-bit microprocessor that contains all the registers and accumulators of the present MC6800 plus an interna! clock oscillator and driver on the same chip. In addition, the MC6802 has 128 bytes of on-board RAM located at hex addresses $0000 to $007F. The first 32 bytes of RAM, at hex addresses $0000 to $001F, may be retained in a low power mode by utilizing Vcc standby; thus, facilitating memory retention during a power-down situation. The MC6802 is completely software compatible with the MC6800 as well as the entire M6800 family of parts. Hence, the MC6802 is expandable to 64K words. @ On-Chip Clock Circuit 1288 Bit On-Chip RAM @ 32 Bytes of RAM are Retainable @ Software-Compatible with the MC6800 @ Expandable to 64K Words @ Standard TTL-Compatible Inputs and Outputs 8-Bit Word Size @ 16-Bit Memory Addressing e Interrupt Capability TYPICAL MICROCOMPUTER Vcc Vcc Vcc Vcc 2 | s Counter/ TRO 1 ounter/ | ae! MC6846 IRQ RESET This block diagram shows a typical cost ef- imer 70} ___} ROM, 1/0, Timer MR fective microcomputer. The MPU is the RESET cso YMA VMA HALT Ho T center of the microcomputer system and is _S Clock E = shown in a minimum system interfacing with wee 2k Bytes ROM RW _ RE a ROM combination chip. It is not intended et = 10 1/0 Lines BIW, a cego2 NMI that this system be limited to this function Paraliel } ~#-#y 9 3 | ines Timer MPU but that it be expandable with other parts in vo}. DO-07 DO-D7 DO-D7 BAT the M6800 Microcomputer family a xp EXTALL __ > A0- A10 = Controi | i esi A0-A15 AO-AISXTALE I _ Hr This document contains information on a new product. Specifications and information herein are subject to change without notice. MOTOROLA MICROPROCESSOR DATA 3-256MC6802 MAXIMUM RATINGS Rating Symboi Value Unit This input contains circuitry to protect the _ inputs against damage due to high static voit- Supply Voltage Vec 0.3t0 +7.0| V ages or electric fields; however, it is advised Input Voltage Vin -0.3to +7.0| V that normal precautions be taken to avoid Operating Temperature Range TA C application of any voltage higher than max- MC6802, MC680A02, MC680802 Oto +70 imum rated voltages to this high-impedance MC6802C, MC680A02C -40 to +85 circuit. Reliability of operation is enhanced if Storage Temperature Range Tetg_| 55 to +150 C unused inputs are tied to an appropriate logic voltage tevel (e.g., either Vgg or Vcc). THERMAL CHARACTERISTICS Characteristic Symbol Value Unit Average Thermal Resistance (Junction to Ambient) Plastic Osa 100 Cw POWER CONSIDERATIONS The average chip-junction temperature, Ty, in C can be obtained from: Ty=Tat (Pp ya) () where: Ta = Ambient Temperature, C CaN = Package Thermal Resistance, Junction-to-Ambient, C/W PD = PiInT+ PpoRT ; PIntT = 'cc*Vcc, Watts Chip Internal Power PporT = Port Power Dissipation, Watts User Determined For most applications PegoRT Control XTAL ey index Bus Available & Register ,, Valid Memory Address & Read/Wnte (R/W) ~& Accumuiator A Instruction Register Accumulator 8 Condition Code Register Vec=Ping Vss=Pins 1, 21 Data Buffer DBD? D6 DS D4 D3 02 DI DO MOTOROLA MICROPROCESSOR DATA 3-260MC6802 MPU REGISTERS A general block diagram of the MC6802 is shown in Figure 1. As shown, the number and configuration of the registers are the same as for the MC6800. The 128 x 8- bit RAM* has been added to the basic MPU. The first 32 bytes can be retained during powerup and power- down conditions via the RE signal. The MPU has three 16-bit registers and three 8-bit registers available for use by the programmer (Figure 7). PROGRAM COUNTER The program conter is a two byte (16-bit) register that points to the current program address. STACK POINTER The stack pointer is a two byte register that contains the address of the next available location in an external pushdown/pop-up stack. This stack is normally a ran- dom access read/write memory that may have any lo- cation (address) that is convenient. In those applications that require storage of information in the stack when power is lost, the stack must be non-volatile. INDEX REGISTER The index register is a two byte register that is used to store data or a 16-bit memory address for the indexed mode of memory addressing. ACCUMULATORS The MPU contains two 8-bit accumulators that are used to hold operands and results from an arithmetic logic unit (ALU). CONDITION CODE REGISTER The condition code register indicates the results of an Arithmetic Logic Unit operation: Negative (N), Zero (Z), Overflow (V), Carry from bit 7 (C), and Half Carry from bit 3 (H). These bits of the Condition Code Register are used as testable conditions for the conditional branch instructions. Bit 4 is the interrupt mask bit (I). The un- used bits of the Condition Code Register (b6 and b7) are ones. Figure 8 shows the order of saving the microproces- sor status within the stack. *If programs are not executed from on-board RAM, TAV1 applies. If programs are to be stored and executed from on-board RAM, TAV2 applies. For normal data storage in the on-board RAM, this extended delay does not apply. Programs cannot be executed from on-board RAM when using A and B parts (MC68A02 and MC68B02). On-board RAM can be used for data storage with all parts. FIGURE 7 PROGRAMMING MODEL OF THE MICROPROCESSING UNIT ~ ACCA N ACCB i N i fo} Accumulator A jo Accumulator B Index Register IO Program Counter la Stack Pointer fey Condition Codes TIMI] LIN|ZIVIC] Register Carry (From Bit 7} Overflow Zero Negative Interrupt Half Carry (From Bit 3) MOTOROLA MICROPROCESSOR DATA 3MC6802 FIGURE 8 SAVING THE STATUS OF THE MICROPROCESSOR IN THE STACK SP - Stack Pointer CC = Condition Codes (Also called the Processor Status Byte) ACCB = Accumulator B ACCA = IXH = index Register, Higher Order & Bits {XL = Index Register, Lower Order 8 Bits PCH - Program Counter, Higher Order 8 Bits PCL = Program Counter, Lower Order 8 Bits Accumulator & m-2 m-1 mtd mt2 Before After MPU SIGNAL DESCRIPTION Proper operation of the MPU requires that certain control and timing signals be provided to accomplish specific func- tions and that other signal lines be monitored to determine the state of the processor. These control and timing signals are similar to those of the MC6800 except that TSC, DBE, 1, $2 input, and two unused pins have been eliminated, and the following signal and timing lines have been added: RAM Enable (RE) Crystal Connections EXTAL and XTAL Memory Ready (MR} Vcc Standby Enable $2 Output (E) The following is a summary of the MPU signals: ADDRESS BUS (A0-A15) Sixteen pins are used for the address bus. The outputs are capable of driving one standard TTL load and 90 pF. These lines do not have three-state capability. DATA BUS (00-D7) Eight pins are used for the data bus. It is bidirectional, transferring data to and from the memory and peripheral devices. It also has three-state output buffers capable of driving one standard TTL load and 130 pF. Data bus will be in the output mode when the internal RAM is accessed and RE will be high. This prohibits external data entering the MPU. It should be noted that the internal RAM is fully decoded from $0000 to $007F. External RAM at $0000 to $007F must be disabled when internal RAM is ac- cessed. HALT When this input is in the low state, all activity in the machine will be halted. This input is level sensitive. In the HALT mode, the machine will stop at the end of an instruc- tion, bus available will be at a high state, valid memory ad- dress will be at a low state. The address bus will display the address of the next instruction. To ensure single instruction operation, transition of the HALT line must occur tpcs before the rising edge of E and the HALT line must go high for one clock cycle. HALT should be tied high if not used. This is good engineering design practice in general and necessary to en- sure proper operation of the part. READ/WRITE (R/W) This TTL-compatible output signals the peripherals and memory devices whether the MPU is in a read (high) or write (low) state. The normal standby state of this signal is read (high). When the processor is halted, it will be in the read state. This output is capable of driving one standard TTL load and 90 pF. VALID MEMORY ADDRESS (VMA) This output indicates to peripheral devices that there is a valid address on the address bus. In normal operation, this signal should be utilized for enabling peripheral interfaces such as the PIA and ACIA. This signal is not three-state. One standard TTL load and 90 pF may be directly driven by this active high signal. BUS AVAILABLE (BA) The bus available signal will nor- mally be in the low state; when activated, it will go to the high state indicating that the microprocessor has stopped and that the address bus is available (but not in a three-state condition). This will occur if the HALT line is in the low state or the processor is in the WAIT state as a result of the execu- tion of a WAIT instruction. At such time, all three-state out- put drivers will go to their off-state and other outputs to their normally inactive level. The processor is removed from the MOTOROLA MICROPROCESSOR DATA 3-262MC6802 WAIT state by the occurrence of a maskable (mask bit | = 0) or nonmaskable interrupt. This output is capable of driving one standard TTL load and 30 pF. INTERRUPT REQUEST (IRQ) A low level on this input requests that an interrupt se- quence be generated within the machine. The processor will wait until it completes the current instruction that is being excuted before it recognizes the request. At that time, if the interrupt mask bit in the condition code register is not set, the machine will begin an interrupt sequence. The index register, program counter, accumulators, and condition code register are stored away on the stack. Next the MPU will respond to the interrupt request by setting the interrupt mask bit high so that no further interrupts may occur. At the end of the cycle, a 16-bit vectoring address which is located in memory locations $FFF8 and $FFF9 is loaded which causes the MPU to branch to an interrupt routine in memory. The HALT line must be in the high state for interrupts to be serviced. Interrupts will be latched internally while HALT is low. A nominal 3 kQ puliup resistor to Vcc should be used for wire-OR and optimum control of interrupts. iRO may be tied directly to Vcc if not used. RESET This input is used to reset and start the MPU from a power-down condition, resulting from a power failure or an initial start-up of the processor. When this line is low, the MPU is inactive and the information in the registers will be lost. If a high level is detected on the input, this will signal the MPU to begin the restart sequence. This will start execu- tion of a routine to initialize the processor from its reset con- dition. All the higher order address lines will be forced high. For the restart, the last two ($FFFE, $FFFF) locations in memory will be used to load the program that is addressed by the program counter. During the restart routine, the inter- rupt mask bit is set and must be reset before the MPU can be interrupted by TRG. Power-up and reset timing and power- down sequences are shown in Figures 9 and 10, respectively RESET, when brought low, must be held low at least three clock cycles. This allows adequate time to respond internally to the reset. This is independent of the tr power-up reset that is required When RESET is released it must go through the low-to- high threshold without bouncing, oscillating, or otherwise causing an erroneous reset (less than three clock cycles} This may cause improper MPU operation until the next valid reset. NON-MASKABLE INTERRUPT (NMI) A low-going edge on this input requests that a non- maskable interrupt sequence be generated within the pro- cessor. As with the interrupt request signal, the processor will complete the current instruction that is being executed before it recognizes the NMI signal. The interrupt mask bit in the condition code register has no effect on NMI. The index register, program counter, accumulators, and condition code registers are stored away on the stack. At the end of the cycle, a 16-bit vectoring address which is located in memory locations $FFFC and $FFFD 1s loaded causing the MPU to branch to an interrupt service routine in memory A nominal 3 kQ@ pullup resistor to Vcc should be used for wire-OR and optimum control of interrupts. NMI may be tied FIGURE 9 POWER-UP AND RESET TIMING =) 4.75V 7 Vec te te 2 Option 1 (See Note Below) RE PCr NOTE: If option 1 is chosen, RESET and RE pins can be tied together oo Option 2 (See Figure 10 tor Power-down Condition! IPCH MOTOROLA MICROPROCESSOR DATA 3-263MC6802 directly to Vcc if not used. Inputs TRO and NMi are hardware interrupt lines that are sampled when E is high and will start the interrupt routine on a low E following the completion of an instruction Figure 11 is a flowchart describing the major decision paths and interrupt vectors of the microprocessor. Tabie 1 gives the memory map for interrupt vectors FIGURE 10 POWER-DOWN SEQUENCE TABLE 1 MEMORY MAP FOR INTERRUPT VECTORS Vector Description MS LS SFFFE SFFFF Restart SFFFC SFFED Non-Maskable Interrupt SFFFA | SFFFB Software Interrupt SFFF8 SFEFFQ Interrupt Request FIGURE 11 MPU FLOWCHART Start Sequence SFFFE, SFFFF f Yes HALT Machine No on Halt Y Yes ss HAUT NMI No No Yes TRO No Yes Mask No. On Y ' Fetch Instruct Execute ete ruction Interrupt Routine Execute Instruction NMI TRO $FFFC $FFFS $FFFD SFFF9 - ! 7 MOTOROLA MICROPROCESSOR DATA 3-264MC6802 FIGURE 12 CRYSTAL SPECIFICATIONS 1 Cin Cour 3.58 MHz 2? pF 27 pF 4 MHz 27 pF 27 pF 38 0 39 6 MHz 20 pF 20 oF Couars v1 T Cin 8 MHz 18 pF 18 pF Crystal Loading iDt Ta Y1 ui C1 Rs , co IC Ww Nominal Crystal Parameters* 3.58 MHz 4.0 MHz 6.0 MHz 8.0 MHz Rs 600 502 30-60 0 20-40 Q CO 3.5 pF 6.5 pF 4-6 pF 4-6 pF ci 0.015 pF 0.025 pF 0.01-0.02 pF 0.01-0.02 pF Q > 40K > 30K > 20K > 20K These are representative AT-cut parallel resonance crystal parameters only Crystals of other types of cuts may also be used Figure 13 SUGGESTED PC BOARD LAYOUT Example of Board Design Using the Crystal Oscillator 20 mm max YL fo a Signals are Not Wired in this Area Z CL Crystal CL Y NS 8 m \ 20 mm max9 E Signal is Wired Apart trom 38 Pin and 39 Pin 28 MOTOROLA MICROPROCESSOR DATA 3-265FMGVRE 14 MEMORY READY SY NCHRONEZATION tity Oscillator EXT AL a XTAL EI MCE = MAF Religie Alaeaedd y Gana iron C5 Loge SNe4aL574 FOGLE 16 MA NEGATIVE SETUP TIME REGLAREMENT E Glock Sireteh The EF Goce will OG p1ratched at end of 6 Pegi of ine cyte Gureng whech MA negates mets the fps setup wee. The ps Sette kerr od. reherenced to the Tall of E_ ti ipo) sebup time is not met, E wall be saretcned at the end of che ine Ehigh 4 creole. vill ba enrescheed in in- Reged ereullieikes of a fiche Assuming E Clocking etecs ee etpcs fe Pcs ee es q I T | Siriched E i Lf le 1 " Ll The E cock well eum! nonnal operon abe end othe 4 cyclo durmug which Al aagertion meets the TR Be Tere, Tha tp tua tee Bceterenoed po iransitans of F waned ried aeetched Wipes setup time is mag mae, E aall tall at ihe secerd poscble Waersiteae tenes otter ha A asserted. That is mo direct means of determining wiher the pes neflargnces oncur, uinieas The aynchroninag decid of Frgur t4 is ume MOTOROLA MICROPROCESSOR DATA 3-266MC6802 RAM ENABLE (RE) A TTL-compatible RAM enable input controls the on- chip RAM of the MC6802, When placed in the high state, the on-chip memory is enabled to respond to the MPL eontrods. bn the low state, RAM is disabled. This pin may alan be utilized to disable reading and writing the on- chip RAM during @ powerdown on. RAM Enable must be lonw three cycles before Voc goes below 4.76 V during powerdown, RE should be tied to the correct high or low state Wf not ued. EXT AL AND XTAL These inputs ame wered for the inbermal oscillator that may - ee crystal conirolled, Thes connections am for a parallel resonant fundamental crystal Isee Figure 12). (&T-cut) a dnvice-by-four circuit has bean atided so a4 Mg crystal may be used in liau ofa 1 W4He oryetal for a more oost-ellectve system. An example of the onsiial circu layout & Shown in Figure 13. Pin 39 may be driven expennally by & TTL inpug signal four times the required E clock frequency. Pin 38 re to be grounded. 4n AC network is mot direcily usable as a frequency Sonne on pins and oO. An AC network type TTL or CMOS oscillator will work well as long a thee TTL or CMOS output drives ihe on-chip oscillator. LO networks are not meoommended ta be used in place of ihe crystal, if an external chock i used, it may mot be halted for more than tpyvaL. The MO6802 is a dynamic pan except for the internal RAM, and requires the excternal clock to retain balhonnaatic MEMORY READY (MF) MF is a TTL-compatible input signal controlling. the sini: ching of E. Use of MA requires synchinonization with the 4a, sgnal, as Shown in Figure 14. Viren MA ig. igh. E ved be in normal operation. Vireen MIR ig low, E wll be girepched in- tegral qumbers of half periods. thus allowiew interface to Blea menunes. Aherenry Flach taming cs Shc Figure 715. MIA showd ba tied high boommecred directly to Vee! if nor veed. This is neGeSsary TO ensure Propel aparation of ihe part. A mann stretch i toy). ENAGLE \E) This pin supplies the clock forthe MPU and the rest od the fystem, This & @ single-phase, TTL-compatibla clack. This deck may be conditioned by a memory read signal, This equivalent to @2 on the MOGSO0. This quipur is capable of drhang one stendand TTL toed and 13) pr. Voc STANDBY This pin supplies the de voltage to the first 32 bytes of RGM as well as the RAM Enable (RE) control logic. Thus, retention of data in this portion of the RAM on a PoOWwerLUp, powdr-down, of standby condition is quar anteed. Maximum current drain at gp maximun is ISBB- MPU INSTRUCTION SET The instruction set has 7a diferent instructions. inched are benary and dechral avithmate:, bogecal, shit, rojabe, bead, Hore, Conditional of untonditional Branch, interrupt and stack manipulation instructions (Tables 2 qhrough G}. The in- airuction set is ihe same as that for the MCBAOD. ~ MPU ADDRESSING MODES Theta are seven address modes that can be used by 6 pro- gearnmner, with tha addresing mode & functors of both the Tyee ool instruction and the coding withen the inatipttion. & gumenery of ine addressing modes for a partcular ingtructon can be found en Table 7 along ven the assoc ied ingtruchon @eecution time that is gwen in machine cyces. With & bus. Treguency of 1 MHz, these tines. woudl bet microaeconds. ACCUMULATOR (400%) ADDRESSING hn accunallaior only addressing. either acocurmultor A os accumulator ts speciied, These are ane-byie mituctiong. IMMEDLATE ADDRESSING ln inneciate addemssevg, the operand 16 centeimed in the second byte of ihe instructen except LUbS and LOX which have ihe opeaind on ihe second and ghird bytes of tee im- siruction. Tha MPL adcnasses (hit locates wen 11 fechas. ihe irmediaie struction for execution. These are tan of INT eS Byte mires. DIRECT ADDRESSING in direct addressing, the address of the operand 6 comtain- ed in the second byte of the inatruction. Owect ackdressing allows the user te dingctly acehress the loans: 2505 bree ori thee machine, at. locations 2ero through 256. Erhavced aaecu- hon es ane ached by Storing data in these locates, fn mos confeguraions, | Should be 4 nanden-aocees mrenary These are teoe bye instructs. EXTENDED ADDRESSING In soended addressing, ihe atkdinass contained mn the oe- ond byte of that insimection 1 weed 3 the Regiver eight bits ot the address of the operndnd, The thied byte of ihe inetrecian ipueped as the loaner eight bets of the aceireaa foe the operand. This 8 an absolute address in memory. These ate three-byte MeL. INDEXED ADDRESSING In iniesed ackineinmg, thet achdinesa cortaened in the sa cond byte of the ingtruction & added to the index regimes Lowest eight bats in the MPL. The carry ie ther eck to the higher order sight bits of the index requester. This result is then used to addness mameory. The modified adidiness ts braid in & tempers addmest register so then i ho Change ta the indew raginier. These are teo-byte insimections. MOTOROLA MICROPROCESSOR DATA 3-267Mc6B802 IMPLIED ADDRESSING byte of the instruction is adkdec to the program counter's In the aripliad addeeaging made, the inainactian gives the lowest @ight Bits plus io. Ther canny or ibontow is Then added achiess (1.2.. Stak Denter, index regener, atc.!. Theae are to the hegh eight bits, Tris adbowvs ihe weer to address data pme-Ey te ingtruictions. Within grange ol 128 to + 129 bytes of ihe presen mestruc- hon, Thee ane techie inrections, RELATIVE ADDRESSING In relative achdinessing, thee address Gostained in ihe second TABLE 2 MICROPROCESSOR INSTRUCTION SET - ALPHABETIC SEQUENCE ao Ade) Acurnulabors GLA Claw Pu Pull Cata Adil with Garry oy Citar Chenin ADD Aad CMP Compme BOL Rotate Lett AND = Logical And COM Complement non Rotate Fgh ASL Anitiimeti: Shit Lett CPX Compare Index Register Pasar Fram Witderruapa ASH Anthmaric Shit Plight ATS. FReatunn from Siberia tena AA Cecimad Acquict SBA | @CC Branch # Cary Cisar DEC Decrement BBO eae! Recuatwlalore Bos Branch if Casry Sant DES Decrement Slack Fomor SEC ubtract weit Carry BEQ Branch # Equal to Zed BEX Decrement Index Puegesber Se Carry BGE Branch # Greater or Equal Zero SE! Set Interne Mash BGT Branch # Greater than Zero EGA = Euchaive OF SEV 3o4 Cveviiow BH = Branch i Higher INC Increase STS Biore Arcumulaice EaT Bill Tees INS. ine t Stack P 51S Sion Stach Pegs: SLE Branch # Logs of Equal ii increment inden Fiegigser ae aes Index Fimgestar BLS Braren @ Lower o Same wee Sw Latte eet BLT Branch # Less than Zero 4 Aang | Sodhwaee intannupa Bal Branch # Mirus JA Jump to Subroubre Tag Trangher Accurmulators: BNE Branch @ Net Equal to Fer Li Load Accunmulaior TAP Tranefar Accurnmalpbors te Conon Coe Fag BPL Branch # Pous LDS Lowel Seach Poonber TRA Tranafer Acturmuladors. ERA Branch Alay LIOx Lined Inchon Foegeatar TRA Trarefter Condition Come Flag. to Accumulator asa Granch 16 Subroubew LSA Logical Stat Aight TST Tal BYC Branch @ Cwartow Clear NEG Negate TSH Tranater Stack Power to leche: Plegister avs Branch @ Overfiow Sat HOP ie Ts Tierder ines Fheqester to Slack Powter CBA Compare Accumulator: WA Wiad for intbennugt cle Clos Cary OPA Inchugive OF Accunnalaice CLI eer inbertapl Mask PSH Push Gata ee MOTOROLA MICROPROCESSOR DATA 3-268McCEa02 TABLE 3 ACCUMULATOR AND MEMORY INSTRUCTIONS SOA RAC eS SRO Rane A TE TIC PARTI TOeo SOB eee on 0 DIRECA aa B iT ee aA Le age eoayaja oe _Grtaalat wacmowec | or - |e alee =] aR sl or - iets tm come mre pee add aOR = 7 a of} ff) ab & 2] an aes ee ee 40ba (2. y #]/08 @] te & FP bh #@ 9 Bit - 12 i Fuld Aemiery i att i 7b) meek |! : add ae Cary a0 Ge mF J] @ BD J) ae & J) ar 2s | meme fa remylgey rye DC0 fi + @) 8 9 FFP & Fee # oF Beek -& ile rtd meg ana m@ fF f/m 4 fF wh & FP # 7 o-w ale =|e ane om oF jgtoe sy rhe & Fl re & F i'M -8 wpegi yc] ay# a Cee site me 7 FL 1 F as S FL a FT ae wlayt |i) ale ate C # Fhoh 7 F[et & Fhes @ 8 a miei} t)al@ tna cLe mm 7 pow 6 3 ob -u &) aha CLA a oF oUt Ma a) )e |e} aya CLAl moF oft Mci a) all eja i] cola fe o7 Fide a zat 4s fF) et @ 7 a woe cys oMaE ae o7 Filoro+ afi 8 ayee a o a i wyeyry: : (a vine oa j al cea re mele poy riya: Career. 1% com f 3 og) & 47 @-u eypeysy rye Chel 416]0a/ d-# ole ais Dake 1 hi + 1] ae a|f BAYS Livers ne Fu REG lou rpm aw 3 @ om ele Dac Rages aoa, | [ao Fo ov)a aes ia] a Lia: wEOG Peo F ti] moa: web: |= he Doers ae chart ah ous iF 1 fh Gipeeeea Beau Het of CO Ceri | 5 cowie BACB) Fa el Dagens bee ao 2 fk oF OG mot Mw le : i Depa (ah 2 ot | aA wok ele]: ae DECE I 1 aa | B oi f-& wee li yt - avira OF rapa mo: ot) ge ko piae bo afg@n 4 4 aie +a ejei | idede ee Choa fim & Fl eh & F]eH 4 1 | griue =a eyelo yo ale ine tHE fc ot og|/m & 2 | Mor -# aye) ls ae ie ; ae Fo ft get ed ale : E|* | mucE | | eo ee | *|* . ue Lewd om abka | dk oF oF) 2 Fl ob & J) me 4D jum eyes cya Loe % 2 F)o8 3 tlie 5 i} te & 2 ; wil ele) tc] afe 2h, Uriel ine Oeag ia 7 F)aa 7 z| a2 4 liga @ 7 | we ow =| = A *| (4iae to 27 Fie 1 Foe 4 Pita a 5! Rem -& =) = >| aja Punts Dotan Pe | i @ 1) wo sep GF ot ae | a) ay rl | out Bo-Mge Oe +e =| Lo) Pali Data Pula ! oot |) eT ee) i FULE | 100 | See oe ee | a) aa Aguile hati ADL leo oa fla & 4a u - = ua ! =| mais | oon | =- i . 5 bEue | | c = a) | Sues Meer aga ee Tb FF, & 1 a] = . * at eure l 46 F 4 | | ee a COT} |= HAE | % F tlt + ow ~*~ w * : Grol) [aly Gedtesria deh | | @ 2 Fl a & 3 : } - - ! ails 4 7 tok a - 5 s[el: 1 AGLE wm 7 oils c br 4 alert Gay Feghn, dl remti asa | woo oa[on 3 | = ales]: a jaro rorya =] = omit): ayp odo a elelo i: Seis Flap Leip i LSA | m@ or apm eg 4] mM a)ala : LRA a7 4 | a|eja-? 7 LaRa aor oF) @ E ajeiae: : Seine dpa 1a lar a gla: zler& & | as ee Ce Sree Good Shab & FE_rt & & pou =| 2) a) Swi! Paes HOF OP a Ola 2 Mee als =|" ae <6 7 a@]m@e 1 fy) o& Fifa 4 4 kb MOR a| 4 babies dare we ig 7 1 | a& of a afer oy: hemi: wih Cay Se ar oi of) os afar & Fig? 4 3 a 6 bea a|@ =| = seca of cr or o2[ pk B oF] ke & ale a ah | Bw Le Fela) s):| 2 Taal Ferd CiaB Mod oF] ack yey tee ibe | a7 ot | ok ayes | fl = Hew Jed dd Wit Thi io * #F\ 45 & 1 j -i alm ol a mah ip } i] t-o a) +l ale 1s18 | ob * 1/5 mlm ln 5 - hu i fi rive Lio bee. Chao i Tet COOL SYeOLs OF Detravee Dede Mirah LH! 2 decades ln tho et 08 ~ Fiembe ot MPL Gye El Rates Evite k = Aske it Pegeain Bate BZ Told: a ! 7 Baugucopis: Pig * Teper begs LT dpe Broa i Bis fer z Wawa 2 Moo o@yu' feo Yo Ghemrtga 7 coger Bg Cre reine eit bites ee ee Stee Pd cE Gay him Be? A Git! Bonin! Print Riga) a Ot ee gee ry eri ed a a lt ae PED tegen 5 Srl i har : Tau aed oe Foye cibwetd Oe Bo Pgh ieecr eo MOTOROLA MICROPROCESSOR DATAMCBa02 TABLE 4 INDEX REGISTER AMO STACK MANHAUILATION INSTRUCTIONS COND. COE REG. HED OWREET ae exteo | PLEO sla, a)rlila@ PRINTER ORERATIONS MMpemet | Oe eijer) =| efor) = | ler) ~ | =| or] ~ | = | ADORE AM /ARITMMETIC OPERATION | yt MZ) yc Camparr Lagea fleg cru BE P/O) 4] PlAC Te) 2 yeep ge | 7 Tq- MM Tes Tk * 2h) l= Deciamend Ladin Aay DEX miei L-0 Tk ae elise Dera mena Stark Pry ols | malt a | -5P se lel ele [ne terran besten Alege IMix 1 m,a) i Kel ck -_- 2 i+ 4 im nae ok. Per a i mya i SPa1 -F .* *\* a| aud Indes Arg LOK |e BOE) a) Fyee | eB alee) aya | i 1s 2: z\* aad Stacie Pra Los or at a/mel a! fag] a op ijae! Ss ta L Mo BPy cls OF SPL je eg: ee feos Ince Bary at oF) & | blew) rs, ride) B&B] 4 i ee we eo Be fone Suck Poe sty ae) S| lari ri) r aFi a | ri | OPy = SR, iM + Ol ees ale vd: Beg Guach Pr TS : } |i |x paul eo ee 2 eee Suck Fras - inte Reg was i - | mati aP +1 -% vies alee TABLE 6 JUMP AND BRANCH INS TRPCTIONG (COND. CORE REG. RELATIVE | INCRE eta | ieee DH eialala] a |i PER TOs mabe oF | lor) ~ | lope ~ | =| or] ~ | = aAROH TEET Hw) bt wl zi[wle Bitar Alves ena mi) alz Mare alae a] | | Braeca It Caory Cheat oc a4) ca = js =| =| Grane if Gerry Set BCS BM) a ]2 E=1 sie a} el ete Branch I + Zen ano v4 )2 | EI ee Branch if 2 Bera AGE a | AV * | @| ae) ele Branct I > Zero BGT Weatay | i Penewieg ee Granct |! Hightr be Iki & j 2 | | f Cetao =m oem | ae Geaach FS Zora OLE wlada | foinGyvi= bi oe 8) | a] @ Fr Geanch ff Lower Oe Saree ALS zi? C+ze ee ee ee ee Beach 8 = Pera BL mila]? A@iwe=t o! # |e) ae) e Brasch @ en Eee Te) & Zz moo -_ *| - - * Bigech H Hea Egil Zea BR 1a) & | 2 f i fad | eo) oe) eye Baarcth 1 Coe lliteer Ciarar But. mi} ajz : v= =| =, *| | | # Branch H Ghvert| oer het bw mlaj]a | Wea ee Buueah H Plas ot ja) a | F ao oe) oe) oe] o] oe) Graongh To Subecstine Bef a) a] f * | =| ohm) * Jer jer te} a! ga) me} a) 3 ; See Spero Desire |e a) ole) jump Ta Subleubre 1s an} e)z}aohel a (Figure WH . rit] alale Me Ceeation ao Oi] ryt Adan Peg Cem Only ele] eo! a] =| riven Fee te perapt aT mie] tl i Rett brim Sebecalioe ATS Bie ji i *) |") * ale a owl May a fen Specie Oe wire eee Viet tor Irimerage wal ae |e ja j CFiggare 18) | 5 ej) el we) ie MOTOROLA MICROPROCESSOR DATA 3-270SPECIAL OPERA THOS SA, JUMP TO GBROUTINE: fi eel ned iain Peegrier: Ao: Je = Ofer Adee Mba |irtar, FIGURE 16 = SPECIAL OPERATIONS i= BB Unnigead Ystue * avril net nad Ex TAO Adgeg Mga rs leapt BSA, SAAMCH TO SLBA UTINE McCess802 oF oF SF Sime k ra fda yt rp ie + Kf lin Gas, ten Jae # | letHl qi let Ti, Pom nud facia ft Subrawi ine + Vu Seariied | sett la+dh jetHi 14, Poatrrered Fr get Sy eal $1 8 Grech Power Atte Eooceiras i an Progra td Suck ria Sua rive be n | 60 2 BSA EP-3 eee Eb it Sobel net | om Colwat c> ari | |nazl ne] | Mees Men ieow o lie 2a "Ko Bit Sogred Wubur, ne? Partted Fram la Fay get is ty SP, JLAP PE Mao Progam ew 0 G2 = jae 1 nad | 6 Olber wet footer Oko r EX TENUED Fok ag & ao ATE, RETURA FROM SURG Tin PE Sabreunire e ha a. . 4 ~ ATS Pp Wei Mba ent SPal fy - SF-e | ay AT) ROTI FOw INTER RT: ee _teterrupt Progr GF PL fot Bogan & bt ATI op ' Peewi ais Irait => Spat iiadana C cer Y merriir | aeons A SP aa Laer gP+4 leis A aP +o + f+7 TABLE 6 CONDITION CODE REGISTER MANIPULATION INSTRUCTIONS. COMO DO Flt eee Per 5 4 9 Fit ff OriaTioNs Mmeenenet | oF] ~ BOGLC AN OPERATION | Hi a Fiv lees Carry rir pela] ee es. # ee oF Gaur Wniwrugt Wak Cia Mf? I ol 2; i #*# & @ Ciera Dear iigres Che bapa] i Bed ie # @ & & Sat Catty SEL i ik ee ee ee ee Bec Drippenioge Pty pe SFI ie oe I To oe 8 s + & & Sat Ohare! are SEW way? t 1-5 *, #@: # ik @ aowir A CCR rap ay? A -ECH ii - - CCA Ace a hPa arly | i COR +a epee COMDITOON CODE REGISTER MOTUS: Wet ett tect aia aed cteor hd anhereniee (he wi Test few = eee 2 (ori Tart Sege ber ae ppd 1S Bie = 17 ech Tea Rao | SOO a [Ba WR Ten 2s ceengterman cerita Pra debe of AG pep ee! om Ch tewi Gerad sabre ol etc) dep ar A Coates greeter Pha rota? 7 tei Tak Repel) es Pgs pera (Bi bh Te Cig clemeedl ptiveturity tit | io aa Load Cosmic: Goede Angeriee trees Siete Chet Seecal Operas cea et W Ta Opened = MOO aoe ge ewan? TE (iri) Sa ver eeierrapt dtcuts IP prewigeeiy eel a Acer Muka bir Ba Vl Tee Gperered = GUO ET epic de eeecube Vereen pri as remade, EPep edd, SLE [Ba W Tept Set aqpeul dail of ARC Pee dh ha Gerd Ve imal Seri acberdhesg ta [he beretats of Aicparstator A MOTOROLA MICROPROCESSOR DATA 3-271TABLE 7 = INSTRUCTION ACDRESSING MODES AND ASSOCIATED EXECUTION TIMES (Tires in Machina Cycie) a | Peery pepuee y ang An ee xOOF Pur aa Ay Peeps | BRE PRPS ag HepRUWY Roy [ue aE) PAL | CFP PRK TT ee ay eee eS oe ee Te ee ee ee ee ee ee SRP T EM PRE Te eee eT eee ee ee ee ee ee ee ee ee a | ag OFA ATs SEA 260 SEC BEI SEY STA STs STK Sue Si TAB TAP THA TPA TST TSM TSe Wal TI IRE REE LOA LSA e325 ee ee ee i ee Mette ee REY a ee too Pb wite be ee a ee aa PO eh errr te be a aaa eer eo ee ee PHA tek eee Pa aa ea aaa a eo hit & ee te eee Pea eae a eS See eee te Pe ee a a he a re ee ee ee a z a a a 1 BSR Bw Bus CHA ELe fehl CLA LY CoP COM CPx oa DEC oes OE EOR &OT BHa HIT aLE BS BLT Boi Babe: BPL BAA (errs terme se 82 ciecien trom ae ened of MOTE The Cru being eeecuten, emcee toliossng aA A trustee Thee tis cycles MOTOROLA MICROPROCESSOR DATA 3-272MCBEBO2 SUMMARY OF CYCLE-BY-CYCLE OPERATION. Table 8 provides 3 detaiked description of the inf@mation present cn the: aches. bus, data fue, valid merry address line VASE, and that readowvrite line (RW during ach cycke tor #ach mestruction This informatiqn if uselul in Comparing actual with &- as ihe control program i executed, The information categorized in groups etoording to addressing modes and number of cycles per insireciian. lin general, instructions with the same addressing mode and qumber of cyches ex: @oute in tht 52m manner: eceptions ae indecatad in the pected results diusing debug of both sothwar and hardware Late. TABLES OPERATIONS SUMMARY Address Woo Cyele | Vi Aa and Inpirestions Cycles = | Line Address Bue Line Geta Bus (MRE DH ATE ABC EOR 1 1 Op Code Address 1 Op Com Sno GMA , 2 | + | Gp Code Addras +4 1 | Gperenet Cont BIT 38Cc CMP Sue crx 1 1 Op Goce Jaca k Op Cone: toe } 4 1 | Go Gode Acdinem + 1 1) | Operanad Gara deegh Geder Byte 3 i Oho Code Address +2 4 Onerend Data (Low Onder Byte! CiRECT ADC EA 1 i Op Code Acdoiners i Op Code OND oR 4 z i Op Code Addreri + 1 1 futdress of Operant BIT Sac a 1 Aetdross of Chperared 1 Oepetrared Deena CMP Sue crx 1 tT Op Code 4.cidrese i Op Coste ro 4 2 1 | Op Cede Ades + 1 1 | Adkiress of Querancl d 1 Address of Opened | Opnand Dara (High roe Byte 4 1 Dperaed Scores + 7 Kk Operand Gate dlaw Oeder Byte ST 4 1 i Oo Code Acdcrees 4 Op Coe 4 Hy i Op Coda Address + 0 4 Gaanacten Address + o Gettination Agel ree i lcreteant Gate IWete 1 ad 1 Gastinaclon uddress a Daa feaen Aerie STs 1 1 Op Coe Ache ada 1 On Code aTk t 1 On Code Odeiress = 1 1 Atdeeds of Oporand 5 x 0 Ackdren of Ope ant t trreleveni Gaia (Mote 11 a 1 Addr of Openend O Fioguter Ooaa (Hign Order Byte! 5 1 Adidreni of Operand + 1 o Rogier Gaia lLow Orce Byte: IMCHE EC e 1 | 7 | Op Code Adcnens 1 | Op Cote 4 2 1 Op Code Address * 1 i Otaer 3 o Indes Fosgister 1 lerglawant Cate iMate of a lide Plagister Plo Od heed belo Carryh 4 lreeelavant Date IMede 1h ADC EOR i 1 Gip Code Adhete aad 1 Op Code Pet Ee 2 * | Ge Cade Metres 4 1 t | Ffeet BIT See & 4 a Index Magister 1 lerektwane Data |Miote 1) cMP Sus 4 ny Index lagicter Flue Of Feet tui Cary) Do | berelewery Qevta Mate 1! fi 1 Index Plegivber Plus Otfser 1 Oparand Data CPx k 1 Op Code Acdciness 1 Op Cee OK ? 1 | Op Code Adaress +1 1 | Otises & 3 o indian Alegierer 1 irrelevant Daca (Mote 1! 4 o Indes Flegieter Plus Ot tset levio Genny] 1 Irretevant Gpte (Mobs tt 5 i Indien Fspiscer Pius Cofi et 1 Opened Gata High Order Byrel a rl Ingen Foepitter Plus Offset 1 1 Operaend Dats [Low Order Bytal MOTOROLA MICROPROCESSOR DATA 3-273TABLE @ OPERATIONS SUMMA Y (ON TINUED) Aicines Mocs Cros Vea AA anu Inetrusteon Eo Line Addren But Llrom Dats Bot INDEXED (Continesd| STA 1 1 Oo Code Achdinens 1 Op Conia 2 1 Op Code Acdires + 1 1 Oftteee a o inde Flggintae 1 inredevent Dace ieee 1h 4 a inden Plagecper Pius OfFdaet feelio Corry! 1 lorelevent Date (Mote 1} 5 a Inclgs Foegesner Plus O0 tse 1 Irrelevant Gane (Nowe 1h 6 W Indo Foegasber Plug Oldant a Operand Gata ag. Lse ' 1 Op Code Address 1 Chp Coscia Aen MES 2 1 | Op Code Address 1 1 | crftsat CoM BOR a 0 index Faegisear t lrrelevert Date (Mega 1h rd TST a Oo Inde Poegisner Flos O@tped Gea Carey 1 berelowert Gata iMone 1) 5 1 inde Fregianer Plas Cleat i funrent Opeaend Geis 6 o Jndee Fegiger Plus Otis 1 benelewont Guta (Nome 1) T ae leiate Alegisiee Plus CM feet o Mw Qierand Chota (Mote Fl i STS 1 1 2p Code Soden 1 Op Code sTk 2 1 Oe Code Agere + 1 1 | Geen a a ined Poegisner 1 trrelevant Gite INone 1) a o Indgs Feegiser Flos Ottaes bea'o Caregt 1 brreleant Date INege 1) 6 o indas Rogismar Plus Ofipe 1 Irrelevant Gate IMote 1) 6 i Ince Flagieger Pla Ce taet D Operend Dam High Order Bye) ? i inden Regier Plus Offset +1 O ) Oiserend Chevte (Low Grder Gye JS i 1 Oo Cocke Arciebrena. Op Code z 4 Op Code icdress 1 i OT aet a o index Fleyiiter 1 forelevend Coste (Mote tb 4 1 Stack Pointer a Peta Act ags (Low Oroer Gyr 5 1 Stack Posner 1 a Getuen Aaidrese (High Geode Ayre) 6 o Saackh Poster F 1 irrelevant Dota [Mote 1) 7 a indo, Register T Irretigvant Oate IMoie 13 a a Indes Flegiaar Flu Odteed leo Garey? t lrretewainie Data WM 1) EXTENDED JKaP rl 1 Sp Code Address i Op Code z 1 Op Code Addresi + 1 q durrgt Aderesa |H egh Chreder Bybel i I Op Code Address #2 4 Jump uddrees. Low Oro Biycek abt FO 1 I Op Code Aceireds 4 Op Cede ane One 2 i Op Code Address + 1 1) | Address of Qnerand (High Order Bytel BIT Sac 3 1 Op Code Addreds + 2 1 Addren of Cierand (Low Order Gytel CMP SUB a i Gddres. of Giperancd 1 Oyperored Dura CPx 1 1 Oe Greve Ascher ana 1 On Code toe 2 1 Op Gode Aeidress + 1 1 Address of Cperand (High Order Bartel q 1 Op Goede Adkdran + 7 1 Address ol Cherand |oowwy Order Byte 4 1 Addins of Cpa 1 Opera Dana iHigh Cider Bye 6 1 Sudorece of Oper + 1 1 Operand Date (Loew Onder By tel BTA A 1 1 Op Gode Acidress 1 Op Code sTA B 2 i Oo Code Addinegs + 1 1 Bestimation Auddress didigh Grdier Sytet 3 1 Op Code Address + 2 1 Gemination Adereas [Loew Order Byral 4 Oo Opera Bettinaten Acide W brrelevent Cate iAiote 1) & | Oped Gestieation acidirere O Gate Wom decile ASL LSA 1 1 Oe Code Achlreng 1 Os Cade CLA ne Zz t Op Code Adres * 1 fl Agteers of Operaeno (Magh Order Byte) COM ROR a 1 Op Code Adielrass + 7 1 Adin of Opened lew Cede Bye cee TST 4 | 0 | etches of Coperandi 1 | Current Operand Gata 5 a Aeneas of Cypeea rad 1 ieneevarnt Cave ioe 11 a nme aides of Opera a Mew Ooeend Gate (Mose Fh #1 MOTOROLA MICROPROCESSOR DATA a-274TABLE & OPERATIONS SUMMARY (OOM TIBLHED a Steck Pointer + 1 Stack Pointer + 7 Agden Mode Cyote | VA a and bnacruethoed Cyehes = | Lee Aeiress Boe L bre Bete Bua EXTENDED [Cantinged) STS 7 7 tip Code Aderen 1 Op cede STx 2 | 1 | Gocode adden 1 1 | dcidirest of Gperand (High Crder Bytel q 1 Op Cote Aceirasa + 7 1 Addn of Opened (low Oedar Bytel 4 o Atidred of O perm 1 ioreevant Date [Note 1} a 1 addres of Open a Optrand Gaaw (Haigh Order Bytel 5 1 Acicleea: eof Opera + 7 io Operand Chara (Lew Order Bynes A i 1 Op Code scidieeas 1 Op Code 7 1 Dp Code Addeeq + 1 i Atari of Subroutine lAigh Corder Syed 5 1 Op Code Achim: + 2 | Address of Sutteoutiog (Low Order Byte! a 1 Sub reutine Searing Adela i Op Code of Mee liareceion 4g 5 fi Steck Polriter 6 Return Addrere (Low Order Byiel 6 i Stack Poser 1 Oo Retunn Address (4igh Order Byte! T o Steck Poirier 2 A irrelevant Date (Mote 11 8 o On Cece Agdreni + 2 I Irrelevant Dana (hots 11 gq 1 Ge Code Adore + 2 f Addreii of Subreauwtine | Low Order Byem INHERENT AGA 04a S8 7 1 1 Op Code Address 1 Op Coda ten ee Bel ao) o4 | Gp toda adcress +1 1 | Op Code of Next Instraction CBA LSA TAB CLO NEG TAP CLI NOP Tea CLA ROL TRA LyY ACA TST COM Shs DES 7 1 Op Code Aatdr aon 1 Op Cece cEx 3 1 Op Code Adicdress + 1 fl Op Code al Meek ingiruction rh a Oo Previous Aegnaer Cones 1 irrelevant Dice (Note Uf 4 o New Feegetter Contests i ivralevent Duta (Nene o1 Par 1 i] Op Goce acidrass 1 Op Coca 3 1 On Code Adedraaa + 1 1 Op Code of Ment baruceian 3 1 Stack Pointer O &ccurmalato Gata a o Stack Points 4 1 docoutslaece Data PUL 1 1 On Code Address 1 Dp Code 4 F 1 Op Code Accra = 1 1 Op Code of Maras lgruceion I a Steck Pointer 1 Urrelgeent Date (Mote f] a i Stack Poinves + 1 1 Opeand Caea tron Stacie TSx 1 1 Of Code Addredt i Oe Cocke 3 1 On Gode adhe + 1 1 Op Goce of Mast knarucian 4 a Stack Puiriber 1 rrateant Bete [Mote iF 4 0 Mena Irie Flegigner 1 lerelart Dot IMo 1h THS 1 | | Op Code Adcre | | Oe Come 4 3 1 Op Code Adcrers + 1 1 Op Code of Maat lristructor I o bide Foegigter 4 irtelaweny Chaba dd o hee Stack Pointer 1 Irrelevant Cita RATS 1 1 Op Code ddd t fp Code 2 1 Chip Goce Adchregs r 1 1 irrelevend Devte OMiote 23 & a a Stack Pointer t Ural Data OMone 1) 4 1 1 Aatdrigge of Agere Ieetrction |eligh Larder Bieta! Agicress of Meocg lingtraction (Low Ohndier Bite] MOTOROLA MICROPROCESSOR DATA 3-275MC6802 TABLE @ OFGRATIONS SUMMARY (CONCLUDED! ocidemes: Ml cha Cyeie| ve a anal bnitrot thn Cycles # | Line Aderaas But Line (Chat Bit INHERENT ([Gomminueadl Wal 1 1 [Gp Code Adidvess: 1 [Op Code i 1 |Op Code Actdewes + 1 1 ] Oe Cache af Mace legen z 1 | Stack Pointer 0 | Aatun Address ow Order Byte! a 1 | Stack Pointer - 1 0 | Retum Address (High Order Byte a 5 1 | Stack Pointer 2 D J indes Begivter | Low Order Byrtel {1 | Stock Pointer 3 0 | lnches Flagiver [High Onder Bytel 7 1 | Stack Pointer 4 0 | Contents of &ccumuyister A a 1 | Seack Poleter - & O | Gerben of Accumularor 8 ga 1 | Steck Pointer 6 1 | Contents of Cond, Cece Ragianer ATI 1 the Goce Acie 1 | On Code 3 10 | Qe Code Acedreas + 1 1 | irretecant Dota (Mone 2) a D | Stack Painter 1 | leraeveet Geta (Mote 1) 4 1 |Saack Polnter * fi 1 contents of Gord. Cocke Flegerter troen Lae 1 5 1 | Stack Pointer #2 1 | Geeten of Accumulator from Stack & 1 | Stee Pointar + 3 1 | Gootents: of Accuttylatar A tegen Sack FJ 1 | Stack Pointe + 4 t wae Fiegaier trom Steck [High Order BE | | Stack Pointer + 5 1 index Flegriper from Steck [Low Order Byte 5 1 | Stack Porter + 6 1 | Mert ingirction Address from Stack (High Order Bytall 1 1 | Stack Poitier + 7 1) | Newt Indtruetion Addeess from Stack {Low Grier Bytel Sey 1 1 [Op Cocie Acdcdemes 1 | So Code 2 1 | Op Code Qoddrecs * 1 1 | eeetevernt Data OMote 1h a 1 | Stace: Poanter O | Return Aces (Low Order Gyre 4 1 | Stack Pointer 1 D | Revue diccepe (High Ore Bybel 6 1 | Steck Poinme F | laden Fegigner (Low Oeder Byte! 1 6 | | Stack Pointer 3 | lades Fegarter [Hogh Order By rel t 1 | Steck Pointer 4 | Contents of Accumulator 4 8 Y | Stack Pointer 5 0 | Contents of Accumulane 8 4 f | Ssack Poircer 6 D | Contents of Cond. Code Pegerter 10 O | Stack Pointer -- 7 1 | inveigemnt Gate (Mote 1) it 1 | Veenor Qc FPP A lee 1 a of Sworowtine |iegh Onder 17 1 | Weenor dudcirecs F PPE Cee) I earns of Subrouting (Low Circer te he RELATIVE Bcc BHF BNE 1 1 | Gp Code Addrecs 1 | Op Coca eee BLE ae 4 3 1 [Gp Code Adare + 1 1 | Branch Offeet BGE BOLT Svc a O | Op Cos Achdrase = 7 1) beretevend Gate (Mowe if BGT BE ByS 4 O | @rench Addraim 1 | irrelevant Qaea (More TF BSA I 1 | Op Code 4dcrece 1 | Op Coe z + |) O@ Cade Adams +1 1 | Branch Offtaen 3 O | Aeturn Acres o! Maan Progam 1 J drretevant Geta (Mog 12 & 4 1 | Sawek Pointer O | Raum Address (lowe Cher Byrtel 5 1 | Stack Poinear 1 6 | Return Adgdraaa CHigh Order Bynn! O | Stack Poimser 7 1 | brredevent Gata [Mote 11] 7 O | Betws Address of Main Program ft | btreigvent Darna UNon 11 # O | Subang Addie | Moan 41 1 | brelevent Gare (Note 1] NOTES 1 if devin which addressed during thes cycle ula WAG. Ingn the Daw Bus wel go to ihe high-impedance thres-aiate corcitean Depending on bus capacitance, daa fram ihe preg cyte ay De reained on ihe Dats Bus. 2. Date 1 noted by Tha MPL 3. Foe TS7, WaA=0 and Opeand data does oad char 4.45 Byte of Address Bus= MS Gyro of Qddrect of BSR msiecion and LS Byte of Address Bus=LS Byie of Sub-Aowine Address a MOTOROLA MICROPROCESSOR DATA 3-276MCBBO2 MECHANICAL DATA AND ORDERING INFORMATION ORDERING INFORMATION Package Type | Frequency MHz Temperature Order Na rmber Plastic 1,0 FC te FC MORRO SP P Sutin 10 40C to 4-86" MOGROZCr 16 FC to FOC hiteAgar 1 a0 te +80 MCEBADeCP z0 C to HC McABoeP Ceardip 10 FC ta TC MOGRI?S & Suffix 10 40 to +8 MCEedecs 1.6 Cw wc MOEBADES 1.5 art to +Bs"C Ms Ages 2.0 FC to TC MCEBBO2S FIN ASSIGNMENT Vss ) RESET Halt EXTAL Mik TAL rho 1 Wve, RE Rieti 1 Veg Standby BA RA Vic yet A Gt Aq D3 Az Wo AS oa ul Os AB N Be AB oO AT n AIS AB 1 Ald Ag Aq aid AI? Ali 1 Ves MOTOROLA MICROPROCESSOR DATA 3-277