XTSC423.xxx - 0201 Extreme Temperature Silicon Capacitor Rev 3.1 Key features Key applications n Ultra High temperature up to 250C: n 250C requirements, High temperature applications, such as military, aerospace, automotive and downhole industries. w Voltage <0.1 %/V n High reliability applications w Negligible capacitance loss through aging w Temperature Coeff : <1.5%(-55 C to +250C) n Replacement of X8R and C0G dielectrics n Unique high capacitance in EIA/0201 package size, up to 10 nF n Decoupling / Filtering / Charge pump (i.e.: pressure sensor, motor management) n High reliability (FIT <0.017 parts / billion hours) n Downsizing n Low leakage current down to 100 pA n Low ESL and Low ESR n Suitable for lead free reflow-soldering *Please refer to our assembly Application Note for further recommendations Thanks to the unique IPDiA Silicon capacitor The technology, most of the problems encountered in integration capability (up to 250nF/mm ) which demanding applications can be solved. allows a capacitance value similar to X8R EXtreme Temperature Silicon Capacitors are dielectric, but with better electrical performances appropriate for applications used in extreme than C0G/NP0 dielectrics. operating temperature range (up to 250C). This technology also offers high reliability, up to XTSC industry leading performances allow to 10 propose a 10nF in 0201 with a TC<1.5% over technologies, such as Tantalum or MLCC, and the full -55C/+250C temperature range. eliminates cracking phenomena. This technology also offers a negligible ageing This Silicon based technology is RoHS compliant and a stable insulation resistance, even at very and compatible with lead free reflow soldering high temperature, as well as a stable capacitor process. value over the full operating. IPDiA technology features a capacitor times better than alternative capacitor XTSC423.xxx Electrical specification Capacitance value 10 Contact IPDIA Sales Contact 10 pF IPDIA Sales Contact 0.1 nF IPDIA Sales 10nF: 935.133.423.510 1 nF 935.133.723.510 22 33 47 68 Contact IPDIA Sales Contact IPDIA Sales Contact IPDIA Sales Contact IPDIA Sales Contact IPDIA Sales Contact IPDIA Sales Contact IPDIA Sales Contact IPDIA Sales Contact IPDIA Sales Contact IPDIA Sales Contact IPDIA Sales Contact IPDIA Sales Contact IPDIA Sales Contact IPDIA Sales Contact IPDIA Sales Parameters Capacitance range Capacitance tolerances Operating temperature range Storage temperatures Temperature coefficient Breakdown voltage (BV) Capacitance variation versus RVDC Equivalent Serial Inductor (ESL) Equivalent Serial Resistor (ESR) (*) Thinner thickness (as low as 100 m thick) available, see Low Profile Silicon Capacitor product: LPSC Value 10 nF(**) 15 %(**) -55 C to 250 C - 70 C to 265 C <1.5 %, from -55 C to +250 C 11 VDC, 30VDC 0.1 % /V (from 0 V to RVDC) Max 100 pH (**) Max 400mW 50GW min @ 3V,25C 10GW min @ 3V,250C Negligible, < 0.001 % / 1000 h FIT<0.017 parts / billion hours, (*) Max 400 m Insulation resistance (**) Other values on request. Ageing Reliability Capacitor height DC Voltage stability MLCC capacitors vs. PICS ESL (nH) @25C 0402 C0G(NPO) vs. PICS 10 1,1 PICS 0 1 -10 C0G 0,9 C0G -20 Capacitance change (%) 0,8 -30 0,7 X7R ESL(nH) Unit 1 pF 15 -40 -50 0,6 0,5 0,4 -60 0,3 -70 -80 0,2 Y5V PICS 0,1 -90 0 -100 0 1 2 3 4 5 6 7 0 50 100 150 200 250 300 350 450 500 550 600 650 700 750 Fig.2 Capacitance change versus voltage variation compared with alternative dielectrics Fig.3 ESL versus capacitance value compared with alternative dielectrics Part Number 935.133. i.e.: 10 nF/0201 case (XTSC type) a 935.133.423.510 B.2 S. Breakdown Voltage 4 = 11V 7 = 30V U Size 3 = 0201 Unit 0 = 10 f 1 = 0.1 p 2=1p 3 = 10 p 4 = 0.1 n xx Value (E6) 10 15 22 33 47 68 5=1n 6 = 10 n 7 = 0.1 8=1 9 = 10 Termination and Outline Termination Lead-free nickel/solder coating compatible with automatic soldering technologies: reflow and manual. Package outline Typical dimensions, all dimensions in mm. L Typ. 0201 W Comp. size L 0.80.03 W 0.600.03 Land pattern IPD component Solder Resist (0201 PCB footprint) Packaging Tape and reel, tray, waffle pack or wafer delivery Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. 800 Capacitance (pF) Bias voltage (V) Fig.1 Capacitance change versus temperature variation compared with alternative dielectrics 400 For more information, please visit: http://www.ipdia.com To contact us, email to: sales@ipdia.com Date of release: 28th February 2014 Document identifier: CL431 111 615 123 850 900 950 1000 IPD Capacitor Assembly Set Up Rev 1.0 Application Note Outline Silicon Capacitor for surface mounting device (SMD) assembly is a Wafer Level Chip Scale Packaging with the following features: x x x x Package dedicated to solve tombstoning effect of small SMD package; Package compatible with SMD assembly; Package without underfilling step; Interconnect available with various optional finishing for specific assembly. Assembly consideration x x x Standard pick & place equipment dedicated to WLCSP down to 400m pitch. Solder paste type 3 in most cases of EIA size. Reflow has to be done with standard lead-free profile (for SAC alloys) or according to JEDEC recommendations J-STD 020D-01. Lead Leadfree Tp: 235 C Tp: 260 C TL: 183 C TL: 217 C Ts min: 100 C Ts min: 150 C Ts max: 150 C Ts max: 200 C tL: 60-150 s tL: 60-150 s Process recommendation After soldering, no solder paste should touch the side of the capacitor die as that might results in leakage currents due to remaining flux. In order to use IPDiA standard capacitors within the JEDEC format and recommendation, the solder flux must be cleaned after reflow soldering step. Notes: for a proper flux cleaning process, "rosin" flux type (R) or "water soluble" flux type (WS) is recommended for the solder printing material. "No clean" flux (NC) solder paste is not recommended. In case the flux is not cleaned after the reflow soldering, the standard JEDEC would probably not be appropriate and the solder volume must be controlled: - using smallest aperture design for the stencil, and using finer solder paste type 4 or 5 for a proper printing process. - Mirroring pads would be the best recommendation Application Note Pad recommendation The capacitor is compatible with generic requirements for flip chip design (IPC7094). Standard IPDiA 3D package can be compliant with established EIA size (0201, 0402, 0603, ...). Die size and land pattern dimensions is set up according to following range : EIA size 0201 0402 0603 0805 1206 1812 Dimension max(X1 x X2) mm 0.86x0.66 1.26x0.76 1.86x1.16 2.26x1.46 3.46x1.86 4.76x3.66 Typical . die thickness X3 (mm) 0.1 or 0.4 Typical pad size* (mm) 0.15x0.40 0.30x0.50 0.40x0.90 0.50x1.20 0.60x1.60 0.90x3.40 Typical pad separation (X4 mm) 0.3 0.4 0.8 1 2 2.7 X3 X2 X1 Top side silicon Typ.UBM thickness 3 to 5 m X4 After soldering, no solder paste should touch the side of the capacitor die as that might result in leakage currents due to remaining flux. Rev 1.0 2 of 3 Application Note Manual Handling Considerations These capacitors are designed to be mounted with a standard SMT line, using solder printing step, pick and place machine and a final reflow soldering step. In case of manual handling and mounting conditions, please follow below recommendations: x x x x Minimize mechanical pressure on the capacitors (use of a vacuum nozzle is recommended). Use of organic tip instead of metal tip for the nozzle. Minimize temperature shocks (Substrate pre-heating is recommended). No wire bonding on 0402 47nF, 0402 100nF, 1206 1F and 1812 3,3F Process steps: x On substrate, form the solder meniscus on each land pattern targeting 100 m height after reflow (screen printing, dispensing solder paste or by wire soldering). x Pick the capacitor from the tape & reel or the Gel Pack keeping backside visible using a vacuum nozzle and organic tip. x Temporary place the capacitor on land pattern assuming the solder paste (Flux) will stick and maintain the capacitor. x Reflow the assembly module with a dedicated thermal profile (see reflow recommendation profile). Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. For more information, please visit: http://www.ipdia.com To contact us, email to: sales@ipdia.com Date of release: 20th April 2012 Document identifier: Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: IPDiA: 935133423510-T3N 935133423510-T1N 935133723510-T1N 935133723510-T3N