XT
SC423.xxx - 0201
Extreme Temperature
Silicon Capacitor
Rev 3.1
The IPDiA technology features a capacitor
integra
tion capability (up to 250nF/mm²
) which
allows a
capacitance value similar to X8R
dielectric, but with better
electrical performances
than C0G/NP0
dielectrics.
This technology also offers
high reliability,
up to
10 times better than alternative capacitor
technologies, such as Tantalum or MLCC, and
eliminates cracking phenomena.
Thi
s Silicon based technology is Ro
HS compliant
and compatible with lead free reflow soldering
process.
Thanks to the unique IPDiA Silicon capacitor
technology, most of the problems encountered in
demanding appli
cations can be solved.
E
Xtreme Temperature Silicon C
apacitors are
appropriate for applications used in extreme
operating temperature range (up to
250°C).
XTSC indu
stry leading performances allow
to
propose a
10nF in 0201 with a TC<±1.5%
over
the full
-55°C/+250°C temperature range.
This technology also offers a negligible ageing
and a stable insulation resistance, even at very
high temperature, as well as a stable capacitor
value over the full operating.
Key features
n Ultra High temperature up to 250°C:
w Temperature Coeff : <±1.5%(-55 °C to +250°C)
w Voltage <0.1 %/V
w Negligible capacitance loss through aging
n Unique high capacitance in EIA/0201 package
size, up to 10 nF
n High reliability (FIT <0.017 parts / billion hours)
n Low leakage current down to 100 pA
n Low ESL and Low ESR
n Suitable for lead free reflow-soldering *Please refer to
our assembly Application Note for further recommendations
Key applications
n 250°C requirements, High temperature
applications, such as military, aerosp
ace,
automotive and downhole industries.
n High reliability applications
n Replacement of X8R and C0G dielectrics
n Decoupling / Filtering / Charge pump
(i.e.: pressure sensor, motor management)
n Downsizing
Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner. The information
presented in this document does not form part of any
quotation or contract, is believed to be accurate and reliable
and may be changed without notice. No liability will be
accepted
by the publisher for any consequence of its use.
Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
For more information, please visit: http://www.ipdia.com
To contact us, email to: sales@ipdia.com
Date of release: 28th February 2014
Document identifier: CL431 111 615 123
XTSC423.xxx
Electrical specification
(*) Thinner thickness (as low as 100 µm thick) available, see Low Profile Silicon Capacitor product: LPSC
(**) Other values on request.
Part Number
935.133. B.2 S. U xx
i.e.: 10 nF/0201 case (XTSC type)
à 935.133.423.510
Termination and Outline
(0201 PCB footprint)
Packaging
Parameters
Value
Capacitance range
10 nF(**)
Capacitance tolerances
±15 %(**)
Operating temperature range
-55 °C to 250 °C
Storage temperatures
- 70 °C to 265 °C
Temperature coefficient
<±1.5 %, from -55 °C to +250 °C
Breakdown voltage (BV)
11 VDC, 30VDC
Capacitance variation versus
RVDC
0.1 % /V (from 0 V to RVDC)
Equivalent Serial Inductor (ESL)
Max 100 pH
Equivalent Serial Resistor (ESR)
Max 400mW(**)
Insulati
on resistance
50G
W
min @ 3V,25°C
10G
W
min @ 3V,250°C
Ageing
Negligible, < 0.001 % / 1000 h
Reliability
FIT<0.017 parts / billion hours,
Capacitor height
Max 400 µm (*)
Capacitance value
10
15
22
33
47
68
Unit
1 pF
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1 nF
10nF:
935.13
3
.423.510
935.133.723.510
Typ.
0201
Comp.
size
L
0.8
±
0.03
W
0.60
±
0.03
Termination
Lead
-
free nickel/solder coating compatible
with automatic soldering technologies:
reflow and manual
.
Typical dimensions, all dimensions in mm.
Package outline
W
L
Land
pattern
IPD
component
Solder
Resist
Tape and reel, tray, waffle pack or wafer delivery
Fig.1 Capacitance change versus temperature
variation compar
ed with alternative dielectrics
DC Voltage stability
MLCC capacitors vs. PICS
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
0 1 2 3 4 5 6 7
Bias voltage (V)
Capacitance change (%)
Y5V
X7R
PICS
C0G
Fig.2 Capacitance change versus voltage
variation compared with alternative
dielectrics
ESL (nH) @25°C
0402 C0G(NPO) vs. PICS
0
0,1
0,2
0,3
0,4
0,5
0,6
0,7
0,8
0,9
1
1,1
0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000
Capacitance (pF)
ESL(nH)
PICS
C0G
Fig.3 ESL versus capacitance value
compared with alternative dielectrics
Size
3 = 0201
Breakdown
Voltage
4 = 11V
7 = 30V
Value (E6)
10
15
22
33
47
68
5 = 1 n
6 = 10
n
7 = 0.1
µ
8 = 1 µ
9 = 10
µ
Unit
0 = 10 f
1 = 0.1
p
2 = 1 p
3 = 10 p
4 = 0.1 n
IPD Capacitor Assembly Set Up
Rev 1.0
Outline
Silicon Capacitor for surface mounting device (SMD) assembly is a Wafer Level Chip Scale Packaging
with the following features:
xPackage dedicated to solve tombstoning effect of small SMD package;
xPackage compatible with SMD assembly;
xPackage without underfilling step;
xInterconnect available with various optional finishing for specific assembly.
Assembly consideration
xStandard pick & place equipment dedicated to WLCSP down to 400µm pitch.
xSolder paste type 3 in most cases of EIA size.
xReflow has to be done with standard lead-free profile (for SAC alloys) or
according to JEDEC recommendations J-STD 020D-01.
Lead
Tp: 235 °C
TL: 183 °C
Ts min: 100 °C
Ts max: 150 °C
tL: 60-150 s
Leadfree
Tp: 260 °C
TL: 217 °C
Ts min: 150 °C
Ts max: 200 °C
tL: 60-150 s
Process recommendation
After soldering, no solder paste should touch the side of the capacitor die as that might results in
leakage currents due to remaining flux.
In order to use IPDiA standard capacitors within the JEDEC format and recommendation, the solder
flux must be cleaned after reflow soldering step.
Notes: for a proper flux cleaning process, “rosin” flux type (R) or “water soluble” flux type (WS) is
recommended for the solder printing material. “No clean” flux (NC) solder paste is not recommended.
In case the flux is not cleaned after the reflow soldering, the standard JEDEC would probably not be
appropriate and the solder volume must be controlled:
- using smallest aperture design for the stencil, and using finer solder paste type 4 or 5 for a
proper printing process.
- Mirroring pads would be the best recommendation
Application Note
Rev 1.0 2 of 3
Application Note
Top side
silicon
X3
Typ.UBM thickness
3 to 5 µm
X1
X4
X2
Pad recommendation
The capacitor is compatible with generic requirements for flip chip design (IPC7094).
Standard IPDiA 3D package can be compliant with established EIA size (0201, 0402, 0603, …).
Die size and land pattern dimensions is set up according to following range :
EIA size 0201 0402 0603 0805 1206 1812
Dimension max(X1 x X2) mm 0.86x0.66 1.26x0.76 1.86x1.16 2.26x1.46 3.46x1.86 4.76x3.66
Typical . die thickness X3 (mm) 0.1 or 0.4
Typical pad size* (mm) 0.15x0.40 0.30x0.50 0.40x0.90 0.50x1.20 0.60x1.60 0.90x3.40
Typical pad separation (X4
mm)
0.3 0.4 0.8 1 2 2.7
After soldering, no solder paste should touch the side of the capacitor die as that might result in
leakage currents due to remaining flux.
Application Note
Manual Handling Considerations
These capacitors are designed to be mounted with a standard SMT line, using solder printing step,
pick and place machine and a final reflow soldering step. In case of manual handling and mounting
conditions, please follow below recommendations:
xMinimize mechanical pressure on the capacitors (use of a vacuum nozzle is
recommended).
xUse of organic tip instead of metal tip for the nozzle.
xMinimize temperature shocks (Substrate pre-heating is recommended).
xNo wire bonding on 0402 47nF, 0402 100nF, 1206 1ȝF and 1812 3,3µF
Process steps:
xOn substrate, form the solder meniscus on each land pattern targeting 100 µm
height after reflow (screen printing, dispensing solder paste or by wire soldering).
xPick the capacitor from the tape & reel or the Gel Pack keeping backside visible
using a vacuum nozzle and organic tip.
xTemporary place the capacitor on land pattern assuming the solder paste (Flux)
will stick and maintain the capacitor.
xReflow the assembly module with a dedicated thermal profile (see reflow
recommendation profile).
Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner. The information
presented in this document does not form part of any
quotation or contract, is believed to be accurate and reliable
and may be changed without notice. No liability will be
accepted by the publisher for any consequence of its use.
Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
For more information, please visit: http://www.ipdia.com
To contact us, email to: sales@ipdia.com
Date of release: 20th April 2012
Document identifier:
