1997-2012 Microchip Technology Inc. DS21189S-page 1
24AA64/24LC64/24FC64
Device Selection Table
Features:
• Single-Supply with Operation down to 1.7V for
24AA64/24FC64 Devices, 2.5V for 24LC64
Devices
• Low-Power CMOS Technology:
- Active current 3 mA, max.
- Standby current 1 A, max.
• 2-Wire Serial Interface, I2C™ Compatible
• Packages with 3 Address Pins are Cascadable up
to 8 Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• 1 MHz Clock for FC versions
• Page Write Time 5 ms, max.
• Self-timed Erase/Write Cycle
• 32-Byte Page Write Buffer
• Hardware Write-Protect
• ESD Protection > 4,000V
• More than 1 Million Erase/Write Cycles
• Data Retention > 200 Years
• Factory Programming Available
• Packages include 8-lead PDIP, SOIC, SOIJ,
TSSOP, X-Rotated TSSOP, MSOP, DFN, TDFN,
5-lead SOT-23 or Chip Scale
• Pb-Free and RoHS Compliant
• Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
Description:
The Microchip Technology Inc. 24AA64/24LC64/
24FC64 (24XX64*) is a 64 Kbit Electrically Erasable
PROM. The device is organized as a single block of
8K x 8-bit memory with a 2-wire serial interface. Low-
voltage design permits operation down to 1.7V, with
standby and active currents of only 1 A and 3 mA,
respectively. It has been developed for advanced, low-
power applications such as personal communications
or data acquisition. The 24XX64 also has a page write
capability for up to 32 bytes of data. Functional
address lines allow up to eight devices on the same
bus, for up to 512 Kbits address space. The 24XX64 is
available in the standard 8-pin PDIP, surface mount
SOIC, SOIJ, TSSOP, DFN, TDFN and MSOP
packages. The 24XX64 is also available in the 5-lead
SOT-23, and Chip Scale packages.
Block Diagram
Package Types
Part
Number
VCC
Range
Max. Clock
Frequency
Temp.
Ranges
24AA64 1.7-5.5 400 kHz(1) I
24LC64 2.5-5.5 400 kHz I, E
24FC64 1.7-5.5 1 MHz(2) I
Note 1: 100 kHz for VCC <2.5V.
2: 400 kHz for VCC <2.5V.
HV
EEPROM
Array
Page
YDEC
XDEC
Sense Amp.
Memory
Control
Logic
I/O
Control
Logic
I/O
WP
SDA
SCL
VCC
VSS
R/W Control
Latches
Generator
A2A1A0
A0
A1
A2
V
SS
V
CC
WP
SCL
SDA
1
2
3
4
8
7
6
5
PDIP/MSOP/SOIC/SOIJ/TSSOP DFN/TDFN
A0
A1
A2
VSS
WP
SCL
SDA
VCC
8
7
6
5
1
2
3
4
SOT-23
1
2
34
5WP
VCC
SCL
VSS
SDA
CS (Chip Scale)(1)
12
3
45
VCC
WP
SDA
SCL
VSS
(Top Down View,
Balls Not Visible)
Note 1: Available in I-temp, “AA” only.
X-Rotated TSSOP
WP
V
CC
A0
A1
1
2
3
4
8
7
6
5
SCL
SDA
V
SS
A2
(X/ST)
64K I2C™ Serial EEPROM
* 24XX64 is used in this document as a generic part number for the 24AA64/24LC64/24FC64 devices.
24AA64/24LC64/24FC64
DS21189S-page 2 1997-2012 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.3V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins 4kV
TABLE 1-1: DC CHARACTERISTICS
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C, VCC = +1.7V to +5.5V
Automotive (E): T
A = -40°C to +125°C, VCC = +2.5V to +5.5V
Param.
No. Sym. Characteristic Min. Typ. Max. Units Conditions
—A0, A1, A2, WP, SCL
and SDA pins
—————
D1 VIH High-level input voltage 0.7 VCC ——V—
D2 VIL Low-level input voltage — — 0.3 VCC
0.2 VCC
V
V
VCC 2.5V
VCC 2.5V
D3 VHYS Hysteresis of Schmitt
Trigger inputs (SDA,
SCL pins)
0.05 VCC ——VVCC 2.5V (Note 1)
D4 VOL Low-level output voltage — — 0.40 V IOL = 3.0 mA @ VCC = 4.5V
IOL = 2.1 mA @ VCC = 2.5V
D5 ILI Input leakage current ——±1AVIN = VSS or VCC, WP = VSS
VIN = VSS or VCC, WP = VCC
D6 ILO Output leakage current ——±1AVOUT = VSS or VCC
D7 CIN,
COUT
Pin capacitance
(all inputs/outputs)
——10pFVCC = 5.0V (Note 1)
T
A = 25°C, FCLK = 1 MHz
D8 ICC write Operating current —0.1 3mAVCC = 5.5V, SCL = 400 kHz
D9 ICC read — 0.05 400 A
D10 ICCS Standby current —
—
0.01
—
1
5
A
A
Industrial
Automotive
SDA = SCL = VCC
A0, A1, A2, WP = VSS
Note 1: This parameter is periodically sampled and not 100% tested.
2: Typical measurements taken at room temperature.
1997-2012 Microchip Technology Inc. DS21189S-page 3
24AA64/24LC64/24FC64
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C
Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to 125°C
Param.
No. Sym. Characteristic Min. Max. Units Conditions
1F
CLK Clock frequency —
—
—
—
100
400
400
1000
kHz 1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 2.5V 24FC64
2.5V VCC 5.5V 24FC64
2THIGH Clock high time 4000
600
600
500
—
—
—
—
ns 1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 2.5V 24FC64
2.5V VCC 5.5V 24FC64
3TLOW Clock low time 4700
1300
1300
500
—
—
—
—
ns 1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 2.5V 24FC64
2.5V VCC 5.5V 24FC64
4T
RSDA and SCL rise time
(Note 1)
—
—
—
1000
300
300
ns 1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 5.5V 24FC64
5T
FSDA and SCL fall time
(Note 1)
—
—
300
100
ns All except, 24FC64
1.7V VCC 5.5V 24FC64
6THD:STA Start condition hold time 4000
600
600
250
—
—
—
—
ns 1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 2.5V 24FC64
2.5V VCC 5.5V 24FC64
7T
SU:STA Start condition setup time 4700
600
600
250
—
—
—
—
ns 1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 2.5V 24FC64
2.5V VCC 5.5V 24FC64
8THD:DAT Data input hold time 0 — ns (Note 2)
9TSU:DAT Data input setup time 250
100
100
—
—
—
ns 1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 5.5V 24FC64
10 TSU:STO Stop condition setup time 4000
600
600
250
—
—
—
—
ns 1.7 V VCC 2.5V
2.5 V VCC 5.5V
1.7V VCC 2.5V 24FC64
2.5 V VCC 5.5V 24FC64
11 TSU:WP WP setup time 4000
600
600
—
—
—
ns 1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 5.5V 24FC64
12 THD:WP WP hold time 4700
1300
1300
—
—
—
ns 1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 5.5V 24FC64
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site
at www.microchip.com.
24AA64/24LC64/24FC64
DS21189S-page 4 1997-2012 Microchip Technology Inc.
FIGURE 1-1: BUS TIMING DATA
13 TAA Output valid from clock
(Note 2)
—
—
—
—
3500
900
900
400
ns 1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 2.5V 24FC64
2.5V VCC 5.5V 24FC64
14 TBUF Bus free time: Time the bus
must be free before a new
transmission can start
4700
1300
1300
500
—
—
—
—
ns 1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 2.5V 24FC64
2.5V VCC 5.5V 24FC64
15 TOF Output fall time from VIH
minimum to VIL maximum
CB 100 pF
10 + 0.1CB250
250
ns All except, 24FC64 (Note 1)
24FC64 (Note 1)
16 TSP Input filter spike suppression
(SDA and SCL pins)
— 50 ns All except, 24FC64 (Notes 1
and 3)
17 TWC Write cycle time (byte or
page)
—5ms—
18 — Endurance 1,000,000 — cycles Page Mode 25°C, 5.5V (Note 4)
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C
Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to 125°C
Param.
No. Sym. Characteristic Min. Max. Units Conditions
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site
at www.microchip.com.
(unprotected)
(protected)
SCL
SDA
IN
SDA
OUT
WP
5
7
6
16
3
2
89
13
D3 4
10
11 12
14
1997-2012 Microchip Technology Inc. DS21189S-page 5
24AA64/24LC64/24FC64
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
2.1 A0, A1, A2 Chip Address Inputs
The A0, A1 and A2 inputs are used by the 24XX64 for
multiple device operation. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
Up to eight devices may be connected to the same bus
by using different Chip Select bit combinations. These
inputs must be connected to either VCC or VSS.
In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable device, the chip
address pins must be driven to logic ‘0’ or logic ‘1’
before normal device operation can proceed. Address
pins are not available in the SOT-23 or Chip Scale
packages.
2.2 Serial Data (SDA)
SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. Since it is an open-
drain terminal, the SDA bus requires a pull-up resistor
to VCC (typical 10 k for 100 kHz, 2 kfor 400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.3 Serial Clock (SCL)
The SCL input is used to synchronize the data transfer
from and to the device.
2.4 Write-Protect (WP)
This pin must be connected to either VSS or VCC. If tied
to VSS, write operations are enabled. If tied to VCC,
write operations are inhibited but read operations are
not affected.
3.0 FUNCTIONAL DESCRIPTION
The 24XX64 supports a bidirectional, 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, while a device
receiving data is defined as a receiver. The bus has to
be controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and
generates the Start and Stop conditions, while the
24XX64 works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
Name PDIP SOIC TSSOP Rotated
TSSOP DFN(1) TDFN(1) MSOP SOT-23 CS Description
A0 1 1 1 3 1 1 1 — — Chip Address Input
A1 2 2 2 4 2 2 2 — — Chip Address Input
A2 3 3 3 5 3 3 3 — — Chip Address Input
VSS 444 6444 22Ground
SDA 5 5 5 7 5 5 5 3 5 Serial Address/Data I/O
SCL 6 6 6 8 6 6 6 1 4 Serial Clock
WP 7 7 7 1 7 7 7 5 3 Write-Protect Input
VCC 8 8 8 2 8 8 8 4 1 +1.7V to 5.5V Power Supply
Note 1: The exposed pad on the DFN/TDFN packages can be connected to VSS or left floating.
24AA64/24LC64/24FC64
DS21189S-page 6 1997-2012 Microchip Technology Inc.
4.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1 Bus Not Busy (A)
Both data and clock lines remain high.
4.2 Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3 Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
4.4 Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of data
bytes transferred between Start and Stop conditions is
determined by the master device and is, theoretically,
unlimited (although only the last thirty two will be stored
when doing a write operation). When an overwrite does
occur, it will replace data in a first-in first-out (FIFO)
fashion.
4.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the Acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24XX64) will leave the data line
high to enable the master to generate the Stop
condition.
FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
Note: The 24XX64 does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
SCL
SDA
(A) (B) (D) (D) (A)(C)
Start
Condition
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
1997-2012 Microchip Technology Inc. DS21189S-page 7
24AA64/24LC64/24FC64
5.0 DEVICE ADDRESSING
A control byte is the first byte received following the
Start condition from the master device (Figure 5-1).
The control byte consists of a four-bit control code. For
the 24XX64, this is set as ‘1010’ binary for read and
write operations. The next three bits of the control byte
are the Chip Select bits (A2, A1, A0). The Chip Select
bits allow the use of up to eight 24XX64 devices on the
same bus and are used to select which device is
accessed. The Chip Select bits in the control byte must
correspond to the logic levels on the corresponding A2,
A1 and A0 pins for the device to respond. These bits
are, in effect, the three Most Significant bits of the word
address.
For the SOT-23 and Chip Scale packages, the address
pins are not available. During device addressing, the
A2, A1 and A0 Chip Select bits (Figure 5-2) should be
set to ‘0’.
The last bit of the control byte defines the operation to
be performed. When set to a ‘1’, a read operation is
selected. When set to a ‘0’, a write operation is
selected. The next two bytes received define the
address of the first data byte (Figure 5-2). Because
only A12...A0 are used, the upper-three address bits
are “don’t care” bits. The upper-address bits are
transferred first, followed by the Less Significant bits.
Following the Start condition, the 24XX64 monitors the
SDA bus, checking the device-type identifier being
transmitted. Upon receiving a ‘1010’ code and appro-
priate device-select bits, the slave device outputs an
Acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the 24XX64 will select a read or
write operation.
FIGURE 5-1: CONTROL BYTE FORMAT
5.1 Contiguous Addressing Across
Multiple Devices
The Chip Select bits A2, A1 and A0 can be used to
expand the contiguous address space for up to 512K
bits by adding up to eight 24XX64 devices on the same
bus. In this case, software can use A0 of the control
byte as address bit A13; A1 as address bit A14; and A2
as address bit A15. It is not possible to sequentially
read across device boundaries.
The SOT-23 and Chip Scale packages do not support
multiple device addressing on the same bus.
FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS
1010A2 A1 A0SACKR/W
Control Code
Chip Select
Bits
Slave Address
Acknowledge Bit
Start Bit
Read/Write Bit
1 010A
2
A
1A
0R/W xxx A
11
A
10 A
9
A
7
A
0
A
8••••••
A
12
Control Byte Address High Byte Address Low Byte
Control
Code
Chip
Select
bits
x = “don’t care” bit
24AA64/24LC64/24FC64
DS21189S-page 8 1997-2012 Microchip Technology Inc.
6.0 WRITE OPERATIONS
6.1 Byte Write
Following the Start condition from the master, the
control code (four bits), the Chip Select (three bits) and
the R/W bit (which is a logic low) are clocked onto the
bus by the master transmitter. This indicates to the
addressed slave receiver that the address high byte will
follow once it has generated an Acknowledge bit during
the ninth clock cycle. Therefore, the next byte transmit-
ted by the master is the high-order byte of the word
address and will be written into the Address Pointer of
the 24XX64. The next byte is the Least Significant
Address Byte. After receiving another Acknowledge
signal from the 24XX64, the master device will transmit
the data word to be written into the addressed memory
location. The 24XX64 acknowledges again and the
master generates a Stop condition. This initiates the
internal write cycle and, during this time, the 24XX64
will not generate Acknowledge signals (Figure 6-1). If
an attempt is made to write to the array with the WP pin
held high, the device will acknowledge the command,
but no write cycle will occur, no data will be written and
the device will immediately accept a new command.
After a byte Write command, the internal address coun-
ter will point to the address location following the one
that was just written.
6.2 Page Write
The write control byte, word address and the first data
byte are transmitted to the 24XX64 in the same way as
in a byte write. However, instead of generating a Stop
condition, the master transmits up to 31 additional
bytes which are temporarily stored in the on-chip page
buffer and will be written into memory once the master
has transmitted a Stop condition. Upon receipt of each
word, the five lower Address Pointer bits are internally
incremented by one. If the master should transmit more
than 32 bytes prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the Stop condition is received, an inter-
nal write cycle will begin (Figure 6-2). If an attempt is
made to write to the array with the WP pin held high, the
device will acknowledge the command, but no write
cycle will occur, no data will be written, and the device
will immediately accept a new command.
6.3 Write Protection
The WP pin allows the user to write-protect the entire
array (0000-1FFF) when the pin is tied to VCC. If tied to
VSS the write protection is disabled. The WP pin is
sampled at the Stop bit for every Write command
(Figure 4-1). Toggling the WP pin after the Stop bit will
have no effect on the execution of the write cycle.
Note: When doing a write of less than 32 bytes
the data in the rest of the page is refreshed
along with the data bytes being written.
This will force the entire page to endure a
write cycle, for this reason endurance is
specified per page.
Note: Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size (or
‘page size’) and end at addresses that are
integer multiples of [page size – 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page, as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
1997-2012 Microchip Technology Inc. DS21189S-page 9
24AA64/24LC64/24FC64
FIGURE 6-1: BYTE WRITE
FIGURE 6-2: PAGE WRITE
xxx
Bus Activity
Master
SDA Line
Bus Activity
S
T
A
R
T
Control
Byte
Address
High Byte
Address
Low Byte Data
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
x = “don’t care” bit
S1010 0
A
2A
1A
0P
xxx
Bus Activity
Master
SDA Line
Bus Activity
S
T
A
R
T
Control
Byte
Address
High Byte
Address
Low Byte Data Byte 0
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
Data Byte 31
A
C
K
x = “don’t care” bit
S1010 0
A
2A
1A
0P
24AA64/24LC64/24FC64
DS21189S-page 10 1997-2012 Microchip Technology Inc.
7.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally-timed write cycle and ACK polling
can then be initiated immediately. This involves the
master sending a Start condition followed by the control
byte for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, the Start bit and control byte must
be re-sent. If the cycle is complete, the device will
return the ACK and the master can then proceed with
the next Read or Write command. See Figure 7-1 for a
flow diagram of this operation.
FIGURE 7-1: ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
No
Yes
1997-2012 Microchip Technology Inc. DS21189S-page 11
24AA64/24LC64/24FC64
8.0 READ OPERATION
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
control byte is set to one. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1 Current Address Read
The 24XX64 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address ‘n’ (n is any legal address), the
next current address read operation would access data
from address n + 1.
Upon receipt of the control byte with R/W bit set to one,
the 24XX64 issues an acknowledge and transmits the
eight-bit data word. The master will not acknowledge
the transfer, but does generate a Stop condition and the
24XX64 discontinues transmission (Figure 8-1).
8.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To
perform this type of read operation, the word address
must first be set. This is accomplished by sending
the word address to the 24XX64 as part of a write
operation (R/W bit set to ‘0’). Once the word address
is sent, the master generates a Start condition
following the acknowledge.
This terminates the write operation, but not before
the internal Address Pointer is set. The master then
issues the control byte again, but with the R/W bit set
to a one. The 24XX64 will then issue an acknowl-
edge and transmit the 8-bit data word. The master
will not acknowledge the transfer, but does generate
a Stop condition, which causes the 24XX64 to
discontinue transmission (Figure 8-2). After a
random Read command, the internal address coun-
ter will point to the address location following the one
that was just read.
8.3 Sequential Read
Sequential reads are initiated in the same way as
random reads, except that once the 24XX64 transmits
the first data byte, the master issues an acknowledge as
opposed to the Stop condition used in a random read.
This acknowledge directs the 24XX64 to transmit the
next sequentially-addressed 8-bit word (Figure 8-3).
Following the final byte being transmitted to the master,
the master will NOT generate an acknowledge, but will
generate a Stop condition. To provide sequential reads,
the 24XX64 contains an internal Address Pointer which
is incremented by one at the completion of each
operation. This Address Pointer allows the entire
memory contents to be serially read during one opera-
tion. The internal Address Pointer will automatically roll
over from address 1FFF to address 0000 if the master
acknowledges the byte received from the array address
1FFF.
FIGURE 8-1: CURRENT ADDRESS READ
SP
Bus Activity
Master
SDA Line
Bus Activity
S
T
O
P
Control
Byte Data (n)
A
C
K
N
O
A
C
K
S
T
A
R
T
24AA64/24LC64/24FC64
DS21189S-page 12 1997-2012 Microchip Technology Inc.
FIGURE 8-2: RANDOM READ
FIGURE 8-3: SEQUENTIAL READ
xxx
Bus Activity
Master
SDA Line
Bus Activity
A
C
K
N
O
A
C
K
A
C
K
A
C
K
A
C
K
S
T
O
P
S
T
A
R
T
Control
Byte Address
High Byte Address
Low Byte Control
Byte Data
Byte
S
T
A
R
T
x = “don’t care” bit
S1010
AAA0
210 S1010AAA1
210 P
Bus Activity
Master
SDA Line
Bus Activity
Control
Byte Data n Data n + 1 Data n + 2 Data n + x
N
O
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
S
T
O
P
P
1997-2012 Microchip Technology Inc. DS21189S-page 13
24AA64/24LC64/24FC64
9.0 PACKAGING INFORMATION
9.1 Package Marking Information
XXXXXXXX
T/XXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
8-Lead SOIC (3.90 mm) Example:
XXXXXXXT
XXXXYYWW
NNN
8-Lead TSSOP Example:
24LC64
I/P 13F
0527
24LC64I
SN 0527
13F
XXXX
TYWW
NNN
4LB
I527
13F
8-Lead MSOP Example:
4L64I
52713F
8-Lead SOIC (5.28 mm) Example:
XXXXXXXX
T/XXXXXX
YYWWNNN
24LC64
I/SM
052713F
8-Lead 2x3 DFN
Example:
274
527
I3
XXX
YWW
NN
3
e
3
e
3
e
XXXXXT
YWWNNN
24AA64/24LC64/24FC64
DS21189S-page 14 1997-2012 Microchip Technology Inc.
Note: T = Temperature grade (I, E)
Part Number
1st Line Marking Codes
TSSOP TSSOP
X-Rotated
MSOP DFN TDFN SOT-23
I Temp. E Temp. I Temp. E Temp. I Temp. E Temp.
24AA64 4AB 4ABX 4A64T 271 — A71 — 7HNN —
24LC64 4LB 4LBX 4L64T 274 275 A74 A75 7GNN 7JNN
24FC64 4FB — 4F64T 27A — A7A — — —
Legend: XX...X Part number or part number code
T Temperature (I, E)
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn)
Note: For very small packages with no room for the Pb-free JEDEC designator
, the marking will only appear on the outer carton or reel label.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
5-Lead Chip Scale
XW
Example:
75
Example:
A74
527
I3
8-Lead 2x3 TDFN
XXX
YWW
NN
5-Lead SOT-23
XXNN
Example:
7GNN
NN 13
1997-2012 Microchip Technology Inc. DS21189S-page 15
24AA64/24LC64/24FC64
N
E1
NOTE 1
D
123
A
A1
A2
L
b1
b
e
E
eB
c
24AA64/24LC64/24FC64
DS21189S-page 16 1997-2012 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1997-2012 Microchip Technology Inc. DS21189S-page 17
24AA64/24LC64/24FC64
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
24AA64/24LC64/24FC64
DS21189S-page 18 1997-2012 Microchip Technology Inc.
! ""#$%& !'
1997-2012 Microchip Technology Inc. DS21189S-page 19
24AA64/24LC64/24FC64
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
24AA64/24LC64/24FC64
DS21189S-page 20 1997-2012 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1997-2012 Microchip Technology Inc. DS21189S-page 21
24AA64/24LC64/24FC64
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
24AA64/24LC64/24FC64
DS21189S-page 22 1997-2012 Microchip Technology Inc.
( !)""!) !)*
φ
N
b
E
E1
D
123
e
e1
A
A1
A2 c
L
L1
1997-2012 Microchip Technology Inc. DS21189S-page 23
24AA64/24LC64/24FC64
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
24AA64/24LC64/24FC64
DS21189S-page 24 1997-2012 Microchip Technology Inc.
)+ +", ! )-%-) !
D
N
E
E1
NOTE 1
12
b
e
c
A
A1
A2
L1 L
φ
1997-2012 Microchip Technology Inc. DS21189S-page 25
24AA64/24LC64/24FC64
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
24AA64/24LC64/24FC64
DS21189S-page 26 1997-2012 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1997-2012 Microchip Technology Inc. DS21189S-page 27
24AA64/24LC64/24FC64
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
24AA64/24LC64/24FC64
DS21189S-page 28 1997-2012 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1997-2012 Microchip Technology Inc. DS21189S-page 29
24AA64/24LC64/24FC64
.$,/0'*11%&.
D
N
E
NOTE 1
12
EXPOSED PAD
NOTE 1
21
D2
K
L
E2
N
e
b
A3 A1
A
NOTE 2
BOTTOM VIEW
TOP VIEW
24AA64/24LC64/24FC64
DS21189S-page 30 1997-2012 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1997-2012 Microchip Technology Inc. DS21189S-page 31
24AA64/24LC64/24FC64
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
24AA64/24LC64/24FC64
DS21189S-page 32 1997-2012 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1997-2012 Microchip Technology Inc. DS21189S-page 33
24AA64/24LC64/24FC64
.$,/0*11%2().
24AA64/24LC64/24FC64
DS21189S-page 34 1997-2012 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1997-2012 Microchip Technology Inc. DS21189S-page 35
24AA64/24LC64/24FC64
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Please contact your local Microchip representative for specific details.
24AA64/24LC64/24FC64
DS21189S-page 36 1997-2012 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1997-2012 Microchip Technology Inc. DS21189S-page 37
24AA64/24LC64/24FC64
APPENDIX A: REVISION HISTORY
Revision H (12/2003)
Corrections to Section 1.0, Electrical Characteristics.
Revision J (04/2005)
Added DFN package.
Revision K (08/2005)
Revised Sections 7.1 and 7.4.
Revision L (03/2007)
Added 24FC64 Part; Revised Device Selection Table;
Revised Features Section; Deleted Rotated TSSOP
Package; Revised Table 1-2; Revised Table 7-1;
Revised Package Information; Replaced Package
Drawings; Revised Product ID Section.
Revision M (01/2009)
Updated package drawings. Added 8-lead TDFN and
5-lead SOT-23 packages.
Revision N (03/2009)
Added 5-lead Chip Scale package.
Revision P (03/2009)
Added 5-lead Chip Scale Package Diagram and Land
Pattern. Revised Block Diagram.
Revision Q (06/09)
Revised Features section; Revised Table 1-2, Para. 18;
Added note to Table 2-1; Revised SOT-23 package
example.
Revision R (03/2010)
Added TSSOP X-Rotated package; Updated Package
Drawings; Updated Product ID.
Revision S (01/2012)
Updated Package Drawings: Updated Product ID.
24AA64/24LC64/24FC64
DS21189S-page 38 1997-2012 Microchip Technology Inc.
NOTES:
1997-2012 Microchip Technology Inc. DS21189S-page 39
24AA64/24LC64/24FC64
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
•Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
•General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
•Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Development Systems Information Line
Customers should contact their distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
24AA64/24LC64/24FC64
DS21189S-page 40 1997-2012 Microchip Technology Inc.
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
TO: Technical Publications Manager
RE: Reader Response
Total Pages Sent ________
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
Application (optional):
Would you like a reply? Y N
Device: Literature Number:
Questions:
FAX: (______) _________ - _________
DS21189S24AA64/24LC64/24FC64
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
1997-2012 Microchip Technology Inc. DS21189S-page41
24AA64/24LC64/24FC64
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX
PackageTemperature
Range
Device
Device: 24AA64: 1.7V, 64 Kbit I2C™ Serial EEPROM
24AA64T: 1.7V, 64 Kbit I2C Serial EEPROM
(Tape and Reel)
24AA64X: 1.7V, 32 Kbit I2C Serial EEPROM in
alternate pinout (ST only)
24AA64XT: 1.7V, 32 KbitI2C Serial EEPROM in
alternate pinout (ST only)
24LC64: 2.5V, 64 Kbit I2C Serial EEPROM
24LC64T: 2.5V, 64 Kbit I2C Serial EEPROM
(Tape and Reel)
24LC64X: 2.5V, 32 Kbit I2C Serial EEPROM in
alternate pinout (ST only)
24LC64XT: 2.5V, 32 KbitI2C Serial EEPROM in
alternate pinout (ST only)
24FC64: 2.5V, 64 Kbit I2C Serial EEPROM
24FC64T: 2.5V, 64 Kbit I2C Serial EEPROM (Tape
and Reel)
Temperature
Range:
I = -40°C to +85°C
E = -40°C to +125°C
Package: P = Plastic DIP (300 mil body), 8-lead
SN = Plastic SOIC (3.90 mm body), 8-lead
SM = Plastic SOIC (5.28 mm body), 8-lead
ST = Plastic TSSOP (4.4 mm), 8-lead
MS = Plastic MSOP (Micro Small Outline), 8-lead
MC = Plastic DFN (2x3x0.9 mm body), 8-lead
MNY(1)= Plastic TDFN (2x3x0.75 mm body), 8-lead
OT = Plastic SOT-23, 5-lead (Tape and Reel only)
CS16K(2)=Chip Scale (CS), 5-lead (I-temp, "AA", Tape
and Reel only)
Examples:
a) 24AA64-I/P: Industrial Temperature,
1.7V, PDIP package
b) 24AA64-I/SN: Industrial Temperature,
1.7V, SOIC package
c) 24AA64-I/SM: Industrial Temperature,
1.7V, SOIC (5.28 mm) package
d) 24AA64T-I/ST: Industrial Temperature,
1.7V, TSSOP package, tape and reel
e) 24LC64-I/P: Industrial Temperature,
2.5V, PDIP package
f) 24LC64-E/SN: Extended Temperature,
2.5V, SOIC package
g) 24LC64-E/SM: Extended Temperature,
2.5V, SOIC (5.28 mm) package
h) 24LC64-I/ST: Industrial Temperature,
2.5V, TSSOP package
i) 24AA64T-I/CS16K: Industrial Tempera-
ture, 1.7V, CS package, tape and reel
X
Note 1: "Y" indicates a Nickel Palladium Gold (NiPdAu) finish.
2: "16K" indicates 160K technology.
24AA64/24LC64/24FC64
DS21189S-page 42 1997-2012 Microchip Technology Inc.
NOTES:
1997-2012 Microchip Technology Inc. DS21189S-page 43
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 1997-2012, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-958-8
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS21189S-page 44 1997-2012 Microchip Technology Inc.
AMERICAS
Corporate Office
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Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
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Web Address:
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11/29/11
