HUF76121S3ST - Fairchild Semiconductor

HUF76121P3 , HUF76121S3S

47A, 30V, 0.021 Ohm, N-Channel, Logic

Level UltraFET Power MOSFETs

These N-Chann el power MOSFETs

are manufactured using the

innovative Ul traFET™ pr ocess.

This advanced process technology

achie ves the lo west pos sible on-resi stance per sil icon area,

resultin g in outstanding performanc e. This dev ice is capable

of wit hstanding hi gh energ y in the avalanche mode and the

diode e xhibits v ery lo w revers e recovery time and stored

charge. It w as designed for use in applica ti ons where po wer

efficiency is important, such as switching regulators,

switching converters , motor drivers , relay drivers, low-

voltage bus s w itches, and power management in portab le

and battery-operated products.

Formerly deve lopmental type TA76121.

Features

• Logic Level Gate Driv e

• 47A, 30V

• Ultra Low On- Resistance, rDS(ON) = 0.021Ω

• Tem peratur e Com pensating PSPI CE® Model

• Tem peratur e Com pensating SABER© Model

• Thermal Impedanc e SPICE Model

• Thermal Impedanc e SABER Model

• Peak Current vs Pulse Widt h Curve

• UIS Rating Curve

• Related Literature

- TB334, “G uidelines for Soldering Surface Mount

Components to PC Boards”

Symbol

Packaging

JEDEC TO-220AB JEDEC TO-263AB

Ordering Information

PART NUMBER PACKAGE BRAND

HUF76121P3 TO-220AB 76121P

HUF76121S3S TO-263AB 76121S

NOTE: When ordering, use the entire part number. Add the suffix T to

obtain the TO-263AB variant in tape and reel, e.g., HUF76121S3ST.

DRAIN

SOURCE

GATE

DRAIN

(FLANGE)

GATE

SOURCE

DRAIN

(FLANGE)

Data Sheet Januar y 2003

Absolute Maximum Rat ings TC = 25oC, Unless Otherwise Specif ied UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS 30 V

Drain to G ate Vo lt age (R GS = 2 0 k Ω) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR 30 V

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±20 V

Drain C urr e nt

Continuo us (TC = 25oC, VGS = 10V) (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID

Continuo us (TC = 100oC, VGS = 5V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID

Continuo us (TC = 100oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM

Figu re 4

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Figure s 6, 17 ,1 8

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD

Der ate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

0.6 W

W/oC

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T STG -40 to 150 oC

Maximu m Tempe rature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL

Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300

260

CAUT ION: St ress es above those list ed in “Abs olute Maximum Rati ngs” may cause per mane nt damage to the device. This is a str ess only rating and operati on of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. TJ = 25oC to 150oC.

Electrical Speci fications TA = 25oC, Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

OFF STATE SPECIFICATIONS

Dr ain t o Sou rce Breakdown Voltag e BVDSS ID = 25 0µA, VGS = 0V (Fig ure 1 2) 30 - - V

Z ero Gat e V ol tag e D rain C urr e nt IDSS VDS = 25V, VGS = 0V - - 1 µA

VDS = 25V, VGS = 0V, TC = 150oC--250µA

Ga te t o Sour c e Le ak ag e C urr e nt IGSS VGS = ±20V - - ±100 nA

ON STATE SPECIFICATIONS

Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 11) 1 - 3 V

Drain t o Source On Resistance rDS(ON) ID = 47A , VGS = 10V (Fi gure s 9, 10 ) - 0.015 0.021 Ω

ID = 25A, VGS = 5V (Fig ure 9 ) - 0. 019 0.028 Ω

ID = 24A, VGS = 4.5V (Figure 9) - 0.021 0.031 Ω

THERMAL SPECIFICATIONS

T her m al Res ista nc e Ju ncti on to Case R θJC (F i gu re 3) - - 1. 66 oC/W

Thermal Resistance Junction to Ambient RθJA TO-220 and T O-263 - - 62 oC/W

SWITCHING SPECIFICATIONS (VGS = 4.5V)

Turn -On Time tON VDD = 15V, ID ≅ 24A , RL = 0.6 3Ω,

VGS =4.5V, RGS = 10.0Ω

(Figure s 15, 21 , 22)

--265ns

Turn-O n Delay Time td(ON) -15-ns

Rise Time tr-160- ns

Turn-O ff Delay Time td(OFF) -14-ns

Fa ll Time tf-31-ns

Turn -Off Time tOFF --70ns

HUF76121P3, HUF76121S3S

SWITCHING SPECIFICATIONS (VGS = 10V )

Turn -On Time tON VDD = 15V, ID ≅ 47A , RL = 0.3 2Ω,

VGS = 10V, RGS = 12.5Ω

(Figure s 16, 21 , 22)

--80ns

Turn-O n Delay Time td(ON) -6-ns

Rise Time tr-47-ns

Turn-O ff Delay Time td(OFF) -47-ns

Fa ll Time tf-42-ns

Turn -Off Time tOFF --135ns

GATE CHARGE SPECIFICATIONS

T otal G ate Charg e Qg(TOT) VGS = 0V to 10V VDD = 15V, ID ≅ 25 A,

RL = 0.6Ω

Ig(REF) = 1.0mA

(Figure s 14, 1 9, 20)

-2430nC

Gat e Charg e at 5V Qg(5) VGS = 0 V to 5V - 13 1 6 nC

T hresh old G ate Ch arge Qg(TH) VGS = 0V to 1 V - 1.0 1.2 nC

Ga te to Sourc e Gate Charg e Qgs -2.50- nC

Ga te t o Drai n “M iller ” C ha rge Qgd -7.80- nC

CAPACITANCE SPECIFICATIONS

Input Capacitance CISS VDS = 25V, VGS = 0V, f = 1MHz

(Fi gu r e 13 ) -850- pF

Output Capacitance COSS -465- pF

Reverse Transfer Capacitance CRSS -100- pF

Electrical Speci fications TA = 25oC, Unless Otherwise Specified (C on tinue d)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Specific ations

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Volta ge VSD ISD = 25A - - 1.25 V

Reverse Recovery Time trr ISD = 25A, dISD/dt = 100A/µs--65ns

Reverse Recovered Charge QRR ISD = 25A, dISD/dt = 100A/µs - - 100 nC

Typical Performance Curves

FIGURE 1. NORMALIZED PO WER DISSIPATION vs CASE

TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPER ATURE

TA, AMBIENT TEMPERATURE (oC)

POWER DISSIPATION MULTIPLIER

00 25 50 75 100 150

0.2

0.4

0.6

0.8

1.0

1.2

125 0

ID, DRAIN CURRENT (A)

TC, CASE TEMPERATURE (oC)

VGS = 10V

VGS = 4.5V

50 75 100 125 150

HUF76121P3, HUF76121S3S

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

FIGURE 4. PEAK CURRENT CAPABILITY

FIGURE 5. FORWARD BIAS SAFE OPERATING AREA

NOTE: Refer to Fai rchi ld Application Notes AN9321 and A N9322.

FIGURE 6. UNCL AMPED INDUCTIVE SWITCHING CAPABILITY

Typical Performance Curves (Continued)

0.01

0.1

10-5 10-4 10-3 10-2 10-1 100101

ZθJC, NORMALIZE D

THERMAL IMPEDANCE

SINGLE PULSE NOTES:

DUTY FACTOR: D = t1/t2

PEAK TJ = PDM x ZθJC x RθJC + TC

PDM

t1t2

DUTY CYCLE - DESCENDING ORDER

0.5

0.2

0.1

0.05

0.01

0.02

t, RECTANGULAR PULSE DURATION (s)

TC = 25oC

I = I25 150 - TC

125

FOR TEMPERATURES

ABOVE 25oC DERATE PEAK

CURRENT AS FOLLOWS:

VGS = 1 0V

TRANSCONDUCTANCE

MAY LIMIT CURRENT

IN THIS REGION

VGS = 5 V

100

1000

10-5 10-4 10-3 10-2 10-1 100101

IDM, PEAK CURRENT (A)

t, PULSE WIDTH (s)

100

1000

1 10 100

TJ = MAX RATED

TC = 25oC

100µs

10ms

1ms

VDS, DRAIN TO SOURCE VOLTAGE (V)

ID, DRAIN CURRENT (A)

LIMITED BY rDS(ON)

AREA MAY BE

OPERATION IN THIS

BVDSS MAX = 30V 1

100

0.001 0.01 0.1 1 10 100

500

IAS, AVALANCHE CURRENT (A)

tAV, TIME IN AVALANCHE (ms)

tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)

If R = 0

If R ≠ 0

tAV = (L/R ) l n [ (I AS* R)/(1. 3*RATED BVDSS - VDD) +1]

STARTING TJ = 25oC

STARTING TJ = 150oC

HUF76121P3, HUF76121S3S

FIGURE 7. TRANSFER CHARACTERISTICS FIGURE 8. SATURATION CHARACTERISTICS

FIGURE 9. SOURCE TO DRAIN ON RESISTANCE vs GATE

VOLTAGE AND DRAIN CURRENT FIGURE 10. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

FIGURE 11. NORMALIZED GATE THRESHOLD V OLTAGE vs

JUNCTION TEMPERATURE FIGURE 12. NORMALIZED DRAIN T O SOURCE BRE AKDOW N

VOLTAGE vs JUNCTION TEMPERATURE

Typical Performance Curves (Continued)

100

012345

ID, DRAIN CURRENT (A)

VGS, GATE TO SOURCE VOLTAGE (V)

150oC

-40oC

25oC

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

VDD = 15 V 0

100

012345

ID, DRAIN CURRENT (A)

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 4V

VGS = 3V

VGS = 3.5V

VGS = 4.5V

VGS = 10V

VGS = 5V

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

246810

VGS, GATE TO SOURCE VOLTAGE (V)

ID = 47A

ID = 28A

ID = 15A

rDS(ON), DRAIN TO SOURCE

ON RESISTANCE (mΩ)

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

1.0

1.2

1.4

1.6

-60 0 60 120 180

0.8

NORMALIZED DRAIN TO SOURCE

TJ, JUNCTION TEMPERATURE (oC)

ON RESISTANCE

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

VGS = 10V, ID = 47A

0.8

1.0

1.2

-60 0 60 120 180

0.6

NORMALIZED GATE

TJ, JUNCTION TEMPERATURE (oC)

THRESHOLD VOLTAGE

VGS = VDS, ID = 250µA

1.0

1.1

1.2

-60.0 0.0 60.0 120 180

0.9

TJ, JUNCTION TEMPERATURE (oC)

ID = 250µA

NORMALIZED DRAIN TO SOURCE

BREAKOWN VOLTAGE

HUF76121P3, HUF76121S3S

FIGURE 13. CAPACI TANCE vs DRAIN TO SOURCE VOLTAGE

NOTE: Refer to Fai rchi ld Application Notes AN7254 and A N7260.

FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT

GATE CURRENT

FIGURE 15. SWITCHING TIME vs GATE RESISTANCE FIGURE 16. SWITCHING TIME vs GATE RESISTANCE

Test Circuits and Waveforms

FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 18. UNCLAMPED ENERGY WAVEFORMS

Typical Performance Curves (Continued)

300

600

900

1200

0 5 10 15 20 25 30

C, CAPACITANCE (pF)

VDS, DRAIN T O SOURCE VOLTAGE (V)

CISS

COSS

CRSS

VGS = 0V, f = 1MHz

CISS = CGS + CGD

CRSS = CGD

COSS ≈ CDS + CGD

0 5 10 15 20 25

VGS, GATE TO SOURCE VOLTAGE (V)

VDD = 15V

Qg, GATE CHARGE (nC)

ID = 47A

ID = 28A

ID = 15A

WAVEFORMS IN

DESCENDING ORDER:

100

200

300

400

500

10 20 30 40 50

00RGS, GATE TO SOURCE RESISTANCE (Ω)

VGS = 4.5V, VDD = 15V, ID = 24A, RL = 0.63Ω

td(OFF) tf

td(ON)

SWITCHING TIME (ns)

100

150

200

10 20 30 40 50

SWITCHING TIME (ns)

RGS, GATE TO SOURCE RESISTANCE (Ω)

td(OFF)

td(ON)

VGS = 10V, VDD = 15V, ID = 47A, RL = 0.32Ω

VGS

0.01Ω

IAS

VDS

VDD

DUT

VARY tP TO OBTAIN

REQUIRED PEAK IAS

VDD

VDS

BVDSS

IAS

tAV

HUF76121P3, HUF76121S3S

FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS

FIGURE 21. SWI TCHING TIME TEST CIRCUIT FIGURE 22. SWITCHIN G TIME WAV EFORM

Test Circuits and Waveforms (Continued)

VGS +

VDS

VDD

DUT

Ig(REF)

VDD

Qg(TH)

VGS = 1V

Qg(5)

VGS = 5V

Qg(TOT)

VGS = 10V

VDS

VGS

IgREF)

VGS

RGS DUT

-VDD

VDS

VGS

tON

td(ON)

90%

10%

VDS 90%

10%

td(OFF)

tOFF

90%

50%

10% PULSE WIDTH

VGS

HUF76121P3, HUF76121S3S

PSPICE Electrical Model

.SUBCKT HUF76121 2 1 3 ; rev March 1998

C A 12 8 1. 2e- 9

CB 15 14 1.23e -9

CIN 6 8 7.6e-10

D BODY 7 5 DBODYM O D

DBREAK 5 11 DBREAKMOD

DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 33.4

EDS 14 8 5 8 1

EGS 13 8 6 8 1

ESG 6 10 6 8 1

EVTH RES 6 21 19 8 1

EVTEM P 20 6 18 22 1

IT 8 1 7 1

LDRAIN 2 5 1e-9

LGATE 1 9 3.57e- 9

LSOU RCE 3 7 4.25e-9

MMED 16 6 8 8 M M EDMOD

MSTR O 16 6 8 8 M S T ROM O D

MWEAK 16 21 8 8 M WE AKMOD

RBREAK 17 18 RBREAKMOD 1

RDRAIN 50 16 RDRAINMOD 2.5e-3

RG ATE 9 20 4

RL DRAIN 2 5 10

RLGATE 1 9 35 .7

RLSOURCE 3 7 42.5

RSLC1 5 51 R SL CM OD 1e-6

RSLC2 5 50 1e 3

RSOURCE 8 7 RSOURCEMOD 10e-3

RVT HRE S 2 2 8 RVTHRESM OD 1

RVTEMP 18 19 RVTEMPMOD 1

S1A 6 12 13 8 S1A M OD

S1B 13 12 13 8 S1BMO D

S2A 6 15 14 13 S2AMO D

S2B 13 15 14 13 S2BMOD

VBAT 22 19 DC 1

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*181),4))}

.MO DE L DB ODYM OD D (IS = 4e-13 RS = 6.3 e-3 TRS1 = 1e-3 TRS 2 = 3e-6 CJO = 1.33e- 9 TT = 2.8e-8 M = 0.4 XTI = 4.3 N = 0.95 I KF = 5)

.MODEL DBREAKMOD D (RS = 1.05e-1 TRS1 = 0 TRS2 = 2.5e-5)

.MODEL DPLCAPMOD D (CJO = 7.8e-10 IS = 1e-30 N = 10 M = 0.63)

.MODE L M M E DMOD NMOS (VT O = 1.8 KP = 3.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 4)

.MO DEL M STROMOD NMOS (VTO = 2. 08 KP = 65 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)

.MODEL MWEAKMOD NMOS (VTO = 1.54 KP = 0.1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 40 RS = 0.1)

.MO DE L RB REAK M OD RES (TC1 = 9. 7e-4 TC2 = 7e-7)

.MODEL RDRAINMOD RES (TC1 = 1.6e-2 TC2 = 4e-5)

.MO DE L RS LCM OD RES (TC1 = 5e- 3 T C2 = 8e-6)

.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)

.MO DE L RVTHRESMOD RES (TC = -1. 7e-3 TC2 = -4e-6)

.MO DEL RVT EMPMOD RES (T C1 = -1.2e-3 TC2 = 1e-6)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5 VOFF= -3)

.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3 VOFF= -5)

.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.5 VOFF= 2)

.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2 VOFF= -0.5)

.ENDS

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global

Temperat ure O ptions; IEEE Power Electronics Specialist Conf e rence Records, 1991, written by William J. Hepp and C. Frank Wheatley.

RBREAK

RVTEMP

VBAT

RVTHRES

17 18

S1A

S1B

S2A

S2B

CA CB

EGS EDS

814

MWEAK

EBREAK DBODY

RSOURCE

SOURCE

LSOURCE

RLSOURCE

CIN

RDRAIN

EVTHRES 16

MMED

MSTRO

DRAIN

LDRAIN

RLDRAIN

DBREAK

DPLCAP

ESLC

RSLC1

RSLC2

GATE RGATE EVTEMP

ESG

LGATE

RLGATE 20

HUF76121P3, HUF76121S3S

SABER Electrical Model

REV March 1998

template huf76121 n2, n1, n3

el ect r i cal n2, n1 , n3

{

var i iscl

d..model dbody m od = (i s = 4e-13 , xti = 4. 3, cjo = 1.33e-9, tt = 2.8 e-8, n = 0.95, m = 0.4)

d..model dbreakmod = ()

d..model dplcap m od = (cjo = 7.8e -10, is = 1e-30, n = 10 , m = 0.6 3)

m..model mmedmod = (type=_n, vt o = 1.8, kp = 3. 5, is = 1e-30, tox = 1)

m..model ms t rongmod = (ty pe=_n, vt o = 2. 08, kp = 65, is = 1e-30 , t ox = 1)

m..model mweakmod = (type=_n, vt o = 1. 54, kp = 0.1, i s = 1e-30, tox = 1)

sw_v cs p..mo del s1amod = (ron = 1e -5, roff = 0.1, vo n = -5, vof f = -3)

sw_v cs p..mo del s1bmod = (ron = 1e -5, roff = 0.1, vo n = -3, vof f = -5)

sw_v cs p..mo del s2amod = (ron = 1e -5, roff = 0.1, vo n = -0. 5, vof f = 2)

sw_v cs p..mo del s2bmod = (ron = 1e -5, roff = 0.1, vo n = 2, voff = -0.5)

c . ca n1 2 n8 = 1.2e -9

c.c b n15 n14 = 1. 23e-9

c.cin n6 n8 = 7.6e -10

d.dbody n7 n71 = model=dbodymod

d.dbreak n72 n11 = m odel=dbreakmod

d.dplcap n10 n5 = m odel =dplcapmod

i.it n8 n17 = 1

l.ldrain n2 n5 = 1e-9

l.lg ate n1 n9 = 3.57e-9

l.lsource n3 n7 = 4.25e-9

m.mmed n16 n6 n8 n8 = model=m m edmod, l = 1u, w = 1u

m.ms t rong n16 n6 n8 n8 = model=m strongmod, l = 1u, w = 1u

m.mw eak n16 n21 n8 n8 = model=m weakmod , l = 1u, w = 1u

res. rbreak n17 n18 = 1, tc1 = 9.7e-4, tc2 = 7e-7

res. rdbody n71 n5 = 6.3 e-3, tc1 = 1e-3, tc 2 = 3e-6

res. rdbreak n7 2 n5 = 1. 05e-1, tc 1 = 0, tc 2 = 2.5e- 5

res. rdrain n50 n16 = 2.5e- 3, tc 1 = 1.6e-2 , t c2 = 4e-5

r e s .rg ate n9 n2 0 = 4

res. rl drain n2 n5 = 10

res. rl gate n1 n9 = 35.7

res. rl sour ce n3 n7 = 42. 5

res. rslc1 n5 n51 = 1e- 6, tc1 = 5e-3, tc2 = 8e-6

res. rslc2 n5 n50 = 1e 3

res.rsource n8 n7 = 10e-3, tc1 = 0, tc2 = 0

res. rvte m p n18 n19 = 1, tc1 = -1.2 e-3, tc2 = 1e-6

res. rvth res n22 n8 = 1, tc1 = -1. 7e-3, tc 2 = -4e-6

spe. ebreak n11 n7 n17 n18 = 33. 4

spe. eds n14 n8 n5 n8 = 1

spe. egs n13 n8 n6 n8 = 1

spe. esg n6 n10 n6 n8 = 1

spe. evtemp n20 n6 n18 n22 = 1

spe.evthres n6 n21 n19 n8 = 1

sw_v cs p.s1a n6 n12 n13 n8 = model =s1a m od

sw_v cs p.s1 b n13 n12 n13 n8 = model=s1bmod

sw_v cs p.s2 a n6 n15 n14 n13 = model=s2amod

sw_v cs p.s2 b n13 n15 n14 n13 = mod el =s2bmod

v.vbat n22 n19 = dc = 1

equations {

i (n51->n50) + = iscl

iscl : v (n51, n50) = ((v (n5,n51) / (1e-9+abs (v(n5,n51))))*(( abs(v (n5,n 51)*1e6/ 181))** 4))

}

RBREAK

RVTEMP

VBAT

RVTHRES

17 18

S1A

S1B

S2A

S2B

CA CB

EGS EDS

814

MWEAK

EBREAK DBODY

RSOURCE

SOURCE

LSOURCE

RLSOURCE

CIN

RDRAIN

EVTHRES 16

MMED

MSTRO

DRAIN

LDRAIN

RLDRAIN

DBREAK

DPLCAP

ISCL

RSLC1

RSLC2

GATE RGATE EVTEMP

ESG

LGATE

RLGATE 20

RDBODY

RDBREAK

HUF76121P3, HUF76121S3S

SPICE Thermal Model

REV March 1998

HUF76121

CTHERM1 th 6 1.1e-3

CTHERM2 6 5 2.9e-3

CTHERM3 5 4 3.2e-3

CTHERM4 4 3 1.5e-2

CTHERM5 3 2 3.9e-1

CTHERM6 2 tl 2.2

RTHERM1 th 6 1.0e-4

RTHERM2 6 5 2.0e-3

RTHERM3 5 4 3.4e-1

RTHERM4 4 3 4.6e-1

RTHERM5 3 2 1.8e-1

RTHERM6 2 tl 7.0e-2

SABER Thermal Mod el

Saber thermal model HUF76121

template thermal_model th tl

thermal_c th, tl

{

c therm.ctherm1 th 6 = 1.1e-3

c therm.cther m2 6 5 = 2.9e-3

c therm.cther m3 5 4 = 3.2e-3

c therm.cther m4 4 3 = 1.5e-2

c therm.cther m5 3 2 = 3.9e-1

ctherm.ctherm6 2 tl = 2.2

rtherm.rtherm1 th 6 = 1 .0e-4

rtherm.rtherm2 6 5 = 2.0e-3

rtherm.rtherm3 5 4 = 3.4e-1

rtherm.rtherm4 4 3 = 4.6e-1

rtherm.rtherm5 3 2 = 1.8e-1

rtherm.rtherm6 2 tl = 7.0e-2

}

RTHERM4

RTHERM6

RTHERM5

RTHERM3

RTHERM2

RTHERM1

CTHERM4

CTHERM6

CTHERM5

CTHERM3

CTHERM2

CTHERM1

th JUNCTION

CASE

HUF76121P3, HUF76121S3S

Rev. I2

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intended to be an exhaustive list of all such trademarks.

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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY

PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY

LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;

NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR

CORPORATION.

As used h ere in:

1. Life support devices or systems are devices or systems

wh ich, (a) ar e int ende d fo r s urgic al i mpla nt into the body ,

or (b) support or sustain life, or (c) whose failure to perform

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to

result in significant injury to the user.

2. A c r it ic al c om pon ent is an y c om pone n t o f a life s u pp or t

device or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS

Defini ti on of Terms

ACEx™

ActiveArray™

Bottomless™

CoolFET™

CROSSVOLT™

DOME™

EcoSPARK™

E2CMOS™

EnSigna™

FACT™

FACT Quiet Series™

FAST®

FASTr™

FRFET™

GlobalOptoisolator™

GTO™

HiSeC™

I2C™

ImpliedDisconnect™

ISOPLANAR™

LittleFET™

MicroFET™

MicroPak™

MICROWIRE™

MSX™

MSXPro™

OCX™

OCXPro™

OPTOLOGIC®

OPTOPLANAR™

PACMAN™

POP™

Power247™

PowerTrench®

QFET™

QS™

QT Optoelectronics™

Quiet Serie s™

RapidConfigure™

RapidConnect™

SILENT SWITCHER®

SMART START™

SPM™

Stealth™

SuperSOT™-3

SuperSOT™-6

SuperSOT™-8

SyncFET™

TinyLogic®

TruTranslation™

UHC™

UltraFET®

VCX™

A cross the board. Around the world.™

T he Power Franchi se™

P rogramma ble Acti ve Droop™

Datasheet Identification Product Status Definition

Advance Information Formativ e or In

Design This datasheet contains the design specificat ions for

product development. Specifications may change in

any manner without notice.

Preliminary First Production This datasheet co ntains preliminary data , and

supplementary data will be published at a later date.

Fairchild Semiconductor reserves the right to make

changes at any t ime without notice in order to impr ove

design.

No Identification Needed Full Production This datasheet contains final specifications. Fairchild

Semiconductor reserves the right to make chan ges at

any time without notice in order to improve design.

Obsolete Not In Producti on This datasheet cont ains spec if ications on a prod uct

that has been discontinu ed by Fairchild s emico nductor.

The datasheet is printed for reference information only.