NJU3555NJU3555NJU8714
-1-
Ver.2004-05-21
STEREO BTL OUTPUTS SWITCHING DRIVER
FOR Class D AMPLIFIER
GENERAL DESCRIPTION
The NJU8714 is a stereo BTL outputs switching driver
for class D amplifier. It receives PWM/PDM signals from
DSP outputs, and drives headphones or speakers by BTL
outputs.
Output drivers are composed of Series-Connected
N-channel FETs, and output voltage levels can be
controlled by variable power supply with keeping all of
input signal information.
The NJU8714 incorporates BTL outputs amplifiers,
which eliminate AC coupling capacitors. Also, it provides
“SEL” terminal which selects “Synchronous” or
“Asynchronous”. “Asynchronous” can be reduced the
operating current. Therefore, it is suitable for portable
audio set and others.
FEATURES
2-channel 1bit Audio Signal Input
Stereo BTL Outputs
Output Power : Typ.150mW@8Ω
BEEP Function
Standby Function
Output Driver Control Function
Operating Voltage VDD: 1.7V to 2.7V
V
DDO: 0V to 2.0V
V
G: 4.5V to 5.25V
CMOS Technology
Package Outline :SSOP20-B2
BLOCK DIAGR AM
PIN CONFIGURATION
PACKAGE OUTLINE
NJU8714VB2
DIN2
DIN1
BEEPIN
M
CK
S
TBYB
Level
Shifter
V
SS
Pre
Driver
OBEEP1
OBEEP2
Level
Shifter
Level
S
hif
ter
Level
Shifter
VG
V
DD
HALTB Level
S
hif
ter
V
SSO
OUT1
X
V
DDO1
OUT1
V
SSO
OUT2
X
V
DDO2
OUT2
Control
Logic
Control
Logic
Level
Shifter
S
EL
Pre
Driver
MC
K
VSS
HALTB
DIN1
BEEPIN
VDD
SEL
STBYB
DIN2
VG
1
2
3
4
5
20
19
18
17
16
6
7
8
9
10
OBEEP1
OUT1
VSSO
OUT1
X
VDDO1
15
14
13
12
11
OBEEP2
OUT2
VSSO
OUT2
X
VDDO2
NJU8714
- 2 - Ver.2004-05-21
TERMINAL DESCRIPTIO N
No. SYMBOL I/O FUNCTION
1 MCK I Master Clock Input Terminal
2 VSS - Power GND: VSS=0V (Note.1)
3 HALTB I Output Driver Control Terminal
4 DIN1 I 1bit Data Input Terminal 1
5 BEEPIN I BEEP Signal Input Terminal
6 OBEEP1 O BEEP Output terminal 1
7 OUT1 O Positive Output Terminal 1
8,13 VSSO - Output GND terminal: VSS=0V (Note. 1)
9 OUT1X O Negative Output 1
10 VDDO1 - Output Power supply 1(Note. 2)
11 VDDO2 - Output Power supply 2(Note. 2)
12 OUT2X O Negative Output 2
14 OUT2 O Positive Output Terminal 2
15 OBEEP2 O BEEP Output terminal 2
16 VG - Pre-driver Power supply
17 DIN2 I 1bit Data Input Terminal 2
18 STBYB I Standby control terminal (L:Standby)
19 SEL I
Input Signal Synchronization With “MCK”
(H: Synchronous., L: Asynchronous.)
20 VDD - Power Supply: VDD=2.5V
(Note. 1) Pin No.2(VSS), 8(VSSO) and 13(VSSO) should be connected at the nearest point to the IC.
(Note. 2) Pin No.10(VDDO1) and 11(VDDO2) should be connected at the nearest point to the IC.
INPUT TERMIN AL STRUCTURE
MCK, HALTB, DIN1, DIN2, BEEPIN, STBYB, SEL
VDD
VSS
Input Terminal
NJU3555NJU3555NJU8714
-3-
Ver.2004-05-21
FUNCTIONAL DESCRIPTION
(1) Signal Output
The OUT1/1X and OUT2/2X generate respectively L-channel and R-channel output signals, which will be
converted to analog signals via external 2nd-order or higher LC filter. A switching regulator with a high response
against a voltage fluctuation is the best selection for the VDDO1 and VDDO2, which are the power supply for output
drivers. To obtain better T.H.D. performance, the stabilization of the power is required.
(2) Master Clock (MCK)
Input 1-bit audio signals such as PWM or PDM to the DIN1 and DIN2 pins. By setting the SEL pin to ”H”, master
clock (MCK) synchronizes the audio signal inputs (DIN1 and DIN2). In case of “SEL” = “L”, input signals go into the
amplifier circuits by own timing. Therefore, it requires careful design of PCB patterns from DSP to NJU8714.
The setup time and the hold time should be kept in the AC characteristics because DIN1 and DIN2 are fetched with
the rising edge of MCK. MCK requires jitter-free or jitter as small as possible because the jitter downs S/N ratio.
(3) Power Supply
VDD : Power supply for input part.
VG : Power supply for control logic and pre-driver which drives the transistor gates of output drivers.
It requires much higher power supply voltage than VDDO1 and VDDO2 for better T.H.D..
VDDO1, VDDO2 : Power supply for output drivers.
(4) Output Control
Output circuit is selected by the conditions of STBYB, HALTB, SEL, DIN1, DIN2 and MCK.
STBYB HALTB SEL DIN1, DIN2 MCK OUT1OUT2OUT1X OUT2X
L * * *
H L * * * VSSO VSSO VSSO V
SSO
L H * * * Hi-z Hi-z Hi-z Hi-z
L VSSO VSSO VDDO1 V
DDO2
L H * VDDO1 VDDO2 VSSO V
SSO
L VSSO VSSO VDDO1 V
DDO2
H H
H H VDDO1 VDDO2 VSSO V
SSO
*Don’t care
BEEP circuit is operated regardless of STBYB and HALTB.
(5) Input Signal Synchronization Function
DIN1 and DIN2 are synchronized with master clock by setting SEL pin to ”H”.
By setting SEL pin to ”L”, DIN1 and DIN2 are asynchronous with master clock.
(6) Output Driver Control Function
By setting HALTB pin to ”L”, high side output drivers become OFF and Low side output drivers become ON,
then both of OUT1/1X and OUT2/2X output VSSO level signals. This function works regardless of STBYB pin
setting.
(7) Standby Control Function
By setting STBYB pin to ”L”, the NJU8714 becomes standby condition. During standby condition, by setting
HALTB to ”L”, OUT1/1X and OUT2/2X become VSSO, and by setting HALTB pin to ”H”, OUT1/1X and OUT2/2X
become Hi-z.
To save the power supply current at standby, MCK requires ”L” level.
NJU8714
- 4 - Ver.2004-05-21
ABSOLUTE MAXIMUM RATINGS
(Ta=25°C)
PARAMETER SYMBOL RATING UNIT
VDD -0.3 to +2.75
VG V
DD to +5.5
Supply Voltage
VDDO -0.3 to +5.5
V
Input Voltage Vin -0.3 to VDD+0.3 V
Operating Temperature Topr -40 to +85 °C
Storage Temperature Tstg -40 to +125 °C
Power Dissipation PD 450* mW
* : Mounted on two-layer board of based on the JEDEC.
Note.1) All voltage values are specified as VSS=0V.
Note.2) If the LSI is used on condition beyond the absolute maximum rating, the LSI may be destroyed.
Using LSI within electrical characteristics is strongly recommended for normal operation. Use beyond
the electrical characteristics conditions will cause malfunction and poor reliability.
Note.3) The relations of VDDO < VG must be maintained during operations.
ELECTRICAL CHAR ACTERISTICS
(Ta=25°C, VDD=2.5V, VG=5.0V, VDDO1= VDDO2=1.7V, VSS=VSSO=0V,
STBYB=HALTB=SEL=2.5V, Load Impedance=32Ω, fS=44.1kHz, unless otherwise noted)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT
VDD Supply Voltage VDD - 1.7 2.5 2.7
VDDO1,2 Input Voltage VDDO - 0 - 2.0
VG Supply Voltage VG - 4.5 5.0 5.25
V
Output Driver
High side Resistance RHPH
OUT1, OUT1X,
OUT2, OUT2X
= VDDO1,2 – 0.1V
VG=5.0V
- 1.2 2 Ω
Output Driver
Low side Resistance RHPL
OUT1, OUT1X,
OUT2, OUT2X
= 0.1V
VG= 5.0V
- 1.2 2 Ω
Beep
High side Resistance RBEEPH O
BEEP1, OBEEP2= VDD– 0.1V - 9.0 15 Ω
Power Supply Current
At Standby IST
Stopping
MCK, DIN1, DIN2, BEEPIN
STBYB= 0V
- - 1.0 uA
IDD - 0.05 0.1
IDDO - 0.25 0.5
Power Supply Current
At Operating
(Mute signal input) IG
No-load operating,
MCK= 256fS,
DIN1, DIN2= 32fS,
VDDO1= VDDO2= 0.18V 1.0 2.0
mA
VIH 0.7VDD - VDD V
Input Voltage VIL 0 -
0.3
VDD V
Input Leakage Current ILK
MCK, DIN1, DIN2, BEEPIN,
HALTB, STBYB, SEL
- - ±1.0 uA
Note 1) High side resistance and low side resistance depend on VG and VDDO. Therefore, VG and VDDO should be
adjusted on the application system.
Note 2) Output power using 8Ω speaker is 150mW(TYP:THD+N=10%) at the following condition.
→VDD=2.5V, VG=5.0V, VDDO1= VDDO2=3.0V
NJU3555NJU3555NJU8714
-5-
Ver.2004-05-21
TIMING CHARACTERISTICS
• Audio Signal Input
(Ta=25°C, VDD=2.5V, VDDO1=VDDO2=1.7V, VSS=VSSO=0V,
STBYB=HALTB=SEL=2.5V, fs=44.1kHz, unless otherwise noted)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT
MCK Frequency fMCKI 8 - 35 MHz
MCK Pulse Width (H) tMCKH 9 -
-
ns
MCK Pulse Width (L) tMCKL 9 -
-
ns
DIN1,DIN2 Setup Time tDS 5 -
-
ns
DIN1,DIN2 Hold Time tDH 5 -
-
ns
BEEP Frequency fb 0.1
20
kHz
• Output Control Signal Input
(Ta=25°C, VDD=2.5V, VDDO1=VDDO2=1.7V, VSS=VSSO=0V,
STBYB=HALTB=SEL=2.5V, fs=44.1kHz, unless otherwise noted)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT
Rise Time tUP - - 50 ns
Fall Time tDN - - 50 ns
tDN tUP
BEEPIN, HALTB
STBYB, SEL
0.9VDD
0.1VDD
tMCKH
tDS tDH
MC
K
DIN1,DIN2
tMCKL
0.7VDD
0.7VDD
0.3VDD
0.3VDD
NJU8714
- 6 - Ver.2004-05-21
APPLICATION CI RCUIT
-Load Impedance: 32Ω
-Load Impedance: 8Ω
Note 3) De-coupling capacitors must be connected between each power supply pin and GND pin.
Note 4) The power supply for VDDO requires fast driving response performance such as a switching regulator
for T.H.D..
Note 5) The above circuit shows only application example and does not guarantee the any electrical
characteristics. Therefore, please consider and check the circuit carefully to fit your application.
VDD VDDO
OUT1X(9)
OUT1(7)
STBYB
(
18
)
MCK(1)
VDD(20)
DIN1(4)
DIN2(17)
HALTB(3)
VSS(2)
NJU8714
VSSO(8)
100uF
2.2uF
VDDO1(10)
VSSO(13)
VDDO2(11)
Speaker
32Ω
0.22uF
100uH
0.22uF
100uH
OUT2X(12)
OUT2(14)
VG(16) VG
10uF2.2uF
100uF
2.2uF
10uF 2.2u
SEL
(
19
)
Speaker
32Ω
0.22uF
100uH
0.22uF
100uH
VDD VDDO
OUT1X(9)
OUT1(7)
STBYB
(
18
)
MCK(1)
VDD(20)
DIN1(4)
DIN2(17)
HALTB(3)
VSS(2)
NJU8714
VSSO(8)
100uF
2.2uF
VDDO1(10)
VSSO(13)
VDDO2(11)
Speaker
8Ω
1.0uF
22uH
1.0uF
22uH
OUT2X(12)
OUT2(14)
VG(16) VG
10uF2.2uF
100uF
2.2uF
10uF 2.2u
SEL
(
19
)
Speaker
8Ω
1.0uF
22uH
1.0uF
22uH
NJU3555NJU3555NJU8714
-7-
Ver.2004-05-21
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
