EK64904-12 - PEREGRINE SEMICONDUCTOR

Page 1 of 11

Product Description

The PE64904 is a DuNE™-enhanced Digitally Tunable

Capacitor (DTC) based on Peregrine’s UltraCMOS®

technology. DTC products provide a monolithically

integrated impedance tuning solution for demanding RF

applications.

The PE64904 offers high RF power handling and

ruggedness, while meeting challenging harmonic and

linearity requirements.

This highly versatile product can be used in series or shunt

configurations to support a wide variety of tuning circuit

topologies.

The device is controlled through the widely supported

3-wire (SPI compatible) interface. All decoding and biasing

is integrated on-chip and no external bypassing or filtering

components are required.

Peregrine’s DuNE™ technology enables excellent linearity

and exceptional harmonic performance. DuNE devices

deliver performance superior to GaAs devices with the

economy and integration of conventional CMOS.

Product Specification

UltraCMOS® Digitally Tunable Capacitor

(DTC) 100 - 3000 MHz

PE64904

Features

 3-wire (SPI compatible) Serial Interface

with built-in bias voltage generation and

ESD protection

 DuNE™-enhanced UltraCMOS® device

 5-bit 32-state Digitally Tunable Capacitor

 Series configuration C = 0.60 - 4.60 pF

(7.7:1 tuning ratio) in discrete 129 fF steps

 Shunt configuration C = 1.14 - 5.10 pF

(4.6:1 tuning ratio) in discrete 129 fF steps

 High RF Power Handling (up to 38 dBm,

30 Vpk RF) and High Linearity

 Wide power supply range (2.3 to 3.6V)

and low current consumption

(typ. 140 μA at 2.6V)

 Excellent 1.5 kV HBM ESD tolerance

on all pins

 2 x 2 x 0.45 mm QFN package

 Applications include:

 Tunable Filter Networks

 Tunable Antennas

 RFID

 Tunable Matching Networks

 Phase Shifters

 Wireless Communications

Figure 2. Package Type

10L 2 x 2 x 0.45 mm QFN package

Figure 1. Functional Block Diagram

71-0066-01

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Product Specification

PE64904

Page 2 of 11

Table 1. Electrical Specifications @ 25°C, VDD = 2.6V

Parameter Configuration Condition Min Typ Max Units

Operating Frequency Range Both 100 3000 MHz

Minimum Capacitance Series

Shunt

State = 00000, 100 MHz (RF+ to RF-)

State = 00000, 100 MHz (RF+ to Grounded RF-)

0.49

0.99

0.60

1.10

0.71

1.21 pF

Maximum Capacitance Series

Shunt

State = 11111, 100 MHz (RF+ to RF-)

State = 11111, 100 MHz (RF+ to Grounded RF-)

4.09

4.59

4.60

5.10

5.11

5.61 pF

Parasitic Capacitance Series All States, 100 MHz (RF+ to GND, RF- to GND) 0.5 pF

Tuning Ratio Series

Shunt

100 MHz

100 MHz 7.7:1

4.6:1

Step Size Both 5 bits (32 states), constant step size (100 MHz) 0.129 pF

Equivalent Series Resistance Series State = 00000

State = 11111 1.40

1.33 Ω

Quality Factor (Cmin)1 Shunt

100 MHz, with Ls removed

1 GHz, with Ls removed

2 GHz, with Ls removed

3 GHz, with Ls removed

Quality Factor (Cmax)1 Shunt

100 MHz, with Ls removed

1 GHz, with Ls removed

2 GHz, with Ls removed

3 GHz, with Ls removed

Self Resonant Frequency Shunt State 00000

State 11111 7.5

3.1 GHz

Harmonics (2fo)2

Series

100 MHz - 3 GHz -36 dBm

Harmonics (3fo)2 100 MHz - 3 GHz -36 dBm

Input Intercept Point (2nd Order) Series 100 MHz - 3 GHz, +18 dBm per tone, 1 MHz Spacing 105 dBm

Input Intercept Point (3rd Order) Series 100 MHz - 3 GHz, +18 dBm per tone, 1 MHz Spacing 65 dBm

Switching Time3, 4 Both 50% CTRL to 10/90% delta capacitance between any two

states 12 µs

Start-up Time3 Both Time from VDD within specification to all performances within

specification 100 µs

Wake-up Time3, 4 Both

State change from standby mode to RF state to all perfor-

mances within specification 100 µs

Notes: 1. Q for a Shunt DTC based on a Series RLC equivalent circuit.

Q = XC/R = (X-XL)/R, where X = XL+XC , XL = 2*pi*f*L, XC = -1/(2*pi*f*C), which is equal to removing the effect of parasitic inductance LS.

2. In series or shunt between 50 Ω ports. Pulsed RF input with 4620 µs period, 50% duty cycle, measured per 3GPP TS 45.005.

3. DC path to ground at RF+ and RF- must be provided to achieve specified performance.

4. State change activated on falling edge of SEN following data word.

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Product Specification

PE64904

Page 3 of 11

Pin # Pin Name Description

1 RF- Negative RF Port1

2 RF- Negative RF Port1

3 DGND Ground

4 VDD Power supply pin

5 SCL Serial interface Clock input

6 SEN Serial Interface Latch Enable Input

7 SDA Serial interface Data input

8 RF+ Positive RF Port1

9 RF+ Positive RF Port1

10 GND RF Ground

Table 3. Operating Ranges

Figure 3. Pin Configuration (Top View)

Table 2. Pin Descriptions

Exceeding absolute maximum ratings may cause

permanent damage. Operation should be restricted

to the limits in the Operating Ranges table.

Operation between operating range maximum and

absolute maximum for extended periods may reduce

reliability.

Table 4. Absolute Maximum Ratings

Symbol Parameter/Conditions Min Max Units

VDD Power supply voltage -0.3 4.0 V

VI Voltage on any DC input -0.3 4.0 V

VESD ESD Voltage (HBM, MIL_STD

883 Method 3015.7) 1500 V

Electrostatic Discharge (ESD) Precautions

When handling this UltraCMOS® device, observe

the same precautions that you would use with other

ESD-sensitive devices. Although this device

contains circuitry to protect it from damage due to

ESD, precautions should be taken to avoid

exceeding the specified rating. 



Latch-Up Avoidance

Unlike conventional CMOS devices, UltraCMOS®

devices are immune to latch-up.

Moisture Sensitivity Level

The Moisture Sensitivity Level rating for the

PE64904 in the 10-lead 2 x 2 x 0.45 mm QFN

package is MSL1.

Note 1: Pins 1-2 and 8-9 must be tied together on PCB for optimal performance.

Parameter Min Typ Max Units

VDD Supply Voltage 2.3 2.6 3.6 V

IDD Power Supply Current (VDD = 2.6V) 140 200 µA

VIH Control Voltage High 1.2 1.8 3.6 V

VIL Control Voltage Low 0 0 0.57 V

Peak Operating RF Voltage2

VP to VM

VP to RFGND

VM to RFGND

Vpk

TOP Operating Temperature Range -40 +85 °C

TST Storage Temperature Range -65 +150 °C

IDD Standby Current (VDD = 2.6V) 25 µA

RF Input Power (50Ω)1

698 - 915 MHz

1710 -1910 MHz

+34

+32

dBm

Notes: 1. Maximum Power Available from 50Ω Source. Pulsed RF input with

4620 µS period, 50% duty cycle, measured per 3GPP TS 45.005.

2. Node voltages defined per Equivalent Circuit Model Schematic

(Figure 18). When DTC is used as a part of reactive network, impedance

transformation may cause the internal RF voltages (VP, VM) to exceed Peak

Operating RF Voltage even with specified RF Input Power Levels. For

operation above about +20 dBm (100 mW), the complete RF circuit must

be simulated using actual input power and load conditions, and internal

node voltages (VP, VM in Figure 18) monitored to not exceed 30 Vpk.

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Product Specification

PE64904

Page 4 of 11

Figure 6. Measured Step Size vs State

(frequency)

Figure 5. Measured Shunt S11 (major states)

Figure 7. Measured Series S11/S22 (major states)

Performance Plots @ 25°C and 2.6V unless otherwise specified

0.0

2.5

5.0

7.5

10.0

12.5

15.0

17.5

20.0

0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00

Capacitance (pF)

Frequency (GHz)

C16

C31

-262

-131

131

262

393

524

655

786

917

1048

0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32

Step Size (fF)

State

100 MHz

1000 MHz

2000 MHz

2500 MHz

-2

-1

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

02468101214161820222426283032

Delta C (%), Relative to C at +25C

Capacitance (pF)

State

Measured Shunt C vs. State (Temperature)

C (pF) at +85C

C (pF) at +25C

C (pF) at -40C

Delta C (%) at +85C

Delta C (%) at -40C

Figure 8. Measured Shunt C vs

Frequency (major states)

Figure 9. Measured Series S21 vs Frequency

(major states)

Figure 4. Measured Shunt C (@ 100 MHz) vs

State (temperature)

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Product Specification

PE64904

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Figure 11. Measured Shunt Q (state 0) vs

Frequency (temperature)

0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00

Frequency [GHz]

Q16

Q31

Figure 10. Measured Shunt Q vs

Frequency (major states)

-15

-10

-5

0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00

Delta Q (%) Relative to 25C

Frequency (GHz)

Q (C31) at +85C

Q (C0) at -40C

Q (C0) at +25C

Delta Q (%) at +85C

Delta Q (%) at -40C

Figure 12. Measured Shunt Q (state 31) vs

Frequency (temperature)

-10

-5

0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00

Delta Q (%) Relative to 25C

Frequency (GHz)

Q (C0) at +85C

Q (C0) at +25C

Q (C0) at -40C

Delta Q (%) at +85C

Delta Q (%) at -40C

Q (C0) at +85C

Q (C0) at -40C

Q (C0) at +25C

Delta Q (%) at +85C

Delta Q (%) at -40C

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Product Specification

PE64904

Page 6 of 11

Operation at Frequencies Below 100 MHz

The PE64904 may be operated below the

100 MHz specified minimum operating frequency.

The total capacitance and peak operating RF

voltage are de-rated down to 1 MHz. Figure 13

shows the total shunt capacitance from 1 MHz

through 100 MHz. As seen in Figure 14, the

maximum RF voltage that can be placed across

the RF terminals or across either RF terminal to

Ground is de-rated as a function of frequency.

Note: Table 1 performance specifications are not guaranteed below 100 MHz.

Figures 13, 14, and 15 reflect performance of a typical PE64904.

0 102030405060708090100

Quality Factor

Frequency (MHz)

C16

C31

0.0

2.5

5.0

7.5

10.0

12.5

15.0

17.5

20.0

0 102030405060708090100

Capacitance (pF)

Frequency (MHz)

C16

C31

Figure 13. Measured Shunt C vs Frequency

(major states, 1 MHz - 100 MHz)

Figure 15. Measured Shunt Q vs Frequency

(major states, 1 MHz - 100 MHz)

0 20406080100

Vmax RF (V)

Frequency (MHz)

Figure 14. Voltage Derating vs Frequency

(1 MHz - 100 MHz)

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Product Specification

PE64904

Page 7 of 11

Table 6. Serial Interface Timing Characteristics

b4 b3 b2 b1 b0

d4 d3 d2 d1 d0

STB1

b7 b6

0 0

MSB

(first in)

LSB

(last in)

Table 5. Register Map

Serial Interface Operation and Sharing

The PE64904 is controlled by a three wire SPI-

compatible interface. As shown in Figure 16, the serial

master initiates the start of a telegram by driving the

SEN (Serial Enable) line high. Each bit of the 8-bit

telegram is clocked in on the rising edge of the SCL

(Serial Clock) line. SDA bits are clocked by most

significant bit (MSB) first, as shown in Table 5 and

Figure 16. Transactions on SDA (Serial Data) are

allowed on the falling edge of SCL. The DTC activates

the data on the falling edge of SEN. The DTC does not

count how many bits are clocked and only maintains

the last 8 bits it received.

Figure 17. Recommended Bus sharing

SCL

SDA

VDD

GND

DGND

RF-

RF+

SCL

SDA

VDD

SEN

GND

DGND

RF-

RF+

SCL

SDA

VDD

DTC 1

SEN

SEN2

SEN1

DTC 2

More than 1 DTC can be controlled by one interface by

utilizing a dedicated enable (SEN) line for each DTC.

SDA, SCL, and VDD lines may be shared as shown in

Figure 17. Dedicated SEN lines act as a chip select such

that each DTC will only respond to serial transactions

intended for them. This makes each DTC change states

sequentially as they are programmed.

Alternatively, a dedicated SDA line with common SEN

can be used. This allows all DTCs to change states

simultaneously, but requires all DTCs to be programmed

even if the state is not changed.

Figure 16. Serial Interface Timing Diagram (oscilloscope view)

Note 1: The DTC is active when low (set to 0) and in

low-current stand-by mode when high (set to 1)

b5b6

DHD

DSU

1/f

CLK

b7 b0b4 b3 b2 b1

m-1

<7:0> D

<7:0>

m-2

<7:0>

EPW

ESU

EHD

SEN

SCL

SDA

DTC Data

VDD = 2.6V, -40°C < TA < +85°C, unless otherwise specified

Symbol Parameter Min Max Units

fCLK Serial Clock Frequency 26 MHz

tR SCL, SDA, SEN Rise Time 6.5 ns

tF SCL, SDA, SEN Fall Time 6.5 ns

tESU

SEN rising edge to SCL rising

edge 19.2 ns

tEHD

SCL rising edge to SEN falling

edge 19.2 ns

tDSU SDA valid to SCL rising edge 13.2 ns

tDHD SDA valid after SCL rising edge 13.2 ns

tEOW

SEN falling edge to SEN rising

edge 38.4 ns

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Product Specification

PE64904

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Figure 18. Equivalent Circuit Model Schematic

Equivalent Circuit Model Description

The DTC Equivalent Circuit Model includes all

parasitic elements and is accurate in both Series

and Shunt configurations, reflecting physical circuit

behavior accurately and providing very close

correlation to measured data. It can easily be used

in circuit simulation programs. Most parameters are

state independent, and simple equations are

provided for the state dependent parameters.

The Tuning Core capacitance CS represents

capacitance between RF+ and RF- ports. It is

linearly proportional to state (0 to 31 in decimal) in

a discrete fashion. The Series Tuning Ratio is

defined as CSmax/CSmin.

CP represents the circuit and package parasitics

from RF ports to GND. In Shunt configuration the

total capacitance of the DTC is higher due to

parallel combination of CP and CS. In Series

configuration, CS and CP do not add in parallel and

the DTC appears as an impedance transformation

network.

Parasitic inductance due to circuit and package is

modeled as LS and causes the apparent

capacitance of the DTC to increase with frequency

until it reaches Self Resonant Frequency (SRF).

The value of SRF depends on state and is

approximately inversely proportional to the square

root of capacitance.

The overall dissipative losses of the DTC are

modeled by RS, RP1 and RP2 resistors. The

parameter RS represents the Equivalent Series

Resistance (ESR) of the tuning core and is

dependent on state. RP1 and RP2 represent losses

due to the parasitic and biasing networks, and are

state-independent.

Table 8. Equivalent Circuit Model Parameters

Table 9. Equivalent Circuit Data

Variable Equation (state = 0, 1, 2…31) Units

CS 0.129*state + 0.600 pF

RS 20/(state+20/(state+0.7)) + 0.7 Ω

RP1 7 Ω

RP2 10 kΩ

CP 0.5 pF

LS 0.27 nH

State DTC Core

Binary Decimal Cs [pF] Rs [Ω]

00000 0 0.60 1.40

00001 1 0.73 2.27

00010 2 0.86 2.83

00011 3 0.99 3.08

00100 4 1.12 3.12

00101 5 1.25 3.05

00110 6 1.37 2.93

00111 7 1.50 2.78

01000 8 1.63 2.64

01001 9 1.76 2.51

01010 10 1.89 2.39

01011 11 2.02 2.27

01100 12 2.15 2.17

01101 13 2.28 2.08

01110 14 2.41 2.00

01111 15 2.54 1.93

10000 16 2.66 1.86

10001 17 2.79 1.80

10010 18 2.92 1.75

10011 19 3.05 1.70

10100 20 3.18 1.65

10101 21 3.31 1.61

10110 22 3.44 1.57

10111 23 3.57 1.54

11000 24 3.70

1.51

11001 25 3.83 1.48

11010 26 3.95 1.45

11011 27 4.08 1.42

11100 28 4.21 1.40

11101 29 4.34 1.37

11110 30 4.47 1.35

11111 31 4.60 1.33

Table 7. Maximum Operating RF Voltage

Condition Limit

VP to VM 30 Vpk

VP to RFGND 30 Vpk

VM to RFGND 30 Vpk

RF-

RF+

RFGND

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Product Specification

PE64904

Page 9 of 11

Figure 20. Recommended Layout of Multiple DTCs

Figure 19. Recommended Schematic of

Multiple DTCs

Layout Recommendations

For optimal results, place a ground fill directly under

the DTC package on the PCB. Layout isolation is

desired between all control and RF lines. When

using the DTC in a shunt configuration, it is

important to make sure the RF-pin is solidly

grounded to a filled ground plane. Ground traces

should be as short as possible to minimize

inductance. A continuous ground plane is preferred

on the top layer of the PCB. When multiple DTCs

are used together, the physical distance between

them should be minimized and the connection

should be as wide as possible to minimize series

parasitic inductance.

Evaluation Board

The 101-0597 Evaluation Board (EVB) was designed

for accurate measurement of the DTC impedance

and loss. Two configurations are available: 1 Port

Shunt (J3) and 2 Port Series (J4, J5). Three

calibration standards are provided. The open (J2)

and short (J1) standards (104 ps delay) are used for

performing port extensions and accounting for

electrical length and transmission line loss. The Thru

(J9, J10) standard can be used to estimate PCB

transmission line losses for scalar de-embedding of

the 2 Port Series configuration (J4, J5).

The board consists of a 4 layer stack with 2 outer

layers made of Rogers 4350B (εr = 3.48) and 2 inner

layers of FR4 (εr = 4.80). The total thickness of this

board is 62 mils (1.57 mm). The inner layers provide

a ground plane for the transmission lines. Each

transmission line is designed using a coplanar

waveguide with ground plane (CPWG) model using

a trace width of 32 mils (0.813 mm), gap of 15 mils

(0.381 mm), and a metal thickness of 1.4 mils

(0.051 mm).

Figure 21. Evaluation Board Layout

101-0597

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Product Specification

PE64904

Page 10 of 11

Figure 23. Marking Specifications

PPZZ

YWW

Marking Spec

Symbol

Package

Marking Definition

PP CG Part number marking for PE64904

ZZ 00-99 Last two digits of lot code

Y 0-9 Last digit of year, starting from 2009

(0 for 2010, 1 for 2011, etc)

WW 01-53 Work week

Figure 22. Package Drawing

10-lead 2 x 2 x 0.45 mm

17-0112

19-2002

Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com

Product Specification

PE64904

Page 11 of 11

Order Code Package Description Shipping Method

PE64904MLBB-Z 10-lead QFN 2 x 2 x 0.45 mm Package Part in Tape and Reel 3000 units/T&R

EK64904-12 Evaluation Kit Evaluation Kit 1 Set/Box

Figure 24. Tape and Reel Specifications

10-lead 2 x 2 x 0.45 mm

Tape Feed Direction

Table 9. Ordering Information

Advance Information: The product is in a formative or design stage. The datasheet contains

design target specifications for product development. Specifications and features may change

in any manner without notice. Preliminary Specification: The datasheet contains preliminary

data. Additional data may be added at a later date. Peregrine reserves the right to change

specifications at any time without notice in order to supply the best possible product. Product

Specification: The datasheet contains final data. In the event Peregrine decides to change the

specifications, Peregrine will notify customers of the intended changes by issuing a CNF

(Customer Notification Form).

The information in this datasheet is believed to be reliable. However, Peregrine assumes no

liability for the use of this information. Use shall be entirely at the user’s own risk.

No patent rights or licenses to any circuits described in this datasheet are implied or granted to any

third party.

Peregrine’s products are not designed or intended for use in devices or systems intended for surgical

implant, or in other applications intended to support or sustain life, or in any application in which the

failure of the Peregrine product could create a situation in which personal injury or death might occur.

Peregrine assumes no liability for damages, including consequential or incidental damages, arising out

of the use of its products in such applications.

The Peregrine name, logo, UltraCMOS and UTSi are registered trademarks and HaRP, MultiSwitch

and DuNE are trademarks of Peregrine Semiconductor Corp. All other trademarks mentioned herein

are the property of their respective companies.

Sales Contact and Information

For sales and contact information please visit www.psemi.com.

Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com