8-Channel DAS with 18-Bit, Bipolar, Simultaneous Sampling ADC AD7608 Data Sheet FEATURES APPLICATIONS 8 simultaneously sampled inputs True bipolar analog input ranges: 10 V, 5 V Single 5 V analog supply and 2.3 V to 5.25 V VDRIVE Fully integrated data acquisition solution Analog input clamp protection Input buffer with 1 M analog input impedance Second-order antialiasing analog filter On-chip accurate reference and reference buffer 18-bit ADC with 200 kSPS on all channels Oversampling capability with digital filter Flexible parallel/serial interface SPI/QSPITM/MICROWIRETM/DSP compatible Pin compatible solutions from 14-bits to 18-bits Performance 7 kV ESD rating on analog input channels 98 dB SNR, -107 dB THD Low power: 100 mW Standby mode: 25 mW 64-lead LQFP package Power line monitoring and protection systems Multiphase motor controls Instrumentation and control systems Multiaxis positioning systems Data acquisition systems (DAS) COMPANION PRODUCTS External References: ADR421, ADR431 Digital Isolators: ADuM1402, ADuM5000, ADuM5402 Voltage Regulator Design Tool: ADIsimPower, Supervisor Parametric Search Complete list of complements on AD7608 product page Table 1. High Resolution, Bipolar Input, Simultaneous Sampling DAS Solutions SingleEnded Inputs AD76081 AD7606 AD7606-6 AD7606-4 AD7607 Resolution 18 Bits 16 Bits 14 Bits True Differential Inputs AD7609 Number of Simultaneous Sampling Channels 8 8 6 4 8 FUNCTIONAL BLOCK DIAGRAM AVCC CLAMP CLAMP V2 CLAMP V2GND CLAMP V3 CLAMP V3GND CLAMP V4 V4GND CLAMP CLAMP V5 CLAMP V5GND CLAMP V6 CLAMP V6GND CLAMP V7 CLAMP V7GND CLAMP V8 CLAMP V8GND CLAMP RFB 1M RFB 1M RFB 1M RFB 1M RFB 1M RFB 1M RFB 1M RFB 1M RFB 1M RFB 1M RFB 1M RFB 1M RFB 1M RFB 1M RFB 1M RFB SECOND ORDER LPF AVCC REGCAP REGCAP 2.5V LDO 2.5V LDO T/H REFCAPB REFCAPA REFIN/REFOUT SECOND ORDER LPF T/H 2.5V REF SECOND ORDER LPF T/H REF SELECT AGND OS 2 OS 1 OS 0 SECOND ORDER LPF T/H SERIAL 8:1 MUX SECOND ORDER LPF T/H 18-BIT SAR DIGITAL FILTER PARALLEL/ SERIAL INTERFACE DOUTA DOUTB RD/SCLK CS PAR/SER SEL VDRIVE SECOND ORDER LPF T/H PARALLEL DB[15:0] AD7608 SECOND ORDER LPF SECOND ORDER LPF T/H CLK OSC CONTROL INPUTS T/H AGND CONVST A CONVST B RESET RANGE BUSY FRSTDATA 08938-001 V1 V1GND 1M Figure 1. 1 Patent pending. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2011-2012 Analog Devices, Inc. All rights reserved. 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AD7608 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Converter Details ....................................................................... 19 Applications ....................................................................................... 1 Analog Input ............................................................................... 19 Companion Products ....................................................................... 1 ADC Transfer Function ............................................................. 20 Functional Block Diagram .............................................................. 1 Internal/External Reference ...................................................... 21 Revision History ............................................................................... 2 Typical Connection Diagram ................................................... 22 General Description ......................................................................... 3 Power-Down Modes .................................................................. 22 Specifications..................................................................................... 4 Conversion Control ................................................................... 23 Timing Specifications .................................................................. 6 Digital Interface .............................................................................. 24 Absolute Maximum Ratings.......................................................... 10 Parallel Interface (PAR/SER SEL = 0) ...................................... 24 Thermal Resistance .................................................................... 10 Serial Interface (PAR/SER SEL = 1) ......................................... 25 ESD Caution ................................................................................ 10 Reading During Conversion ..................................................... 25 Pin Configuration and Function Descriptions ........................... 11 Digital Filter ................................................................................ 26 Typical Performance Characteristics ........................................... 14 Layout Guidelines....................................................................... 30 Terminology .................................................................................... 18 Outline Dimensions ....................................................................... 32 Theory of Operation ...................................................................... 19 Ordering Guide .......................................................................... 32 REVISION HISTORY 1/12--Rev. 0 to Rev. A Changes to Analog Input Ranges Section ************************************19 4/11--Revision 0: Initial Version Rev. A | Page 2 of 32 Data Sheet AD7608 GENERAL DESCRIPTION The AD7608 is an 18-bit, 8-channel simultaneous sampling, analog-to-digital data acquisition system (DAS). The part contains analog input clamp protection, a second-order antialiasing filter, a track-and-hold amplifier, an 18-bit charge redistribution successive approximation analog-to-digital converter (ADC), a flexible digital filter, a 2.5 V reference and reference buffer, and high speed serial and parallel interfaces. The AD7608 operates from a single 5 V supply and can accommodate 10 V and 5 V true bipolar input signals while sampling at throughput rates up to 200 kSPS for all channels. The input clamp protection circuitry can tolerate voltages up to 16.5 V. The AD7608 has 1 M analog input impedance regardless of sampling frequency. The single supply operation, on-chip filtering, and high input impedance eliminate the need for driver op amps and external bipolar supplies. The AD7608 antialiasing filter has a 3 dB cutoff frequency of 22 kHz and provides 40 dB antialias rejection when sampling at 200 kSPS. The flexible digital filter is pin driven, yields improvements in SNR, and reduces the 3 dB bandwidth. Rev. A | Page 3 of 32 AD7608 Data Sheet SPECIFICATIONS VREF = 2.5 V external/internal, AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V; fSAMPLE = 200 kSPS, TA = TMIN to TMAX, unless otherwise noted. 1 Table 2. Parameter DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) 2, 3 Signal-to-(Noise + Distortion) (SINAD)2 Dynamic Range Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD)2 Second-Order Terms Third-Order Terms Channel-to-Channel Isolation2 ANALOG INPUT FILTER Full Power Bandwidth tGROUP DELAY DC ACCURACY Resolution Differential Nonlinearity2 Integral Nonlinearity2 Total Unadjusted Error (TUE) Positive Full-Scale Error2, 5 Positive Full-Scale Error Drift Positive Full-Scale Error Matching2 Bipolar Zero Code Error2, 6 Bipolar Zero Code Error Drift Bipolar Zero Code Error Matching2 Negative Full-Scale Error2, 5 Negative Full-Scale Error Drift Negative Full-Scale Error Matching2 Test Conditions/Comments fIN = 1 kHz sine wave unless otherwise noted Oversampling by 16; 10 V range; fIN = 130 Hz Oversampling by 16; 5 V range; fIN = 130 Hz No oversampling; 10 V range No oversampling; 5 V range No oversampling; 10 V range No oversampling; 5 V range No oversampling; 10 V range No oversampling; 5 V range Min Typ 98 95.5 89.5 88.5 88.5 88 99.5 97.5 90.9 90 90.5 89.5 91.5 90.5 -107 -108 Max -95 Unit dB dB dB dB dB dB dB dB dB dB fa = 1 kHz, fb = 1.1 kHz fIN on unselected channels up to 160 kHz -110 -106 -95 dB dB dB -3 dB, 10 V range -3 dB, 5 V range -0.1 dB, 10 V range -0.1 dB, 5 V range 10 V range 5 V range 23 15 10 5 11 15 kHz kHz kHz kHz s s No missing codes 10 V range 5 V range External reference Internal reference External reference Internal reference 10 V range 5 V range 10 V range 5 V range 10 V range 5 V range 10 V range 5 V range External reference Internal reference External reference Internal reference 10 V range 5 V range Rev. A | Page 4 of 32 18 0.75 2.5 15 40 15 40 2 7 12 30 3.5 3.5 10 5 3 21 15 40 4 8 12 30 -0.99/+2.6 7.5 128 95 128 24 48 30 65 128 95 128 Bits LSB 4 LSB LSB LSB LSB LSB ppm/C ppm/C LSB LSB LSB LSB V/C V/C LSB LSB LSB LSB ppm/C ppm/C LSB LSB Data Sheet Parameter ANALOG INPUT Input Voltage Ranges Analog Input Current Input Capacitance 7 Input Impedance REFERENCE INPUT/OUTPUT Reference Input Voltage Range DC Leakage Current Input Capacitance7 Reference Output Voltage Reference Temperature Coefficient LOGIC INPUTS Input High Voltage (VINH) Input Low Voltage (VINL) Input Current (IIN) Input Capacitance (CIN)7 LOGIC OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) Floating-State Leakage Current Floating-State Output Capacitance7 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS AVCC VDRIVE ITOTAL Normal Mode (Static) Normal Mode (Operational)8 Standby Mode Shutdown Mode Power Dissipation Normal Mode (Static) Normal Mode (Operational) 8 Standby Mode Shutdown Mode AD7608 Test Conditions/Comments Min RANGE = 1 RANGE = 0 10 V; see Figure 28 5 V; see Figure 28 Typ Max Unit 10 5 V V A A pF M 2.525 1 V A pF V 5.4 2.5 5 1 2.475 REF SELECT = 1 REFIN/REFOUT 2.5 7.5 2.49/ 2.505 10 ppm/C 0.9 x VDRIVE 0.1 x VDRIVE 2 V V A pF 0.2 20 V V A pF 5 ISOURCE = 100 A ISINK = 100 A VDRIVE - 0.2 1 5 Twos complement All eight channels included; see Table 3 4 1 200 s s kSPS 5.25 5.25 V V 16 20 5 2 22 27 8 11 mA mA mA A 80 100 25 10 115.5 142 42 58 mW mW mW W Per channel, all eight channels included 4.75 2.3 Digital inputs = 0 V or VDRIVE fSAMPLE = 200 kSPS fSAMPLE = 200 kSPS Temperature range for B version is -40C to +85C. See the Terminology section. 3 This specification applies when reading during a conversion or after a conversion. If reading during a conversion in parallel mode with VDRIVE = 5 V, SNR typically reduces by 1.5 dB and THD by 3 dB. 4 LSB means least significant bit. With 5 V input range, 1 LSB = 38.14 V. With 10 V input range, 1 LSB = 76.29 V. 5 These specifications include the full temperature range variation and contribution from the internal reference buffer but do not include the error contribution from the external reference. 6 Bipolar zero code error is calculated with respect to the analog input voltage. 7 Sample tested during initial release to ensure compliance. 8 Operational power/current figure includes contribution when running in oversampling mode. 1 2 Rev. A | Page 5 of 32 AD7608 Data Sheet TIMING SPECIFICATIONS AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, VREF = 2.5 V external reference/internal reference, TA = TMIN to TMAX, unless otherwise noted. 1 Table 3. Parameter PARALLEL/SERIAL/BYTE MODE tCYCLE Limit at TMIN, TMAX Min Typ Max Unit 5 s 10.5 s s tWAKE-UP STANDBY 4.15 9.1 18.8 39 78 158 315 100 s s s s s s s s tWAKE-UP SHUTDOWN Internal Reference 30 ms External Reference 13 ms 5 Description 1/throughput rate Parallel mode, reading during or after conversion; or serial mode: VDRIVE = 3.3 V to 5.25 V, reading during a conversion using DOUTA and DOUTB lines Serial mode reading during conversion; VDRIVE = 2.7 V Serial mode reading after a conversion; VDRIVE = 2.3 V, DOUTA and DOUTB lines Conversion time Oversampling off Oversampling by 2 Oversampling by 4 Oversampling by 8 Oversampling by 16 Oversampling by 32 Oversampling by 64 STBY rising edge to CONVST x rising edge; power-up time from standby mode tCONV 3.45 7.87 16.05 33 66 133 257 tRESET tOS_SETUP tOS_HOLD t1 t2 t3 t4 t5 2 t6 t7 PARALLEL/BYTE READ OPERATION t8 t9 t10 50 20 20 25 ns ns ns ns ns ns ns ms ns ns 0 0 ns ns 40 25 25 0 0.5 25 10F9F t11 t12 4 E A STBY rising edge to CONVST x rising edge; power-up time from shutdown mode STBY rising edge to CONVST x rising edge; power-up time from shutdown mode RESET high pulse width BUSY to OS x pin setup time BUSY to OS x pin hold time CONVST x high to BUSY high Minimum CONVST x low pulse Minimum CONVST x high pulse BUSY falling edge to CS falling edge setup time Maximum delay allowed between CONVST A, CONVST B rising edges Maximum time between last CS rising edge and BUSY falling edge Minimum delay between RESET low to CONVST x high E A A E A A E A A E A A CS to RD setup time CS to RD hold time RD low pulse width VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V RD high pulse width CS high pulse width (see Figure 5); CS and RD linked E E A A A A E E A A A A E A A 16 21 25 32 15 22 ns ns ns ns ns ns E A A E A E A Rev. A | Page 6 of 32 A E A A A Data Sheet Parameter t13 AD7608 Limit at TMIN, TMAX Min Typ Max Unit E ns ns ns ns t143 E A A 16 21 25 32 22 ns ns ns ns ns ns ns 23.5 17 14.5 11.5 MHz MHz MHz MHz 6 6 E A t18 A E A A E A A SERIAL READ OPERATION fSCLK Frequency of serial read clock VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Delay from CS until DOUTA/DOUTB three-state disabled/delay from CS until MSB valid VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE = 2.3 V to 2.7 V Data access time after SCLK rising edge VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V SCLK low pulse width SCLK high pulse width SCLK rising edge to DOUTA/DOUTB valid hold time CS rising edge to DOUTA/DOUTB three-state enabled E E A A 15 20 30 ns ns ns 17 23 27 34 ns ns ns ns ns ns 22 ns t19 3 1F t20 t21 t22 t23 A A 16 20 25 30 t15 t16 t17 Description Delay from CS until DB[15:0] three-state disabled VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Data access time after RD falling edge VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Data hold time after RD falling edge CS to DB[15:0] hold time Delay from CS rising edge to DB[15:0] three-state enabled 0.4 tSCLK 0.4 tSCLK 7 FRSTDATA OPERATION t24 A E A A Delay from CS falling edge until FRSTDATA three-state disabled VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Delay from CS falling edge until FRSTDATA high, serial mode VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Delay from RD falling edge to FRSTDATA high VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V E A A 15 20 25 30 t25 15 20 25 30 ns ns ns ns ns ns ns ns ns t26 E A A E A 16 20 25 30 ns ns ns ns Rev. A | Page 7 of 32 A A AD7608 Data Sheet Limit at TMIN, TMAX Min Typ Max Parameter t27 Unit Description Delay from RD falling edge to FRSTDATA low VDRIVE = 3.3 V to 5.25 V VDRIVE = 2.3 V to 2.7 V Delay from 16th SCLK falling edge to FRSTDATA low VDRIVE = 3.3 V to 5.25 V VDRIVE = 2.3 V to 2.7 V Delay from CS rising edge until FRSTDATA three-state enabled E A A 19 24 ns ns 17 22 24 ns ns ns t28 t29 E A A Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <40 LSB performance matching between channel sets. 3 A buffer is used on the data output pins for these measurements, which is equivalent to a load of 20 pF on the output pins. 1 2 Timing Diagrams t5 CONVST A/ CONVST B tCYCLE CONVST A/ CONVST B t2 t3 tCONV t1 BUSY t4 CS t7 08938-002 tRESET RESET Figure 2.CONVST x Timing--Reading After a Conversion t5 CONVST A/ CONVST B tCYCLE CONVST A/ CONVST B t2 t3 tCONV t1 BUSY t6 CS t7 08938-003 tRESET RESET Figure 3. CONVST x Timing--Reading During a Conversion CS t8 t16 t13 t14 DATA: DB[15:0] FRSTDATA V1 [17:2] INVALID t24 t26 V1 [1:0] t17 t15 V2 [17:2] V2 [1:0] V8 [17:2] t27 V8 [1:0] t29 Figure 4. Parallel Mode Separate CS and RD Pulses E A Rev. A | Page 8 of 32 E A A A 08938-004 RD t9 t11 t10 Data Sheet AD7608 t12 CS, RD t16 t13 V1 [17:2] V1 [1:0] V2 [17:2] V2 [1:0] V7 [17:2] V7 [1:0] V8 [17:2] t17 V8 [1:0] 08938-005 DATA: DB[15:0] FRSTDATA Figure 5. CS and RD Linked Parallel Mode E A E A A A CS t21 SCLK t19 t18 DOUTA, DOUTB t20 DB17 t22 DB16 DB15 t25 DB1 t23 DB0 t29 08938-006 t28 FRSTDATA Figure 6. Serial Read Operation (Channel 1) Rev. A | Page 9 of 32 AD7608 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Table 4. Parameter AVCC to AGND VDRIVE to AGND Analog Input Voltage to AGND1 Digital Input Voltage to AGND Digital Output Voltage to AGND REFIN to AGND Input Current to Any Pin Except Supplies1 Operating Temperature Range B Version Storage Temperature Range Junction Temperature Pb/SN Temperature, Soldering Reflow (10 sec to 30 sec) Pb-Free Temperature, Soldering Reflow ESD (All Pins Except Analog Inputs) ESD (Analog Input Pins Only) 1 Rating -0.3 V to +7 V -0.3 V to AVCC + 0.3 V 16.5 V -0.3 V to VDRIVE + 0.3 V -0.3 V to VDRIVE + 0.3 V -0.3 V to AVCC + 0.3 V 10 mA -40C to +85C -65C to +150C 150C 240 (+0)C 260 (+0)C 2 kV 7 kV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. These specifications apply to a 4-layer board. Table 5. Thermal Resistance Package Type 64-Lead LQFP ESD CAUTION Transient currents of up to 100 mA do not cause SCR latch-up. Rev. A | Page 10 of 32 JA 45 JC 11 Unit C /W Data Sheet AD7608 64 63 62 61 60 59 58 V1GND V1 V2 V3 V2GND V4 V3GND V5 V4GND V6 V5GND V6GND V7 V7GND V8 V8GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 57 56 55 54 53 52 51 50 49 48 AVCC AVCC 1 ANALOG INPUT PIN 1 AGND 2 OS 0 3 DECOUPLING CAPACITOR PIN 47 AGND 46 REFGND POWER SUPPLY OS 1 4 45 REFCAPB GROUND PIN OS 2 5 44 REFCAPA PAR/SER SEL 6 DATA OUTPUT REFERENCE INPUT/OUTPUT 42 REFIN/REFOUT TOP VIEW (Not to Scale) RANGE 8 DIGITAL INPUT 43 REFGND AD7608 STBY 7 DIGITAL OUTPUT 41 AGND CONVST A 9 40 AGND CONVST B 10 39 REGCAP RESET 11 38 AVCC RD/SCLK 12 37 AVCC 36 REGCAP CS 13 BUSY 14 35 AGND FRSTDATA 15 DB0 16 34 REF SELECT 33 DB15 08938-007 DB14 DB13 DB12 DB11 DB10 DB9 AGND DB7/DOUTA DB8/DOUTB VDRIVE DB6 DB5 DB4 DB3 DB2 DB1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 7. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1, 37, 38, 48 Type 1 P Mnemonic AVCC 2, 26, 35, 40, 41, 47 P AGND 5, 4, 3 DI OS [2: 0] 6 DI 12F1F PAR/SER SEL E A A Description Analog Supply Voltage 4.75 V to 5.25 V. This supply voltage is applied to the internal front-end amplifiers and to the ADC core. These supply pins should be decoupled to AGND. Analog Ground. This pin is the ground reference point for all analog circuitry on the AD7608. All analog input signals and external reference signals should be referred to these pins. All six of these AGND pins should connect to the AGND plane of a system. Oversampling Mode Pins. Logic inputs. These inputs are used to select the oversampling ratio. OS 2 is the MSB control bit, while OS 0 is the LSB control bit. See the Digital Filter section for further details on the oversampling mode of operation and Table 8 for oversampling bit decoding. Parallel/Serial Interface Selection Input. Logic input. If this pin is tied to a logic low, the parallel interface is selected. If this pin is tied to a logic high, the serial interface is selected. In serial mode, the RD/SCLK pin functions as the serial clock input. The DB7/DOUTA and DB8/DOUTB pins function as serial data outputs. When the serial interface is selected, DB[15:9] and DB[6:0] pins should be tied to GND. Standby Mode Input. This pin is used to place the AD7608 into one of two power-down modes: standby mode or shutdown mode. The power-down mode entered depends on the state of the RANGE pin as shown in Table 7. When in standby mode, all circuitry, except the on-chip reference regulators, and regulator buffers, is powered down. When in shutdown mode, all circuitry is powered down. Analog Input Range Selection. Logic input. The polarity on this pin determines the input range of the analog input channels. If this pin is tied to a logic high, the analog input range is 10 V for all channels. If this pin is tied to a logic low, the analog input range is 5 V for all channels. A logic change on this pin has an immediate effect on the analog input range. Changing this pin during a conversion is not recommended. See the Analog Input section for more details. Conversion Start Input A, Conversion Start Input B. Logic inputs. These logic inputs are used to initiate conversions on the analog input channels. For simultaneous sampling of all input channels, CONVST A and CONVST B can be shorted together and a single convert start signal applied. Alternatively, CONVST A can be used to initiate simultaneous sampling for V1, V2, V3, and V4, and CONVST B can be used to initiate simultaneous sampling on the other analog inputs (V5, V6, V7, and V8). This is only possible when oversampling is not switched on. When the CONVST A or CONVST B pin transitions from low to high, the front-end track-and-hold circuitry for their respective analog inputs is set to hold. This function allows a phase delay to be created inherently between the sets of analog inputs. E A 7 DI 8 DI RANGE 9, 10 DI CONVST A, CONVST B STBY E A A Rev. A | Page 11 of 32 AD7608 Data Sheet Pin No. 11 Type 1 DI 12 DI 12F1F Mnemonic RESET RD/SCLK E A A Description Reset Input. When set to logic high, the rising edge of RESET resets the AD7608. Once tWAKE-UP has elapsed, the part should receive a RESET pulse after power up. The RESET high pulse should be typically 100 ns wide. If a RESET pulse is applied during a conversion, the conversion is aborted. If a RESET pulse is applied during a read, the contents of the output registers resets to all zeros. Parallel Data Read Control Input when Parallel Interface is Selected (RD)/Serial Clock Input when the Serial Interface is Selected (SCLK). When both CS and RD are logic low in parallel mode, the output bus is enabled. In parallel mode, two RD pulses are required to read the full 18 bits of conversion results from each channel. The first RD pulse outputs DB[17:2], the second RD pulse outputs DB[1:0]. In serial mode, this pin acts as the serial clock input for data transfers. The CS falling edge takes the data output lines, DOUTA and DOUTB, out of three-state and clocks out the MSB of the conversion result. The rising edge of SCLK clocks all subsequent data bits onto the DOUTA and DOUTB serial data outputs. For further information, see the Conversion Control section. Chip Select. This active low logic input frames the data transfer. When both CS and RD are logic low in parallel mode, the output bus, DB[15:0], is enabled and the conversion result is output on the parallel data bus lines. In serial mode, the CS is used to frame the serial read transfer and clock out the MSB of the serial output data. Busy Output. This pin transitions to a logic high after both CONVST A and CONVST B rising edges and indicates that the conversion process has started. The BUSY output remains high until the conversion process for all channels is complete. The falling edge of BUSY signals that the conversion data is being latched into the output data registers and is available to be read after a Time t4. Any data read while BUSY is high must be complete before the falling edge of BUSY occurs. Rising edges on CONVST A or CONVST B have no effect while the BUSY signal is high. Digital Output. The FRSTDATA output signal indicates when the first channel, V1, is being read back on either the parallel or serial interface. When the CS input is high, the FRSTDATA output pin is in three-state. The falling edge of CS takes FRSTDATA out of three-state. In parallel mode, the falling edge of RD corresponding to the result of V1 then sets the FRSTDATA pin high indicating that the result from V1 is available on the output data bus. The FRSTDATA output returns to a logic low following the third falling edge of RD. In serial mode, FRSTDATA goes high on the falling edge of CS as this clocks out the MSB of V1 on DOUTA. It returns low on the 18th SCLK falling edge after the CS falling edge. See the Conversion Control section for more details. Parallel Output Data Bits, DB6 to DB0. When PAR/SER SEL = 0, these pins act as three-state parallel digital output pins. When CS and RD are low, these pins are used to output DB8 to DB2 of the conversion result during the first RD pulse and output 0 during the second RD pulse. When PAR/SER SEL = 1, these pins should be tied to GND. Logic Power Supply Input. The voltage (2.3 V to 5.25 V) supplied at this pin determines the operating voltage of the interface. This pin is nominally at the same supply as the supply of the host interface (that is, DSP and FPGA). Parallel Output Data Bit 7 (DB7)/Serial Interface Data Output Pin (DOUTA). When PAR/SER SEL = 0, this pin acts as a three-state parallel digital output pin. When CS and RD are low, this pin is used to output DB9 of the conversion result. When PAR/SER SEL = 1, this pin functions as DOUTA and outputs serial conversion data. See the Conversion Control section for further details. Parallel Output Data Bit 8 (DB8)/Serial Interface Data Output Pin (DOUTB). When PAR/SER SEL = 0, this pin acts as a three-state parallel digital output pin. When CS and RD are low, this pin is used to output DB10 of the conversion result. When PAR/SER SEL = 1, this pin functions as DOUTB and outputs serial conversion data. See the Conversion Control section for further details. Parallel Output Data Bits, DB13 to DB9. When PAR/SER SEL = 0, these pins act as three-state parallel digital output pins. When CS and RD are low, these pins are used to output DB15 to DB11 of the conversion result during the first RD pulse and output zero during the second RD pulse. When PAR/SER SEL = 1, these pins should be tied to GND. Parallel Output Data Bit 14 (DB14). When PAR/SER SEL = 0, this pin act as three-state parallel digital output pin. When CS and RD are low, this pin is used to output DB16 of the conversion result during the first RD pulse and DB0 of the same conversion result during the second RD pulse. When PAR/SER SEL = 1, this pins should be tied to GND. Parallel Output Data Bit 15 (DB15). When PAR/SER SEL = 0, this pin acts as three-state parallel digital output pin. This pin is used to output DB17 of the conversion result during the first RD pulse and DB1 of the same conversion result during the second RD pulse. When PAR/SER SEL = 1, this pins should be tied to GND. E A A E E A A A A E A A E E A A A A E A A 13 DI CS E A E A E A A A E A A 14 DO BUSY 15 DO FRSTDATA E A A E A A E A A E E A A A A E A A 22 to 16 DO DB[6:0] E A A E E A A A A E E A A 23 P VDRIVE 24 DO DB7/DOUTA A E A A A E A A E E A A A A E A A 25 DO DB8/DOUTB E A A E A A E A A E A A 31 to 27 DO DB[13:9] E A E A E A A A A E A E A A A E A 32 DO/DI DB14 A E A A E A A E A A E A 33 DO/DI DB15 E A E A A A E A A E A E A Rev. A | Page 12 of 32 E A A A A A Data Sheet AD7608 Pin No. 34 Type 1 DI Mnemonic REF SELECT 36, 39 P REGCAP 42 REF REFIN/ REFOUT 43, 46 44, 45 REF REF 49, 51, 53, 55, 57, 59, 61, 63 50, 52, 54, 56, 58, 60, 62, 64 AI REFGND REFCAPA, REFCAPB V1 to V8 AI/ GND V1GND to V8GND 1 12F1F Description Internal/External Reference Selection Input. Logic input. If this pin is set to logic high then the internal reference is selected and is enabled, if this pin is set to logic low then the internal reference is disabled and an external reference voltage must be applied to the REFIN/REFOUT pin. Decoupling Capacitor Pins for Voltage Output from Internal Regulator. These output pins should be decoupled separately to AGND using a 1 F capacitor. The voltage on these output pins is in the range of 2.5 V to 2.7 V. Reference Input/Reference Output. The on-chip reference of 2.5 V is available on this pin for external use if the REF SELECT pin is set to a logic high. Alternatively, the internal reference can be disabled by setting the REF SELECT pin to a logic low and an external reference of 2.5 V can be applied to this input. See the Internal/External Reference section. Decoupling is required on this pin for both the internal or external reference options. A 10 F capacitor should be applied from this pin to ground close to the REFGND pins. Reference Ground Pins. These pins should be connected to AGND. Reference Buffer Output Force/Sense Pins. These pins must be connected together and decoupled to AGND using a low ESR 10 F ceramic capacitor. Analog Inputs. These pins are single-ended analog inputs. The analog input range of these channels is determined by the RANGE pin. Analog Input Ground Pins. These pins correspond to the V1 to V8 analog input pins. Connect all analog input AGND pins to the AGND plane of a system. Refers to classification of pin type; P denotes power, AI denotes analog input, REF denotes reference, DI denotes digital input, DO denotes digital output. Rev. A | Page 13 of 32 AD7608 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 4.0 3.5 AVCC, VDRIVE = 5V INTERNAL REFERENCE fSAMPLE = 200 kSPS TA = 25C 10V RANGE SNR = 91.23dB SINAD = 91.17dB THD = 108.69dB 16384 POINT FFT fIN = 1kHz 60k 70k 80k 90k 100k Figure 12. Typical DNL, 10 V Range -80 -100 -2.0 -2.5 -3.0 -140 -3.5 -4.0 AVCC, VDRIVE = 5V INTERNAL REFERENCE fSAMPLE = 200 kSPS TA = 25C 5V RANGE 0 -120 -160 0 1k 2k 3k 4k 5k INPUT FREQUENCY (Hz) 6k 08938-109 AMPLITUDE (dB) -60 INL (LSB) AVCC, VDRIVE = 5V INTERNAL REFERENCE fSAMPLE = 12.5 kSPS TA = 25C 10V RANGE SNR = 100.26dB SINAD = 100.15dB THD = -115.21dB 16384 POINT FFT fIN = 131Hz 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 Figure 10. FFT Over Sampling by 16, 10 V Range 25,000 0 -40 08938-010 CODE Figure 9. FFT Plot, 5 V Range -20 08938-011 50k INPUT FREQUENCY (Hz) CODE Figure 13. Typical INL, 5 V Range Rev. A | Page 14 of 32 08938-012 40k 250,000 30k 250,000 20k 225,000 10k 200,000 0 250,000 262,144 -160 08938-009 0 -140 200,000 -120 AVCC, VDRIVE = 5V INTERNAL REFERENCE fSAMPLE = 200 kSPS TA = 25C 10V RANGE 175,000 -100 175,000 -80 150,000 AMPLITUDE (dB) -60 DNL (LSB) AVCC, VDRIVE = 5V INTERNAL REFERENCE fSAMPLE = 200 kSPS TA = 25C 5V RANGE SNR = 90.46dB SINAD = 90.43dB THD = 110.74dB 16384 POINT FFT fIN = 1kHz 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1.0 25,000 0 -40 225,000 CODE Figure 11. Typical INL, 10 V Range Figure 8. FFT Plot, 10 V Range -20 225,000 100k 200,000 90k 175,000 80k 150,000 70k 125,000 60k 125,000 50k 100,000 40k INPUT FREQUENCY (Hz) 100,000 30k 75,000 20k 75,000 10k 150,000 0 0 08938-008 -160 125,000 -3.5 -4.0 100,000 -140 75,000 -120 -2.0 -2.5 -3.0 -100 50,000 -1.0 -1.5 50,000 -80 0 -0.5 50,000 SNR (dB) -60 1.0 0.5 25,000 -40 2.0 1.5 INL (LSB) -20 AVCC, VDRIVE = 5V INTERNAL REFERENCE fSAMPLE = 200 kSPS TA = 25C 10V RANGE 3.0 2.5 0 AD7608 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1.0 40 AVCC, VDRIVE = 5V INTERNAL REFERENCE fSAMPLE = 200 kSPS TA = 25C 5V RANGE PFS ERROR 24 16 NFS ERROR 8 0 -8 -16 -24 10V RANGE AVCC, VDRIVE = 5V EXTERNAL REFERENCE 08938-013 250,000 262,144 225,000 200,000 175,000 150,000 125,000 100,000 75,000 50,000 25,000 -32 -40 -40 -25 -10 35 50 65 80 10 80 60 8 PFS/NFS ERROR (%FS) 10V RANGE 20 5V RANGE 0 -20 6 4 AVCC, VDRIVE = 5V fSAMPLE = 200 kSPS TA = 25C EXTERNAL REFERENCE SOURCE RESISTANCE IS MATCHED ON THE VxGND INPUT 10V AND 5V RANGE 2 -40 0 200kSPS AVCC, VDRIVE = 5V EXTERNAL REFERENCE -25 -10 5 20 35 50 65 80 TEMPERATURE (C) -2 08938-017 -60 0 20k 40k 60k 80k 100k 120k SOURCE RESISTANCE () 08938-019 40 NFS ERROR (LSB) 20 Figure 17. NFS/PFS Error Matching Figure 14. Typical DNL, 5 V Range -80 -40 5 TEMPERATURE (C) CODE 08938-018 NFS/PFS CHANNEL MATCHING (LSB) 32 0 DNL (LSB) Data Sheet Figure 18. PFS/NFS Error vs. Source Resistance Figure 15. NFS Error vs. Temperature 80 105 60 100 0 5V RANGE -20 10V RANGE 95 90 -40 200kSPS AVCC, VDRIVE = 5V EXTERNAL REFERENCE -60 -80 -40 -25 -10 5 20 35 50 TEMPERATURE (C) 65 80 OS x 64 OS x 32 OS x 16 OS x 8 OS x 4 OS x 2 NO OS 85 AVCC, VDRIVE = 5V fSAMPLE CHANGES WITH OS RATE TA = 25C INTERNAL REFERENCE 10V RANGE 80 10 100 1k INPUT FREQUENCY (Hz) Figure 16. PFS Error vs. Temperature 10k 100k 08938-119 SNR (dB) 20 08938-118 PFS ERROR (LSB) 40 Figure 19. SNR vs. Input Frequency for Different Oversampling Rates, 10 V Range Rev. A | Page 15 of 32 AD7608 Data Sheet 105 4.0 90 AVCC, VDRIVE = 5V fSAMPLE CHANGES WITH OS RATE TA = 25C INTERNAL REFERENCE 5V RANGE 1k 10k 0 5V RANGE -0.8 -1.6 10V RANGE -2.4 200kSPS AVCC, VDRIVE = 5V EXTERNAL REFERENCE 100k INPUT FREQUENCY (Hz) -4.0 -40 -25 -10 5 20 35 50 65 80 TEMPERATURE (C) Figure 20. SNR vs. Input Frequency for Different Oversampling Rates, 5 V Range Figure 23. Bipolar Zero Code Error vs. Temperature -40 BIPOLAR ZERO CODE ERROR MATCHING (LSB) 10V RANGE AVCC, VDRIVE = 5V -50 f SAMPLE = 200kSPS RSOURCE MATCHED ON Vx AND VxGND INPUTS -60 -80 105k 48.7k 23.7k 10k 5k 1.2k 100 51 0 -90 -100 -110 -120 1k 10k 100k INPUT FREQUENCY (Hz) 08938-021 THD (dB) -70 CHANNEL-TO-CHANNEL ISOLATION (dB) -60 -80 105k 48.7k 23.7k 10k 5k 1.2k 100 51 0 10k INPUT FREQUENCY (Hz) 100k 08938-122 THD (dB) -70 -120 1k 4 10V RANGE 0 -4 -8 200kSPS AVCC, VDRIVE = 5V EXTERNAL REFERENCE -12 -16 -40 -25 -10 5 20 35 50 65 80 -50 5V RANGE AVCC, VDRIVE = 5V -50 f SAMPLE = 200kSPS RSOURCE MATCHED ON Vx AND VxGND INPUTS -110 5V RANGE 8 Figure 24. Bipolar Zero Code Error Matching Between Channels -40 -100 12 TEMPERATURE (C) Figure 21. THD vs. Input Frequency for Various Source Impedances, 10 V Range -90 16 08938-024 100 0.8 -3.2 80 10 1.6 Figure 22. THD vs. Input Frequency for Various Source Impedances, 5 V Range Rev. A | Page 16 of 32 AVCC, VDRIVE = 5V INTERNAL REFERENCE AD7608 RECOMMENDED DECOUPLING USED fSAMPLE = 150kSPS -70 T = 25C A INTERFERER ON ALL UNSELECTED CHANNELS -80 -60 -90 10V RANGE -100 5V RANGE -110 -120 -130 -140 0 20 40 60 80 100 120 NOISE FREQUENCY (kHz) Figure 25. Channel-to-Channel Isolation 140 160 08938-025 OS x 64 OS x 32 OS x 16 OS x 8 OS x 4 OS x 2 NO OS 85 08938-120 SNR (dB) 95 2.4 08938-023 BIPOLAR ZERO CODE ERROR (LSB) 3.2 100 Data Sheet AD7608 110 22 20 5V RANGE 95 90 AVCC, VDRIVE = 5V TA = 25 C INTERNAL REFERENCE fSAMPLE SCALES WITH OS RATIO fIN SCALES WITH OS RATIO 85 80 NO OS OS x 2 OS x 4 OS x 8 OS x 16 OS x 32 OS x 64 OVERSAMPLING RATIO 18 16 14 12 AVCC, VDRIVE = 5V 10 TA = 25C INTERNAL REFERENCE fSAMPLE VARIES WITH OS RATE 8 NO OS OS2 OS4 OS8 AVCC = 5.25V AVCC = 5V 2.5000 2.4995 AVCC = 4.75V 2.4990 2.4980 -40 -25 -10 5 20 35 50 65 80 TEMPERATURE (C) 08938-129 2.4985 Figure 27. Reference Output Voltage vs. Temperature for Different Supply Voltages AVCC, VDRIVE = 5V 6 fSAMPLE = 200kSPS 4 2 0 -2 -4 -6 -6 -4 -2 0 2 INPUT VOLTAGE (V) 4 6 8 10 08938-028 +85C +25C -40C -8 120 10V RANGE 110 5V RANGE 100 90 80 AVCC, VDRIVE = 5V INTERNAL REFERENCE AD7608 RECOMMENDED DECOUPLING USED fSAMPLE = 200kSPS TA = 25C 70 60 0 100 200 300 400 500 600 Figure 28. Analog Input Current vs. Input Voltage Across Temperature Rev. A | Page 17 of 32 700 800 AVCC NOISE FREQUENCY (kHz) Figure 30. PSRR 8 -8 130 900 1000 1100 08938-130 POWER SUPPLY REJECTION RATIO (dB) 2.5005 REFOUT VOLTAGE (V) OS64 140 2.5010 INPUT CURRENT (A) OS32 Figure 29. Supply Current vs. Oversampling Rate Figure 26. Dynamic Range vs. Oversampling Ratio -10 -10 OS16 OVERSAMPLING RATIO 08938-027 AVCC SUPPLY CURRENT (mA) 10V RANGE 100 08938-026 DYNAMIC RANGE (dB) 105 AD7608 Data Sheet TERMINOLOGY Integral Nonlinearity The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, at 1/2 LSB below the first code transition; and full scale, at 1/2 LSB above the last code transition. Differential Nonlinearity The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Bipolar Zero Code Error The deviation of the midscale transition (all 1s to all 0s) from the ideal, which is 0 V - 1/2 LSB. Bipolar Zero Code Error Match The absolute difference in bipolar zero code error between any two input channels. Positive Full-Scale Error The deviation of the actual last code transition from the ideal last code transition (10 V - 11/2 LSB (9.99988) and 5 V - 11/2 LSB (4.99994)) after bipolar zero code error is adjusted out. The positive full-scale error includes the contribution from the internal reference buffer. Positive Full-Scale Error Match The absolute difference in positive full-scale error between any two input channels. Negative Full-Scale Error The deviation of the first code transition from the ideal first code transition (-10 V + 1/2 LSB (-9.99996) and -5 V + 1/2 LSB (-4.99998)) after the bipolar zero code error is adjusted out. The negative full-scale error includes the contribution from the internal reference buffer. Negative Full-Scale Error Match The absolute difference in negative full-scale error between any two input channels. Signal-to-(Noise + Distortion) Ratio The measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2, excluding dc). The ratio depends on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB Thus, for an 18-bit converter, the signal-to-(noise + distortion) is 110.12 dB. Total Harmonic Distortion (THD) The ratio of the rms sum of the harmonics to the fundamental. For the AD7608, it is defined as THD (dB) = 20log V2 2 + V3 2 + V4 2 + V5 2 + V6 2 + V7 2 + V8 2 + V9 2 V1 where: V1 is the rms amplitude of the fundamental. V2 to V9 are the rms amplitudes of the second through ninth harmonics. Peak Harmonic or Spurious Noise The ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is determined by a noise peak. Intermodulation Distortion (IMD) With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3. Intermodulation distortion terms are those for which neither m nor n is equal to 0. For example, the second-order terms include (fa + fb) and (fa - fb), and the third-order terms include (2fa + fb), (2fa - fb), (fa + 2fb), and (fa - 2fb). The calculation of the intermodulation distortion is per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels (dB). Power Supply Rejection Ratio (PSRR) Variations in power supply affect the full-scale transition but not the converter's linearity. PSR is the maximum change in fullscale transition point due to a change in power supply voltage from the nominal value. The PSR ratio (PSRR) is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV p-p sine wave applied to the ADC's VDD and VSS supplies of Frequency fS. PSRR (dB) = 10 log (Pf/PfS) where: Pf is equal to the power at Frequency f in the ADC output. PfS is equal to the power at Frequency fS coupled onto the AVCC supply. Channel-to-Channel Isolation Channel-to-channel isolation is a measure of the level of crosstalk between all input channels. It is measured by applying a full-scale sine wave signal, up to 160 kHz, to all unselected input channels and then determining the degree to which the signal attenuates in the selected channel with a 1 kHz sine wave signal applied (see Figure 25). Rev. A | Page 18 of 32 Data Sheet AD7608 THEORY OF OPERATION CONVERTER DETAILS Analog Input Clamp Protection The AD7608 is a data acquisition system that employs a high speed, low power, charge redistribution, successive approximation analog-to-digital converter (ADC) and allows the simultaneous sampling of eight analog input channels. The analog inputs on the AD7608 can accept true bipolar input signals. The RANGE pin is used to select either 10 V or 5 V as the input range. The AD7608 operates from a single 5 V supply. Figure 31 shows the analog input structure of the AD7608. Each AD7608 analog input contains clamp protection circuitry. Despite single 5 V supply operation, this analog input clamp protection allows for an input overvoltage up to 16.5 V. ANALOG INPUT Vx CLAMP VxGND CLAMP 1M SECONDORDER LPF RFB 08938-029 The AD7608 contains input clamp protection, input signal scaling amplifiers, a second-order antialiasing filter, track-andhold amplifiers, an on-chip reference, reference buffers, a high speed ADC, a digital filter, and high speed parallel and serial interfaces. Sampling on the AD7608 is controlled using the CONVST x signals. RFB 1M Figure 31. Analog Input Circuitry Figure 32 shows the voltage vs. current characteristic of the clamp circuit. For input voltages of up to 16.5 V, no current flows in the clamp circuit. For input voltages that are above 16.5 V, the AD7608 clamp circuitry turns on. 30 Analog Input Ranges When in a power-down mode, it is recommended to tie the analog inputs to GND. As per the input clamp protection section, the overvoltage clamp protection is recommended for use in transient overvoltage conditions and should not remain active for extended periods. Stressing the analog inputs outside of the conditions mentioned here may degrade the Bipolar Zero Code error and THD performance of the AD7608. 10 0 -10 -20 -40 -25 -20 -15 -10 -5 0 5 10 15 20 25 SOURCE VOLTAGE (V) 08938-030 AVCC, VDRIVE = 5V TA = 25 C -30 Figure 32. Input Protection Clamp Profile A series resistor should be placed on the analog input channels to limit the current to 10 mA for input voltages above 16.5 V. In an application where there is a series resistance on an analog input channel, Vx, a corresponding resistance is required on the analog input GND channel, VxGND (see Figure 33). If there is no corresponding resistor on the VxGND channel, an offset error occurs on that channel. Analog Input Impedance The analog input impedance of the AD7608 is 1 M. This is a fixed input impedance that does not vary with the AD7608 sampling frequency. This high analog input impedance eliminates the need for a driver amplifier in front of the AD7608, allowing for direct connection to the source or sensor. With the need for a driver amplifier eliminated, bipolar supplies (which are often a source of noise in a system) can be removed from the signal chain. Rev. A | Page 19 of 32 RFB AD7608 ANALOG INPUT SIGNAL R R C Vx VxGND CLAMP CLAMP 1M 1M RFB Figure 33. Input Resistance Matching on the Analog Input 08938-031 During normal operation, the applied analog input voltage should remain within the analog input range selected via the range pin. A RESET pulse must be applied after power-up to ensure the analog input channels are configured for the range selected. 20 INPUT CLAMP CURRENT The AD7608 can handle true bipolar, single-ended input voltages. The logic level on the RANGE pin determines the analog input range of all analog input channels. If this pin is tied to a logic high, the analog input range is 10 V for all channels. If this pin is tied to a logic low, the analog input range is 5 V for all channels. A logic change on the RANGE pin has an immediate effect on the analog input range; how-ever, there is typically a settling time of approximately 80 s, in addition to the normal acquisition time requirement. The recommended practice is to hardwire the RANGE pin according to the desired input range for the system signals. AD7608 Data Sheet Analog Input Antialiasing Filter An analog antialiasing filter (a second-order Butterworth) is also provided on the AD7608. Figure 34 and Figure 35 show the frequency and phase response, respectively, of the analog antialiasing filter. In the 5 V range, the -3 dB frequency is typically 15 kHz. In the 10 V range, the -3 dB frequency is typically 23 kHz. 5 5V RANGE -15 -20 -25 -30 -35 10V RANGE -40 +25 +85 0.1dB 10,303Hz 9619Hz 9326Hz 3dB 24,365Hz 23,389Hz 22,607Hz 5V RANGE -40 +25 +85 0.1dB 5225Hz 5225Hz 4932Hz 3dB 16,162Hz 15,478Hz 14,990Hz -40 100 1k 10k 08938-135 ATTENUATION (dB) -5 -10 10V RANGE AVCC, VDRIVE = 5V fSAMPLE = 200kSPS TA = 25C 100k INPUT FREQUENCY (Hz) Figure 34. Analog Antialiasing Filter Frequency Response 16 ADC TRANSFER FUNCTION 5V RANGE 12 10V RANGE 10 VIN x 131,072 x 10V VIN 5V CODE = x 131,072 x 5V 10V CODE = 8 6 011...111 011...110 2 ADC CODE 4 AVCC, VDRIVE = 5V fSAMPLE = 200kSPS TA = 25C 0 -2 100 1k 10k INPUT FREQUENCY (Hz) 100k 08938-033 PHASE DELAY (s) The conversion clock for the part is internally generated, and the conversion time for all channels is 4 s on the AD7608. The BUSY signal returns low after all eight conversions to indicate the end of the conversion process. On the falling edge of BUSY, the track-and-hold amplifiers return to track mode. New data can be read from the output register via the parallel, parallel byte, or serial interface after BUSY goes low; or, alternatively, data from the previous conversion can be read while BUSY is high. Reading data from the AD7608 while a conversion is in progress has little effect on performance and allows a faster throughput to be achieved. In parallel mode at VDRIVE > 3.3 V, the SNR is reduced by ~1.5 dB when reading during a conversion. The output coding of the AD7608 is twos complement. The designed code transitions occur midway between successive integer LSB values, that is, 1/2 LSB, 3/2 LSB. The LSB size is FSR/262,144 for the AD7608. The ideal transfer characteristic for the AD7608 is shown in Figure 36. 18 14 The end of the conversion process across all eight channels is indicated by the falling edge of BUSY; and it is at this point that the track-and-holds return to track mode, and the acquisition time for the next set of conversions begins. 000...001 000...000 111...111 REF 2.5V REF 2.5V LSB = +FS - (-FS) 218 100...010 100...001 100...000 -FS + 1/2LSB Figure 35. Analog Antialiasing Filter Phase Response 0V - 1LSB +FS - 3/2LSB ANALOG INPUT Track-and-Hold Amplifiers The track-and-hold amplifiers on the AD7608 allow the ADC to accurately acquire an input sine wave of full-scale amplitude to 18-bit resolution. The track-and-hold amplifiers sample their respective inputs simultaneously on the rising edge of CONVST x. The aperture time for track-and-hold (that is, the delay time between the external CONVST x signal and the +FS 10V RANGE +10V 5V RANGE +5V MIDSCALE 0V 0V -FS -10V -5V LSB 76.29V 38.15V 08938-034 0 track-and-hold actually going into hold) is well matched, by design, across all eight track-and-holds on one device and from device to device. This matching allows more than one AD7608 device to be sampled simultaneously in a system. Figure 36. AD7608 Transfer Characteristic The LSB size is dependent on the analog input range selected. Rev. A | Page 20 of 32 Data Sheet AD7608 INTERNAL/EXTERNAL REFERENCE Internal Reference Mode The AD7608 contains an on-chip 2.5 V band gap reference. The REFIN/REFOUT pin allows access to the 2.5 V reference that generates the on-chip 4.5 V reference internally, or it allows an external reference of 2.5 V to be applied to the AD7608. An externally applied reference of 2.5 V is also gained up to 4.5 V, using the internal buffer. This 4.5 V buffered reference is the reference used by the SAR ADC. One AD7608 device, configured to operate in the internal reference mode, can be used to drive the remaining AD7608 devices, which are configured to operate in external reference mode (see Figure 39). The REFIN/REFOUT pin of the AD7608, configured in internal reference mode, should be decoupled using a 10 F ceramic decoupling capacitor. The other AD7608 devices, configured in external reference mode, should use at least a 100 nF decoupling capacitor on their REFIN/REFOUT pins. REFIN/REFOUT SAR 10F REFCAPA 2.5V REF Figure 37. Reference Circuitry The AD7608 contains a reference buffer configured to gain the REF voltage up to ~4.5 V, as shown in Figure 37. The REFCAPA and REFCAPB pins must be shorted together externally, and a ceramic capacitor of 10 F applied to REFGND, to ensure that the reference buffer is in closed-loop operation. The reference voltage available at the REFIN/REFOUT pin is 2.5 V. AD7608 AD7608 AD7608 REF SELECT REF SELECT REF SELECT REFIN/REFOUT REFIN/REFOUT REFIN/REFOUT 100nF 100nF 100nF 08938-037 ADR421 0.1F Figure 38. Single External Reference Driving Multiple AD7608 REFIN Pins External Reference Mode One ADR421 external reference can be used to drive the REFIN/REFOUT pins of all AD7608 devices (see Figure 38). In this configuration, each REFIN/REFOUT pin of the AD7608 should be decoupled with at least a 100 nF decoupling capacitor. VDRIVE AD7608 AD7608 AD7608 REF SELECT REF SELECT REF SELECT REFIN/REFOUT REFIN/REFOUT REFIN/REFOUT + 10F 100nF 100nF Figure 39. Internal Reference Driving Multiple AD7608 REFIN Pins Rev. A | Page 21 of 32 08938-036 When the AD7608 is configured in external reference mode, the REFIN/REFOUT pin is a high input impedance pin. For applications using multiple AD7608 devices, the following configurations are recommended, depending on the application requirements. REFCAPB BUF 08938-035 The REF SELECT pin is a logic input pin that allows the user to select between the internal reference or an external reference. If this pin is set to logic high, the internal reference is selected and enabled. If this pin is set to logic low, the internal reference is disabled and an external reference voltage must be applied to the REFIN/REFOUT pin. The internal reference buffer is always enabled. After a reset, the AD7608 operates in the reference mode selected by the REF SELECT pin. Decoupling is required on the REFIN/REFOUT pin for both the internal and external reference options. A 10 F ceramic capacitor is required on the REFIN/REFOUT pin. AD7608 Data Sheet TYPICAL CONNECTION DIAGRAM The power-down mode is selected through the state of the RANGE pin when the STBY pin is low. Table 7 shows the configurations required to choose the desired power-down mode. When the AD7608 is placed in standby mode, the current consumption is 8 mA maximum and power-up time is approximately 100 s because the capacitor on the REFCAPA and REFCAPB pins must charge up. In standby mode, the on-chip reference and regulators remain powered up, and the amplifiers and ADC core are powered down. E Figure 40 shows the typical connection diagram for the AD7608. There are four AVCC supply pins on the part, and each of the four pins should be decoupled using a 100 nF capacitor at each supply pin and a 10 F capacitor at the supply source. The AD7608 can operate with the internal reference or an externally applied reference. In this configuration, the AD7608 is configured to operate with the internal reference. When using a single AD7608 device on the board, the REFIN/REFOUT pin should be decoupled with a 10 F capacitor. Refer to the Internal/External Reference section when using an application with multiple AD7608 devices. The REFCAPA and REFCAPB pins are shorted together and decoupled with a 10 F ceramic capacitor. A A When the AD7608 is placed in shutdown mode, the current consumption is 11 A maximum and power-up time is approximately 13 ms (external reference mode). In shutdown mode, all circuitry is powered down. When the AD7608 is powered up from shutdown mode, a RESET signal must be applied to the AD7608 after the required power-up time has elapsed. The VDRIVE supply is connected to the same supply as the processor. The VDRIVE voltage controls the voltage value of the output logic signals. For layout, decoupling, and grounding hints, see the Layout Guidelines section. Table 7. Power-Down Mode Selection STBY Power-Down Mode Standby Shutdown After supplies have been applied to the AD7608, apply a RESET signal to the device to ensure it is configured for the correct mode of operation. E A 0 0 POWER-DOWN MODES There are two power-down modes available on the AD7608: standby mode and shutdown mode. The STBY pin controls whether the AD7608 is in normal mode or in one of the two power-down modes. E A ANALOG SUPPLY VOLTAGE 5V1 1F REFIN/REFOUT 100nF 100nF REGCAP2 AVCC VDRIVE REFCAPA 10F DB0 TO DB15 + REFCAPB REFGND EIGHT ANALOG INPUTS V1 TO V8 V1 V1GND V2 V2GND V3 V3GND V4 V4GND V5 V5GND V6 V6GND V7 V7GND V8 V8GND AD7608 CONVST A, B CS RD BUSY RESET OS 2 OS 1 OS 0 REF SELECT PARALLEL INTERFACE OVERSAMPLING VDRIVE PAR/SER SEL RANGE STBY VDRIVE AGND 1DECOUPLING SHOWN ON THE AV CC PIN APPLIES TO EACH AVCC PIN (PIN 1, PIN 37, PIN 38, PIN 48). DECOUPLING CAPACITOR CAN BE SHARED BETWEEN AV CC PIN 37 AND PIN 38. 2DECOUPLING SHOWN ON THE REGCAP PIN APPLIES TO EACH REGCAP PIN (PIN 36, PIN 39). Figure 40. Typical Connection Diagram Rev. A | Page 22 of 32 08938-038 + MICROPROCESSOR/ MICROCONVERTER/ DSP 10F DIGITAL SUPPLY VOLTAGE +2.3V TO +5V RANGE 1 0 Data Sheet AD7608 CONVERSION CONTROL Simultaneously Sampling Two Sets of Channels Simultaneous Sampling on All Analog Input Channels The AD7608 also allows the analog input channels to be sampled simultaneously in two sets. This can be used in powerline protection and measurement systems to compensate for phase differences introduced by PT and CT transformers. In a 50 Hz system, this allows for up to 9 of phase compensation; and in a 60 Hz system, it allows for up to 10 of phase compensation. The AD7608 allows simultaneous sampling of all analog input channels. All channels are sampled simultaneously when both CONVST x pins (CONVST A, CONVST B) are tied together. A single CONVST x signal is used to control both CONVST x inputs. The rising edge of this common CONVST x signal initiates simultaneous sampling on all analog input channels. This is accomplished by pulsing the two CONVST x pins independently and is possible only if oversampling is not in use. CONVST A is used to initiate simultaneous sampling of the first set of channels (V1 to V4) and CONVST B is used to initiate simultaneous sampling on the second set of analog input channels (V5 to V8), as illustrated in Figure 41. On the rising edge of CONVST A, the track-and-hold amplifiers for the first set of channels are placed into hold mode. On the rising edge of CONVST B, the track-and-hold amplifiers for the second set of channels are placed into hold mode. The conversion process begins once both rising edges of CONVST x have occurred; therefore BUSY goes high on the rising edge of the later CONVST x signal. In Table 3, Time t5 indicates the maximum allowable time between CONVST x sampling points. The AD7608 contains an on-chip oscillator that is used to perform the conversions. The conversion time for all ADC channels is tCONV. The BUSY signal indicates to the user when conversions are in progress, so when the rising edge of CONVST x is applied, BUSY goes logic high and transitions low at the end of the entire conversion process. The falling edge of the BUSY signal is used to place all eight track-and-hold amplifiers back into track mode. The falling edge of BUSY also indicates that the new data can now be read from the parallel bus (DB[15:0]), or the DOUTA and DOUTB serial data lines. There is no change to the data read process when using two separate CONVST x signals. Connect all unused analog input channels to AGND. The results for any unused channels are still included in the data read because all channels are always converted. V1 TO V4 TRACK-AND-HOLD ENTER HOLD V5 TO V8 TRACK-AND-HOLD ENTER HOLD CONVST A t5 CONVST B AD7608 CONVERTS ON ALL 8 CHANNELS BUSY tCONV CS, RD V1 V2 V8 08938-039 DATA: DB[15:0] FRSTDATA Figure 41. Simultaneous Sampling on Channel Sets Using Independent CONVST A/CONVST B Signals--Parallel Mode Rev. A | Page 23 of 32 AD7608 Data Sheet DIGITAL INTERFACE The AD7608 provides two interface options: a parallel interface and high speed serial interface. The required interface mode is selected via the PAR/SER SEL pin. The CS signal can be permanently tied low, and the RD signal can be used to access the conversion results as shown in Figure 4. A read operation of new data can take place after the BUSY signal goes low (Figure 2), or alternatively a read operation of data from the previous conversion process can take place while BUSY is high (Figure 3). E E A A The operation of the interface modes is discussed in the following sections. PARALLEL INTERFACE (PAR/SER SEL = 0) A E A A A E A E A A E E A A A E A A A A A The RD pin is used to read data from the output conversion results register. Two RD pulses are required to read the full 18-bit conversion result from each channel. Applying a sequence of 16 RD pulses to the AD7608 RD pin clocks the conversion results out from each channel onto the 16-bit parallel output bus in ascending order. The first RD falling edge after BUSY goes low clocks out DB[17:2] of the V1 result, the next RD falling edge updates the bus with DB[1:0] of V1 result. It takes 16 RD pulses to read the eight 18-bit conversion results from the AD7608. On the AD7608, the 16th falling edge of RD clocks out the DB[1:0] conversion result for Channel V8. When the RD signal is logic low, it enables the data conversion result from each channel to be transferred to the digital host (DSP, FPGA). E Data can be read from the AD7608 via the parallel data bus with standard CS and RD signals. To read the data over the parallel bus, the PAR/SER SEL pin should be tied low. The CS and RD input signals are internally gated to enable the conversion result onto the data bus. The data lines, DB15 to DB0, leave their high impedance state when both CS and RD are logic low. E E A A A A A E A A E E A A A A E A A E A A AD7608 INTERRUPT E BUSY 14 A A E CS 13 RD/SCLK 12 DB[15:0] [33:24] DIGITAL HOST [22:16] 08938-040 A E E E A A A The rising edge of the CS input signal three-states the bus and the falling edge of the CS input signal takes the bus out of the high impedance state. CS is the control signal that enables the data lines, it is the function that allows multiple AD7608 devices to share the same parallel data bus. A E A E A A A E A A A Figure 42. AD7608 interface diagram--One AD7608 Using the Parallel Bus; CS and RD Shorted Together A A When there is only one AD7608 in a system/board and it does not share the parallel bus, data can be read using just one control signal from the digital host. The CS and RD signals can be tied together as shown in Figure 5. In this case, the data bus comes out of three-state on the falling edge of CS/RD. The combined CS and RD signal allows the data to be clocked out of the AD7608 and to be read by the digital host. In this case, CS is used to frame the data transfer of each data channel. In this case, 16 CS pulses are required to read the eight channels of data. E A E A A A E A E A E A A A E A A A E A A A Rev. A | Page 24 of 32 A E Data Sheet AD7608 SERIAL INTERFACE (PAR/SER SEL = 1) The SCLK input signal provides the clock source for the serial read operation. CS goes low to access the data from the AD7608. The falling edge of CS takes the bus out of three-state and clocks out the MSB of the 18-bit conversion result. This MSB is valid on the first falling edge of the SCLK after the CS falling edge. The subsequent 17 data bits are clocked out of the AD7608 on the SCLK rising edge. Data is valid on the SCLK falling edge. Eighteen clock cycles must be provided to the AD7608 to access each conversion result. E To read data back from the AD7608 over the serial interface, the PAR/SER SEL pin should be tied high. The CS and SCLK signals are used to transfer data from the AD7608. The AD7608 has two serial data output pins, DOUTA, and DOUTB. Data can be read back from the AD7608 using one or both of these DOUT lines. For the AD7608, conversion results from Channel V1 to Channel V4 first appear on DOUTA while conversion results from Channel V5 to Channel V8 first appear on DOUTB. E E A A A The CS falling edge takes the data output lines (DOUTA and DOUTB) out of three-state and clocks out the MSB of the conversion result. The rising edge of SCLK clocks all subsequent data bits onto the serial data outputs, DOUTA and DOUTB. The CS input can be held low for the entire serial read, or it can be pulsed to frame each channel read of 18 SCLK cycles. E A A A E A A The FRSTDATA output signal indicates when the first channel, V1, is being read back. When the CS input is high, the FRSTDATA output pin is in three-state. In serial mode, the falling edge of CS takes FRSTDATA out of three-state and sets the FRSTDATA pin high indicating that the result from V1 is available on the DOUTA output data line. The FRSTDATA output returns to a logic low following the 18th SCLK falling edge. If all channels are read on DOUTB, the FRSTDATA output does not go high when V1 is output on the serial data output pin. It only goes high when V1 is available on DOUTA (and this is when V5 is available on DOUTB). E A E A A A Figure 43 shows a read of eight simultaneous conversion results using two DOUT lines on the AD7608. In this case, a 72 SCLK transfer is used to access data from the AD7608 and CS is held low to frame the entire 72 SCLK cycles. Data can also be clocked out using just one DOUT line, in which case DOUTA is recommended to access all conversion data as the channel data is output in ascending order. For the AD7608 to access all eight conversion results on one DOUT line, a total of 144 SCLK cycles are required. These 144 SCLK cycles can be framed by one CS signal or each group of 18 SCLK cycles can be individually framed by the CS signal. The disadvantage of using just one DOUT line is that the throughput rate is reduced if reading after conversion. The unused DOUT line should be left unconnected in serial mode. For the AD7608, if DOUTB is used as a single DOUT line, the channel results will output in the following order: V5, V6, V7, V8, V1, V2, V3, V4; however, the FRSTDATA indicator returns low once V5 is read on DOUTB. E A E A E A A E A A A E A A Figure 6 shows the timing diagram for reading one channel of data, framed by the CS signal, from the AD7608 in serial mode. READING DURING CONVERSION Data can be read from the AD7608 while BUSY is high and conversions are in progress. This has little effect on the performance of the converter and allows a faster throughput rate to be achieved. A parallel or serial read may be performed during conversions and when oversampling may or may not be in use. Figure 3 shows the timing diagram for reading while BUSY is high in parallel or serial mode. Reading during conversions allows the full throughput rate to be achieved when using the serial interface with a VDRIVE of 3.3 V to 5.25 V. Data can be read from the AD7608 at any time other than on the falling edge of BUSY because this is when the output data registers get updated with the new conversion data. Time t6, as outlined in Table 3, should be observed in this condition. E A CS 72 SCLK DOUTA V1 V2 V3 V4 DOUTB V5 V6 V7 V8 Figure 43. AD7608 Serial Interface with two DOUT Lines Rev. A | Page 25 of 32 08938-041 A A AD7608 Data Sheet Figure 44 shows that the conversion time extends as the oversampling rate is increased, and the BUSY signal lengthens for the different oversampling rates. For example, a sampling frequency of 10 kSPS yields a cycle time of 100 s. Figure 44 shows OS x 2 and OS x 4; for a 10 kSPS example, there is adequate cycle time to further increase the oversampling rate and yield greater improvements in SNR performance. In an application where the initial sampling or throughput rate is at 200 kSPS, for example, and oversampling is turned on, the throughput rate must be reduced to accommodate the longer conversion time and to allow for the read. To achieve the fastest throughput rate possible when oversampling is turned on, the read can be performed during the BUSY high time. The falling edge of BUSY is used to update the output data registers with the new conversion data; therefore, the reading of conversion data should not occur on this edge. DIGITAL FILTER The AD7608 contains an optional digital first-order sinc filter that should be used in applications where slower throughput rates are used or where higher signal-to-noise ratio or dynamic range is desirable. The oversampling ratio of the digital filter is controlled using the oversampling pins, OS [2:0] (see Table 8). OS 2 is the MSB control bit, and OS 0 is the LSB control bit. Table 8 provides the oversampling bit decoding to select the different oversample rates. The OS pins are latched on the falling edge of BUSY. This sets the oversampling rate for the next conversion (see Figure 45). In addition to the oversampling function, the output result is decimated to 18-bit resolution. If the OS pins are set to select an OS ratio of 8, the next CONVST x rising edge takes the first sample for each channel, and the remaining seven samples for all channels are taken with an internally generated sampling signal. These samples are then averaged to yield an improvement in SNR performance. Table 8 shows typical SNR performance for both the 10 V and the 5 V range. As Table 8 indicates, there is an improvement in SNR as the OS ratio increases. As the OS ratio increases, the 3 dB frequency is reduced, and the allowed sampling frequency is also reduced. In an application where the required sampling frequency is 10 kSPS, an OS ratio of up to 16 can be used. In this case, the application sees an improvement in SNR, but the input 3 dB bandwidth is limited to ~6 kHz. tCYCLE tCONV CONVST A, CONVST B 19s 9s 4s OS = 0 OS = 2 OS = 4 BUSY t4 t4 t4 CS The CONVST A and CONVST B pins must be tied/driven together when oversampling is turned on. When the oversampling function is turned on, the BUSY high time for the conversion process extends. The actual BUSY high time depends on the oversampling rate selected: the higher the oversampling rate, the longer the BUSY high, or total conversion time (see Table 3). 08938-043 RD DATA: DB[15:0] Figure 44. No Oversampling, Oversampling x 2, and Oversampling x 4 While Using Read After Conversion CONVST A, CONVST B CONVERSION N OVERSAMPLE RATE LATCHED FOR CONVERSION N + 1 CONVERSION N + 1 BUSY tOS_HOLD 08938-042 tOS_SETUP OS x Figure 45. OS Pin Timing Table 8. Oversample Bit Decoding OS [2:0] 000 001 010 011 100 101 110 111 1 OS Ratio No OS 2 4 8 16 32 64 Invalid SNR 5 V Range (dB)1 90.5 92.5 94.45 96.5 99.1 101.7 103 SNR 10 V Range (dB)1 91.2 93.4 95.7 98 100.4 102.8 103.5 3 dB BW 5 V Range (kHz) 15 15 13.7 10.3 6 3 1.5 SNR values taken with a full scale 100 Hz input signal. Rev. A | Page 26 of 32 3 dB BW 10 V Range (kHz) 22 22 18.5 11.9 6 3 1.5 Maximum Throughput CONVST x Frequency (kHz) 200 100 50 25 12.5 6.25 3.125 Data Sheet AD7608 NO OVERSAMPLING 1377 1170 1208 1200 1001 2176 2000 708 1500 1000 648 0 411 400 -2 -1 0 CODE 146 82 66 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 CODE 2 3 4 5 21 5 6 7 0 1 2 2 3 4 8 9 Figure 46. Histogram of Codes--No OS (18 Codes) 2000 OVERSAMPLING BY 2 1759 1800 1600 1524 1397 1400 1200 1065 OVERSAMPLING BY 16 3947 4000 NUMBER OF OCCURENCES 0 -3 44 4500 188 3 78 4 Figure 49. Histogram of Codes--OS x 8 (9 Codes) 328 3 35 457 -4 588 600 1756 3500 3000 2703 2500 2000 1500 1081 1000 385 500 1000 69 902 7 0 -2 800 -1 0 1 2 3 CODE 538 600 498 08938-148 800 2500 500 852 200 NUMBER OF OCCURENCES 3027 1000 08938-044 NUMBER OF OCCURENCES 1400 OVERSAMPLING BY 8 3000 08938-047 1600 3500 NUMBER OF OCCURENCES Figure 46 to Figure 52 illustrates the effect of oversampling on the code spread in a dc histogram plot. As the oversample rate is increased, the spread of codes is reduced. (In Figure 46 to Figure 52, AVCC = VDRIVE = 5 V and the sampling rate was scaled with OS ratio.) Figure 50. Histogram of Codes--OS x 16 (6 Codes) 400 1 57 15 54 -8 -7 -6 -5 -4 -3 -2 -1 0 CODE 1 2 3 4 5 OVERSAMPLING BY 32 9 6 Figure 47. Histogram Of Codes--OS x 2 (14 Codes) 2500 2224 1913 2000 1551 3000 2000 1460 1301 0 -2 684 199 4 40 -5 -4 64 -3 -2 -1 0 CODE 1 2 3 -1 0 CODE 1 2 Figure 51. Histogram of Codes--OS x 32 (5 Codes) 427 500 17 11 4 14 5 Figure 48. Histogram of Codes--OS x 4 (11 Codes) Rev. A | Page 27 of 32 08938-149 1072 1000 0 4000 1000 1500 08938-046 NUMBER OF OCCURENCES OVERSAMPLING BY 4 5403 5000 NUMBER OF OCCURENCES 0 165 08938-045 0 6000 208 200 AD7608 Data Sheet 7000 OVERSAMPLING BY 64 0 6489 AVCC = 5V VDRIVE = 5V TA = 25C 10V RANGE OS BY 4 -10 -20 5000 ATTENUATION (dB) NUMBER OF OCCURENCES 6000 4000 3000 2000 1238 -30 -40 -50 -60 -70 -80 1000 465 1 -20 10M -30 -40 -50 -60 -70 -80 -90 -100 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 55. Digital Filter Response for OS x 8 -30 0 AVCC = 5V VDRIVE = 5V TA = 25C 10V RANGE OS BY 16 -40 -10 -50 -20 -70 -80 10k 100k FREQUENCY (Hz) 1M 10M Figure 53. Digital Filter OS x 2 -30 -40 -50 -60 -70 -80 -90 -100 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 56. Digital Filter Response for OS x 16 Rev. A | Page 28 of 32 10M 08938-154 1k ATTENUATION (dB) -60 -90 100 1M AVCC = 5V VDRIVE = 5V TA = 25C 10V RANGE OS BY 8 -10 AVCC = 5V VDRIVE = 5V TA = 25C 10V RANGE OS BY 2 08938-151 ATTENUATION (dB) 0 ATTENUATION (dB) Figure 53 to Figure 58 show the digital filter frequency profiles for oversampling by 2 to oversampling by 64. The combination of the analog antialiasing filter and the oversampling digital filter can be used to eliminate or reduce the complexity of the design of the filter before the AD7608. The digital filtering combines steep roll-off and linear phase response. -20 100k Figure 54. Digital Filter Response for OS x 4 When the oversampling mode is selected, this has the effect of adding a digital filter function after the ADC. The different oversampling rates and the CONVST x sampling frequency produces different digital filter frequency profiles. -10 10k FREQUENCY (Hz) Figure 52. Histogram of Codes--OS x 64 (3 Codes) 0 1k 08938-153 0 CODE 08938-150 -1 -100 100 08938-152 -90 0 Data Sheet AD7608 0 -20 -20 ATTENUATION (dB) -30 -40 -50 -60 -70 -80 -30 -40 -50 -60 -70 -80 -90 1k 10k 100k 1M FREQUENCY (Hz) 10M Figure 57. Digital Filter Response for OS x 32 -100 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 58. Digital Filter Response for OS x 64 Rev. A | Page 29 of 32 10M 08938-156 -90 -100 100 AVCC = 5V VDRIVE = 5V TA = 25C 10V RANGE OS BY 64 -10 08938-155 ATTENUATION (dB) 0 AVCC = 5V VDRIVE = 5V TA = 25C 10V RANGE OS BY 32 -10 AD7608 Data Sheet LAYOUT GUIDELINES The printed circuit board that houses the AD7608 should be designed so that the analog and digital sections are separated and confined to different areas of the board. If the AD7608 is in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at only one point: a star ground point should be established as close as possible to the AD7608. Good connections should be made to the ground plane. Avoid sharing one connection for multiple ground pins. Individual vias or multiple vias to the ground plane should be used for each ground pin. Avoid running digital lines under the devices because doing so couples noise onto the die. Allow the analog ground plane to run under the AD7608 to avoid noise coupling. Fast switching signals like CONVST A, CONVST B, or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and they should never run near analog signal paths. Avoid crossover of digital and analog signals. Run traces on layers in close proximity on the board at right angles to each other to reduce the effect of feedthrough through the board. 08938-051 Use at least one ground plane. It can be common or split between the digital and analog sections. In the case of the split plane, the digital and analog ground planes should be joined in only one place, preferably as close as possible to the AD7608. Figure 59. Top Layer Decoupling REFIN/REFOUT, REFCAPA, REFCAPB, and REGCAP Pins Good decoupling is also important to lower the supply impedance presented to the AD7608 and to reduce the magnitude of the supply spikes. The decoupling capacitors should be placed close to (ideally right up against) these pins and their corresponding ground pins. Place the decoupling capacitors for the REFIN/ REFOUT pin and the REFCAPA and REFCAPB pins as close as possible to their respective AD7608 pins and where possible they should be placed on the same side of the board as the AD7608 device. Figure 59 shows the recommended decoupling on the top layer of the AD7608 board. Figure 60 shows bottom layer decoupling. Bottom layer decoupling is for the four AVCC pins and the VDRIVE pin. Rev. A | Page 30 of 32 08938-052 The power supply lines to the AVCC and VDRIVE pins on the AD7608 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Where possible, use supply planes. Good connections should be made between the AD7608 supply pins and the power tracks on the board. Use a single via or multiple vias for each supply pin. Figure 60. Bottom Layer Decoupling Data Sheet AD7608 To ensure good device-to-device performance matching, in a system that contains multiple AD7608 devices, a symmetrical layout between the AD7608 devices is important. Figure 61 shows a layout with two devices. The AVCC supply plane runs to the right of both devices. The VDRIVE supply track runs to the left of the two devices. The reference chip is positioned between both the two devices and the reference voltage track runs north to Pin 42 of U1 and south to Pin 42 to U2. A solid ground plane is used. AVCC U2 These symmetrical layout principles can be applied to a system that contains more than two AD7608 devices. The AD7608 devices can be placed in a north-south direction with the reference voltage located midway between the AD7608 devices with the reference track running in the north-south direction similar to Figure 61. 08938-053 U1 Figure 61. Layout for Multiple AD7608 Devices--Top Layer and Supply Plane Layer Rev. A | Page 31 of 32 AD7608 Data Sheet OUTLINE DIMENSIONS 0.75 0.60 0.45 12.20 12.00 SQ 11.80 1.60 MAX 64 49 1 48 PIN 1 10.20 10.00 SQ 9.80 TOP VIEW (PINS DOWN) 0.15 0.05 SEATING PLANE 0.20 0.09 7 3.5 0 16 0.08 COPLANARITY VIEW A 33 32 17 VIEW A 0.50 BSC LEAD PITCH 0.27 0.22 0.17 ROTATED 90 CCW COMPLIANT TO JEDEC STANDARDS MS-026-BCD 051706-A 1.45 1.40 1.35 Figure 62. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD7608BSTZ AD7608BSTZ-RL EVAL-AD7608EDZ CED1Z 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C Package Description 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] Evaluation Board for the AD7608 Converter Evaluation Development Z = RoHS Compliant Part. (c)2011-2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08938-0-1/12(A) Rev. A | Page 32 of 32 Package Option ST-64-2 ST-64-2