Document number: MM908E626
Rev. 10.0, 8/2012
Freescale Semiconductor
Technical Data
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2005-2012. All rights reserved.
Integrated Stepper Motor Driver
with Embedded MCU and LIN
Serial Communication
The 908E626 is an integrated single package solution that includes
a high performance HC08 microcontroller with a SMARTMOS analog
control IC. The HC08 includes flash memory, a timer, enhanced serial
communications interface (ESCI), an analog-to-digital converter
(ADC), internal serial peripheral interface (SPI), and an internal clock
generator (ICG) module. The analog control die provides fully
protected H-Bridge outputs, voltage regulator, autonomous watchdog,
and local interconnect network (LIN) physical layer.
The single package solution, together with LIN, provides optimal
application performance adjustments and space-saving PCB design. It
is well-suited for the control of automotive stepper applications like
climate control and light-leveling.
Features
• High performance M68HC08EY16 core
•16 KB of on-chip flash memory
•512 B of RAM
• Internal clock generation module
• Two 16-bit, two-channel timers
• 10-bit analog-to-digital converter
• Four low RDS(ON) half-bridge outputs
• 13 microcontroller I/Os
Figure 1. 908E626 Simplified Application Diagram
908E626
STEPPER MOTOR DRIVER
WITH EMBEDDED MCU AND LIN
EK SUFFIX (PB-FREE)
98ARL10519D
54-PIN SOICW-EP
ORDERING INFORMATION
Device
(Add an R2 suffix for Tape
and reel orders)
Temperature
Range (TA)Package
MM908E626AVPEK -40 to 115 °C 54 SOICW EP
MM908E626AVEK
LIN
VREFH
VDDA
EVDD
VDD
VREFL
VSSA
RST A
RST
IRQ A
IRQ
EVSS
VSS
SS
PTB1/AD1
RXD
PTE1/RXD
PTD1/TACH1
FGEN
BEMF
PTD0/TACH0/BEMF
HB1
HB2
HB3
HB4
HVDD
PORTA I/Os
PORTB I/Os
GND[1:2] EP
VSP1:3]
Microcontroller Ports
Switchable Internal VDD Output
PORTC I/Os
Bipolar
N
S
Step
Motor
908E626
Analog Integrated Circuit Device Data
2Freescale Semiconductor
908E626
Figure 2. 908E626 Simplified Internal Block Diagram
IRQ
PTB6/AD6/TBCH0
RST
VREFL
VSSA
EVSS
EVDD
VDDA
VREFH
PTB7/AD7/TBCH1
PTB5/AD5
PTB4/AD4
PTB3/AD3
PTB0/AD0
PTA0/KBD0
PTA1/KBD1
PTA2/KBD2
PTA3/KBD3
PTA4/KBD4
PTC4/OSC1
PTC3/OSC2
PTC2/MCLK
FLSVPP
PTA5/SPSCK
PTC1/MOSI
PTC0/MISO
PTE0/TXD
PTD1/TACH1
PTD0/TACH0
PTB1/AD1
PTE1/RXD
Voltage
Regulator
SPI
&
CONTROL
Reset
Control
Module
Autonomous
Watchdog
LIN Physical
Layer
Analog
Multiplexer
Half Bridge
Driver &
Diagnostic
Switched VDD
Driver &
Diagnostic
VSS
VDD
HVDD
HB1
HB2
HB3
HB4
IRQ_A
RST_A
SS
BEMF
FGEN
VSUP1-3
GND1-2
LIN
ADOUT
TXD
SPSCK
MOSI
MISO
RXD
Chip Temp
VSUP
Prescaler
Interrupt
Control
Module
VSUP
VSUP
VSUP
VSUP
FGEN
SS
BEMF
Analog Die
MCU Die
M68HC08 CPU
ALU
PORT B
DDRB
PTB0/AD0
CPU
Registers
DDRE
PORT E
PTE1/RXD
PTE0/TXD
PTB0/AD0
PTB2/AD2
PTB3/AD3
PTB4/AD4
PTB5/AD5
PTB6/AD6/TBCH0
PTB7/AD7/TBCH1
DDRD
PORT D
PTD1/TACH1
PTD0/TACH0
PORT C
DDRC
PTC4/OSC1
PTC3/OSC2
PTC2/MCLK
PTC1/MOSI
PTC0/MISO
BEMF Module
Prescaler Module
Arbiter Module
Periodic Wake-up
Timebase Module
Configuration
Register Module
Serial Peripheral
Interface Module
Computer Operating
Properly Module
Enhanced Serial
Communication
Interface Module
2-channel Timer
Interface Module B
2-channel Timer
Interface Module A
5-Bit Keyboard
Interrupt Module
Single Breakpoint
Break Module
DDRA
PORT A
PTA0/KBD0
PTA1/KBD1
PTA2/KBD2
PTA3/KBD3
PTA4/KBD4
PTA5/SPSCK
PTA6/SS
Security Module
Power-ON
Reset Module
POWER
VSS
VDD
10 Bit Analog-to-
Digital Converter
Module
VSSA
VREFL
VDDA
VREFH
Single External
IRQ Module
IRQ
24 Integral System
Integration Module
RST
Internal Clock
Generator Module
OSC1
OSC2
User Flash Vector
Space, 36 Bytes
Flash programming
(Burn-in), 1024 Bytes
Monitor ROM, 310 Bytes
User RAM, 512 Bytes
User Flash, 15,872 Bytes
Control and Status
Register, 64 Bytes
Internal Bus
Half Bridge
Driver &
Diagnostic
Half Bridge
Driver &
Diagnostic
Half Bridge
Driver &
Diagnostic
BEMF
BEMF
BEMF
FGEN
FGEN
FGEN
Analog Integrated Circuit Device Data
Freescale Semiconductor 3
908E626
PIN CONNECTIONS
PIN CONNECTIONS
Figure 3. 908E626 Pin Connections
Table 1. 908E626 PIN DEFINITIONS
A functional description of each pin can be found in the Functional Pin Description section beginning on page 15.
Die Pin Pin Name Formal Name Definition
MCU 1
2
6
7
8
11
PTB7/AD7/TBCH1
PTB6/AD6/TBCH0
PTB5/AD5
PTB4/AD4
PTB3/AD3
PTB1/AD1
Port B I/Os These pins are special function, bidirectional I/O port pins that are
shared with other functional modules in the MCU.
MCU 3
4
5
PTC4/OSC1
PTC3/OSC2
PTC2/MCLK
Port C I/Os These pins are special function, bidirectional I/O port pins that are
shared with other functional modules in the MCU.
MCU 9IRQ External Interrupt
Input
This pin is an asynchronous external interrupt input pin.
MCU 10 RST External Reset This pin is bidirectional, allowing a reset of the entire system. It is
driven low when any internal reset source is asserted.
MCU 12
13
PTD0/TACH0/BEMF
PTD1/TACH1
Port D I /Os These pins are special function, bidirectional I /O port pins that are
shared with other functional modules in the MCU.
PTA0/KBD0
PTA1/KBD1
PTA2/KBD2
PTA3/KBD3
PTA4/KBD4
VREFH
VDDA
EVDD
EVSS
VSSA
VREFL
PTE1/RXD
RXD
VSS
NC
VDD
NC
NC
NC
HVDD
NC
HB4
VSUP3
GND2
HB3
NC
FLSVPP
PTB7/AD7/TBCH1
PTB6/AD6/TBCH0
PTC4/OSC1
PTC3/OSC2
PTC2/MCLK
PTB5/AD5
PTB4/AD4
PTB3/AD3
IRQ
RST
PTB1/AD1
PTD0/TACH0/BEMF
PTD1/TACH1
NC
FGEN
BEMF
RST_A
IRQ_A
SS
LIN
NC
NC
HB1
VSUP1
GND1
HB2
VSUP2
1
11
12
13
14
15
16
17
18
19
20
9
10
21
22
23
24
25
26
27
6
7
8
4
5
2
3
54
44
43
42
41
40
39
38
37
36
35
46
45
34
33
32
31
30
29
28
49
48
47
51
50
53
52
Exposed
Pad
Transparent Top
View of Package
Analog Integrated Circuit Device Data
4Freescale Semiconductor
908E626
PIN CONNECTIONS
–14, 21, 22,
28, 33, 35,
36, 37, 39
NC No Connect Not connected.
MCU 42 PTE1/ RXD Port E I /O This pin is a special function, bidirectional I/O port pin that can is
shared with other functional modules in the MCU.
MCU 43
48
VREFL
VREFH
ADC References These pins are the reference voltage pins for the analog-to-digital
converter (ADC).
MCU 44
47
VSSA
VDDA
ADC Supply Pins These pins are the power supply pins for the analog-to-digital
converter.
MCU 45
46
EVSS
EVDD
MCU Power Supply
Pins
These pins are the ground and power supply pins, respectively. The
MCU operates from a single power supply.
MCU 49
50
52
53
54
PTA4/KBD4
PTA3/KBD3
PTA2/KBD2
PTA1/KBD1
PTA0/KBD0
Port A I /Os These pins are special function, bidirectional I/O port pins that are
shared with other functional modules in the MCU.
MCU 51 FLSVPP Test Pin For test purposes only. Do not connect in the application.
Analog 15 FGEN Current Limitation
Frequency Input
This is the input pin for the half-bridge current limitation PWM
frequency.
Analog 16 BEMF Back Electromagnetic
Force Output
This pin gives the user information about back electromagnetic force
(BEMF).
Analog 17 RST_A Internal Reset This pin is the bidirectional reset pin of the analog die.
Analog 18 IRQ_A Internal Interrupt
Output
This pin is the interrupt output pin of the analog die indicating errors
or wake-up events.
Analog 19 SS Slave Select This pin is the SPI slave select pin for the analog chip.
Analog 20 LIN LIN Bus This pin represents the single-wire bus transmitter and receiver.
Analog 23
26
29
32
HB1
HB2
HB3
HB4
Half-bridge Outputs This device includes power MOSFETs configured as four half-bridge
driver outputs. These outputs may be configured for step motor
drivers, DC motor drivers, or as high side and low side switches.
Analog 24
27
31
VSUP1
VSUP2
VSUP3
Power Supply Pins These pins are device power supply pins.
Analog 25
30
GND1
GND2
Power Ground Pins These pins are device power ground connections.
Analog 34 HVDD Switchable VDD
Output
This pin is a switchable VDD output for driving resistive loads
requiring a regulated 5.0 V supply; e.g., 3 pin Hall-effect sensors.
Analog 38 VDD Voltage Regulator
Output
The 5.0 V voltage regulator output pin is intended to supply the
embedded microcontroller.
Analog 40 VSS Voltage Regulator
Ground
Ground pin for the connection of all non-power ground connections
(microcontroller and sensors).
Analog 41 RXD LIN Transceiver
Output
This pin is the output of LIN transceiver.
–EP Exposed Pad Exposed Pad The exposed pad pin on the bottom side of the package conducts
heat from the chip to the PCB board.
Table 1. 908E626 PIN DEFINITIONS
A functional description of each pin can be found in the Functional Pin Description section beginning on page 15.
Die Pin Pin Name Formal Name Definition
Analog Integrated Circuit Device Data
Freescale Semiconductor 5
908E626
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted. Exceeding limits on any pin may cause permanent damage to
the device.
Rating Symbol Value Unit
ELECTRICAL RATINGS
Supply Voltage
Analog Chip Supply Voltage under Normal Operation (Steady-
state)
Analog Chip Supply Voltage under Transient Conditions (1)
Microcontroller Chip Supply Voltage
VSUP(SS)
VSUP(PK)
VDD
- 0.3 to 28
- 0.3 to 40
- 0.3 to 6.0
V
Input Pin Voltage
Analog Chip
Microcontroller Chip
VIN
(ANALOG)
VIN
(MCU)
- 0.3 to 5.5
VSS - 0.3 to VDD + 0.3
V
Maximum Microcontroller Current per Pin
All Pins Except VDD, VSS, PTA0 : PTA6, PTC0 : PTC1
Pins PTA0 : PTA6, PTC0 : PTC1
IPIN(1)
IPIN(2)
±15
± 25
mA
Maximum Microcontroller VSS Output Current IMVSS 100 mA
Maximum Microcontroller VDD Input Current IMVDD 100 mA
LIN Supply Voltage
Normal Operation (Steady-state)
Transient Conditions (1)
VBUS(SS)
VBUS(DYNAMIC)
-18 to 28
40
V
ESD Voltage
Human Body Model (2)
Machine Model (3)
Charge Device Model (4)
VESD1
VESD2
VESD3
± 3000
± 150
± 500
V
Notes
1. Transient capability for pulses with a time of t < 0.5 sec.
2. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP
= 1500 ).
3. ESD2 testing is performed in accordance with the Machine Model (CZAP
= 200 pF, RZAP
= 0 ).
4. ESD3 testing is performed in accordance with Charge Device Model, robotic (CZAP
= 4.0 pF).
Analog Integrated Circuit Device Data
6Freescale Semiconductor
908E626
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
THERMAL RATINGS
Storage Temperature TSTG - 40 to 150 C
Operating Case Temperature (5) TC- 40 to 115 C
Operating Junction Temperature(6) TJ- 40 to 135 C
Peak Package Reflow Temperature During Solder Mounting (7)(8) TPPRT Note 8 C
Notes
5. The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking.
6. The temperature of analog and MCU die is strongly linked via the package, but can differ in dynamic load conditions, usually because
of higher power dissipation on the analog die. The analog die temperature must not exceed 150 °C under these conditions
7. Pin soldering temperature is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
8. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts (i.e. MC33xxxD enter 33xxx), and review parametrics.
Table 2. MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted. Exceeding limits on any pin may cause permanent damage to
the device.
Rating Symbol Value Unit
Analog Integrated Circuit Device Data
Freescale Semiconductor 7
908E626
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. STATIC ELECTRICAL CHARACTERISTICS
All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller
chip. Characteristics noted under conditions 9.0 V VSUP 16 V, -40 C TJ 135 C, unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
SUPPLY VOLTAGE
Nominal Operating Voltage VSUP 8.0 – 18 V
SUPPLY CURRENT
NORMAL Mode
VSUP = 12 V, Power Die ON (PSON = 1), MCU Operating Using
Internal Oscillator at 32 MHz (8.0 MHz Bus Frequency), SPI, ESCI,
ADC Enabled
STOP Mode (9)
VSUP = 12 V, Cyclic Wake-up Disabled
IRUN
ISTOP
–
–
20
–
–
75
mA
A
DIGITAL INTERFACE RATINGS (ANALOG DIE)
Output Pins RST_A, IRQ_A
Low State Output Voltage (IOUT = - 1.5 mA)
High State Output Voltage (IOUT = 1.0 A)
VOL
VOH
–
3.85
–
–
0.4
–
V
Output Pins BEMF, RXD
Low State Output Voltage (IOUT = - 1.5 mA)
High State Output Voltage (IOUT = 1.5 mA)
VOL
VOH
–
3.85
–
–
0.4
–
V
Output Pin RXD – Capacitance (10) CIN –4.0–pF
Input Pins RST_A, FGEN, SS
Input Logic Low Voltage
Input Logic High Voltage
VIL
VIH
–
3.5
–
–
1.5
–
V
Input Pins RST_A, FGEN, SS – Capacitance (10) CIN –4.0–pF
Pins RST_A, IRQ_A – Pull-up Resistor RPULLUP1–10–k
Pin SS – Pull-up Resistor RPULLUP2–60–k
Pins FGEN, MOSI, SPSCK – Pull-down Resistor RPULLDOWN –60–k
Pin TXD – Pull-up Current Source IPULLUP –35–A
Notes
9. STOP mode current will increase if VSUP exceeds 15 V.
10. This parameter is guaranteed by process monitoring but is not production tested.
Analog Integrated Circuit Device Data
8Freescale Semiconductor
908E626
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
SYSTEM RESETS AND INTERRUPTS
High Voltage Reset
Threshold
Hysteresis
VHVRON
VHVRH
27
–
30
1.5
33
–
V
Low Voltage Reset
Threshold
Hysteresis
VLVRON
VLVRH
3.6
–
4.0
100
4.7
–
V
mV
High Voltage Interrupt
Threshold
Hysteresis
VHVION
VHVIH
17.5
–
21
1.0
23
–
V
Low Voltage Interrupt
Threshold
Hysteresis
VLVION
VLVIH
6.5
–
–
0.4
8.0
–
V
High Temperature Reset (12)
Threshold
Hysteresis
TRON
TRH
–
5.0
170
–
–
–
C
High Temperature Interrupt (13)
Threshold
Hysteresis
TION
TIH
–
5.0
160
–
–
–
C
VOLTAGE REGULATOR
Normal Mode Output Voltage
IOUT = 60 mA, 6.0 V < VSUP < 18 V
VDDRUN
4.75 5.0 5.25
V
Load Regulation
IOUT = 80 mA, VSUP = 9.0 V
VLR
– – 100
mV
STOP Mode Output Voltage (Maximum Output Current 100 A)(11) VDDSTOP 4.45 4.7 5.0 V
Notes
11. Tested to be VLVRON < VDDSTOP
12. This parameter is guaranteed by process monitoring but is not production tested.
13. High Temperature Interrupt (HTI) threshold is linked to High Temperature Reset (HTR) threshold (HTR = HTI + 10 C).
Table 3. STATIC ELECTRICAL CHARACTERISTICS (continued)
All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller
chip. Characteristics noted under conditions 9.0 V VSUP 16 V, -40 C TJ 135 C, unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
Analog Integrated Circuit Device Data
Freescale Semiconductor 9
908E626
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
LIN PHYSICAL LAYER
Output Low Level
TXD LOW, 500 Pull-up to VSUP
VLIN-LOW
––1.4
V
Output High Level
TXD HIGH, IOUT = 1.0 A
VLIN-HIGH
VSUP - 1.0 – –
V
Pull-up Resistor to VSUP RSLAVE 20 30 60 k
Leakage Current to GND
Recessive State (- 0.5 V < VLIN < VSUP)
IBUS_PAS_REC
0.0 – 20
A
Leakage Current to GND (VSUP Disconnected)
Including Internal Pull-up Resistor, VLIN @ -18 V
Including Internal Pull-up Resistor, VLIN @ +18 V
IBUS_NO_GND
IBUS
–
–
- 600
25
–
–
A
LIN Receiver
Recessive
Dominant
Threshold
Input Hysteresis
VIH
VIL
VITH
VIHY
0.6VLIN
0
–
0.01VSUP
–
–
VSUP
/ 2
–
VSUP
0.4VLIN
–
0.1VSUP
V
LIN Wake-up Threshold VWTH –V
SUP
/ 2 – V
HALF-BRIDGE OUTPUTS (HB1 : HB4)
Switch ON Resistance @ TJ = 25 C with ILOAD = 1.0 A
High Side
Low Side
RDS(ON)HB_HS
RDS(ON)HB_LS
–
–
425
400
500
500
m
High Side Over-current Shutdown IHBHSOC 3.0 – 7.5 A
Low Side Over-current Shutdown IHBLSOC 2.5 – 7.5 A
Low Side Current Limitation @ TJ = 25 C
Current Limit 1 (CLS2 = 0, CLS1 = 1, CLS0 = 1)
Current Limit 2 (CLS2 = 1, CLS1 = 0, CLS0 = 0)
Current Limit 3 (CLS2 = 1, CLS1 = 0, CLS0 = 1)
Current Limit 4 (CLS2 = 1, CLS1 = 1, CLS0 = 0)
Current Limit 5 (CLS2 = 1, CLS1 = 1, CLS0 = 1)
ICL1
ICL2
ICL3
ICL4
ICL5
–
210
300
450
600
55
260
370
550
740
–
315
440
650
880
mA
Half-bridge Output HIGH Threshold for BEMF Detection VBEMFH –- 300.0V
Half-bridge Output LOW Threshold for BEMF Detection VBEMFL – - 60 - 5.0 mV
Hysteresis for BEMF Detection VBEMFHY –30–mV
Low Side Current-to-Voltage Ratio (VADOUT [V] / IHB [A])
CSA = 1
CSA = 0
RATIOH
RATIOL
7.0
1.0
12.0
2.0
14.0
3.0
V/A
Table 3. STATIC ELECTRICAL CHARACTERISTICS (continued)
All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller
chip. Characteristics noted under conditions 9.0 V VSUP 16 V, -40 C TJ 135 C, unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
Analog Integrated Circuit Device Data
10 Freescale Semiconductor
908E626
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
SWITCHABLE VDD OUTPUT (HVDD)
Over-current Shutdown Threshold IHVDDOCT 24 30 40 mA
VSUP DOWN-SCALER
Voltage Ratio (RATIOVSUP = VSUP / VADOUT)RATIO
VSUP 4.8 5.1 5.35 –
INTERNAL DIE TEMPERATURE SENSOR
Voltage / Temperature Slope STTOV –19–mV/ °C
Output Voltage @ 25 °C VT25 1.7 2.1 2.5 V
Table 3. STATIC ELECTRICAL CHARACTERISTICS (continued)
All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller
chip. Characteristics noted under conditions 9.0 V VSUP 16 V, -40 C TJ 135 C, unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
Analog Integrated Circuit Device Data
Freescale Semiconductor 11
908E626
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
MICROCONTROLLER PARAMETRICS
Table 4. DYNAMIC ELECTRICAL CHARACTERISTICS
All characteristics are for the analog chip only. Please refer to the 68HC908EY16 datasheet for characteristics of the
microcontroller chip. Characteristics noted under conditions 9.0 V VSUP 16 V, -40 C TJ 135 C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
LIN PHYSICAL LAYER
Propagation Delay (14), (15)
TXD LOW to LIN LOW
TXD HIGH to LIN HIGH
LIN LOW to RXD LOW
LIN HIGH to RXD HIGH
TXD Symmetry
RXD Symmetry
t TXD-LIN-LOW
t
TXD-LIN-HIGH
t LIN-RXD-LOW
t LIN-RXD-HIGH
t TXD-SYM
t RXD-SYM
–
–
–
–
- 2.0
- 2.0
–
–
4.0
4.0
–
–
6.0
6.0
8.0
8.0
2.0
2.0
s
Output Falling Edge Slew Rate (14), (16)
80% to 20%
SRF
-1.0 - 2.0 - 3.0
V/s
Output Rising Edge Slew Rate (14), (16)
20% to 80%, RBUS > 1.0 k, CBUS < 10 nF
SRR
1.0 2.0 3.0
V/s
LIN Rise / Fall Slew Rate Symmetry (14), (16) SRS- 2.0 – 2.0 s
AUTONOMOUS WATCHDOG (AWD)
AWD Oscillator Period t
OSC –40–s
AWD Period Low = 512 t
OSC
TJ < 25 °C
TJ 25 °C
t
AWDPH
16
16
27
22
34
28
ms
AWD Period High = 256 t
OSC
TJ < 25 °C
TJ 25 °C
t
AWDPL
8.0
8.0
13.5
11
17
14
ms
AWD Cyclic Wake-up On Time t
AWDHPON –90–s
Notes
14. All LIN characteristics are for initial LIN slew rate selection (20 kbaud) (SRS0 : SRS1= 00).
15. See Figure 4, page 12.
16. See Figure 5, page 13.
Table 5. MICROCONTROLLER
For a detailed microcontroller description, refer to the MC68HC908EY16 datasheet.
Module Description
Core High Performance HC08 Core with a Maximum Internal Bus Frequency of 8.0 MHz
Timer Two 16-Bit Timers with Two Channels (TIM A and TIM B)
Flash 16 k Bytes
RAM 512 Bytes
Analog Integrated Circuit Device Data
12 Freescale Semiconductor
908E626
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
Figure 4. LIN Timing Description
ADC 10 Bit Analog-to-Digital Converter
SPI SPI Module
ESCI Standard Serial Communication Interface (SCI) Module
Bit-Time Measurement
Arbitration
Prescaler with Fine Baud Rate Adjustment
ICG Internal Clock Generation Module
BEMF Counter Special Counter for SMARTMOS BEMF Output
Table 5. MICROCONTROLLER
For a detailed microcontroller description, refer to the MC68HC908EY16 datasheet.
Module Description
Tx
Rx
LIN Recessive State Recessive State
Dominant State
0.9 VSUP
0.4 VSUP
0.6 VSUP
0.1 VSUP
tTx-LIN-low tTx-LIN-high
tLIN-Rx-low tLIN-Rx-high
tTXD-LIN-LOW tTXD-LIN-HIGH
TXD
RXD
0.3 VLIN
TXD
LIN 0.9 VSUP
0.1 VSUP
0.7 VLIN
tLIN-RXD-HIGH
tLIN-RXD-LOW
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ELECTRICAL CHARACTERISTICS
FUNCTIONAL DIAGRAMS
Figure 5. LIN Slew Rate Description
FUNCTIONAL DIAGRAMS
Figure 6. Free Wheel Diode Forward Voltage
SRF =
Dominant State
0.8 VSUP
0.2 VSUP
0.8 VSUP
0.2 VSUP
t Fall-time t Rise-time
V Fall V Rise
V Fall
t Fall-time SRR = V Rise
t Rise-time
0.8 VSUP
0.2 VSUP
0.2 VSUP
0.8 VSUP
Amperes
Volts
Analog Integrated Circuit Device Data
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908E626
ELECTRICAL CHARACTERISTICS
FUNCTIONAL DIAGRAMS
Figure 7. Dropout Voltage on HVDD
0
50
100
150
200
250
0 5 10 15 20 25
ILoad (mA)
Drop Out (mV)
TA = 125°C
T
A
= 25°C
T
A
= -40°C
Dropout (mV)
ILOAD (mA)
5.0
Analog Integrated Circuit Device Data
Freescale Semiconductor 15
908E626
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 908E626 device was designed and developed as a
highly integrated and cost-effective solution for automotive
and industrial applications. For automotive body electronics,
the 908E626 is well suited to perform stepper motor control,
e.g. for climate or light-levelling control via a 3-wire LIN bus.
This device combines an standard HC08 MCU core
(68HC908EY16) with flash memory together with a
SMARTMOS IC chip. The SMARTMOS IC chip combines
power and control in one chip. Power switches are provided
on the SMARTMOS IC configured as four half-bridge
outputs. Other ports are also provided including a selectable
HVDD pin. An internal voltage regulator is provided on the
SMARTMOS IC chip, which provides power to the MCU chip.
Also included in this device is a LIN physical layer, which
communicates using a single wire. This enables the device to
be compatible with 3-wire bus systems, where one wire is
used for communication, one for battery, and the third for
ground.
FUNCTIONAL PIN DESCRIPTION
See Figures 1, for a graphic representation of the various
pins referred to in the following paragraphs. Also, see the pin
diagram on Figures 3 for a depiction of the pin locations on
the package.
PORT A I /O PINS (PTA0:4)
These pins are special function, bidirectional I/O port pins
that are shared with other functional modules in the MCU.
PTA0 : PTA4 are shared with the keyboard interrupt pins,
KBD0 : KBD4.
The PTA5/SPSCK pin is not accessible in this device and
is internally connected to the SPI clock pin of the analog die.
The PTA6/SS pin is likewise not accessible.
For details refer to the 68HC908EY16 datasheet.
PORT B I/O PINS (PTB1, PTB3:7)
These pins are special function, bidirectional I/O port pins
that are shared with other functional modules in the MCU. All
pins are shared with the ADC module. The PTB6 : PTB7 pins
are also shared with the Timer B module.
PTB0/AD0 is internally connected to the ADOUT pin of the
analog die, allowing diagnostic measurements to be
calculated; e.g., current recopy, VSUP, etc. The PTB2/AD2
pin is not accessible in this device.
For details refer to the 68HC908EY16 datasheet.
PORT C I/O PINS (PTC2:4)
These pins are special function, bidirectional I/O port pins
that are shared with other functional modules in the MCU. For
example, PTC2 : PTC4 are shared with the ICG module.
PTC0/MISO and PTC1/MOSI are not accessible in this
device and are internally connected to the MISO and MOSI
SPI pins of the analog die.
For details refer to the 68HC908EY16 datasheet.
PORT D I /O PINS (PTD0:1)
PTD1/ TACH1 and PTD0/ TACH0/BEMF are special
function, bidirectional I /O port pins that can also be
programmed to be timer pins.
In step motor applications, the PTD0 pin should be
connected to the BEMF output of the analog die, to evaluate
the BEMF signal with a special BEMF module of the MCU.
PTD1 pin is recommended for use as an output pin for
generating the FGEN signal (PWM signal), if required by the
application.
PORT E I /O PIN (PTE1)
PTE1/ RXD and PTE0/ TXD are special function,
bidirectional I/O port pins that can also be programmed to be
enhanced serial communication.
PTE0/TXD is internally connected to the TXD pin of the
analog die.The connection for the receiver must be done
externally.
EXTERNAL INTERRUPT PIN (IRQ)
The IRQ pin is an asynchronous external interrupt pin. This
pin contains an internal pull-up resistor that is always
activated, even when the IRQ pin is pulled LOW.
For details refer to the 68HC908EY16 datasheet.
EXTERNAL RESET PIN (RST)
A logic [0] on the RST pin forces the MCU to a known
startup state. RST is bidirectional, allowing a reset of the
entire system. It is driven LOW when any internal reset
source is asserted.
This pin contains an internal pull-up resistor that is always
activated, even when the reset pin is pulled LOW.
For details refer to the 68HC908EY16 datasheet.
Analog Integrated Circuit Device Data
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908E626
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
CURRENT LIMITATION FREQUENCY INPUT PIN
(FGEN)
Input pin for the half-bridge current limitation PWM
frequency. This input is not a real PWM input pin; it should
just supply the period of the PWM. The duty cycle will be
generated automatically.
Important The recommended FGEN frequency should
be in the range of 0.1 kHz to 20 kHz.
BACK ELECTROMAGNETIC FORCE OUTPUT PIN
(BEMF)
This pin gives the user information about back
electromagnetic force (BEMF). This feature allows stall
detection and coil failures in step motor applications. In order
to evaluate this signal the pin must be directly connected to
pin PTD0 / TACH0 / BEMF.
RESET PIN (RST_A)
RST_A is the bidirectional reset pin of the analog die. It is
an open drain with pull-up resistor and must be connected to
the RST pin of the MCU.
INTERRUPT PIN (IRQ_A)
IRQ_A is the interrupt output pin of the analog die
indicating errors or wake-up events. It is an open drain with
pull-up resistor and must be connected to the IRQ pin of the
MCU.
SLAVE SELECT PIN (SS)
This pin is the SPI Slave Select pin for the analog chip. All
other SPI connections are done internally. SS must be
connected to PTB1 or any other logic I /O of the
microcontroller.
LIN BUS PIN (LIN)
The LIN pin represents the single-wire bus transmitter and
receiver. It is suited for automotive bus systems and is based
on the LIN bus specification.
HALF-BRIDGE OUTPUT PINS (HB1: HB4)
The 908E626 device includes power MOSFETs
configured as four half-bridge driver outputs. The HB1: HB4
outputs may be configured for step motor drivers, DC motor
drivers, or as high side and low side switches.
The HB1: HB4 outputs are short-circuit and over-
temperature protected, and they feature current recopy,
current limitation, and BEMF generation. Current limitation
and recopy are done on the low side MOSFETs.
POWER SUPPLY PINS (VSUP1: VSUP3)
VSUP1: VSUP3 are device power supply pins. The
nominal input voltage is designed for operation from 12 V
systems. Owing to the low ON-resistance and current
requirements of the half-bridge driver outputs, multiple VSUP
pins are provided.
All VSUP pins must be connected to get full chip
functionality.
POWER GROUND PINS (GND1 AND GND2)
GND1 and GND2 are device power ground connections.
Owing to the low ON-resistance and current requirements of
the half-bridge driver outputs multiple pins are provided.
GND1 and GND2 pins must be connected to get full chip
functionality.
SWITCHABLE VDD OUTPUT PIN (HVDD)
The HVDD pin is a switchable VDD output for driving
resistive loads requiring a regulated 5.0 V supply; The output
is short-circuit protected.
+ 5.0 V VOLTAGE REGULATOR OUTPUT PIN (VDD)
The VDD pin is needed to place an external capacitor to
stabilize the regulated output voltage. The VDD pin is
intended to supply the embedded microcontroller.
Important The VDD pin should not be used to supply
other loads; use the HVDD pin for this purpose. The VDD,
EVDD, VDDA, and VREFH pins must be connected together.
VOLTAGE REGULATOR GROUND PIN (VSS)
The VSS pin is the ground pin for the connection of all non-
power ground connections (microcontroller and sensors).
Important VSS, EVSS, VSSA, and VREFL pins must be
connected together.
LIN TRANSCEIVER OUTPUT PIN (RXD)
This pin is the output of LIN transceiver. The pin must be
connected to the microcontroller’s Enhanced Serial
Communications Interface (ESCI) module (RXD pin).
ADC REFERENCE PINS (VREFL AND VREFH)
VREFL and VREFH are the reference voltage pins for the
ADC. It is recommended that a high quality ceramic
decoupling capacitor be placed between these pins.
Important VREFH is the high reference supply for the
ADC and should be tied to the same potential as VDDA via
separate traces. VREFL is the low reference supply for the
ADC and should be tied to the same potential as VSS via
separate traces.
For details refer to the 68HC908EY16 datasheet.
ADC SUPPLY PINS (VDDA AND VSSA)
VDDA and VSSA are the power supply pins for the analog-
to-digital converter (ADC). It is recommended that a high
quality ceramic decoupling capacitor be placed between
these pins.
Important VDDA is the supply for the ADC and should be
tied to the same potential as EVDD via separate traces.
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FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
VSSA is the ground pin for the ADC and should be tied to the
same potential as EVSS via separate traces.
For details refer to the 68HC908EY16 datasheet.
MCU POWER SUPPLY PINS (EVDD AND EVSS)
EVDD and EVSS are the power supply and ground pins.
The MCU operates from a single power supply.
Fast signal transitions on MCU pins place high, short-
duration current demands on the power supply. To prevent
noise problems, take special care to provide power supply
bypassing at the MCU.
For details refer to the 68HC908EY16 datasheet.
TEST PIN (FLSVPP)
This pin is for test purposes only. This pin should be either
left open (not connected) or connected to GND.
EXPOSED PAD PIN
The exposed pad pin on the bottom side of the package
conducts heat from the chip to the PCB board. For thermal
performance the pad must be soldered to the PCB board. It
is recommended that the pad be connected to the ground
potential.
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908E626
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
INTERRUPTS
The 908E626 has six different interrupt sources as
described in the following paragraphs. The interrupts can be
disabled or enabled via the SPI. After reset all interrupts are
automatically disabled.
LOW VOLTAGE INTERRUPT
The Low Voltage Interrupt (LVI) is related to the external
supply voltage, VSUP. If this voltage falls below the LVI
threshold, it will set the LVI flag. If the Low Voltage Interrupt
is enabled, an interrupt will be initiated.
With LVI the H-Bridges (high side MOSFET only) are
switched off. All other modules are not influenced by this
interrupt.
During STOP mode the LVI circuitry is disabled.
HIGH VOLTAGE INTERRUPT
The High Voltage Interrupt (HVI) is related to the external
supply voltage, VSUP. If this voltage rises above the HVI
threshold, it will set the HVI flag. If the High Voltage Interrupt
is enabled, an interrupt will be initiated.
With HVI the H-Bridges (high side MOSFET only) are
switched off. All other modules are not influenced by this
interrupt.
During STOP mode the HVI circuitry is disabled.
HIGH TEMPERATURE INTERRUPT
The High Temperature Interrupt (HTI) is generated by the
on-chip temperature sensors. If the chip temperature is
above the HTI threshold, the HTI flag will be set. If the High
Temperature Interrupt is enabled, an interrupt will be
initiated.
During STOP mode the HTI circuitry is disabled.
AUTONOMOUS WATCHDOG INTERRUPT (AWD)
Refer to Autonomous Watchdog (AWD) on page 30.
LIN INTERRUPT
If the LINIE bit is set, a falling edge on the LIN pin will
generate an interrupt. During STOP mode this interrupt will
initiate a system wake-up.
OVER-CURRENT INTERRUPT
If an over-current condition on a half-bridge or the HVDD
output is detected and the OCIE bit is set and an interrupt
generated.
SYSTEM WAKE-UP
System wake-up can be initiated by any of four events:
• A falling edge on the LIN pin
• A wake-up signal from the AWD
• An LVR condition
If one of these wake-up events occurs and the interrupt
mask bit for this event is set, the interrupt will wake-up the
microcontroller as well as the main voltage regulator (MREG)
Figures 8.
Analog Integrated Circuit Device Data
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908E626
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Figure 8. STOP Mode / Wake-up Procedure
INTERRUPT FLAG REGISTER (IFR)
LINF — LIN FLAG BIT
This read / write flag is set on the falling edge at the LIN
data line. Clear LINF by writing a logic [1] to LINF. Reset
clears the LINF bit. Writing a logic [0] to LINF has no effect.
• 1 = Falling edge on LIN data line has occurred.
• 0 = Falling edge on LIN data line has not occurred since
last clear.
HTF — HIGH TEMPERATURE FLAG BIT
This read / write flag is set on a high temperature condition.
Clear HTF by writing a logic [1] to HTF. If a high temperature
condition is still present while writing a logic [1] to HTF, the
writing has no effect. Therefore, a high temperature interrupt
cannot be lost due to inadvertent clearing of HTF. Reset
clears the HTF bit. Writing a logic [0] to HTF has no effect.
• 1 = High temperature condition has occurred.
From Reset
Initialize
Operate
SPI:
GS =1
(MREG off)
STOP
IRQ
Interrupt?
SPI: Reason for
Interrupt
Operate
STOP MREG
Wait for Action
LIN
AWD
Hallport
Assert IRQ_A
Start
MREG
MREG = Main Voltage
Regulator
MCU Die Analog Die
Register Name and Address: IFR - $05
Bit 7 6 5 4 3 2 1 Bit 0
Read 0 0 LINF HTF LVF HVF OCF 0
Write
Reset 00000000
Analog Integrated Circuit Device Data
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908E626
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
• 0 = High temperature condition has not occurred.
LVF — LOW VOLTAGE FLAG BIT
This read / write flag is set on a low voltage condition. Clear
LVF by writing a logic [1] to LVF. If a low voltage condition is
still present while writing a logic [1] to LVF, the writing has no
effect. Therefore, a low voltage interrupt cannot be lost due
to inadvertent clearing of LVF. Reset clears the LVF bit.
Writing a logic [0] to LVF has no effect.
• 1 = Low voltage condition has occurred.
• 0 = Low voltage condition has not occurred.
HVF — HIGH VOLTAGE FLAG BIT
This read / write flag is set on a high voltage condition.
Clear HVF by writing a logic [1] to HVF. If high voltage
condition is still present while writing a logic [1] to HVF, the
writing has no effect. Therefore, a high voltage interrupt
cannot be lost due to inadvertent clearing of HVF. Reset
clears the HVF bit. Writing a logic [0] to HVF has no effect.
• 1 = High voltage condition has occurred.
• 0 = High voltage condition has not occurred.
OCF — OVER-CURRENT FLAG BIT
This read-only flag is set on an over-current condition.
Reset clears the OCF bit. To clear this flag, write a logic [1] to
the appropriate over-current flag in the SYSSTAT Register.
See Figure 9, which shows the two signals triggering the
OCF.
• 1 = High current condition has occurred.
• 0 = High current condition has not occurred.
Figure 9. Principal Implementation for OCF
INTERRUPT MASK REGISTER (IMR)
LINIE — LIN LINE INTERRUPT ENABLE BIT
This read / write bit enables CPU interrupts by the LIN flag,
LINF. Reset clears the LINIE bit.
• 1 = Interrupt requests from LINF flag enabled.
• 0 = Interrupt requests from LINF flag disabled.
HTIE — HIGH TEMPERATURE INTERRUPT
ENABLE BIT
This read / write bit enables CPU interrupts by the high
temperature flag, HTF. Reset clears the HTIE bit.
• 1 = Interrupt requests from HTF flag enabled.
• 0 = Interrupt requests from HTF flag disabled.
LVIE — LOW VOLTAGE INTERRUPT ENABLE BIT
This read / write bit enables CPU interrupts by the low
voltage flag, LVF. Reset clears the LVIE bit.
• 1 = Interrupt requests from LVF flag enabled.
• 0 = Interrupt requests from LVF flag disabled.
HVIE — HIGH VOLTAGE INTERRUPT ENABLE BIT
This read / write bit enables CPU interrupts by the high
voltage flag, HVF. Reset clears the HVIE bit.
• 1 = Interrupt requests from HVF flag enabled.
• 0 = Interrupt requests from HVF flag disabled.
OCIE — OVER-CURRENT INTERRUPT ENABLE BIT
This read / write bit enables CPU interrupts by the over-
current flag, OCF. Reset clears the OCIE bit.
• 1 = Interrupt requests from OCF flag enabled.
• 0 = Interrupt requests from OCF flag disabled.
RESET
The 908E626 chip has four internal reset sources and one
external reset source, as explained in the paragraphs below.
Figure 10 depicts the internal reset sources.
OCF
HVDD_OCF
HB_OCF
Register Name and Address: IMR - $04
Bit 7 6 5 4 3 2 1 Bit 0
Read 0 0 LINIE HTIE LVIE HVIE OCIE
0
Write
Reset 0 0 0 0 0 0 0 0
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FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Figure 10. Internal Reset Routing
RESET INTERNAL SOURCES
Autonomous Watchdog
AWD modules generates a reset because of a timeout
(watchdog function).
High Temperature Reset
To prevent damage to the device, a reset will be initiated if
the temperature rises above a certain value. The reset is
maskable with bit HTRE in the Reset Mask Register. After a
reset the high temperature reset is disabled.
Low Voltage Reset
The LVR is related to the internal VDD. In case the voltage
falls below a certain threshold, it will pull down the RST_A pin.
High Voltage Reset
The HVR is related to the external VSUP voltage. In case
the voltage is above a certain threshold, it will pull down the
RST_A pin. The reset is maskable with bit HVRE in the Reset
Mask Register. After a reset the high voltage reset is
disabled.
RESET EXTERNAL SOURCE
External Reset Pin
The microcontroller has the capability of resetting the
SMARTMOS device by pulling down the RST pin.
Reset Mask Register (RMR)
TTEST — High Temperature Reset Test
This read / write bit is for test purposes only. It decreases
the over-temperature shutdown limit for final test. Reset
clears the HTRE bit.
• 1 = Low temperature threshold enabled.
• 0 = Low temperature threshold disabled.
HVRE — High Voltage Reset Enable Bit
This read / write bit enables resets on high voltage
conditions. Reset clears the HVRE bit.
• 1 = High voltage reset enabled.
• 0 = High voltage reset disabled.
HTRE — High Temperature Reset Enable Bit
This read / write bit enables resets on high temperature
conditions. Reset clears the HTRE bit.
• 1 = High temperature reset enabled.
• 0 = High temperature reset disabled.
HTRE Flag
HVRE Flag
AWDRE Flag
AWD Reset
Sensor
High-Voltage
Reset Sensor
High-Temperature
Reset Sensor
MONO
FLOP
Low-Voltage Reset
VDD
RST_A
SPI REGISTERS
Register Name and Address: RMR - $06
Bit 7 6 5 4 3 2 1 Bit 0
Read TTEST 00000HVRE HTRE
Write
Reset 0 0 0 0 0 0 0 0
Analog Integrated Circuit Device Data
22 Freescale Semiconductor
908E626
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
SERIAL PERIPHERAL INTERFACE
The serial peripheral interface (SPI) creates the
communication link between the microcontroller and the
908E626.
The interface consists of four pins (see Figure 11):
•SS — Slave Select
•MOSI — Master-Out Slave-In
•MISO — Master-In Slave-Out
• SPSCK — Serial Clock (maximum frequency 4.0 MHz)
A complete data transfer via the SPI consists of 2 bytes.
The master sends address and data, slave system status,
and data of the selected address.
Figure 11. SPI Protocol
During the inactive phase of SS, the new data transfer is
prepared. The falling edge on the SS line indicates the start
of a new data transfer and puts MISO in the low-impedance
mode. The first valid data are moved to MISO with the rising
edge of SPSCK.
The MISO output changes data on a rising edge of
SPSCK. The MOSI input is sampled on a falling edge of
SPSCK. The data transfer is only valid if exactly 16 sample
clock edges are present in the active phase of SS.
After a write operation, the transmitted data is latched into
the register by the rising edge of SS. Register read data is
internally latched into the SPI at the time when the parity bit
is transferred. SS HIGH forces MISO to high-impedance.
MASTER ADDRESS BYTE
A4 : A0
Contains the address of the desired register.
R / W
Contains information about a read or a write operation.
•If R/ W = 1, the second byte of master contains no valid
information, slave just transmits back register data.
•If R/ W = 0, the master sends data to be written in the
second byte, slave sends concurrently contents of
selected register prior to write operation, write data is
latched in the SMARTMOS register on rising edge of
SS.
Parity P
The parity bit is equal to “0” if the number of 1 bits is an
even number contained within R/ W, A4 : A0. If the number of
1 bits is odd, P equals “1”. For example, if R/ W = 1, A4 : A0 =
00001, then P equals “0.”
The parity bit is only evaluated during a write operation.
Bit X
Not used.
Master Data Byte
Contains data to be written or no valid data during a read
operation.
S7 S6 S5 S4 S3 S2 S1 S0
R/W A4 A3 A2 A1 A0 P X D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
System Status Register
Read/Write, Address, Parity Data (Register write)
Data (Register read)
Rising edge of SPSCK
Change MISO/MOSI
Output
Falling edge of SPSCK
Sample MISO/MOSI
Input
Slave latch
register address
Slave latch
data
SS
MOSI
MISO
SPSCK
Analog Integrated Circuit Device Data
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FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Slave Status Byte
Contains the contents of the System Status Register ($0c)
independent of whether it is a write or read operation or which
register was selected.
Slave Data Byte
Contains the contents of selected register. During a write
operation it includes the register content prior to a write
operation.
SPI Register Overview
Table 6 summarizes the SPI Register addresses and the
bit names of each register.
ANALOG DIE I / OS
LIN Physical Layer
The LIN bus pin provides a physical layer for single-wire
communication in automotive applications. The LIN physical
layer is designed to meet the LIN physical layer specification.
The LIN driver is a low side MOSFET with internal current
limitation and thermal shutdown. An internal pull-up resistor
with a serial diode structure is integrated, so no external pull-
up components are required for the application in a slave
node. The fall time from dominant to recessive and the rise
time from recessive to dominant is controlled. The symmetry
between both slew rate controls is guaranteed.
The LIN pin offers high susceptibility immunity level from
external disturbance, guaranteeing communication during
external disturbance.
The LIN transmitter circuitry is enabled by setting the
PSON bit in the System Control Register (SYSCTL). If the
transmitter works in the current limitation region, the LINCL
bit in the System Status Register (SYSSTAT) is set. Due to
excessive power dissipation in the transmitter, software is
advised to monitor this bit and turn the transmitter off
immediately.
TXD Pin
The TXD pin is the MCU interface to control the state of the
LIN transmitter (see Figure 2). When TXD is LOW, LIN output
is low (dominant state). When TXD is HIGH, the LIN output
MOSFET is turned off. The TXD pin has an internal pull-up
current source in order to set the LIN bus in recessive state
in the event, for instance, the microcontroller could not control
it during system power-up or power-down.
Table 6. List of Registers
Addr Register Name R/W Bit
76543210
$01 H-bridge Output
(HBOUT)
RHB4_H HB4_L HB3_H HB3_L HB2_H HB2_L HB1_H HB1_L
W
$02 H-bridge Control
(HBCTL)
ROFC_EN CSA 000
CLS2 CLS1 CLS0
W
$03 System Control
(SYSCTL)
R
PSON SRS1 SRS0 00000
WGS
$04 Interrupt Mask
(IMR)
R0 0 LINIE HTIE LVIE HVIE OCIE 0
W
$05 Interrupt Flag
(IFR)
R0 0 LINF HTF LVF HVF OCF 0
W
$06 Reset Mask
(RMR)
RTTEST 00000
HVRE HTRE
W
$07 Analog Multiplexer
Configuration (ADMUX)
R0000
SS3 SS2 SS1 SS0
W
$08 Reserved
R00000
000
W
$09 Reserved R00000000
W
$0a AWD Control
(AWDCTL)
R000
AWDRE AWDIE 0 AWDF AWDR
WAWDRST
$0b Power Output
(POUT)
R0 0 0000HVDDON0
W
$0c System Status
(SYSSTAT)
R0LINCL HVDD_OC
F0LVF HVF HB_OCF HTF
W
Analog Integrated Circuit Device Data
24 Freescale Semiconductor
908E626
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
RXD Pin
The RXD transceiver pin is the MCU interface, which
reports the state of the LIN bus voltage. LIN HIGH (recessive
state) is reported by a high level on RXD, LIN LOW (dominant
state) by a low level on RXD.
STOP Mode/Wake-up Feature
During STOP mode operation the transmitter of the
physical layer is disabled. The receiver pin is still active and
able to detect wake-up events on the LIN bus line.If LIN
interrupt is enabled (LINIE bit in the Interrupt Mask Register
is set), a falling edge on the LIN line causes an interrupt. This
interrupt switches on the main voltage regulator and
generates a system wake-up.
Analog Multiplexer /ADOUT Pin
The ADOUT pin is the analog output interface to the ADC
of the MCU (see Figure 2). An analog multiplexer is used to
read six internal diagnostic analog voltages.
Current Recopy
The analog multiplexer is connected to the four low side
current sense circuits of the half-bridges. These sense
circuits offer a voltage proportional to the current through the
low side MOSFET. High or low resolution is selectable: 5.0 V /
2.5 A or 5.0 V / 500 mA, respectively. (Refer to Half-bridge
Current Recopy on page 27.)
Temperature Sensor
The 908E626 includes an on-chip temperature sensor.
This sensor offers a voltage that is proportional to the actual
chip junction temperature.
VSUP Prescaler
The VSUP prescaler permits the reading or measurement
of the external supply voltage. The output of this voltage is
VSUP / RATIOVSUP.
The different internal diagnostic analog voltages can be
selected with the ADMUX Register.
Analog Multiplexer Configuration Register (ADMUX)
SS3, SS2, SS1, and SS0 — A / D Input Select Bits
These read / write bits select the input to the ADC in the
microcontroller according to Table 7. Reset clears SS3, SS2,
SS1, and SS0 bits.
Power Output Register (POUT)
HVDDON — HVDD On Bit
This read/write bit enables HVDD output. Reset clears the
HVDDON bit.
• 1 = HVDD enabled.
• 0 = HVDD disabled.
Register Name and Address: ADMUX - $07
Bit 7654321Bit 0
Read 0000
SS3 SS2 SS1 SS0
Write
Reset 00000000
Table 7. Analog Multiplexer Configuration Register
SS3 SS2 SS1 SS0 Channel
0000 Current Recopy HB1
0001 Current Recopy HB2
0010 Current Recopy HB3
0011 Current Recopy HB4
0100 V
SUP Prescaler
0101 Temperature Sensor
0110
Not Used
0111
1000
1001
1010
1011
1100
1101
1110
1111
Register Name and Address: POUT - $0b
Bit 7 6 5 4 3 2 1 Bit 0
Read 0 0 0
(17)
0
(17)
0
(17)
0
(17)
HVDD
ON
0
(17)
Write
Reset 00000000
Notes
17. This bit must always be set to 0.
Analog Integrated Circuit Device Data
Freescale Semiconductor 25
908E626
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
HALF-BRIDGES
Outputs HB1 : HB4 provide four low resistive half-bridge
output stages. The half-bridges can be used in H-Bridge, high
side, or low side configurations.
Reset clears all bits in the H-Bridge Output Register
(HBOUT) owing to the fact that all half-bridge outputs are
switched off.
HB1: HB4 output features:
• Short-circuit (over-current) protection on high side and
low side MOSFETs.
• Current recopy feature (low side MOSFET).
• Over-temperature protection.
• Over-voltage and under-voltage protection.
• Current limitation feature (low side MOSFET).
Figure 12. Half-bridge Push-Pull Output Driver
Half-bridge Control
Each output MOSFET can be controlled individually. The
general enable of the circuitry is done by setting PSON in the
System Control Register (SYSCTL). HBx_L and HBx_H form
one half-bridge. It is not possible to switch on both MOSFETs
in one half-bridge at the same time. If both bits are set, the
high side MOSFET has a higher priority.
To avoid both MOSFETs (high side and low side) of one
half-bridge being on at the same time, a break-before-make
circuit exists.Switching the high side MOSFET on is inhibited
as long as the potential between gate and VSS is not below a
certain threshold. Switching the low side MOSFET on is
blocked as long as the potential between gate and source of
the high side MOSFET did not fall below a certain threshold.
Half-bridge Output Register (HBOUT)
HBx_L — Low Side On / Off Bits
These read / write bits turn on the low side MOSFETs.
Reset clears the HBx_L bits.
• 1 = Low side MOSFET turned on for half-bridge output
x.
• 0 = Low side MOSFET turned off for half-bridge output
x.
High Side Driver
Charge Pump,
Over-temperature Protection,
Over-current Protection
Low Side Driver
Current Recopy,
Current Limitation,
Over-current Protection
Control
On/Off
Status
On/Off
Status
Current
Limit
HBx
VSUP
GND
BEMF
Register Name and Address: HBOUT - $01
Bit 7 6 5 4 3 2 1 Bit 0
Read HB4_HHB4_LHB3_HHB3_LHB2_HHB2_LHB1_HHB1_L
Write
Reset 0 0 0 0 0 0 0 0
Analog Integrated Circuit Device Data
26 Freescale Semiconductor
908E626
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
HBx_H — High Side On/Off Bits
These read / write bits turn on the high side MOSFETs.
Reset clears the HBx_H bits.
• 1 = High side MOSFET turned on for half-bridge output
x.
• 0 = High side MOSFET turned on for half-bridge output
x.
HALF-BRIDGE CURRENT LIMITATION
Each low side MOSFET offers a current limit or constant
current feature. This features is realized by a pulse width
modulation on the low side MOSFET. The pulse width
modulation on the outputs is controlled by the FGEN input
and the load characteristics. The FGEN input provides the
PWM frequency, whereas the duty cycle is controlled by the
load characteristics.
The recommended frequency range for the FGEN and the
PWM is 0.1 kHz to 20 kHz.
Functionality
Each low side MOSFET switches off if a current above the
selected current limit was detected. The 908E626 offers five
different current limits (refer to Table 8, for current limit
values). The low side MOSFET switches on again if a rising
edge on the FGEN input was detected (Figure 13).
Figure 13. Half-bridge Current Limitation
Coil Current
Half-bridge
Low Side Output
FGEN Input
(MCU PWM
Signal)
Minimum 50 µs
H-Bridge low side
MOSFET will be switched
off if select current limit is
reached.
H-Bridge low side
MOSFET will be turned on
with each rising edge of
the FGEN input.
t (µs)
t (µs)
t (µs)
Analog Integrated Circuit Device Data
Freescale Semiconductor 27
908E626
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Offset Chopping
If bit OFC_EN in the H-bridge Control Register (HBCTL) is
set, HB1 and HB2 will continue to switch on the low side
MOSFETs with the rising edge of the FGEN signal and HB3
and HB4 will switch on the low side MOSFETs with the falling
edge on the FGEN input. In step motor applications, this
feature allows the reduction of EMI due to a reduction of the
di/dt (Figure 14).
Figure 14. Offset Chopping for Step Motor Control
HALF-BRIDGE CURRENT RECOPY
Each low side MOSFET has an additional sense output to
allow a current recopy feature. This sense source is internally
connected to a shunt resistor. The drop voltage is amplified
and switched to the analog multiplexer.
The factor for the current sense amplification can be
selected via bit CSA in the System Control Register.
• CSA = 1: Low resolution selected (500 mA
measurement range).
• CSA = 0: High resolution selected (2.5 A measurement
range).
HALF-BRIDGE BEMF GENERATION
The BEMF output is set to “1” if a recirculation current is
detected in any half-bridge. This recirculation current flows
via the two freewheeling diodes of the power MOSFETs. The
BEMF circuitry detects that and generates a HIGH on the
BEMF output as long as a recirculation current is detected.
This signal provides a flexible and reliable detection of stall in
step motor applications. For this the BEMF circuitry takes
advantage of the instability of the electrical and mechanical
behavior of a step motor when blocked. In addition the signal
can be used for open load detection (absence of this signal)
(see Figure 15).
Coil2 Current
Coil1 Current
Current in
VSUP Line
FGEN Input
(MCU PWM
Signal) Coil1…..
Coil2…..
HB1
HB2
HB3
HB4
Analog Integrated Circuit Device Data
28 Freescale Semiconductor
908E626
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Figure 15. BEMF Signal Generation
HALF-BRIDGE OVER-TEMPERATURE
PROTECTION
The half-bridge outputs provide an over-temperature
prewarning with the HTF in the Interrupt Flag Register (IFR).
In order to protect the outputs against over-temperature, the
High Temperature Reset must be enabled. If this value is
reached, the part generates a reset and disables all power
outputs.
HALF-BRIDGE OVER-CURRENT PROTECTION
The half-bridges are protected against short to GND, short
to VSUP, and load shorts.
In the event an over-current on the high side is detected,
the high side MOSFETs on all HB high side MOSFETs are
switched off automatically. In the event an over-current on the
low side is detected, all HB low side MOSFETs are switched
off automatically. In both cases, the over-current status flag
HB_OCF in the System Status Register (SYSSTAT) is set.
The over-current status flag is cleared (and the outputs re-
enabled) by writing a logic [1] to the HB_OCF flag in the
System Status Register or by reset.
HALF-BRIDGE OVER-VOLTAGE / UNDER-
VOLTAGE
The half-bridge outputs are protected against under-
voltage and over-voltage conditions. This protection is done
by the low and high voltage interrupt circuitry. If one of these
flags (LVF, HVF) is set, the outputs are automatically
disabled.
The over-voltage / under-voltage status flags are cleared
(and the outputs re-enabled) by writing a logic [1] to the LVF /
HVF flags in the Interrupt Flag Register or by reset. Clearing
this flag is useless as long as a high or low voltage condition
is present.
Half-bridge Control Register (HBCTL)
OFC_EN — H-bridge Offset Chopping Enable Bit
This read / write bit enables offset chopping. Reset clears
the OFC_EN bit.
• 1 = Offset chopping enabled.
• 0 = Offset chopping disabled.
Coil Current
Voltage on
1
1
BEMF Signal
Register Name and Address: HBCTL - $02
Bit 7 6 5 4 3 2 1 Bit 0
Read OFC_EN CSA
000
CLS2 CLS1 CLS0
Write
Reset 0 0000000
Analog Integrated Circuit Device Data
Freescale Semiconductor 29
908E626
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
CSA — H-bridges Current Sense Amplification Select Bit
This read / write bit selects the current sense amplification
of the H-bridges. Reset clears the CSA bit.
• 1 = Current sense amplification set for measuring 0.5 A.
• 0 = Current sense amplification set for measuring 2.5 A.
CLS2 : CLS0 — H-Bridge Current Limitation Selection Bits
These read / write bits select the current limitation value
according to Table 8. Reset clears the CLS2 : CLS0 bits.
Switchable VDD Outputs
The HVDD pin is a switchable VDD output pin. It can be
used for driving external circuitry that requires a VDD voltage.
The output is enabled with bit PSON in the System Control
Register and can be switched on / off with bit HVDDON in the
Power Output Register. Low or high voltage conditions (LVI /
HVI) have no influence on this circuitry.
HVDD Over-temperature Protection
Over-temperature protection is enabled if the high
temperature reset is enabled.
HVDD Over-current Protection
The HVDD output is protected against over-current. In the
event the over-current limit is or was reached, the output
automatically switches off and the HVDD over-current flag in
the System Status Register is set.
System Control Register (SYSCTL)
PSON — Power Stages On Bit
This read / write bit enables the power stages (half-bridges,
LIN transmitter and HVDD output). Reset clears the PSON
bit.
• 1 = Power stages enabled.
• 0 = Power stages disabled.
SRS0 : SRS1 — LIN Slew Rate Selection Bits
These read / write bits enable the user to select the
appropriate LIN slew rate for different baud rate
configurations as shown in Table 9.
The high speed slew rates are used, for example, for
programming via the LIN and are not intended for use in the
application.
Go to STOP Mode Bit (GS)
This write-only bit instructs the 908E626 to power down
and go into STOP mode. Reset or CPU interrupt requests
clear the GS bit.
• 1 = Power down and go into STOP mode
• 0 = Not in STOP mode
System Status Register (SYSSTAT)
LINCL — LIN Current Limitation Bit
This read-only bit is set if the LIN transmitter operates in
current limitation region. Due to excessive power dissipation
in the transmitter, software is advised to turn the transmitter
off immediately.
• 1 = Transmitter operating in current limitation region.
• 0 = Transmitter not operating in current limitation
region.
HVDD_OCF — HVDD Output Over-current Flag Bit
This read / write flag is set on an over-current condition at
the HVDD pin. Clear HVDD_OCF and enable the output by
writing a logic [1] to the HVDD_OCF Flag. Reset clears the
Table 8. H-Bridge Current Limitation Value Selection
Bits
CLS2 CLS1 CLS0 Current Limit
000
No Limit001
010
011 55 mA (typ)
100 260 mA (typ)
101 370 mA (typ)
110 550 mA (typ)
111 740 mA (typ)
Register Name and Address: SYSCTL - $03
Bit 7 6 5 4 3 2 1 Bit 0
Read PSON SRS1 SRS0
0000 0
Write GS
Reset 0 0 0 0000 0
Table 9. LIN Slew Rate Selection Bits
SRS1 SRS0 LIN Slew Rate
0 0 Initial Slew Rate (20 kBaud)
0 1 Slow Slew Rate (10 kBaud)
1 0 High Speed II (8 x)
1 1 High Speed I (4 x)
Register Name and Address: SYSSTAT - $0c
Bit 7 6 5 4 3 2 1 Bit 0
Read
0
LINCL HVDD
_OCF 0
LVF HVF HB_
OCF
HTF
Write
Reset 00000000
Analog Integrated Circuit Device Data
30 Freescale Semiconductor
908E626
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
HVDD_OCF bit. Writing a logic [0] to HVDD_OCF has no
effect.
• 1 = Over-current condition on HVDD has occurred.
• 0 = No over-current condition on HVDD has occurred.
LVF — Low Voltage Bit
This read only bit is a copy of the LVF bit in the Interrupt
Flag Register.
• 1 = Low voltage condition has occurred.
• 0 = No low voltage condition has occurred.
HVF — High Voltage Sensor Bit
This read-only bit is a copy of the HVF bit in the Interrupt
Flag Register.
• 1 = High voltage condition has occurred.
• 0 = No high voltage condition has occurred.
HB_OCF — H-Bridge Over-current Flag Bit
This read / write flag is set on an over-current condition at
the H-Bridges. Clear HB_OCF and enable the H-Bridge
driver by writing a logic [1] to HB_OCF. Reset clears the
HB_OCF bit. Writing a logic [0] to HB_OCF has no effect.
• 1 = Over-current condition on H-Bridges has occurred.
• 0 = No over-current condition on H-Bridges has
occurred.
HTF — Over-temperature Status Bit
This read-only bit is a copy of the HTF bit in the Interrupt
Flag Register.
• 1 = Over-temperature condition has occurred.
• 0 = No over-temperature condition has occurred.
AUTONOMOUS WATCHDOG (AWD)
The Autonomous Watchdog module consists of three
functions:
• Watchdog function for the CPU in RUN mode
• Periodic interrupt function in STOP mode
The Autonomous Watchdog module allows to protect the
CPU against code runaways.
The AWD is enabled if AWDIE, AWDRE in the AWDCTL
Register is set. If this bit is cleared, the AWD oscillator is
disabled and the watchdog switched off.
Watchdog
The watchdog function is only available in RUN mode. On
setting the AWDRE bit, watchdog functionality in RUN mode
is activated. Once this function is enabled, it is not possible to
disable it via software.
If the timer reaches end value and AWDRE is set, a
system reset is initiated. Operations of the watchdog function
cease in STOP mode. Normal operation will be continued
when the system is back to RUN mode.
To prevent a watchdog reset, the watchdog timeout
counter must be reset before it reaches the end value. This is
done by a write to the AWDRST bit in the AWDCTL Register.
PERIODIC INTERRUPT
Periodic interrupt is only available in STOP mode. It is
enabled by setting the AWDIE bit in the AWDCTL Register. If
AWDIE is set, the AWD wakes up the system after a fixed
period of time. This time period can be selected with bit
AWDR in the AWDCTL Register.
Autonomous Watchdog Control Register (AWDCTL)
AWDRST — Autonomous Watchdog Reset Bit
This write-only bit resets the Autonomous Watchdog
timeout period. AWDRST always reads 0. Reset clears
AWDRST bit.
• 1 = Reset AWD and restart timeout period.
• 0 = No effect.
AWDRE — Autonomous Watchdog Reset Enable Bit
This read / write bit enables resets on AWD timeouts. A
reset on the RST_A is asserted when the Autonomous
Watchdog has reached the timeout and the Autonomous
Watchdog is enabled. AWDRE is one-time setable (write
once) after each reset. Reset clears the AWDRE bit.
• 1 = Autonomous watchdog enabled.
• 0 = Autonomous watchdog disabled.
Autonomous Watchdog Interrupt Enable Bit (AWDIE)
This read/write bit enables CPU interrupts by the
Autonomous Watchdog timeout flag, AWFD. IRQ_A is only
asserted when the device is in STOP mode. Reset clears the
AWDIE bit.
• 1 = CPU interrupt requests from AWDF enabled
• 0 = CPU interrupt requests from AWDF disabled
AWDR — Autonomous Watchdog Rate Bit
This read / write bit selects the clock rate of the
Autonomous Watchdog. Reset clears the AWDR bit.
• 1 = Fast rate selected (10 ms).
• 0 = Slow rate selected (20 ms).
Register Name and Address: AWDCTL - $0a
Bit 7 6 5 4 3 2 1 Bit 0
Read 00 0
AWDRE AWDIE 0(18) 0AWDR
Write AWDRST
Reset 00 0 0 0 00 0
Notes
18. This bit must always be set to 0.
Analog Integrated Circuit Device Data
Freescale Semiconductor 31
908E626
FUNCTIONAL DEVICE OPERATION
FACTORY TRIMMING AND CALIBRATION
VOLTAGE REGULATOR
The 908E626 chip contains a low power, low drop voltage
regulator to provide internal power and external power for the
MCU. The VDD regulator accepts a unregulated input supply
and provides a regulated VDD supply to all digital sections of
the device. The output of the regulator is also connected to
the VDD pin to provide the 5.0 V to the microcontroller.
Note: Under loss of power conditions, the discharge of the
VDD capacitor may occur relatively slow. Based on the
selected external components and external VDD load,
additional external load may be required guarantee the MCU
POR threshold being reached before the next power up.
RUN Mode
During RUN mode, the main voltage regulator is on. It
provides a regulated supply to all digital sections.
STOP Mode
During STOP mode the STOP mode regulator supplies a
regulated output voltage. The STOP mode regulator has a
very limited output current capability. The output voltage will
be lower than the output voltage of the main voltage
regulator.
FACTORY TRIMMING AND CALIBRATION
To enhance the ease-of-use of the 908E626, various
parameters (e.g. ICG trim value) are stored in the flash
memory of the device. The following flash memory locations
are reserved for this purpose and might have a value different
from the empty (0xFF) state:
• 0xFD80: 0xFDDF Trim and Calibration Values
• 0xFFFE : 0xFFFF Reset Vector
In the event the application uses these parameters, one
has to take care not to erase or override these values. If these
parameters are not used, these flash locations can be erased
and otherwise used.
Trim Values
Below the usage of the trim values located in the flash
memory is explained
Internal Clock Generator (ICG) Trim Value
The internal clock generator (ICG) module is used to
create a stable clock source for the microcontroller without
using any external components. The untrimmed frequency of
the low frequency base clock (IBASE), will vary as much as
±25%, due to process, temperature, and voltage
dependencies. To compensate this dependencies a ICG trim
values is located at address $FDC2. After trimming the ICG
is a range of typ. ±2% (±3% max.) at nominal conditions
(filtered (100 nF) and stabilized (4.7 F) VDD = 5.0 V,
TAMBIENT~25 °C) and will vary over temperature and voltage
(VDD) as indicated in the 68HC908EY16 datasheet.
To trim the ICG this values has to be copied to the ICG
Trim Register ICGTR at address $38 of the MCU.
Important The value has to be copied after every reset.
Analog Integrated Circuit Device Data
32 Freescale Semiconductor
908E626
TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
DEVELOPMENT SUPPORT
As the 908E626 has the MC68HC908EY16 MCU
embedded, typically all the development tools available for
the MCU also apply for this device. However, due to the fact
of the additional analog die circuitry and the nominal +12 V
supply voltage some additional items have to be considered:
• nominal 12 V rather than 5.0 V or 3.0 V supply
• high voltage VTST might be applied not only to IRQ pin,
but also the IRQ_A pin
For a detailed information on the MCU related
development support, see the MC68HC908EY16 datasheet -
section, development support.
The programming is principally possible at two stages in
the manufacturing process - first on chip level, before the IC
is soldered onto a pcb board, and second, after the IC is
soldered onto the pc board.
Chip level programming
At the Chip level, the easiest way is to only power the MCU
with +5.0 V (see Figure 16), and not provide the analog chip
with VSUP. In this setup, all the analog pins should be left
open (e.g. VSUP[1:3]), and interconnections between the
MCU and the analog die have to be separated (e.g. IRQ -
IRQ_A).
This mode is well described in the MC68HC908EY16
datasheet - section, development support.
Figure 16. Normal Monitor Mode Circuit (MCU only)
It is also possible to supply the whole system with VSUP
(12 V) instead as described in Figure 17.
PCB level programming
If the IC is soldered onto the pc board, it is typically not
possible to separately power the MCU with +5.0 V. The
whole system has to be powered up providing VSUP (see
Figure 17).
MM908E626
RST_A
RST
IRQ_A
IRQ
VSUP[1:3]
GND[1:2]
PTC4/OSC1
PTB3/AD3
PTB4/AD4
PTA0/KBD0
PTA1/KBD1
MAX232
10k
RS232
DB-9
1
3
C1+
C1-
4
5
C2+
C2-
7
8
2
3
5
VCC
GND
16
15
2
V+
V- 6
1µF +
1µF +
+1µF
1µF
+
+
1µF
2
1
3
65
4
74HC125
74HC125
9.8304MHz CLOCK
+5V
+5V
DATA
CLK
+5V
10k
10k
10k
VTST
10
9
T2OUT
R2IN
T2IN
R2OUT
EVDD
VDD
VSS
4.7µF100nF
+5V
VREFL
VDDA
EVSS
VREFH
VSSA
Analog Integrated Circuit Device Data
Freescale Semiconductor 33
908E626
TYPICAL APPLICATIONS
Figure 17. Normal Monitor Mode Circuit
Table 10 summarizes the possible configurations and the
necessary setups.
MM908E626
RST_A
RST
IRQ_A
IRQ
VDD
VSS
VSUP[1:3]
GND[1:2]
PTC4/OSC1
PTB3/AD3
PTB4/AD4
PTA0/KBD0
PTA1/KBD1
MAX232
10k
RS232
DB-9
1
3
C1+
C1-
4
5
C2+
C2-
7
8
2
3
5
VCC
GND
16
15
2
V+
V- 6
1µF +
1µF +
+1µF
1µF
+
+
1µF
2
1
3
65
4
74HC125
74HC125
9.8304MHz CLOCK
VDD
VDD
DATA
CLK
VDD
10k
10k
10k
VDD
VTST
VSUP
47µF +100nF
10
9
T2OUT
R2IN
T2IN
R2OUT
EVDD
4.7µF100nF
VREFL
VDDA
EVSS
VREFH
VSSA
Table 10. Monitor Mode Signal Requirements and Options
Mode IRQ RST Reset
Vector
Serial
Communication
Mode
Selection
ICG COP
Normal
Request
Timeout
Communication Speed
PTA0 PTA1 PTB3 PTB4 External
Clock
Bus
Frequency
Baud
Rate
Normal
Monitor
VTST VDD X 1 0 0 1 OFF disabled disabled 9.8304
MHz
2.4576
MHz
9600
Forced
Monitor
VDD VDD $FFFF
(blank)
1 0 X X OFF disabled disabled 9.8304
MHz
2.4576
MHz
9600
GND ON disabled disabled —Nominal
1.6 MHz
Nominal
6300
User VDD VDD not
$FFFF
(not
blank)
X X X X ON enabled enabled —Nominal
1.6 MHz
Nominal
6300
Notes
19. PTA0 must have a pull-up resistor to VDD in monitor mode
20. External clock is a 4.9152 MHz, 9.8304 MHz or 19.6608 MHz canned oscillator on OCS1
21. Communication speed with external clock is depending on external clock value. Baud rate is bus frequency / 256
22. X = don’t care
23. VTST is a high voltage VDD + 3.5 V VTST VDD + 4.5 V
Analog Integrated Circuit Device Data
34 Freescale Semiconductor
908E626
TYPICAL APPLICATIONS
EMC/EMI RECOMMENDATIONS
This paragraph gives some device specific
recommendations to improve EMC/EMI performance.
Further generic design recommendations can be found on
the Freescale web site, www.freescale.com.
VSUP Pins (VSUP1:VSUP3)
Its recommended to place a high quality ceramic
decoupling capacitor close to the VSUP pins to improve
EMC/EMI behavior.
LIN Pin
For DPI (Direct Power Injection) and ESD (Electrostatic
Discharge) its recommended to place a high quality ceramic
decoupling capacitor near the LIN pin. An additional varistor
will further increase the immunity against ESD. A ferrite in the
LIN line will suppress some of the noise induced.
Voltage Regulator Output Pins (VDD and AGND)
Use a high quality ceramic decoupling capacitor to
stabilize the regulated voltage.
MCU digital supply pins (EVDD and EVSS)
Fast signal transitions on MCU pins place high, short
duration current demands on the power supply. To prevent
noise problems, take special care to provide power supply
bypassing at the MCU. It is recommended that a high quality
ceramic decoupling capacitor be placed between these pins.
MCU analog supply pins (VREFH, VDDA, VREFL, and
VSSA)
To avoid noise on the analog supply pins its important to
take special care on the layout. The MCU digital and analog
supplies should be tied to the same potential via separate
traces and connected to the voltage regulator output.
Figure 18 and Figure 19 show the recommendations on
schematics and layout level and Table 11 indicates
recommended external components and layout
considerations.
Figure 18. EMC/EMI Recommendations
MM908E625
VREFL
VDDA
EVDD
VDD
EVSS
VSS
VSUP1
GND1
VSUP
+
VREFH
VSSA
VSUP2
LINLIN
C1 C2
D1
C3 C4
C5
L1
V1
VSUP3
GND2
Analog Integrated Circuit Device Data
Freescale Semiconductor 35
908E626
TYPICAL APPLICATIONS
Figure 19. PCB Layout Recommendations
.Table 11. Component Value Recommendation
Component Recommended Value(24) Comments / Signal Routing
C1 Bulk Capacitor
C2 100 nF, SMD Ceramic, Low ESR Close (<5.0 mm) to the VSUP1, VSUP2 pins with good ground return
C3 100 nF, SMD Ceramic, Low ESR Close (<3.0 mm) to the digital supply pins (EVDD, EVSS) with good
ground return.
The positive analog (VREFH, VDDA) and the digital (EVDD) supply
should be connected right at the C3.
C4 4,7 F, SMD Ceramic, Low ESR Bulk Capacitor
C5 180 pF, SMD Ceramic, Low ESR Close (<5.0 mm) to LIN pin.
Total Capacitance on LIN has to be below 220 pF.
(CTOTAL = CLIN-PIN + C5 + CVARISTOR ~ 10 pF + 180 pF + 15 pF)
V1(25) Varistor Type TDK AVR-M1608C270MBAAB Optional (close to LIN connector)
L1(25) SMD Ferrite Bead Type TDK MMZ2012Y202B Optional, (close to LIN connector)
Notes
24. Freescale does not assume liability, endorse, or want components from external manufactures that are referenced in circuit drawings
or tables. While Freescale offers component recommendations in this configuration, it is the customer’s responsibility to validate their
application.
25. Components are recommended to improve EMC and ESD performance.
1
2
4
3
5
6
7
8
9
11
10
12
13
14
15
16
18
17
19
20
21
22
23
25
24
26
27
54
53
51
52
50
49
48
47
46
44
45
43
42
41
40
39
37
38
36
35
34
33
32
30
31
29
28
908E626
LIN
VBAT
GND1 GND2
VSUP2
VSUP3
GND
C1
L1
EVDD
EVSS
VDDA
VSSA
VDD
VSS
VSUP1
LIN
VREFH
VREFL
NC
NC
NC
NC
C5
C4
C3
V1
C2
Analog Integrated Circuit Device Data
36 Freescale Semiconductor
908E626
PACKAGING
PACKAGING DIMENSIONS
PACKAGING
PACKAGING DIMENSIONS
Important: For the most current revision of the package, visit www.freescale.com and perform a keyword search on
98ARL10519D. Dimensions shown are provided for reference ONLY.
EK SUFFIX (PB-FREE)
54-PIN
98ARL10519D
ISSUE D
Analog Integrated Circuit Device Data
Freescale Semiconductor 37
908E626
PACKAGING
PACKAGING DIMENSIONS
EK SUFFIX (PB-FREE)
54-PIN
98ARL10519D
ISSUE D
Analog Integrated Circuit Device Data
38 Freescale Semiconductor
908E626
PACKAGING
PACKAGING DIMENSIONS
EK SUFFIX (PB-FREE)
54-PIN
98ARL10519D
ISSUE D
Analog Integrated Circuit Device Data
Freescale Semiconductor 39
908E626
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 1.0)
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 1.0)
Introduction
This thermal addendum ia provided as a supplement to the MM908E626
technical data sheet. The addendum provides thermal performance information
that may be critical in the design and development of system applications. All
electrical, application and packaging information is provided in the data sheet.
Package and Thermal Considerations
This MM908E626 is a dual die package. There are two heat sources in the
package independently heating with P1 and P2. This results in two junction
temperatures, TJ1 and TJ2, and a thermal resistance matrix with RJAmn.
For m, n = 1, RJA11 is the thermal resistance from Junction 1 to the reference
temperature while only heat source 1 is heating with P1.
For m = 1, n = 2, RJA12 is the thermal resistance from Junction 1 to the
reference temperature while heat source 2 is heating with P2. This applies to
RJ21 and RJ22, respectively.
The stated values are solely for a thermal performance comparison of one
package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a
package in an application-specific environment. Stated values were obtained by measurement and simulation according to the
standards listed below.
Standards
Figure 20. Thermal Land Pattern for Direct Thermal
Attachment Per JEDEC JESD51-5Thermal Test Board
54-PIN
SOICW-EP
908E626
98ARL10519D
54-PIN SOICW-EP
Note For package dimensions, refer to
98ARL10519D.
TJ1
TJ2 =
RJA11
RJA21
RJA12
RJA22
.P1
P2
Table 12. Thermal Performance Comparison
Thermal
Resistance
1 = Power Chip, 2 = Logic Chip [C/W]
m = 1,
n = 1
m = 1, n = 2
m = 2, n = 1
m = 2,
n = 2
RJAmn (1)(2) 23 20 24
RJBmn (2)(3) 9.0 6.0 10
RJAmn (1)(4) 52 47 52
RJCmn (5) 1.0 0 2.0
Notes:
1. Per JEDEC JESD51-2 at natural convection, still air
condition.
2. 2s2p thermal test board per JEDEC JESD51-7and
JESD51-5.
3. Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
4. Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
5. Thermal resistance between the die junction and the
exposed pad, “infinite” heat sink attached to exposed pad.
1.0
1.0
0.2
0.2
Soldermast
openings
Thermal vias
connected to top
buried plane
54 Terminal SOIC-EP
0.65 mm Pitch
17.9 mm x 7.5 mm Body
10.3 mm x 5.1 mm Exposed Pad
* All measurements
are in millimeters
Analog Integrated Circuit Device Data
40 Freescale Semiconductor
908E626
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 1.0)
Figure 21. Thermal Test Board
Device on Thermal Test Board
RJAis the thermal resistance between die junction and
ambient air.
RJSmn is the thermal resistance between die junction and
the reference location on the board surface near a center
lead of the package.
This device is a dual die package. Index m indicates the
die that is heated. Index n refers to the number of the die
where the junction temperature is sensed.
908E626 Pin Connections
54-Pin SOICW-EP
0.65 mm Pitch
17.9 mm x 7.5 mm Body
PTA0/KBD0
PTA1/KBD1
PTA2/KBD2
PTA3/KBD3
PTA4/KBD4
VREFH
VDDA
EVDD
EVSS
VSSA
VREFL
PTE1/RXD
RXD
VSS
NC
VDD
NC
NC
NC
HVDD
NC
HB4
VSUP3
GND2
HB3
NC
FLSVPP
PTB7/AD7/TBCH1
PTB6/AD6/TBCH0
PTC4/OSC1
PTC3/OSC2
PTC2/MCLK
PTB5/AD5
PTB4/AD4
PTB3/AD3
IRQ
RST
PTB1/AD1
PTD0/TACH0/BEMF
PTD1/TACH1
NC
FGEN
BEMF
RST_A
IRQ_A
SS
LIN
NC
NC
HB1
VSUP1
GND1
HB2
VSUP2
1
11
12
13
14
15
16
17
18
19
20
9
10
21
22
23
24
25
26
27
6
7
8
4
5
2
3
54
44
43
42
41
40
39
38
37
36
35
46
45
34
33
32
31
30
29
28
49
48
47
51
50
53
52
Exposed
Pad
A
10.3 mm x 5.1 mm Exposed Pad
A
Material: Single layer printed circuit board
FR4, 1.6 mm thickness
Cu traces, 0.07 mm thickness
Outline: 80 mm x 100 mm board area,
including edge connector for thermal
testing
Area A: Cu heat-spreading areas on board
surface
Ambient Conditions: Natural convection, still air
Table 13. Thermal Resistance Performance
Thermal
Resistance
Area A
(mm2)
1 = Power Chip, 2 = Logic Chip (C/W)
m = 1,
n = 1
m = 1, n = 2
m = 2, n = 1
m = 2,
n = 2
RJAmn 053 48 53
300 39 34 38
600 35 30 34
RJSmn 021 16 20
300 15 11 15
600 14 9.0 13
Analog Integrated Circuit Device Data
Freescale Semiconductor 41
908E626
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 1.0)
Figure 22. Device on Thermal Test Board RJA
Figure 23. Transient Thermal Resistance RJA (1.0 W Step Response)
Device on Thermal Test Board Area A = 600 (mm2)
0
10
20
30
40
50
60
Heat spreading area A [mm²]
Thermal Resistance [ºC/W]
0 300 600
R
JA11
R
JA22
R
JA12
=R
JA21
x
0.1
1
10
100
1.00E-03 1.00E-02 1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04
Time[s]
Thermal Resistance [ºC/W]
R
JA11
R
JA22
R
JA12
=R
JA21
x
Analog Integrated Circuit Device Data
42 Freescale Semiconductor
908E626
REVISION HISTORY
REVISION HISTORY
REVISION DATE DESCRIPTION OF CHANGES
4.0 9/2008 • Implemented Revision History page
• Minor corrections throughout the document
• Updated to current Freescale format and style
• Added MM908E626AVEK to the ordering information
• Corrected package drawing designation
• Added STOP mode
5.0 7/2009 • Corrected several non-technical cross-references.
6.0 9/2011 • Corrected text for Autonomous Watchdog Interrupt. Page 17.
• Corrected part number in Go to STOP Mode Bit. Page 30.
• Removed footnotes in register table for SYSCTL and AWDCTL.
• Corrected Figure 4 LIN Timing description.
• Updated Freescale form and style
• Added MM908E626AVPEK to the ordering information.
• Removed the DWB package type.
• Added RoHS image to page 1 and RoHS statement to back page.
• Changed Peak Package Reflow Temperature During Reflow description
• Added note (8)
7.0 4/2012 • Added MM908E626AVPEK to the ordering information
• Removed 908E626AVEK/ R2 from the ordering information
• Updated Freescale form and style
8.0 4/2012 • Corrected Figure 4, LIN Timing Description, replacing VLIN with VSUP
9.0 6/2012 • Added MM908E626AVEK/ R2 to the ordering information
10.0 8/2012 • Corrected broken links within the document.
Document Number: XXxxxx
Rev. X
MM/YYYY
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