RM24C64C-BTAC-T - Adesto Technologies

DS-RM24C64C–057E–9/2015

Features

Memory array: 64Kbit EEPROM-compatible serial memory

Single supply voltage: 2.7V - 3.6V

2-wire I2C interface

Compatible with I2C bus modes:

-100kHz

-400kHz

Page size: 32 byte

-Byte and Page Write from 1 to 32 bytes

Low Energy Byte Write

-Byte Write consuming 60nJ

Low power consumption

-1mA active Read current 

-1.5mA active Write current 

-5µA Standby current

Fast Page and Byte Write

-Page Write in 1ms

-Byte Write in 50µs

Random and sequential Read modes

Write protect of the whole memory array

8-lead SOIC and TSSOP packages

RoHS-compliant and halogen-free packaging

Based on Adesto's proprietary CBRAM® technology

Data Retention: 10 years

Endurance: 25,000 Write Cycles

Unlimited Read Cycles

Description

The Mavriq™RM24C64C is an EEPROM-compatible, 64Kbit non-volatile serial

memory utilizing Adesto's CBRAM resistive memory technology. The memory devices

use a single low-voltage supply ranging from 2.7V to 3.6V.

The Adesto® I2C device is accessed through a 2-wire I2C compatible interface

consisting of a Serial Data (SDA) and Serial Clock (SCL). The maximum clock (SCL)

frequency is 400KHz. The devices have both byte write and page write capability.

Page write is up to 32 bytes. The Byte Write operation of Mavriq serial memory

consumes only 10% of the energy consumed by a Byte Write operation of EEPROM

devices of similar size. The Page Write operation of Mavriq memory is 4-6 times faster

than the Page Write operation of similar EEPROM devices. Both random and

sequential reads are available. Sequential reads are capable of reading the entire

memory in one operation. External address pins permit up to eight devices on the

same data bus. Devices are available in standard 8-pin SOIC and TSSOP packages.

RM24C64C

64Kbit 2.7V Minimum

Non-volatile Serial Memory

I2C Bus

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DS-RM24C64C–057E–9/2015

1. Block Diagram

Figure 1-1. Block Diagram

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2. Pin/Signal Descriptions

Table 2-1. Pin/Signal Descriptions

2.1 Pin Out Diagram

Symbol Pin # Name/Function Description

E0 1LSB - Least Significant Bit,

External Enable

LSB of the three external enable bits (E0, E1 and E2). The levels of

the external enable bits are compared with three enable bits in the

received control byte to provide device selection. The device is

selected if the comparison is true. Up to eight devices may be

connected to the same bus by using different E0, E1, E2

combinations.

E1 2External Enable

The middle of the three external enable bits (E0, E1 and E2). The

levels of the enable bits are compared with three enable bits in the

received control byte to provide device selection. Also see the E0,

E2 pin.

E2 3MSB - Most Significant Bit,

External Enable

MSB of the three external enable bits (E0, E1 and E2). The levels

of the enable bits are compared with three enable bits in the

received control byte to provide device selection. Also see the E0,

E1 pin.

GND 4Ground

SDA 5Serial Data

Bidirectional pin used to transfer addresses and data into and data

out of the device. It is an open-drain terminal, and therefore

requires a pull-up resistor to VCC. Typical pull-up resistors are:

10KΩ for 100KHz, and 2KΩ for 400KHz and 1MHz.

For normal data transfer, SDA is allowed to change only during SCL

low. Changes during SCL high are reserved for indicating the

START and STOP conditions.

SCL 6Serial Clock This input is used to synchronize the data transfer from and to the

device. SCL is an input only, since it is a slave-only device.

WP 7Write Protect

Connect to either VCC or GND. If pulled low, write operations are

enabled. If pulled high, write operations are inhibited, but read

operations are not affected.

Vcc 8Power Power supply pin

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3. I2C Bus Protocol



I2C is a 2-wire serial bus architecture with a clock pin (SCL) for synchronization, and a data pin (SDA) for data transfer.

On the device the SDA pin is bi-directional. The SCL pin is an input only, because the device is slave-only. The SCL and

SDA pins are both externally connected to a positive supply voltage via a current source or pull-up resistor. When the

bus is free, both lines are high. The output stages of devices connected to the bus must have an open drain or open

collector to perform a wired-AND function. Data on the I2C bus can be transferred at rates of up to 400Kbits/s. The

number of interfaces that may be connected to the bus is solely dependent on the bus capacitance limit of 400pF.

The data on the SDA line must be stable during the high period of the clock. The high or low state of the data line can

only change when the clock signal on the SCL line is low (see Figure 3-1).

Figure 3-1. Bit Transfer on the I2C bus

A high-to-low transition on the SDA line while SCL is high indicates a START condition. A low-to-high transition on the

SDA line while SCL is high defines a STOP condition.

START and STOP conditions are always generated by the master. The bus is considered to be busy after the START

condition. The bus is considered to be free again a certain time after the STOP condition (see Figure 3-2).

Figure 3-2. START and STOP conditions

Every byte put on the SDA line must be 8 bits long. The number of bytes that can be transmitted per transfer is

unrestricted. Each byte must be followed by an acknowledge bit; therefore, the number of clock cycles to transfer one

byte is nine. Data is transferred with the most significant bit (MSB) first.

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3.1 I2C Master and Slave Configuration

Thedevicehasatwo‐pinindustry‐standardI2Cinterface.Itisconfiguredasaslave‐onlydeviceandthereforedoesnot

generateaclock.ByconnectingtheE0,E1andE2enablepinsintheconfigurationshownFigure3‐3,uptoeightdevicescan

beconnectedontoanI2CInterfacebuscontrolledbyanI2Cmasterdevice,suchasamicrocontroller.

Figure 3-3. Connection between I2C Maste r and Slaves

4. Device Timing

Figure 4-1. Bus Timing Data

Figure 4-2. Power-up Timing

Power up delay tPUD is based on VCCi which is the voltage level at which the internal reset circuit releases and signals the

controller to initiate the power-on reset condition for a 75µs maximum period.

VCC

min

VCC

max

VCCI

Device in Reset

Program, Read, Erase and Write Commands Rejected

PUD

Device Fully

Accessible

TIME

VCC

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5. Device Addressing

The first byte sent from the master device to the EEPROM following the START condition is the control byte (See Figure

5-1). The first four bits of the control byte is the control code. The control code is “1010” both for read and for write

operations. The next three bits of the control byte are the enable bits (E2, E1 and E0), which are compared to the levels

set on the E0, E1 and E2 pins. The E0, E1 and E2 bits sent in the control byte must correspond to the logic levels set on

the corresponding E0, E1 and E2 pins for a device to be selected. In effect, the E0, E1 and E2 bits in the control register

act as the three MSB bits of a word address. These three bits allow the use of up to eight devices on the same bus. The

last bit of the control byte (R/W) defines the operation to be performed, read or write: if set to a one, a read operation is

selected; if set to a zero, a write operation is selected.

Figure 5-1. Control Byte



Upon receiving a "1010", the chip enable bits, and the R/W bit, the device performs an acknowledge by pulling the SDA

line low during the 9th clock pulse. As stated above, the device will now be set for either a read or a write operation by the

R/W bit.

After the device acknowledges the control byte, two additional bytes are sent by the master to the slave. These define the

target address of the byte in the device to be written. The bit assignment for the address is shown in Figure 5-2. 

It should be noted that not all the address bits are used. For the 64Kbit device, only address A0 to A12 are used; the rest

are don't cares and must be set to "0".

Figure 5-2. Address sequence bit assignment

The device will acknowledge each byte of data that is received by pulling the SDA line low during the 9th clock pulse. If

the device does not provide an acknowledge, it has not received the data; consequently the entire sequence, starting

with the control byte, must be resent.

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6. Byte Write Operation

If the R/W bit in the control byte is set to zero, the device will be in write mode. Once the control byte is received, the

device will perform an acknowledge; it will then be ready to receive the Address High Byte (see Figure 6-1). After

receiving the Address High Byte, the device acknowledges and then is ready to receive the Address Low Byte. After

receiving the Address Low Byte, the device will acknowledge and then write the address (expressed by the high and low

address bytes) into its address pointer. The device is then ready to receive a byte of data to be written into the

addressed memory location. After the device receives the data, it performs an acknowledge. After the master has

received the last acknowledge (after the data byte) the master should send a STOP condition. The STOP condition

initiates the internal write cycle in the device. If the master does not send a STOP, the device will not write the data into

the addressed memory location.

While the device is in the write cycle it will not generate an acknowledge signal. Meanwhile, the master can poll the

device to determine when the write cycle is complete by sending it a control byte and looking for an acknowledge. Once

the write cycle has completed, the device will acknowledge a control byte sent to it.

After the data byte has been written, the internal address pointer will be incremented by one. If, in the RM24C64C, the

byte written is the last byte in a 32-byte page, the address will wrap around to the beginning of the same page. For

instance, if the byte is written to address 001Fh, the incremented address will be 0000h. If the byte is written to address

07FFh, the incremented address will be 07E0h.

If a write cycle is attempted with the WP (write protect) pin held high, the device will acknowledge the command, address,

and data, but no write cycle will occur following the STOP command. The data will not be written, and the device will

immediately be available to accept a new command. However, the internal address pointer will be written; so after the

data byte is transmitted to the device and the STOP command issued by the master, the internal address pointer will

again be incremented by one.

Figure 6-1. Byte Write Cycle

7. Page Write Operation



During a Page Write cycle, a Page with up to 32 bytes of data can be written in one continuous write command. The

Page Write starts in the same manner as the Byte Write. In a Page Write, after the acknowledge following the first data

byte, the master does not send a STOP, but continues to send additional data bytes (See Figure 7-1). At the end of the

number of bytes to be written, the master sends a STOP command. Once the STOP command is sent, the device will

write all the data bytes into memory, starting at the address location given in the address bytes.

If the master should transmit more than 32 bytes prior to generating the STOP command, the internal 32-byte data buffer

in the device will wrap around and the first data bytes transmitted will be overwritten.

Product Density Page Size (byte)

RM24C64C 64Kbit 32

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DS-RM24C64C–057E–9/2015

The internal address pointer will not increment beyond a page boundary but will instead wrap around to the first byte of

the addressed page. For instance, in the RM24C64C, if the address given is 087Ah and ten data bytes are transmitted by

the master before the STOP command occurs, the last data byte received will be written in address location 0863h.

As with the Byte Write cycle, once the STOP command is received the device enters a write cycle. During the write cycle,

the device will not generate an acknowledge signal. Meanwhile, the master can poll the device to determine when the

write cycle is complete by sending it a control byte and looking for an acknowledge. Once the write cycle has completed,

the device will acknowledge a control byte sent to it.

During the Page Write cycle, the first byte in the data byte buffer will be written in the address location indicated by the

address bytes transmitted to the device. Each successive data byte will be written in the successive address locations.

If a Page Write cycle is attempted with the WP pin held high, the device will acknowledge the command, address and

data bytes, but will not enter a write cycle after the STOP command is issued. No data will be written, and the device will

immediately be available to accept a new command. However, the internal address pointer will be written; so after the

Page Write data bytes are transmitted to the device and the STOP command issued by the master, the internal address

pointer will be incremented by the number of data bytes sent (but only within the page addressed).

Note that the Page Write operation is internally executed by sequentially writing the words in the Page Buffer. Therefore

the Page Write time can be estimated as Byte Write time multiplied by the Number of Words to be written.

Figure 7-1. Page Write Cycle

8. Write Protection

The WP pin allows the user to write-protect the entire memory array when the pin is tied to VCC. If the WP pin is tied to

GND, write protection is disabled. The WP pin is sampled at the STOP command for every Write command. Toggling the

WP pin after the STOP command will have no effect on the execution of the write cycle.

9. Polling

The fact that the device will not acknowledge during a write cycle can be used to determine when the write cycle is

complete. By polling the device during the write cycle, bus throughput can be maximized.

Once the STOP command for the write cycle is sent by the master, the device initiates the internally timed write cycle.

Acknowledge polling, by the master, can be initiated immediately. Acknowledge polling involves the master sending a

START command, followed by the control byte for a write command (R/W=0). If the device is still busy with the write

cycle, no acknowledge is returned. If no acknowledge is returned, the START command and control byte can be re-

transmitted. If the write cycle is complete, the device will return an acknowledge. The master can then proceed with the

next read or write command. See Figure 9-1 for a flow diagram.

NOTE: Care must be taken when polling the device. The control byte that was used to initiate the write must match the

control byte used for polling.

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Figure 9-1. Acknowledg e Pol ling Flow

10. Read Operation

Read operations are initiated in the same way as the write operations, except that the R/W bit of the control byte is set to

one. There are three types of read operations: Current Address Read, Random Read, and Sequential Read.

10.1 Current Address Read

The device internal address pointer maintains the address of the last word accessed, internally incremented by one.

Therefore, if the previous read access was to address n (any legal address), the next Current Address Read operation

would access data from address n+1. For the 64Kbit device, if the previous read access was to address 1FFFh, the

incremented address will wrap around to 0000h.

If a Current Address Read is performed after a Byte Write or Page Write, care must be taken to understand that during

the page/byte write command, the address can wrap around within the same page.

Upon receipt of the control byte with the R/W bit set to one, the device issues an acknowledge and transmits the 8-bit

data word located at the address of the internal address pointer. The master will not acknowledge the transfer, but does

generate a STOP condition and the device discontinues transmission. See Figure 10-1.

Figure 10-1. Current Address Read

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10.2 Random Read

Random read operations allow the master to access any memory location in a random manner. To perform a Random

Read, first the address to be accessed must be set. This is done by sending the address to the device as part of a write

operation (R/W = 0). After the address is sent and acknowledged by the device, the master generates a START. This

terminates the write operation, but the address pointer will be set to the address sent. The master then issues the same

control byte as the write operation, but with the R/W bit set to 1. The device will acknowledge and transmit the 8-bit data

byte located at the address location written. The master will not acknowledge the transfer of the data byte, but will instead

generate a STOP condition, which causes the device to discontinue transmission. See Figure 10-2. After the Random

Read operation, the internal address counter will increment to the address location following the one that was just read.

Figure 10-2. Random Read

10.3 Sequential Read

Sequential read allows the whole memory contents to be serially read during one operation. Sequential Read is initiated

in the same way as a Random Read except that after the device transmits the first data byte, the master issues an

acknowledge instead of a STOP condition. This acknowledge from the master directs the device to transmit the next

sequentially addressed byte (See Figure 10-3). Following the final byte transmitted to the master, the master will not

generate an acknowledge, but will generate a STOP condition which causes the device to discontinue transmission.

To provide the Sequential Read, the device contains an internal address pointer which is incremented by one at each

acknowledge received by the master, and by the STOP condition.

Figure 10-3. Sequential Read

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11. Electrical Specifications

11.1 Absolute Maximum Ratings

Table 11-1. Absolute Maximum Ratings*

*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at these, or any other conditions beyond those

indicated in the operational sections of this specification, is not implied. Exposure to absolute maximum rating conditions

for extended periods may affect device reliability.

11.2 DC Characteristics

Parameter Specification

Temperature under Bias 0°C to +70° C

Storage Temperature -20°C to +100°C

All Input voltages with respect to GND - 0.3V to +3.6V

All Output voltages with respect to GND -0.3V to (VCC + 0.3)

ESD protection on all pins (Human Body Model) >2kV

Junction temperature 85°C

Symbol Parameter Condition Min Typ Max Units

TA=0°Cto+70°C,2.7Vto3.6V

VCC Supply Range 2.7V to 3.6V 2.7 3.6 V

VVCCI VCC Inhibit 2.4 V



ICC1



Supply Current, Read VCC= 3.3V SCL at 400kHz 1 2 mA

ICC2



Supply Current, Write VCC= 3.3V 1.5 3mA

ICC3

Supply Current,

Standby VCC= 3.3V. SCL=SDA=3.3V 520 µA

IIL Input Leakage

SCL, SDA, VIN=0V to VCC +1µA

WP, E0, E1, E2, VIN=0V to VCC +5µA

ILO Output Leakage SDA VIN=0V to VCC +1µA

VIL Input Low Voltage SCL, SDA, WP, E0, E1, E2 -0.3 VCC x

0.3 V

VIH Input High Voltage SCL, SDA, WP, E0, E1, E2 VCC x 0.7 VCC +

0.3 V

VOL Output Low Voltage SDA IOL = 3.0mA 0.4 V

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11.3 AC Characteristics

Applicable over recommended operating range: 

TA = 0°C to +70° C, VCC = 2.7V to 3.6V, CL = CB<100pF

Notes: 1. Thisparameterisensuredbycharacterizationonly.

2. Asatransmitter,thedevicemustprovideaninternalminimumdelaytimetobridgetheundefinedregion(minimum

300ns)ofthefallingedgeofSCLtoavoidunintendedgenerationofSTARTorSTOPconditions.

3. VCCmustbeinoperatingrange.

4. AdestomemoryproductsbasedonCBRAMtechnologyare“Direct‐Write”memories.Endurancecyclecalculationsfollow

JEDECspecificationJESD22‐A117B.

5. Subjecttoexpected10‐yeardataretentionspecification.

Symbol Parameter Min Typ Max Units

fCLK SCL clock frequency Vcc 2.7V 100 400 750 KHz

tRI SCL and SDA input rise time (1) 300 ns

tFL SCL and SDA input fall time (1) 100 ns

tSCLH SCL high time 500 ns

tSCLL SCL low time 500 ns

tSTH START condition hold time 250 ns

tSTS START condition setup time 250 ns

tDAH Data input hold time(2) 0ns

tDAS Data input setup time 100 ns

tSTPS STOP condition hold time 250 ns

tWPS WP setup time 600 ns

tWPH WP hold time 1300 ns

tOV Output valid from clock(2) 400 ns

tBFT

Bus free time: time the bus must be free before a new

transmission can start 500 ns

tOF

Output fall time from VIH min to VIL max

CB<100pF 10 + 0.1 CB250 ns

tSP

Input filter spike suppression

SDA and SCL pins 50 ns

tBW Byte write cycle time (one byte) 50 100 µs

tPW Page write cycle time (full page) 1 5 ms

tPUD Vcc power-up delay(3) 75 µs

Endurance

25000(4) Write

Unlimited(5) Read

Retention 70C10 Years

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12. Mechanical Dimensions

12.1 SN (JEDEC SOIC)

DRAWING NO. REV. TITLE GPC

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A1 0.10 – 0.25

A 1.35 – 1.75

b 0.31 – 0.51

C 0.17 – 0.25

D 4.80 – 5.05

E1 3.81 – 3.99

E 5.79 – 6.20

e 1.27 BSC

L 0.40 – 1.27

ØØ 0° – 8°

ØØ

TOP VIEWTOP VIEW

E1E1

END VIEW

A1A1

SIDE VIEWSIDE VIEW

Package Drawing Contact:

contact@adestotech.com

8S1 G

8/20/14

Notes: This drawing is for general information only.

Refer to JEDEC Drawing MS-012, Variation AA

for proper dimensions, tolerances, datums, etc.

8S1, 8-lead (0.150” Wide Body), Plastic Gull

Wing Small Outline (JEDEC SOIC) SWB

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12.2 TA-TSSOP

DRAWING NO. REV. TITLE GPC

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A - - 1.20

A1 0.05 - 0.15

A2 0.80 1.00 1.05

D 2.90 3.00 3.10 2, 5

E 6.40 BSC

E1 4.30 4.40 4.50 3, 5

b 0.19 – 0.30 4

e 0.65 BSC

L 0.45 0.60 0.75

L1 1.00 REF

C 0.09 - 0.20

Side View

End View

Top View

Pin 1 indicator

this corner

Notes: 1. This drawing is for general information only. Refer to JEDEC

Drawing MO-153, Variation AA, for proper dimensions,

tolerances, datums, etc.

2. Dimension D does not include mold Flash, protrusions or gate

burrs. Mold Flash, protrusions and gate burrs shall not exceed

0.15mm (0.006in) per side.

3. Dimension E1 does not include inter-lead Flash or protrusions.

Inter-lead Flash and protrusions shall not exceed 0.25mm

(0.010in) per side.

4. Dimension b does not include Dambar protrusion. Allowable

Dambar protrusion shall be 0.08mm total in excess of the b

dimension at maximum material condition. Dambar cannot be

located on the lower radius of the foot. Minimum space between

protrusion and adjacent lead is 0.07mm.

5. Dimension D and E1 to be determined at Datum Plane H.

8X E

12/8/11

TA, 8-lead 4.4mm Body, Plastic Thin

Shrink Small Outline Package (TSSOP) TNR

Package Drawing Contact:

contact@adestotech.com

RM24C64C

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13. Ordering Information

13.1 Ordering Detail

13.2 Ordering Codes

RM24C64C-BSNC-T

Device Type Shipping Carrier Opon

RM24C = I

C serial access bus B = Tube

T = Tape & Reel

Density Grade & Temperature Range

C = Green,

64 = 64 Kbit Commercial

temperature (0-70 C)

Device/Die Revision Package Opon

CSN = 8 lead 0.150” SOIC , Narrow

Operang Voltage

B = 2.7V to 3.6V

TA = 8 lead TSSOP

Ordering Code Package Density Operating

Voltage Device

Grade Ship

Carrier Qty. Carrier

RM24C64C-BSNC-B

SN 64Kbit 2.7V to 3.6V Commercial

(0C to 70C)

Tube 100

RM24C64C-BSNC-T

Reel 4000

RM24C64C-BTAC-B

TA 64Kbit 2.7V to 3.6V Commercial

(0C to 70C)

Tube 100

RM24C64C-BTAC-T

Reel 6000

Package Type

SN 8-lead 0.150" wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

TA 8-lead 3 x 4.4 mm, Thin Shrink Small Outline Package

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14. Revision History

Doc. Rev. Date Comments

DS-RM24C64C-057A 10/2014 Initial document release.

DS-RM24C64C-057B 1/2015 Updated Standby Current.

DS-RM24C64C-057C 3/2015 Updated formatting and syntax.

DS-RM24C64C-057D 4/2015 Updated Endurance specifications for Read and Write cycles.

DS-RM24C64C-057E 9/2015 Removed Preliminary document status (document complete).

Corporate Office

California | USA

Adesto Headquarters

1250 Borregas Avenue

Sunnyvale, CA 94089

Phone: (+1) 408.400.0578

Email: contact@adestotech.com

Disclaimer: Adesto Technologies Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Adesto's Terms

and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications

detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Adesto are granted by the

Company in connection with the sale of Adesto products, expressly or by implication. Adesto's products are not authorized for use as critical components in life support devices or systems.

For Release Only Under Non-Disclosure Agreement (NDA)

Adesto®, the Adesto logo, CBRAM®, MavriqTM and DataFlash® are registered trademarks or trademarks of Adesto Technologies. All other marks are the property of their

respective owners.