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INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
SEPT. 2011
2011 Integrated Device Technology, Inc. DSC 7117/4c
IDT5V9885T
INDUSTRIAL TEMPERATURE RANGE
3.3V EEPROM
PROGRAMMABLE CLOCK
GENERATOR
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
•Three internal PLLs
•Internal non-volatile EEPROM
•JTAG and FAST mode I2C serial interfaces
•Input Frequency Ranges: 1MHz to 400MHz
•Output Frequency Ranges: 4.9kHz to 500MHz
•Reference Crystal Input with programmable oscillator gain and
programmable linear load capacitance
−
Crystal Frequency Range: 8MHz to 50MHz
•Each PLL has an 8-bit pre-scaler and a 12-bit feedback-divider
•10-bit post-divider blocks
•Fractional Dividers
•Two of the PLLs support Spread Spectrum Generation
capability
•I/O Standards:
−
Outputs - 3.3V LVTTL/ LVCMOS, LVPECL, and LVDS
−
Inputs - 3.3V LVTTL/ LVCMOS
•Programmable Slew Rate Control
•Programmable Loop Bandwidth Settings
•Programmable output inversion to reduce bimodal jitter
•Redundant clock inputs with glitchless auto and manual
switchover options
•JTAG Boundary Scan
•Individual output enable/disable
•Power-down mode
•3.3V VDD
•Available in TQFP and VFQFPN packages
DESCRIPTION:
The IDT5V9885T is a programmable clock generator intended for high
performance data-communications, telecommunications, consumer, and
networking applications. There are three internal PLLs, each individually
programmable, allowing for three unique non-integer-related frequencies.
The frequencies are generated from a single reference clock. The
reference clock can come from one of the two redundant clock inputs. A
glitchless automatic or manual switchover function allows any one of the
redundant clocks to be selected during normal operation.
The IDT5V9885T can be programmed through the use of the I2C or
JTAG interfaces. The programming interface enables the device to be
programmed when it is in normal operation or what is commonly known as
in-system programmable. An internal EEPROM allows the user to save
and restore the configuration of the device without having to reprogram it
on power-up. JTAG boundary scan is also implemented.
Each of the three PLLs has an 8-bit pre-scaler and a 12-bit feedback
divider. This allows the user to generate three unique non-integer-related
frequencies. The PLL loop bandwidth is programmable to allow the user
to tailor the PLL response to the application. For instance, the user can tune
the PLL parameters to minimize jitter generation or to maximize jitter
attenuation. Spread spectrum generation and fractional divides are
allowed on two of the PLLs.
There are 10-bit post dividers on five of the six output banks. Two of the
six output banks are configurable to be LVTTL, LVPECL, or LVDS. The
other four output banks are LVTTL. The outputs are connected to the PLLs
via the switch matrix. The switch matrix allows the user to route the PLL
outputs to any output bank. This feature can be used to simplify and optimize
the board layout. In addition, each output's slew rate and enable/disable
function can be programmed.
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INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
FUNCTIONAL BLOCK DIAGRAM
EEPROM
Control Block for
Multi-Purpose I/O, Programming, Features
OSC.
PLL 0
PLL 1
PLL 2
10-Bit
P2 Divider
10-Bit
P6 Divider
10-Bit
P3 Divider
10-Bit
P4 Divider
10-Bit
P5 Divider
XTALOUT
XTALIN/REFIN
CLKIN
SHUTDOWN/OE
GIN5/CLK_SEL
I C/JTAG
2
GIN0/SDAT/TDI
GIN1/SCLK/TCLK
GIN2/TMS
GIN3/SUSPEND
GIN4/TRST
/2
/2
OUT1
OUT3
OUT4
OUT4
OUT5
OUT5
OUT2
OUT6
GOUT0/TDO/
LOSS_LOCK
GOUT1/
LOSS_CLKIN
(1)
(1)
(1)
(1)
/2
/2
/2
NOTE:
1. OUT4 and OUT5 pairs can be configured to be LVDS, LVPECL, or two single-ended LVTTL outputs. As LVTTL, OUT4 and OUT5 can be configured to be non-inverting.
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INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
PIN CONFIGURATION
31
10
OUT4
30 29 28 27 26 25
11 12 13 14 15 16
GOUT0.TDO/LOSS_LOCK
OUT2
SHUTDOWN/OE
GIN3/SUSPEND
V
D
D
OUT4
OUT6
OUT5
OUT5
V
D
D
GND
GND
32
9
V
D
D
GND
GIN4/TRST
1
2
3
4
5
6
7
8
CLKIN
GND
GOUT1/LOSS_CLKIN
XTALIN/REFIN
OUT1
VDD
OUT3
XTALOUT
18 GND
24
23
22
21
20
19
I C/JTAG
GIN2/TMS
VDD
GIN1/SCLK/TCLK
GIN0/SDA/TDI
GIN5/CLK_SEL
17 VDD
2
TQFP
TOP VIEW
27 26 25 24 23 22
GOUT0.TDO/LOSS_LOCK
OUT2
SHUTDOWN/OE
GIN3/SUSPEND
GND
28
V
D
D
GIN4/TRST
8
OUT4
9 10 11 12 13 14
OUT4
OUT6
OUT5
OUT5
V
D
D
GND
1
2
3
4
5
6
7
CLKIN
GND
GOUT1/LOSS_CLKIN
XTALIN/REFIN
OUT1
OUT3
XTALOUT
21
20
19
18
17
16
I C/JTAG
GIN2/TMS
VDD
GIN1/SCLK/TCLK
GIN0/SDA/TDI
GIN5/CLK_SEL
15 VDD
2
GND
VFQFPN
TOP VIEW
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INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
PIN DESCRIPTION
PF32 NL28
Pin Name Pin# Pin# I/O Type Description
CLKIN 1 1 ILVTTL Input Clock
XTALIN/REFIN 4 4 ILVTTL CRYSTAL_IN - Reference crystal input or external reference clock input
XTALOUT 5 5 OLVTTL CRYSTAL_OUT -Reference crystal feedback
GIN0/SDAT/TDI 19 16 ILVTTL(1,2) Multi-purpose inputs. Can be used for Frequency Control, SDAT(I2C), or TDI(JTAG).
GIN1/SCLK/TCK 20 17 ILVTTL(1,2) Multi-Purpose inputs. Can be used for Frequency Control, SCLK(I2C), or TCK(JTAG).
GIN2/TMS 24 21 ILVTTL(1,2) Multi-Purpose inputs. Can be used for Frequency Control or TMS (JTAG)
GIN3/SUSPEND 27 23 ILVTTL(1,2) Multi-Purpose inputs. Can be used for Frequency Control or as a suspend mode control
input (active HIGH).
GIN4/TRST 25 22 ILVTTL(1,2) Multi-Purpose inputs. Can be used for Frequency Control or TRST (JTAG)
GIN5/CLK_SEL 21 18 ILVTTL(1,2) Multi-Purpose inputs. Can be used for Frequency Control or input clock selector.
SHUTDOWN/OE 28 24 ILVTTL(1,2) Enables/disables the outputs or powers down the chip. The SP bit (0x1C) controls the
polarity of the signal to be either active HIGH or LOW. (Default is active HIGH.)
I2C/JTAG 22 19 I3-level(3) I2C (HIGH) or MFC Mode (MID) or JTAG Programming (LOW)
OUT1 6 6 OLVTTL Configurable clock output 1. Can also be used to buffer the reference clock.
OUT2 29 25 OLVTTL Configurable clock output 2
OUT3 8 7 OLVTTL Configurable clock output 3
OUT4 10 8OAdjustable(4) Configurable clock output 4, Single-Ended or Differential when combined with OUT4
OUT4 11 9OAdjustable(4) Configurable complementary clock output 4, Single-Ended or Differential when
combined with OUT4
OUT5 15 13 OAdjustable(4) Configurable clock output 5, Single-Ended or Differential when combined with OUT5
OUT5 16 14 OAdjustable(4) Configurable complementary clock output 5, Single-Ended or Differential when
combined with OUT5
OUT6 13 11 OLVTTL Configurable clock output 6
GOUT0/TDO/LOSS_LOCK 31 27 OLVTTL(1) Multi-Purpose Output. Can be programmed to use as PLL LOCK signal, LOSS_LOCK
or TDO in JTAG mode
GOUT1/LOSS_CLKIN 3 3 OLVTTL Multi-Purpose Output. Can be programmed to use as LOSS_CLKIN
VDD 7,12,17, 10,15,20 3.3V Power Supply
23,26,32 28
GND 2,9,14, 2,12,26 Ground
18,30
NOTES:
1. The JTAG (TDO, TMS, TCLK, TRST, and TDI) and I2C (SCLK and SDAT) signals share the same pins with GIN signals.
2. Weak internal 100KΩ pull-down resistor.
3. 3-level inputs are static inputs and must be tied to VDD or GND or left floating. These inputs are internally biased to VDD/2. They are not hot-insertable or over voltage tolerant.
4. Outputs are user programmable to drive single-ended 3.3V LVTTL, differential LVDS, or differential LVPECL interface levels.
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INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
PLL FEATURES AND DESCRIPTIONS
PLL2 Block Diagram
PLL0 Block Diagram
PLL1 Block Diagram
VCO
D0 Divider
M0 Multiplier
Spread
Spectrum
Modulation
VCO
D1 Divider
M1 Multiplier
Spread
Spectrum
Modulation
VCO
D2 Divider
M2 Multiplier
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INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
Spread Spectrum
Pre-Divider (D) Values Multiplier (M) Values Programmable Loop Bandwidth Generation Capability
PLL0 1 - 255 2 - 8190 yes yes
PLL1 1 - 255 2 - 8190 yes yes
PLL2 1 - 255 1 - 4095 yes no
REFERENCE CLOCK INPUT PINS AND
SELECTION
The 5V9885T supports up to two clock inputs. One of the clock inputs
(XTALIN/ REFIN) can be driven by either an external crystal or a reference
clock. The second clock input (CLKIN) can only be driven from an external
reference clock. Either clock input can be set as a the primary clock. The primary
clock designation is to establish which is the main reference clock to the PLLs.
The non-primary clock is designated as the secondary clock in case the primary
clock goes absent and a backup is needed. The PRIMCLK bit (0x34)
determines which clock input will be the primary clock. When PRIMCLK bit is
"0", it will select XTALIN/REFIN as the primary, and when "1", it will select CLKIN
as the primary. The two external reference clocks can be manually selected
using the GIN5/CLK_SEL pin, except in Manual Frequency Control (MFC)
mode 2, or via programming by hard wiring the CLK_SEL pin and toggling the
PRIMCLK bit. For more details on the MFC modes, refer to the CONFIGURING
MULTI-PURPOSE I/Os section. When CLK_SEL is LOW, the primary clock
is selected and when HIGH, the secondary clock is selected. The SM bits (0x34)
must be set to "0x" for manual switchover which is detailed in SWITCHOVER
MODES section.
XTAL load cap = 3.5pF + XTALCAP[7:0] * 0.125pF (Eq. 1)
Crystal Input (XTALIN/REFIN)
The crystal oscillators should be fundamental mode quartz crystals: overtone
crystals are not suitable. Crystal frequency should be specified for parallel
resonance with 50Ω maximum equivalent series resonance.
When the XTALIN/REFIN pin is driven by a crystal, it is important to set the
internal oscillator inverter drive strength and internal tuning/load capacitor
values correctly to achieve the best clock performance. These values are
programmable through either I2C or JTAG interface to allow for maximum
compatibility with crystals from various manufacturers, processes, performances,
and qualities. The internal load capacitors are true parallel-plate capacitors for
ultra-linear performance. Parallel-plate capacitors were chosen to reduce the
frequency shift that occurs when non-linear load capacitance interacts with load,
bias, supply, and temperature changes. External non-linear crystal load
capacitors should not be used for applications that are sensitive to absolute
frequency requirements. The value of the internal load capacitors are determined
by XTALCAP[7:0] bits, (0x07). The load capacitance can be set with a resolution
of 0.125 pF for a total crystal load range of 3.5pF to 35.5pF. This value should
be set to two times the crystal load capacitance value stated by the vendor,
subtracting out board capacitance value. Check with the vendor's crystal load
capacitance specification for the exact setting to tune the internal load capacitor.
The following equation governs how the total internal load capacitance is set.
Ex.: For crystal capacitance = 12pF
For board capacitance = 3pF each leg
XTALCAP = 2x [12-3] = 18pF
GIN5/CLK_SEL Selected Clock Input
LPrimary
HSecondary
Parameter Bits Step Min Max Units
XTALCAP 80.125 032 pF
When using an external reference clock instead of a crystal on the XTAL/
REFIN pin, the input load capacitors may be completely bypassed. This allows
for the input frequency to be up to 200MHz. When using an external reference
clock, the XTALOUT pin must be left floating, XTALCAP must be programmed
to the default value of "0", and crystal drive strength bit, XDRV (0x06), must
be set to the default value of "11".
CLKIN Pin
CLKIN pin is a regular clock input pin, and can be driven up to 400MHz.
PRE-SCALER, FEEDBACK-DIVIDER, AND
POST-DIVIDER
Each PLL incorporates an 8-bit pre-scaler and a 12-bit feedback divider
which allows the user to generate three unique non-integer-related frequencies.
For output banks OUT2-OUT6, each bank has a 10-bit post-divider. The
following equation governs how the frequency on output banks OUT2-6 is
calculated.
FOUT = FIN * D (Eq. 2)
Where FIN is the reference frequency, M is the total feedback-divider value,
D is the pre-scaler value, P is the total post-divider value, and FOUT is the resulting
output bank frequency. The value 2 in the denominator is due to the divide-
by-2 on each of the output banks OUT2-6. Note that OUT1 does not have any
type of post-divider. Also, programming any of the dividers may cause glitches
on the outputs.
Pre-Scaler
D[7:0] are the bits used to program the pre-scaler for each PLL, D0 for
PLL0, D1 for PLL1, and D2 for PLL2. The pre-scalers divide down the
reference clock with integer values ranging from 1 to 255. To maintain low jitter,
the divided down clock must be higher than 400KHz; it is best to use the smallest
D divider value possible. If D is set to '0x00', then this will power down the PLL
and all the outputs associated with that PLL.
M
P * 2
( )
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INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
Feedback-Divider
N[11:0] and A[3:0] are the bits used to program the feedback-divider for PLL0 (N0 and A0) and PLL1 (N1 and A1). If spread spectrum generation is enabled
for either PLL0 or PLL1, then the SS_OFFSET[5:0] bits (0x61, 0x69) would be factored into the overall feedback divider value. See the SPREAD SPECTRUM
GENERATION section for more details on how to configure PLL0 and PLL1 when spread spectrum is enabled. The two PLLs can also be configured for fractional
divide ratios. See FRACTIONAL DIVIDER for more details. For PLL2, only the N[11:0] bits (N2) are used to program its feedback divider and there is no spread
spectrum generation and fractional divides capability. The12-bit feedback-divider integer values range from 1 to 4095.
The following equations govern how the feedback divider value is set. Note that the equations are different for PLL0/PLL1 and PLL2
PLL0 and PLL1:
M = 2*N[11:0] + A[3:0] + 1 + SS_OFFSET[5:0] * 1/64 (Eq. 3)
M = 2*N[11:0] + A[3:0] + 1 (spread spectrum disabled) (Eq. 4)
A[3:0] = 0000 = -1
= 0001 = 1
= 0010 = 2
= 0011 = 3
.
.
.
= 1111 = 15
Note: A[3:0] < (N[11:0] - 5), must be met when using A. N cannot be programmed with a value of 4, 8, or 16 when using A.
PLL2:
M = N[11:0] (Eq. 5)
The user can achieve an even or odd integer divide ratio for both PLL0 and PLL1 by setting the A[3:0] bits accordingly and disabling the spread spectrum.
A fractional divide can also be set for PLL0 and PLL1 by using the A[3:0] bits in conjunction with the SS_OFFSET[5:0] bits, which is detailed in the FRACTIONAL
DIVIDER section. Note that the VCO has a frequency range of 10MHz to 1200MHz. To maintain low jitter, it is best to maximize the VCO frequency. For example,
if the reference clock is 100MHz and a 200MHz clock is required, to achieve the best jitter performance, multiply the 100MHz by 12 to get the VCO running at
the highest possible frequency of 1200MHz and then divide it down to get 200MHz. Or if the reference clock is 25MHz and 20MHz is the required clock, multiply
the 25MHz by 40 to get the VCO running at 1000MHz and then divide it down to get 20MHz. If N is set to '0x00', the VCO will slew to the minimum frequency.
Post-Divider
Q[9:0] are the bits used to program the 10-bit post-dividers on output banks OUT2-6. OUT1 bank does not have a 10-bit post-divider or any other post-
divide along its path. The 10-bit post-dividers will divide down the output banks' frequency with integer values ranging from 1 to 1023.
There is the option to choose between disabling the post-divider, utilizing a div/1, a div/2, or the 10-bit post-divider by using the PM[1:0] bits. Each bank,
except for OUT1, has a set of PM bits. When disabling the post-divider, no clock will appear at the outputs, but will remain powered on. The values are listed
in the table below.
PM[1:0] P Post-Divider
00 disabled
01 div/1
10 div/2
11 Q[9:0] + 2 (Eq. 6)
00
01
10
11
/2
/ (Q+2)
PM[1:0]
/2
To Outputs
VCO
P
Post-Divider Diagram
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INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
Note that the actual 10-bit post-divider value has a 2 added to the integer value Q and the outputs are routed through another div/2 block. The post-divider
should never be disabled unless the output bank will never be used during normal operation. The output frequency range for LVTTL outputs are from 4.9KHz
to 200MHz. The output frequency range for LVPECL/LVDS outputs are from 4.9KHz to 500MHz.
SPREAD SPECTRUM GENERATION
PLL0 and PLL1 support spread spectrum generation capability, which users have the option of turning on and off. Spread spectrum profile, frequency, and
spread are fully programmable (within limits). The programmable spread spectrum generation parameters are TSSC[3:0], NSSC[3:0], SS_OFFSET[5:0],
SD[3:0], DITH, and X2 bits. These bits are in the memory address range of 0x60 to 0x67 for PLL0 and 0x68 to 0x6F for PLL1. The spread spectrum generation
on PLL0 & PLL1 can be enabled/disabled using the TSSC[3:0] bits. To enable spread spectrum, set TSSC > '0' and set NSSC, SD[3:0], SD[5:0], and the
A[3:0] in the total M value accordingly. And to disable, set TSSC = '0'.
TSSC[3:0]
These bits are used to determine the number of phase/frequency detector cycles per spread spectrum cycle (ssc) steps. The modulation frequency can be
calculated with the TSSC bits in conjunction with the NSSC bits. Valid TSSC integer values for the modulation frequency range from 5 to 14.
NSSC[3:0]
These bits are used to determine the number of delta-encoded samples used for a single quadrant of the spread spectrum waveform. All four quadrants
of the spread spectrum waveform are mirror images of each other. The modulation frequency is also calculated based off the NSSC bits in conjunction with the
TSSC bits. Valid NSSC integer values range from 1 to 6.
SS_OFFSET[5:0]
These bits are used to program the fractional offset with respect to the nominal M integer value. For center spread, the SS_OFFSET should be set to '0' so
the spread spectrum waveform is about the nominal M (Mnom) value. For down spread, the SS_OFFSET > '0' so the spread spectrum wavform is about the
(Mideal -1 = Mnom) value. The downspread percentage can be thought of in terms of center spread. For example, a downspread of -1% can also be considered
as a center spread of ±0.5% but with Mnom shifted down by one and offset. The SS_OFFSET has integer values ranging from 0 to 63.
SD[3:0]
These bits are used to shape the profile of the spread spectrum waveform. These are delta-encoded samples of the waveform. There are twelve sets of
SD samples for each PLL. The NSSC bits determine how many of these samples are used for the waveform. The sum of these delta-encoded samples (sigma-
delta-encoded samples) determine the amount of spread and should not exceed (63 - SS_OFFSET). The maximum spread is inversely proportional to the
nominal M integer value.
DITH
This bit is for dithering the sigma-delta-encoded samples. This will randomize the least-significant bit of the input to the spread spectrum modulator. Set the
bit to '1' to enable dithering.
X2
This bit will double the total value of the sigma-delta-encoded-samples which will increase the amplitude of the spread spectrum waveform by a factor of two.
When X2 is '0', the amplitude remains nominal but if set to '1', the amplitude is increased by x2.
The following equations govern how the spread spectrum is set:
TSSC = TSSC[3:0] + 2 (Eq. 7)
NSSC = NSSC[3:0] * 2 (Eq. 8)
SD[3:0]K = SJ+1(unencoded) - SJ(unencoded) (Eq. 9)
where SJ is the unencoded sample out of a possible 12 and SDK is the delta-encoded sample out of a possible 12.
Amplitude = (2*N[11:0] + A[3:0] + 1) * Spread% / 100 (Eq. 10)
2
if 1 < Amp < 2, then set X2 bit to '1'.
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INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
Modulation frequency:
FPFD = FIN / D (Eq. 11)
FVCO = FPFD * MNOM (Eq. 12)
FSSC = FPFD / (4 * Nssc * Tssc) (Eq. 13)
Spread:
Σ∆ = SD0 + SD1 + SD2 + … + SD11
the number of samples used depends on the NSSC value
Σ∆ ≤ 63 - SS_OFFSET
±Spread% = Σ∆ * 100 (Eq. 14)
64 * (2*N[11:0] + A{3:0} + 1)
±Max Spread% / 100 = 1 / MNOM or 2 / MNOM (X2=1)
Profile:
Waveform starts with SS_OFFSET, SS_OFFSET + SDJ, SS_OFFSET + SDJ+1, etc.
Spread Spectrum Using Sinusoidal Profile
Σ∆ = 63
(SS_OFFSET = 0)
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INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
Example
FIN = 25MHz, FOUT = 100MHz, Fssc = 33KHz with center spread of ±2%. Find the necessary spread spectrum register settings.
Since the spread is center, the SS_OFFSET can be set to '0'. Solve for the nominal M value; keep in mind that the nominal M should be chosen to maximize
the VCO. Start with D = 1, using Eq.10 and Eq.11.
MNOM = 1200MHz / 25MHz = 48
Using Eq.4, we arbitrarily choose N = 22, A = 3. Now that we have the nominal M value, we can determine TSSC and NSSC by using Eq.12.
Nssc * Tssc = 25MHz / (33KHz * 4) = 190
However, using Eq. 7 and Eq.8, we find that the closest value is when TSSC = 14 and NSSC = 6. Keep in mind to maximize the number of samples used
to enhance the profile of the spread spectrum waveform.
Tssc = 14 + 2 = 16
Nssc = 6 * 2 = 12
Nssc * Tssc = 192
Use Eq.14 to determine the value of the sigma-delta-encoded samples.
±2% = Σ∆ * 100
64 * 48
Σ∆ = 61.44
Either round up or down to the nearest integer value. Therefore, we end up with 61 or 62 for sigma-delta-encoded samples. Since the sigma-delta-encoded
samples must not exceed 63 with SS_OFFSET set to '0', 61 or 62 is well within the limits. It is the discretion of the user to define the shape of the profile that
is better suited for the intended application.
Using Eq.14 again, the actual spread for the sigma-delta-encoded samples of 61 and 62 are ±1.99% and ±2.02%, respectively.
Use Eq.10 to determine if the X2 bit needs to be set;
Amplitude = 48 * (1.99 or 2.02) / 100 = 0.48 < 1
2
Therefore, the X2 = '0 '. The dither bit is left to the discretion of the user.
The example above was of a center spread using spread spectrum. For down spread, the nominal M value can be set one integer value lower to 43.
Note that the 5V9885T should not be programmed with TSSC > '0', SS_OFFSET = '0', and SD = '0' in order to prevent an unstable state in the modulator.
The PLL loop bandwidth must be at least 10x the modulation frequency along with higher damping (larger ωuz) to prevent the spread spectrum from being filtered
and reduce extraneous noise. Refer to the LOOP FILTER section for more detail on ωuz. The A[3:0] must be used for spread spectrum, even if the total multiplier
value is an even integer.
FRACTIONAL DIVIDER
There is the option for the feedback-divider to be programmed as a fractional divider for only PLL0 and PLL. By setting TSSC > '0' and SD bits to '0', the
SS_OFFSET bits would determine the fractional divide value. See the SPREAD SPECTRUM GENERATION section for more details on the TSSC, SD, and
SS_OFFSET bits. The following equation governs how the fractional divide value is set.
M = 2*N[11:0] + A[3:0] + 1 + SS_OFFSET[5:0] *1/64
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INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
The spread spectrum parameters such as the modulation frequency and profile will not be enabled nor will it have any impact on the PLL output when the
PLL is programmed for fractional divide.
The following is an example of how to set the fractional divider.
Example
FIN = 20MHz, FOUT1 = 168.75MHz, FOUT2 = 350MHz
Solving for 350MHz using Eq.2 and Eq.3 with PLL0 and spread spectrum off,
350MHz = 20MHz * (M / D)/ (P * 2)
For better jitter performance, keep D as small as possible
(350MHz * 2/20MHz)= (M/P) = 35
Therefore, we have D = 1, M = 35 (N = 16, A = 2) for PLL0 with P = 1 on output bank4 resulting in 350MHz.
Solving for 168.75MHz with PLL1 and fractional divide enabled:
168.75MHz = 20MHz * (M / D)/(P * 2)
168.75MHz * 2/20MHz = M/P = 16.875/1 or 33.75/2
The 33.75 value is chosen to achieve the highest VCO frequency possible. Next step is to figure out the setting for the fractional divide using Eq.3.
33.75 = 2*N + A + 1 + SS_OFFSET * 1/64
Integer value 33 can be determined by N and A, thus leaving 0.75 left to be solved.
2*N + A + 1 = 33
SS_OFFSET = 64 * 0.75 = 48
Therefore, we have D=1, M=33.75 (N=15, A=2, SS_OFFSET=48) for PLL1 with P=2 on an output bank resulting in 168.75MHz.
The fractional divider can be determined if it is needed by following the steps in the previous example. Note that the 5V9885T should not be programmed
with TSSC > '0', SS_OFFSET = '0', and SD = '0' in order to prevent an unstable state in the modulator. The A[3:0] must be used and set to be greater than
'2' for a more accurate fractional divide.
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INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
LOOP FILTER
The loop filter for each PLL can be programmed to optimize the jitter performance. The low-pass frequency response of the PLL is the mechanism that dictates
the jitter transfer characteristics. The loop bandwidth can be extracted from the jitter transfer. A narrow loop bandwidth is good for jitter attenuation while a wide
loop bandwidth is best for low jitter generation. The specific loop filter components that can be programmed are the resistor via the RZ[3:0] bits, pole capacitor
via the CZ[3:0] bits, zero capacitor via the CP[3:0] bits, and the charge pump current via the IP[2:0] bits.
The following equations govern how the loop filter is set.
Resistor (Rz) = 0.3KΩ + RZ[3:0] * 1KΩ(Eq. 15)
Zero capacitor (Cz) = 6pF + CZ[3:0] * 27.2pF (Eq. 16)
Pole capacitor (Cp) = 1.3pF + CP[3:0] * 0.75pF (Eq. 17)
Charge pump current (Ip) = 5 * 2IP[2:0] µA(Eq. 18)
Parameter Bits Step Min Max Units
RZ 4 1 0.3 15.3 KΩ
CZ 427.2 6414 pF
CP 40.75 1.3 12.55 pF
IP 32n5640 µA
From PFD
V
DD
UP
Ip
DOWN
Ip
Rz
Cz
Cp
To VCO
Charge Pump and Loop Filter Configuration
PLL loop filter design is beyond the scope of this datasheet. Refer to design procedures for 3-order charge-pump based PLLs. For the sake of simplicity,
the fastest and easiest way to calculate the PLL loop bandwidth (Fc) given the programmable loop filter parameters is as follows.
PLL Loop Bandwidth:
Charge pump gain (Kφ) = Ip / 2π(Eq. 19)
VCO gain (KVCO) = 950MHz/V * 2π(Eq. 20)
M = Total multiplier value (See the PRE-SCALERS, FEEDBACK-DIVIDERS, POST-DIVIDERS section for more detail)
ωc = Rz * Kφ * KVCO * Cz (Eq. 21)
M * (Cz + Cp)
Fc = ωc / 2π(Eq. 22)
Note, the phase/frequency detector frequency (FPFD) is typically seven times the PLL closed-loop bandwidth (Fc) but too high of a ratio will reduce your
phase margin thus compromising loop stability.
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INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
To determine if the loop is stable, the phase margin (ωm) would need to be calculated as follows.
Phase Margin:
ωz = 1 / (Rz * Cz) (Eq. 23)
ωp = Cz + Cp (Eq. 24)
Rz * Cz * Cp
φm = (360 / 2π ) * [tan-1(ωc/ ωz) - tan-1(ωc/ ωp)] (Eq. 25)
To ensure stability in the loop, the phase margin is recommended to be > 60° but too high will result in the lock time being excessively long. Certain loop filter
parameters would need to be compromised to not only meet a required loop bandwidth but to also maintain loop stability.
Example
Fc = 150KHz is the desired loop bandwidth. The total M value is 850. The ratio of ωp/ωc should be at least 4. A rule of thumb that will help to aid the way,
the ωp / ωc ratio should be at least 4. Given Fc and M, an optimal loop filter setting needs to be solved for that will meet both the PLL loop bandwidth and maintain
loop stability.
The charge pump gain should be relatively small as possible to achieve a low loop bandwidth.
Ip = 40uA .
Kφ * KVCO = 950MHz/V * 40uA = 38000A/Vs
Loop Bandwidths
ωc = 2π * Fc = 9.42x105 s-1
ωuz = ωp / ωc = 4 (Eq. 26)
ωc2 = ωp * ωz(Eq. 27)
ωp = Cz + Cp = ωz (1 + Cz / Cp)
Rz * Cz * Cp
Solving for Cz, Cp, and Rz
Knowing ωc = Rz * Kφ * KVCO * Cz and substituting in the equations from above,
M * (Cz + Cp)
Cz >>> Cp, therefore, we can easily derive Cp to be
Cp = Kφ * KVCO = 12.60pF
M * ωc2 * ωuz
Similarly for Cz and Rz
Cz = Kφ * KVCO * (ωuz2 - 1) = Cp * (ωuz2 - 1) = 189pF
M * ωc2 * ωuz
Rz = M * ωc * ωuz2 = 22.48KΩ
Kφ * KVCO * (ωuz2 - 1)
Based on the loop filter parameter equations from above, since there are no possible values of 12.60pF for Cp, 189pF for Cz, and 22.48KΩ for Rz, the next
possible values within the loop filter settings are 12.55pF (CP[3:0]=1111), 196.4pF (CZ[3:0]=0111), and 15.3KΩ (RZ[3:0]=1111), respectively. This loop filter
setting will yield a loop bandwidth of about 102KHz. The phase margin must be checked for loop stability.
φm = (360 / 2π ) * [tan-1 (6.41x105 s-1 / 3.33x105 s-1) - tan-1 (6.41x105 s-1 / 5.54x106 s-1)] = 56°
Although slightly below 60°, the phase margin would be acceptable with a fairly stable loop.
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INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
GIN2 Pin GIN1 Pin GIN0 Pin PLL0 Configuration Selection (Mode 1)
0 0 0 Configuration 0
0 0 1 Configuration 1
0 1 0 Configuration 2
0 1 1 Configuration 3
1 0 0 Configuration 4
1 0 1 Configuration 5
1 1 0 Configuration 6
1 1 1 Configuration 7
CONFIGURING THE MULTI-PURPOSE I/Os
The 5V9885T can operate in four distinct modes. These modes are controlled by the MFC bit (0x04) and the I2C/JTAG pin. The general purpose I/O pins
(GIN0, GIN1, GIN2, GIN3, GIN4, GIN5) have different uses depending on the mode of operation. The four available modes of operation are:
1) Manual Frequency Control (MFC) Mode for PLL0 Only
2) Manual Frequency Control (MFC) Mode for all three PLLs
3) I2C Programming Mode
4) JTAG Programming Mode
Along with the GINx pins are also GOUTx output pins that can take up a different function depending on the mode of operation. See table below for description.
Each PLL's programming registers can store up to four different Dx and Mx configurations in combination with two different P configurations in MFC modes.
The post-divider should never be disabled in any of the two P configurations unless the output bank will never be used during normal operation. The PLL's
loop filter settings also has four different configurations to store and select from. This will be explained in the MODE1 and MODE2 sections. The use of the GINx
pins in MFC mode control the selection of these configurations.
MODE1 - Manual Frequency Control (MFC=1) Mode for PLL0 Only
In this mode, only 8 configurations of PLL0 can be changed during operation. The GIN0, GIN1 and GIN2 pins control the selection of eight different
configurations (D, M, Rz, Cz, Cp and Ip) of PLL0. GIN3 becomes PLL SUSPEND pin, GIN4 is not available to users, and GIN5 becomes CLK_SEL pin.
The output GOUT0 will become an indicator for loss of PLL lock (LOSS_LOCK). GOUT1 pin will become an indicator for loss of the primary clock
(LOSS_CLKIN).
The PLL0 has 4 sets of dedicated registers for D, M, Rz, Cz, Cp, Ip and ODIV. For additional 4 sets of registers, the PLL0 uses registers from CONFIG2
and CONFIG3 of PLL1 and PLL2. The PLL1 and PLL2 will still be fully operational, but have only one fixed configuration in this mode, and the default
configuration will be set to CONFIG0 of PLL1 and CONFIG0 of PLL2. (Please see page 18 for register location.)
The output banks will each have two P configurations that can be associated with each of the PLL configurations. Each of the two P configurations has its
own set of PM bits (See the PRE-SCALERS, FEEDBACK-DIVIDERS, POST-DIVIDERS section for more detail on the PM bits). Use the ODIV bit to
choose which post-divider configuration to associate with a specific PLL configuration.
To enter this mode, users must set MFC bit to “1”, and I2C/JTAG pin must be left floating.
NOTE:
1. Please see detail description in Loss of Lock and Input Clock section.
Multi-Purpose Pins Other Signal Functions Signal Description
GIN0 SDAT / TDI I2C serial data input / JTAG serial data input
GIN1 SCLK / TCK I2C clock input / JTAG clock input
GIN2 TMS JTAG control signal to the TAP controller state machine
GIN3 SUSPEND Suspends all outputs of PLL (Active High)
GIN4 TRST JTAG active LOW input to asynchronously reset the BST
GIN5 CLK_SEL Reference clock select between XTALIN/REFIN and CLKIN
GOUT0 TDO / LOSS_LOCK JTAG serial data output / Detects loss of PLL lock(1)
GOUT1 LOSS_CLKIN Detects loss of the primary clock source(1)
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INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
MODE3 - I2C Programming Mode
In this mode, GIN0, GIN1, GIN3 and GIN5 become SDAT (I2C data), SCLK (I2C clock), SUSPEND and CLK_SEL signal pins, respectively. The output GOUT0
will become an indicator for loss of PLL lock (LOSS_LOCK). GOUT1 pin will become an indicator for loss of the primary clock (LOSS_CLKIN). GIN2 and GIN4
are not available to users.
To enter this mode, I2C/JTAG pin must be set HIGH.
MODE4 - JTAG Programming Mode
In this mode, GIN0, GIN1, GIN2, GIN3, GIN4 and GIN5 will become TDI (JTAG data in), TCK (JTAG clock), TMS (JTAG control signal), SUSPEND, TRST
(JTAG reset) and CLK_SEL signal pins, respectively. The output GOUT0 will become JTAG TDO signal, and GOUT1 will be an indicator for loss of the selected
clock (LOSS_CLKIN).
To enter this mode, I2C/JTAG pin must be set LOW.
MODE2 - Manual Frequency Control (MFC=0) Mode for all PLLs
In this mode, the configuration of PLL0, PLL1, and PLL2 can be changed during operation. The GINx pins are used to control the selection of up to four different
Dx, Mx, RZx, CZx, CPx, and IPx configurations for each PLL. GIN0 and GIN1 become configuration selection pins for D0 and M0 of PLL0, GIN2 and GIN3
become configuration selection pins for PLL1, and GIN4 and GIN5 become configuration selection pins for D2 and M2 of PLL2. The output GOUT0 will become
an indicator for loss of PLL lock (LOSS_LOCK). GOUT1 pin will become an indicator for loss of the primary clock (LOSS_CLKIN).
The output banks will have two different P configurations to choose from for each of the four PLL configurations. Each of the two P configurations has its own
set of PM bits (See the PRE-SCALERS, FEEDBACK-DIVIDERS, POST-DIVIDERS section for more detail on the PM bits). Use the ODIV bit to choose which
post-divider configuration to associate with a specific PLL configuration. For example, if ODIV2_CONFIG2=1, then when Config2 is selected Qx[9:0]_CONFIG1
is selected as the post-divider value to be used. Note that there is an ODIVx bit for each of the PLL configurations. In this way, the post-divider values can change
with the configuration.
To enter this mode, users must set MFC bit to "0", and I2C/JTAG pin must be left floating.
GIN1 Pin GIN0 Pin PLL0 Configuration Selection (Mode 2)
0 0 Configuration 0
0 1 Configuration 1
1 0 Configuration 2
1 1 Configuration 3
GIN3 Pin GIN2 Pin PLL1 Configuration Selection (Mode 2)
0 0 Configuration 0
0 1 Configuration 1
1 0 Configuration 2
1 1 Configuration 3
GIN5 Pin GIN4 Pin PLL2 Configuration Selection (Mode 2)
0 0 Configuration 0
0 1 Configuration 1
1 0 Configuration 2
1 1 Configuration 3
Manual Frequency Control modes
Multi-Purpose pins Mode1 Mode2 JTAG I2C
GIN0 GIN0 GIN0 TDI SDAT
GIN1 GIN1 GIN1 TCK SCLK
GIN2 GIN2 GIN2 TMS n/a
GIN3 SUSPEND GIN3 SUSPEND SUSPEND
GIN4 n/a GIN4 TRST n/a
GIN5 CLK_SEL GIN5(1) CLK_SEL CLK_SEL
GOUT0 LOSS_LOCK LOSS_LOCK TDO LOSS_LOCK
GOUT1 LOSS_CLKIN LOSS_CLKIN LOSS_CLKIN LOSS_CLKIN
NOTE:
1. The PLL(s) will lock onto the primary clock and the manual switchover can be controlled by the PRIMCLK bit.
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INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
Understanding the GIN Signals
During power up, the part will virtually be in MFC mode2, therefore, the values of GIN4, GIN3, GIN2, GIN1 and GIN0 will be latched and used for PLL
configuration selection, regardless of the state of the I2C/JTAG pin. GIN5 is not latched, and will assume the LOW state internally when in programming mode.
This means that when in programming mode, the PLL configuration can only be changed by writing directly to the registers of the currently selected configuration.
When in MFC mode 2, configuration 0 or 1 (GIN5=0) should be selected if you do not want to change configurations when entering or leaving programming
mode. The GIN pins should be held LOW during power up to select configuration0 as default.
When not in programming mode, the GIN inputs directly control the selected configuration. The internal GINx signals can be individually disabled via
programming the GINEN bits (0x06). When disabled by setting GINENx to "0", the GINx inputs may be left floating, but during power up, the GIN pins will still
latch. Disabled inputs are interpreted as LOW by the internal state machines. Even if disabled, GIN2, GIN1, GIN0 and GIN4 pins will be enabled if required
for I2C or JTAG programming functions when in programming mode. The SUSPEND and CLK_SEL functions on the GIN3 and GIN5 pins, respectively, will
be rendered completely non-functional when disabled.
SHUTDOWN/SUSPEND/ENABLE OF OUTPUTS
There are two external pins along with internal bits that control the enabling/disabling of the output banks. The two pins are the SHUTDOWN/OE pin and
the GIN3/SUSPEND pin. The SHUTDOWN/OE pin can be programmed to function as an output enable or global shutdown. The polarity of the SHUTDOWN/
OE signal pin can be programmed to be either active HIGH or LOW with the SP bit (0x1C). When SP is "0", the pin becomes active HIGH and when SP is
"1", the pin becomes active LOW. The SH bit(0x1C) determines the function of the SHUTDOWN/OE signal pin. If SH is "1", the signal pin is SHUTDOWN
and functions as a global shutdown. This will override the OEx (0x1C), OSx (0x1D), and PLLSx (0x1E) bits. If SH is "0", the signal pin is OE and functions
as an enable/disable of the output banks. If used as an output enable/disable, each output bank can be individually programmed to be enabled or disabled
by the OE pin.by setting OEx bits to "1". If the OE signal pin is asserted, the output banks that has their corresponding OEx bit set to "1" will be disabled. The
OEMx bits determine the outputs' disable state. When set to "0x" the outputs will be tristated. When set to "10", the outputs will be pulled low. When set to "11",
the outputs will be pulled high. Inverted outputs will be parked in the opposite state. If the OEx bits are set to "0", the states of the corresponding output banks
will not be impacted by the state of the OE pin. To individually enable/disable via programming instead of the OE pin, hard wire the OE pin to Vdd or GND (depending
if it is active HIGH or LOW) as if to disable the outputs. Then toggle the OEx bits to either "0" to enable or "1" to disable.
When the chip is in shutdown, the outputs, the reference oscillator, and the I2C /JTAG pin are powered down. The outputs will be tristated and the I2C
/JTAG pin will be set to MFC mode (MID level). Programming will not be allowed. The GINx pins and clock inputs remain operational. The PLL is not disabled.
The SHUTDOWN pin must be reasserted in order to program the part or to resume operation.
The GIN3/SUSPEND pin, when used as a SUSPEND function, can be used to power down the PLL and/or output banks.. Each output bank can be
individually programmed to be enabled or disabled by the SUSPEND signal pin by setting the OSx bits to "1". If the SUSPEND signal pin is asserted, the output
banks that has their corresponding OSx bit set to "1" will be powered down and outputs tristated. If the OSx bits are set to "0", the states of the corresponding
output banks will not be impacted by the state of the SUSPEND pin. There is also an option to suspend individual PLLs by setting the PLLSx bits (0x1E) to
"1". This will associate the PLL to the SUSPEND pin. When the pin is asserted, the corresponding PLLs will be powered down. It will not only power down
the PLL but also any output bank associated with it. The PLLSx bits will override the OSx bits.
In the event of a PLL suspend, the PLL must achieve lock again after it has been re-enabled, In the event of a global shutdown, the PLL does not have
to re-acquire lock since it is not disabled.
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INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
MFC = 0
MANUAL FREQUENCY CONTROL (MFC) BLOCK DIAGRAM
NOTES:
This illustration shows how the configurations are arranged for each PLL. There is an ODIV bit associated with each of the four configurations.
-GIN0 and GIN1 control four configurations from PLL0.
-GIN2 and GIN3 control four configurations from PLL1.
-GIN4 and GIN4 control four configurations from PLL2.
-ODIV from each configuration determines the selection of two Output Divider Px Configurations.
CONFIG0
CONFIG1
Output Divider P2
ODIV
CONFIG0
CONFIG1
CONFIG2
CONFIG3
PLL0
Prescaler "D"
CONFIG0
CONFIG1
CONFIG2
CONFIG3
ODIV
ODIV
ODIV
ODIV
VCO
Multiplier "M"
CONFIG0
CONFIG1
Output Divider P3
ODIV
CONFIG0
CONFIG1
CONFIG2
CONFIG3
PLL1
Prescaler "D"
CONFIG0
CONFIG1
CONFIG2
CONFIG3
PLL2
Prescaler "D"
CONFIG0
CONFIG1
CONFIG2
CONFIG3
ODIV
ODIV
ODIV
ODIV
VCO
Multiplier "M"
OUTPUT MUX
CONFIG0
CONFIG1
CONFIG2
CONFIG3
ODIV
ODIV
ODIV
ODIV
VCO
Multiplier "M"
18
INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
MFC = 1
NOTES:
This illustration shows how the configurations are arranged for PLL0. Register location for Config_4 and Config_5 are taken from PLL1, and Config_6 and Config_7 are taken from
PLL2. There is an ODIV bit associated with each of the configurations.
-GIN0, GIN1, and GIN2 control eight shaded configurations for PLL0.
-ODIV from each configuration determines the selection of two Output Divider Px Configurations.
MANUAL FREQUENCY CONTROL (MFC) BLOCK DIAGRAM
CONFIG0
CONFIG1
Output Divider P2
ODIV
CONFIG0
CONFIG1
CONFIG2
CONFIG3
PLL0
Prescaler "D"
CONFIG0
CONFIG1
CONFIG2
CONFIG3
ODIV
ODIV
ODIV
ODIV
VCO
Multiplier "M"
CONFIG0
CONFIG1
Output Divider P3
ODIV
CONFIG0
CONFIG4
CONFIG5
PLL1
Prescaler "D"
CONFIG0
CONFIG4
CONFIG5
ODIV
ODIV
ODIV
VCO
Multiplier "M"
CONFIG0
CONFIG6
CONFIG7
PLL2
Prescaler "D"
CONFIG0
CONFIG6
CONFIG7
ODIV
ODIV
ODIV
VCO
Multiplier "M"
OUTPUT MUX
19
INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
BLOCK DIAGRAM FOR SHUTDOWN/OE CONTROL SIGNAL
NOTE:
This illustration shows the internal logic behind the SHUTDOWN/OE pin and the bits associated with it.
OE2
01
10
11
Q2 + 2
/2
PM2
/2
01
10
11
Q3 + 2
/2
PM3
/2
OE3
01
10
11
Q6 + 2
/2
PM6
/2
OE6
01
10
11
Q5 + 2
/2
PM5
/2
OE5
01
10
11
Q4 + 2
/2
PM4
/2
OE4
OE1
MUX
OUT1
OUT3
OUT2
OUT6
OUT4
OUT4
OUT5
OUT5
SHUTDOWN/OE
SP SH
OE MODE
Global SHUTDOWN Mode:
Assert to Shutdown power on the outputs
and 3-Level Pin
20
INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
POWER UP AND POWER SAVING FEATURES
If a global shutdown is enabled, SHUTDOWN pin asserted, most of the chip except for the PLLs will be powered down. In order to have a complete
power down of the chip, the PLLs must be powered down via the SUSPEND function or by setting the pre-scaler bits to '0x00' and disable the internal
GINx signals via the enable bits at memory address 0x05. Note that the register bits will not lose their state in the event of a chip power-down. The only
possibility that the register bits will lose their state is if the part was power-cycled. After coming out of shutdown mode, the PLLs will require time to relock.
During power up, the values of GIN4, GIN3, GIN2, GIN1 and GIN0 will be latched and used for PLL configuration selection, regardless of the state of the
I2C/JTAG pin and GINx being disabled via the GINENx bits. GIN5 will have an internal state of LOW. The GIN pins should be held LOW during power up
to select configuration0 as default. The output levels will be at an undefined state during power up.
The post-divider should never be disabled via PM bits after power up, or else it will render the output bank completely non-functional during normal
operation, (unless the output bank itself will not be used at all).
During power up, the VDD ramp must be monotonic.
LOSS OF LOCK AND INPUT CLOCK
The device employs a loss of lock and loss of input clock detection circuitry. The GOUT0/LOSS_LOCK and GOUT1/LOSS_CLKIN are the outputs that
indicate such failures. LOSS_LOCK signal will be asserted if any of the three powered up PLLs loses frequency lock for any event other than PLL
shutdown. Lock is determined by checking that the reference and feedback clocks are within 1/2 period of each other.Loss_LOCK signal may be falsely
asserted when
- Spread Spectrum is turned on for any of the PLLs
- Fractional divider is used for any of the PLLs
- the reference and feedback clocks are not within 1/2 period of each other.
LOSS_CLKIN is asserted when the currently selected clock is lost or is asserted when both clocks are lost. In the event of the selected clock being
absent up on power up, the loss of the selected clock detection circuitry will reference an internal oscillator. LOSS_LOCK and LOSS_CLKIN cannot be
used as reliable inputs to other devices.
SWITCHOVER MODES
The IDT5V9885T features redundant clock inputs which supports both Automatic and Manual switchover mode. These two modes are determined by
the configuration bits, SM (0x34). The primary clock source can be programmed, via the PRIMCLK bit, to be either XTALIN/REFIN or CLKIN, which is
determined by the PRIMCLK bit. The other clock source input will be considered as the secondary source. This is more detailed in the 'REFERENCE
CLOCK INPUT PINS AND SELECTION'. Note that the switchover modes are asynchronous. If the reference clocks are directly routed to OUTx with no
phase relationship, short pulses can be generated during switchover. The automatic switchover mode will work only when the primary clock source is
XTALIN/REFIN.
MANUAL SWITCHOVER MODE
When SM[1:0] is "0x", the redundant inputs are in manual switchover mode. In this mode, CLK_SEL pin is used to switch between the primary and
secondary clock sources. As previously mentioned, the primary and secondary clock source setting is determined by the PRIMCLK bit. During the
switchover, no glitches will occur at the output of the device, although there may be frequency and phase drift, depending on the exact phase and
frequency relationship between the primary and secondary clocks. If GOUT1 is used as LOSS_CLKIN, it indicates loss of primary clock.
AUTOMATIC SWITCHOVER MODE
When SM[1:0] is "11", the redundant inputs are in automatic revertive switchover mode.
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INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
Programming
Interface Block
EEPROM
Cell
PLLs and Control
Blocks
I C or JTAG
interface
2 Write Enable
I/Os I/Os
Volatile
Configuration
Non-Volatile
Configuration
NOTE: Diagram does not represent actual number of die on chip.
HIGH LEVEL BLOCK DIAGRAM FOR CONFIGURATION SCHEME
Revertive
The input clock selection will switch to the secondary clock source when there are no transitions on the primary clock source. LOSS_CLKIN signals will
be asserted. After a stable and valid primary clock source is present, the input clock selection will automatically switch back to the primary clock source and
LOSS_CLKIN signal will be deasserted. The CLK_SEL pin can be left floating in this auto-revertive mode. Note that both clock inputs must be at the same
frequency (within1000 ppm) in order for the auto-revertive switchover to function properly. If both reference clocks are at different frequencies, the device
will always remain on the primary clock unless it is absent for two secondary clock cycles.
CLOCK SWITCH MATRIX AND OUTPUTS
All three PLL outputs and the currently selected input clock source are routed into and through a clock matrix. The user is able to select which PLL output
and clock source is routed to which output bank via the SRCx bits (0x34, 0x35). Each output bank has its own set of SRC bits. Refer to the RAM table for
more information. Note that OUT1 will be based off the reference clock and the only output bank toggling under the default RAM bit settings.
Outputs 1, 2 and 3 are 3.3V LVTTL. Outputs banks 4 and 5 can be 3.3V LVTTL, LVPECL or LVDS. The LVDS and LVPECL selection is determined
by the LVLx bits (0x54, 0x58). Each output bank has individual slew-rate control (SLEWx bits). Each output can be individually inverted (INVx bits);
when using LVPECL or LVDS modes, one of the outputs in each LVPECL/LVDS pair should be inverted. All output banks except OUT1 have a
programmable 10-bit post-divider (Qx bits) with two selectable divide configurations via the ODIVx bits.
There are four settings for the programmable slew rate, 0.7V/ns, 1.25V/ns, 2V/ns, and 2.75V/ns; this only applies to the 3.3V LVTTL outputs. The
differential outputs are not slew rate programmable in LVPECL or LVDS modes. SLEW4 and/or SLEW5 must be set to 2.75V/ns for stable output operation
. For LVTTL output frequency rates higher than 100MHz, a slew rate of 2V/ns or greater should be selected. The post-dividers can be disabled using
the PMx bit, which is described in the PRE-SCALER, FEEDBACK-DIVIDER, AND POST-DIVIDER section. Each output can also be enabled/disabled,
which is described in the 'SHUTDOWN/SUSPEND/ENABLE of OUTPUTS' section. Refer to the RAM table for all binary settings.
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INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
PROGRAMMING THE DEVICE
I2C and JTAG may be used to program the 5V9885T. The I2C/JTAG pin selects the I2C when HIGH and JTAG when LOW. Note that the TRST pin needs
to be LOW for I2C mode.
Hardwired Parameters for the IDT5V9885T
JTAG identification number = 32'b0000_0000001110101100_00000110011_1
Device (slave) address = 7'b1101010
ID Byte for the 5V9885T = 8'b00010000
I2C PROGRAMMING
The 5V9885T is programmed through an I2C-Bus serial interface, and is an I2C slave device. The read and write transfer formats are supported. The first
byte of data after a write frame to the correct slave address is interpreted as the register address; this address auto-increments after each byte written or read.
The frame formats are shown below.
SDA
SCL
S
Start
Condition
Data Frame
Data is stable during
clock HIGH Stop
Condition
P
SCL
SDA
MSB LSB
R/W
7-bit slave address
R/W
0 - Slave will be written by master
1 - Slave will be read by master
The first byte transmitted by the Master is the Slave Address followed by the R/W bit.
The Slave acknowledges by sending a "1" bit.
ACK from Slave
1 1 0 1 0 1 0
Figure 1: Framing
Figure 2: First Byte Transmittetd on I2C Bus
Each frame starts with a "Start Condition" and ends with an "End Condition". These are both generated by the Master device.
23
INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
EXTERNAL I2C INTERFACE CONDITION
PROGWRITE
Writes can continue as long as a Stop condition is not sent and each byte will increment the register address.
PROGREAD
S Address R/W ACK Command Code Register Data PACKACK ACK
7-bits 0 1-bit 8-bits: xxxxxx00 1-bit 8-bits 1-bit 8-bits 1-bit
S Address R/W ACK Command Code Register PACKACK
7-bits 0 1-bit 8-bits: xxxxxx00 1-bit 8-bits 1-bit
ACK
8-bits
Data_1
1-bit
Sr Address R/W ACK ID Byte NACK
7-bits 1 1-bit 8 bits 1-bit
P
ACK
8-bits
Data_2
1-bit
ACK
8-bits
Data_last
1-bit
Figure 3: Progwrite Command Frame
Note: If the expected read command is not from the next higher register to the previous read or write command, then set a known "read" register address
prior to a read operation by issuing the following command:
KEY:
From Master to Slave
From Master to Slave, but can be omitted if followed by the correct sequence
Normally data transfer is terminated by a STOP condition generated by the Master. However, if the Master still wishes to communicate on the bus, it can
generate a repeated START condition, and address another Slave address without first generating a STOP condition.
From Slave to Master
SYMBOLS:
ACK - Acknowledge (SDA LOW)
NACK - Not Acknowledge (SDA HIGH)
Sr - Repeated Start Condition
S - START Condition
P - STOP Condition
12345
12345
12345
12345
The user can ignore the STOP condition above and use a repeated START condition instead, straight after the slave acknowledgement bit (i.e., followed by
the Progread command):
Note: Figure 4b above by itself is the Progread command format. The ID byte for the 5V9885T is 10hex. Each byte recieved increments the register address.
Figure 4a: Prior to Progread Command Set Register Address
Figure 4b: Progread Command Frame
24
INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
EEPROM INTERFACE
The IDT5V9885T can also store its configuration in an internal EEPROM. The contents of the device's internal programming registers can be saved to the
EEPROM by issuing a save instruction (ProgSave) and can be loaded back to the internal programming registers by issuing a restore instruction (ProgRestore).
To initiate a save or restore using I2C, only two bytes are transferred. The Device Address is issued with the read/write bit set to "0", followed by the appropriate
command code. The save or restore instruction executes after the STOP condition is issued by the Master, during which time the IDT5V9885T will not generate
Acknowledge bits. The IDT5V9885T will acknowledge the instructions after it has completed execution of them. During that time, the I2C bus should be interpreted
as busy by all other users of the bus.
Using JTAG, the ProgSave and ProgRestore instructions selects the BYPASS register path for shifting the data from TDI to TDO during the data register scanning.
During the execution of a ProgSave or ProgRestore instruction, the IDT5V9885T will not accept a new programming instruction (read, write, save, or restore).
All non-programming JTAG instructions will function properly, but the user should wait until the save or restore is complete before issuing a new programming
instruction. If a new programming instruction is issued before the save or restore completes, the new instruction is ignored, and the BYPASS register path remains
in effect for shifting data from TDI to TDO during data register scanning.
The time it takes for the save (TSAVE) and restore (TRESTORE) instructions to complete is:
TSAVE = 100ms max, TRESTORE = 10 ms max
PROGSAVE
PROGRESTORE
NOTE:
PROGWRITE is for writing to the 5V9885T registers.
PROGREAD is for reading the 5V9885T registers.
PROGSAVE is for saving all the contents of the 5V9885T registers to the EEPROM.
PROGRESTORE is for loading the entire EEPROM contents to the 5V9885T registers.
S Address R/W ACK Command Code ACK
7-bits 0 1-bit 8-bits:xxxxxx01 1-bit
P
S Address R/W ACK Command Code ACK
7-bits 0 1-bit 8-bits:xxxxxx10 1-bit
P
JTAG INTERFACE
In addition to the IEEE 1149.1 instructions EXTEST, SAMPLE/PRELOAD,
CLAMP, HIGH-Z and BYPASS, the 5V9885T allows access to internal
programming registers using the REGADDR (set register address), REGDATAR
(read register) and REGDATW (write register instructions. Data is always
accessed by byte, and the register address increments after each read or write.
The full instruction set follows. The IDT5V9885T will be updating the registers
during programming.
The JTAG TAP controller can be reset in one of four ways:
1) Power up in JTAG mode
2) Power up in I2C mode and then go into JTAG mode, or go out of and back
into JTAG mode with the I2C/JTAG pin
3) Apply TRST while in JTAG mode
4) Apply five rising edges of TCK with TMS high while in JTAG mode
IR (3) IR (2) IR (1) IR (0) Instructions
0 0 0 0 EXTEST(1)
0 0 0 1 SAMPLE/PRELOAD(1)
0 0 1 0 IDCODE(1)
0 0 1 1 REGADDR(2)
0 1 0 0 REGDATAW / PROGWRITE(3)
0 1 0 1 REGDATAR / PROGREAD(4)
0 1 1 0 PROGSAVE(5)
0 1 1 1 PROGRESTORE(6)
1 0 0 0 CLAMP(1)
1 0 0 1 HIGHZ(1,7)
1 1 1 1 BYPASS(1)
JTAG INSTRUCTION REGISTER
DESCRIPTION
NOTES:
1. IEEE 1149.1 definition
2. REGADDR is for setting a specific 5V9885T register address.
3. REGDATAW/PROGWRITE is for writing to the 5V9885T registers.
4. REGDATAR/PROGREAD is for reading the 5V9885T registers.
5. PROGSAVE is for saving all the contents of the 5V9885T registers to the EEPROM.
6. PROGRESTORE is for loading the entire EEPROM contents to the 5V9885T registers.
7. The OEMs bits for OUT1-6 must be set for tri-state when using the HIGHZ instruction
25
INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
Standard JTAG Timing
NOTE:
t1 = tTCLKLOW
t2 = tTCLKHIGH
t3 = tTCLKFALL
t4 = tTCLKRISE
t5 = tRST (reset pulse width)
t6 = tRSR (reset recovery)
TCLK
TDI/TMS
TDO
TRST
tTCLK
t1 t2
t3
t4
t5
t6
tDS tDH
tDO
TDO
JTAG
AC ELECTRICAL CHARACTERISTICS
NOTE:
1. Guaranteed by design.
SYSTEM INTERFACE PARAMETERS
Symbol Parameter Min. Max. Units
tDO Data Output(1) —20 ns
tDOH Data Output Hold(1) 0—ns
tDS Data Input, tRISE = 3ns 10 —ns
tDH Data Input, tFALL = 3ns 10 —ns
NOTE:
1. 50pF loading on external output signals.
Symbol Parameter Min. Max. Units
tTCLK JTAG Clock Input Period 100 —ns
tTCLKHIGH JTAG Clock HIGH 40 —ns
tTCLKLOW JTAG Clock Low 40 —ns
tTCLKRISE JTAG Clock Rise Time —5(1) ns
tTCLKFALL JTAG Clock Fall Time —5(1) ns
tRST JTAG Reset 50 —ns
tRSR JTAG Reset Recovery 50 —ns
In order for the save and restore instructions to function properly, the IDT5V9885T must not be in shutdown mode (SHUTDOWN pin asserted). In the event
of an interrupt of some sort such as a power down of the part in the middle of a save or restore operation, the contents to or from the EEPROM will be partially
loaded, and a CRC error will be generated. The CERR bit (0x81) will be asserted to indicate that an error has occurred. The LOSS_LOCK signal will also
be asserted.
On power-up of the IDT5V9885T, an automatic restore is performed to load the EEPROM contents into the internal programming registers. The auto-restore
will not function properly if the device is in shutdown mode (SHUTDOWN pin asserted). The IDT5V9885T will be ready to accept a programming instruction
once it acknowledges its 7-bit I2C address.
26
INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
I2C BUS DC CHARACTERISTICS
Symbol Parameter Conditions Min Typ Max Unit
VIH Input HIGH Level 0.7 * VDD V
VIL Input LOW Level 0.3 * VDD V
VHYS Hysteresis of Inputs 0.05 * VDD V
IIN Input Leakage Current ±1.0 µA
VOL Output LOW Voltage IOL = 3 mA 0.4 V
I2C BUS AC CHARACTERISTICS FOR STANDARD MODE
Symbol Parameter Min Typ Max Unit
FSCLK Serial Clock Frequency (SCLK) 0100 KHz
tBUF Bus free time between STOP and START 4.7 µs
tSU:START Setup Time, START 4.7 µs
tHD:START Hold Time, START 4µs
tSU:DATA Setup Time, data input (SDAT) 250 ns
tHD:DATA Hold Time, data input (SDAT)(1) 0µs
tOVD Output data valid from clock 3.45 µs
CBCapacitive Load for Each Bus Line 400 pF
tRRise Time, data and clock (SDAT, SCLK) 1000 ns
tFFall Time, data and clock (SDAT, SCLK) 300 ns
tHIGH HIGH Time, clock (SCLK) 4µs
tLOW LOW Time, clock (SCLK) 4.7 µs
tSU:STOP Setup Time, STOP 4µs
I2C BUS AC CHARACTERISTICS FOR FAST MODE
Symbol Parameter Min Typ Max Unit
FSCLK Serial Clock Frequency (SCLK) 0400 KHz
tBUF Bus free time between STOP and START 1.3 µs
tSU:START Setup Time, START 0.6 µs
tHD:START Hold Time, START 0.6 µs
tSU:DATA Setup Time, data input (SDAT) 100 ns
tHD:DATA Hold Time, data input (SDAT)(1) 0µs
tOVD Output data valid from clock 0.9 µs
CBCapacitive Load for Each Bus Line 400 pF
tRRise Time, data and clock (SDAT, SCLK) 20 + 0.1 * CB300 ns
tFFall Time, data and clock (SDAT, SCLK) 20 + 0.1 * CB300 ns
tHIGH HIGH Time, clock (SCLK) 0.6 µs
tLOW LOW Time, clock (SCLK) 1.3 µs
tSU:STOP Setup Time, STOP 0.6 µs
NOTE:
1. A device must internally provide a hold time of at least 300ns for the SDAT signal (referred to the VIHMIN of the SCLK signal) to bridge the undefined region of the falling edge
of SCLK.
NOTE:
1. A device must internally provide a hold time of at least 300ns for the SDAT signal (referred to the VIHMIN of the SCLK signal) to bridge the undefined region of the falling edge
of SCLK.
27
INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
Symbol Description Max Unit
VDD Internal Power Supply Voltage -0.5 to +4.6 V
VIInput Voltage -0.5 to +4.6 V
VOOutput Voltage(2) -0.5 to VDD + 0.5 V
TJJunction Temperature 150 °C
TSTG Storage Temperature –65 to +150 °C
ABSOLUTE MAXIMUM RATINGS(1)
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Not to exceed 4.6V.
NOTE:
1. Capacitance levels characterized but not tested.
Symbol Parameter Min. Typ. Max. Unit
CIN Input Capacitance —4—pF
Crystal Specifications
XTAL_FREQ Crystal Frequency 8—50 MHz
XTAL_MIN Minimum Crystal Load Capacitance —3.5 —pF
XTAL_MAX Maximum Crystal Load Capacitance —35.4 —pF
Crystal Load Capacitance Resolution —0.125 —
XTAL_VPP Voltage Swing (peak-to-peak, nominal) —2.3 —V
CAPACITANCE (TA = +25°C, f = 1MHz, VIN = 0V)(1)
Symbol Description Min. Typ. Max. Unit
VDD Power Supply Voltage for LVTTL 33.3 3.6 V
Power Supply Voltage for LVDS/LVPECL 3.135 3.3 3.465
TAOperating Temperature, Ambient –40 —+85 °C
CLOAD_OUT Maximum Load Capacitance (LVTTL only) — — 15 pF
FIN External Reference Crystal 8 — 50 MHz
External Reference Clock, Industrial 1 — 400
tPU Power-up time for all VDDs to reach minimum specified voltage 0.05 — 5ms
(power ramps must be monotonic)
RECOMMENDED OPERATING CONDITIONS
28
INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
POWER SUPPLY CHARACTERISTICS FOR LVTTL OUTPUTS
Symbol Parameter Test Conditions Typ. Max Unit
IDDQ Quiescent VDD Power Supply Current REF = LOW 6 12 mA
Outputs enabled, All outputs unloaded
IDDD Dynamic VDD Power Supply VDD = Max., CL = 0pF 40 60 µA/MHz
Current per Output
FREFERENCE CLOCK = 33MHz, CL = 15pf 26 40
ITOT Total Power VDD Supply Current FREFERENCE CLOCK = 133MHz, CL = 15pf 80 120 mA
FREFERENCE CLOCK = 200MHz, CL = 15pf 112 170
NOTES:
1. These inputs are normally wired to VDD, GND, or left floating. If these inputs are switched dynamically after powerup, the function and timing of the outputs may be glitched, and
the PLL may require additional tAQ time before all datasheet limits are achieved.
2. Dividers must reload reprogrammed values via power-on reset or terminal count reload in order to ensure low-power mode.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VIHH Input HIGH Voltage Level(1) I2C/JTAG 3-Level Input VDD – 0.4 — — V
VIMM Input MID Voltage Level(1) I2C/JTAG 3-Level Input VDD/2 – 0.2 —VDD/2 + 0.2 V
VILL Input LOW Voltage Level(1) I2C/JTAG 3-Level Input — — 0.4 V
VIN = VDD HIGH Level — — 200
I33-Level Input DC Current VIN = VDD/2 MID Level –50 —+50 µA
VIN = GND LOW Level –200 — —
IDD Total Power Supply Current 2 outputs @166MHz; 4 outputs @ 83MHz —120 —mA
(3.3V Supply, VDD)2 outputs @20MHz; 4 outputs @ 40MHz —40 —
IDDS Total Power Supply Current in Global Shutdown Mode —2—mA
Shutdown Mode(2) (PLLs, dividers, outputs, etc. powered down)
DC ELECTRICAL CHARACTERISTICS FOR 3.3V LVTTL(1)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
IOH Output HIGH Current VOH = VDD - 0.5, VDD = 3.3V ± 0.3V 12 24 —mA
IOL Output LOW Current VOL = 0.5V, VDD = 3.3V ± 0.3V 12 24 —mA
VIH Input Voltage HIGH 2— — V
VIL Input Voltage LOW — — 0.8 V
IIH Input HIGH Current(2) VIN = VDD — — 10 µA
IIL Input LOW Current VIN = 0V — — 10 µA
IOZD Output Leakage Current 3-state outputs — — 10 µA
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. IIH specification does not apply to inputs with internal pull-down.
29
INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
DC ELECTRICAL CHARACTERISTICS FOR LVDS
Symbol Parameter Min. Typ. Max Unit
VOT (+) Differential Output Voltage for the TRUE binary state 247 —454 mV
VOT (-) Differential Output Voltage for the FALSE binary state -247 —-454 mV
∆ VOT Change in VOT between Complimentary Output States — — 50 mV
VOS Output Common Mode Voltage (Offset Voltage) 1.125 1.2 1.375 V
∆ VOS Change in VOS between Complimentary Output States — — 50 mV
IOS Outputs Short Circuit Current, VOUT+ or VOUT- = 0V or VDD —924 mA
IOSD Differential Outputs Short Circuit Current, VOUT+ = VOUT-—612 mA
POWER SUPPLY CHARACTERISTICS FOR LVDS OUTPUTS(1)
Symbol Parameter Test Conditions(2) Typ. Max Unit
IDDQ Quiescent VDD Power Supply Current REF = LOW 68 90 mA
Outputs enabled, All outputs unloaded
IDDD Dynamic VDD Power Supply VDD = Max., CL = 0pF 30 45 µA/MHz
Current per Output
FREFERENCE CLOCK = 100MHz, CL = 5pf 86 130
ITOT Total Power VDD Supply Current FREFERENCE CLOCK = 200MHz, CL = 5pf 100 150 mA
FREFERENCE CLOCK = 400MHz, CL = 5pf 122 190
POWER SUPPLY CHARACTERISTICS FOR LVPECL OUTPUTS(1)
Symbol Parameter Test Conditions(2) Typ. Max Unit
IDDQ Quiescent VDD Power Supply Current REF = LOW 86 110 mA
Outputs enabled, All outputs unloaded
IDDD Dynamic VDD Power Supply VDD = Max., CL = 0pF 35 50 µA/MHz
Current per Output
FREFERENCE CLOCK = 100MHz, CL = 5pf 120 180
ITOT Total Power VDD Supply Current FREFERENCE CLOCK = 200MHz, CL = 5pf 130 190 mA
FREFERENCE CLOCK = 400MHz, CL = 5pf 140 210
DC ELECTRICAL CHARACTERISTICS FOR LVPECL
Symbol Parameter Min. Typ. Max Unit
VOH Output Voltage HIGH, terminated through 50Ω tied to VDD - 2V VDD - 1.2 —VDD - 0.9 V
VOL Output Voltage LOW, terminated through 50Ω tied to VDD - 2V VDD - 1.95 —VDD - 1.61 V
VSWING Peak to Peak Output Voltage Swing 0.55 —0.93 V
NOTES:
1. Output banks 4 and 5 are toggling. Other output banks are powered down.
2. The termination resistors are excluded from these measurements.
NOTES:
1. Output banks 4 and 5 are toggling. Other output banks are powered down.
2. The termination resistors are excluded from these measurements.
30
INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
AC TIMING ELECTRICAL CHARACTERISTICS
(SPREAD SPECTRUM GENERATION = OFF)
Symbol Parameter Test Conditions Min. Typ. Max Unit
fIN Input Frequency Input Frequency Limit 1(1) —400 MHz
1/t1 Output Frequency Single Ended Clock output limit (LVTTL) 0.0049 — 200 MHz
Differential Clock output limit (LVPECL/ LVDS) 0.0049 — 500
fVCO VCO Frequency VCO operating Frequency Range 10 —1200 MHz
fPFD PFD Frequency PFD operating Frequency Range 0.4(1) —400 MHz
fBW Loop Bandwidth Based on loop filter resistor and capacitor values 0.03 —40 MHz
t2 Input Duty Cycle Duty Cycle for Input 40 —60 %
t3 Output Duty Cycle Measured at VDD/2, FOUT ≤ 200MHz45 — 55 %
Measured at VDD/2, FOUT > 200MHz40 — 60
Slew Rate Single-Ended Output clock rise and fall time, — 2.75 —
SLEWx(bits) = 00 20% to 80% of VDD (Output Load = 15pf)
Slew Rate Single-Ended Output clock rise and fall time, —2 —
t4(2) SLEWx(bits) = 01 20% to 80% of VDD (Output Load = 15pf) V/ns
Slew Rate Single-Ended Output clock rise and fall time, — 1.25 —
SLEWx(bits) = 10 20% to 80% of VDD (Output Load = 15pf)
Slew Rate Single-Ended Output clock rise and fall time, — 0.75 —
SLEWx(bits) = 11 20% to 80% of VDD (Output Load = 15pf)
Rise Times LVDS, 20% to 80% — 850 —
t5 Fall Times — 850 —ps
Rise Times LVPECL, 20% to 80% — 500 —
Fall Times — 500 —
t6 Output three-state Timing Time for output to enter or leave three-state mode — — 150 + ns
after SHUTDOWN/OE switches 1/FOUTX
t7 Clock Jitter(3,7) Peak-to-peak period jitter, fPFD > 20MHz — —150 ps
CLK outputs measured at VDD/2 fPFD < 20MHz — 200 —
t8 Output Skew Skew between output to output on the same bank — — 150 ps
(bank 4 and bank 5 only)(4, 5)
t9 Lock Time PLL Lock Time from Power-up(6) — 10 20 ms
t10 Lock time(8) PLL Lock time from shutdown mode —20 100 µs
NOTES:
1. Practical lower input frequency is determined by loop filter settings.
2. A slew rate of 2V/ns or greater should be selected for output frequencies of 100MHz and higher.
3. Input frequency is the same as the output with all output banks running at the same frequency.
4. Skew measured between all in-phase outputs in the same bank.
5. Skew measured between the cross points of all differential output pairs under identical input and output interfaces, transitions and load conditions on any one device.
6. Includes loading the configuration bits from EEPROM to PLL registers. It does not include EEPROM programming/write time.
7. Guaranteed by design but not production tested. Actual jitter performance may vary depending on the configuration.
8. Actual PLL lock time depends on the loop configuration.
SPREAD SPECTRUM GENERATION SPECIFICATIONS
Symbol Parameter Description Min. Typ. Max Unit
fIN Input Frequency Input Frequency Limit 1(1) —400 MHz
fMOD Mod Freq Modulation Frequency —33 —kHz
fSPREAD Spread Value Amount of Spread Value (Programmable) - Down Spread -0.5, -1, -2.5, -3.5, -4 %fOUT
Amount of Spread Value (Programmable) - Center Spread -2.0 to +2.0
NOTE:
1. Practical lower input frequency is determined by loop filter settings.
31
INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
OUTPUTS
VDD
GND
0.1µFCLOAD
CLKOUT
TEST CIRCUITS AND CONDITIONS(1)
Test Circuits for DC Outputs
OTHER TERMINATION SCHEME (BLOCK DIAGRAM)
OUTPUTS
GND
CLOAD
CLKOUT
CLOAD
CLKOUT
RLOAD
VDD-2V
OUTPUTS
GND
OUTPUTS
GND
CLOAD
CLKOUT
CLOAD
CLKOUT
RLOAD
VDD-2V
CLOAD
CLKOUT
RLOAD
LVTTL: -15pF for each output
LVPECL: - 50
ΩΩ
ΩΩ
Ω
to VDD-2V for each output with 5pF
LVDS: - 100
ΩΩ
ΩΩ
Ω
between differential outputs with 5pF
NOTE:
1. All VDD pins must be tied together.
32
INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
RAM (PROGRAMMING REGISTER) TABLES
XDRV=crystal drive strength ("00" = 1.4V, "01" = 2.3V, "10"= 3.2V pk-pk swing typical, "11"=XTAL_IN with external clock-
default); When "11", XTALCAP[7:0] value must also be set to "0".
Bits 7,6, 3, 2, 1, 0 are reserved and should be set to "0"
XTAL load cap = 3.5pF+ (0.125 x XTALCAP[7:0]) , 3.5pF to 35.4pF; Each XTAL pin to GND;
(For example, "00000001"=0.125pF, "00000010"=0.25pF, "00000100"=0.5pF); Default = "00000000";
No registers exist.
MFC=Manual Frequency Control Mode ('0'=All PLL Control (Default), "1"=PLL0 Control Only );
GINEN0 to GINEN5=GINx Pins Enable Bits, ("1"=Enable (Default), "0"=No Connect (Internal State will be "Low"));
PLL0 LOOP FILTER SETTING
ADDR 7 6 5 4 3 2 1 0 Register
Hex Value 7 6 5 4 3 2 1 0
0x00
0x01
0x02
0x03
0x04 0 0 0 0 0 0 0 0 00 MFC
0x05 1 1 1 1 1 1 1 1 FF GINEN5 GINEN4 GINEN3 GINEN2 GINEN1 GINEN0
0x06 0 0 1 1 0 0 0 0 30
0x07 0 0 0 0 0 0 0 0 00
0x08 0 0 0 0 0 0 0 0 00 ODIV0_CONFIG0
0x09 0 0 0 0 0 0 0 0 00 ODIV0_CONFIG1
0x0A 0 0 0 0 0 0 0 0 00 ODIV0_CONFIG2
0x0B 0 0 0 0 0 0 0 0 00 ODIV0_CONFIG3
0x0C 0 0 0 0 0 0 0 0 00
0x0D 0 0 0 0 0 0 0 0 00
0x0E 0 0 0 0 0 0 0 0 00
0x0F 0 0 0 0 0 0 0 0 00
0x10 0 0 0 0 0 0 0 0 00
0x11 0 0 0 0 0 0 0 0 00
0x12 0 0 0 0 0 0 0 0 00
0x13 0 0 0 0 0 0 0 0 00
BIT # BIT #
D0 [7:0]_CONFIG3
D0 [7:0]_CONFIG0
RZ0[3:0]_CONFIG3IP0[2:0]_CONFIG3
CP0[3:0]_CONFIG1
CZ0[3:0]_CONFIG0CP0[3:0]_CONFIG0
CZ0[3:0]_CONFIG1
CZ0[3:0]_CONFIG3
CP0[3:0]_CONFIG2
D0 [7:0]_CONFIG1
CZ0[3:0]_CONFIG2
CP0[3:0]_CONFIG3
D0 [7:0]_CONFIG2
RZ0[3:0]_CONFIG1
Reserved
IP0[2:0]_CONFIG1
RZ0[3:0]_CONFIG2IP0[2:0]_CONFIG2
IP0[2:0]_CONFIG0 RZ0[3:0]_CONFIG0
XDRV[1:0]
XTALCAP[7:0]
DESCRIPTION
XDRV=crystal drive strength ("00" = 1.4V, "01" = 2.3V, "10"= 3.2V pk-pk swing typical, "11"=XTAL_IN with external clock-default); When
"11", XTALCAP[7:0] value must also be set to "0".
Bits 7,6, 3, 2, 1, 0 are reserved and should be set to "0"
XTAL load cap = 3.5pF+ (0.125 x XTALCAP[7:0]) , 3.5pF to 35.4pF; Each XTAL pin to GND;
(For example, "00000001"=0.125pF, "00000010"=0.25pF, "00000100"=0.5pF); Default = "00000000" ;
No registers exist
MFC=Manual Frequency Control Mode ('0'=All PLL Control (Default), "1"=PLL0 Control Only );
GINEN0 to GINEN 5=GINx Pins Enable Bits, ("1"=Enable (Default ), "0"=No Connect (Internal State will be "Low"));
PLL0 LOOP FILTER SETTING
ODIV0_CONFIGx=Determines whic h one of the 2 "Qx-Divider" Configurations to use wi
PLL0 INPUT DIVIDER D0 SETTING
0x14 0 0 0 0 0 0 0 0 00
0x15 0 0 0 0 0 0 0 0 00
0x16 0 0 0 0 0 0 0 0 00
0x17 0 0 0 0 0 0 0 0 00
0x18 0 0 0 0 0 0 0 0 00
0x19 0 0 0 0 0 0 0 0 00
0x1A 0 0 0 0 0 0 0 0 00
0x1B 0 0 0 0 0 0 0 0 00
0x1C 0 0 0 0 0 0 0 0 00 SP SH OE6 OE5 OE4 OE3 OE 2 OE1
0x1D 0 1 0 0 0 0 0 0 40 OKC OS6 OS5 OS4 OS3 OS 2 OS1
0x1E 0 0 0 0 0 0 0 0 00 PLLS2 PLLS1 PLLS0
N0 [7:0]_CONFIG0
N0[11:8]_CONFI G0
A0[3:0]_CONFIG3
N0 [7:0]_CONFIG2
A0[3:0]_CONFIG0
A0[3:0]_CONFIG2
A0[3:0]_CONFIG1 N0[11:8]_CONFIG1
N0[11:8]_CONFI G3
N0[11:8]_CONFI G2
N0 [7:0]_CONFIG3
N0 [7:0]_CONFIG1
SP=Shutdown/OE Polarity for SHUTDOWN/OE signal pin, ("0"= Active High (Default), "1"= Active Low);
OE x=Output Disable Function for OUTx, ("1"=OUTx disabled based on OE pin (Default for OUT2-6, Disable mode is defined by OEMx
bits), "0"= Outputs enabled and no association with OE pin (Default));
OS x=Output Power Suspend function for OUTx, ("1"=OUTx will be suspended on GIN3/SUSPEND pin (MFC="1"), "0"= Always Enabled
(Default));
PLLSx=Determines which PLLx to suspend when GIN3 is programmed to be used as SUSPEND, It suspends all the outputs associated
with that PLL, ("1"= suspends based on SUSPEND pin, "0"= PLL enabled and no association with SUSPEND pin (Default)); It over-rides
OS x bi ts;
SH=Determines the function of the SHUTDOWN/OE signal pin. ("1"=Global Shutdown; this over-ri des OEx and OSx bits, "0"=Ouput
Enable/Disable (Default))
OK C=clock OK count, "0"=8 cycles, "1"=1024 cycles (Default) of Input Clocks for Revertive Switchover Mode:
Address 0x1D, Bit 7; Address 0x1E, Bits [7:3] are reserved and should be set to "0"
PLL0 MULTIPLIER SET TING
CONFI G0 will be selected if GINx are disabled and operating in MFC mode.
N0[11:0]_CONFIGx - Part of PLL0 M Int eger Feedback Divider Values (see equation below) - For 4 Configurations (Default value is '0');
A0[3:0]_CONFIGx - Part of PLL0 M Integer Feedback Divider Values (see equation below) - For 4 Configurations (Default value is '0');
SSC_OFFSET0[5:0] - Spread Spectrum Fractional Multiplier Offset Value. See Spread Spectrum Settings in register address range
0x60-0x67
Tot al Multiplier Value M0 = 2 * N0[11:0] + A0 + 1 + SS_OFFSET0 * 1/64
When A0[3:0] = 0 and spread spectrum disabled, M0= 2 * N0[11:0];
When A0[3:0] > 0 and spread spectrum disabled, M0 = 2 * N0[11:0] + A0 + 1;
(Note: A < N-1, i.e. valid M values are 2, 4, 6, 8, 9, 10, 11, 12, 13, ..., 4095 assuming within fPFD and fVCO spec);
33
INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
RAM (PROGRAMMING REGISTER) TABLES
ADDR 7 6 5 4 3 2 1 0
Default
Register
Hex Value
7 6 5 4 3 2 1 0
BIT #
BIT #
(Default Settings)
DESCRIPTION
0x1F 0 0 0 0 0 0 0 0 00 INV1
0x20 0 0 0 0 0 0 0 0 00 ODIV1_CONFIG0
0x21 0 0 0 0 0 0 0 0 00 ODIV1_CONFIG1
0x22 0 0 0 0 0 0 0 0 00 ODIV1_CONFIG2
0x23 0 0 0 0 0 0 0 0 00 ODIV1_CONFIG3
0x24 0 0 0 0 0 0 0 0 00
0x25 0 0 0 0 0 0 0 0 00
0x26 0 0 0 0 0 0 0 0 00
0x27 0 0 0 0 0 0 0 0 00
0x28 0 0 0 0 0 0 0 0 00
0x29 0 0 0 0 0 0 0 0 00
0x2A 0 0 0 0 0 0 0 0 00
0x2B 0 0 0 0 0 0 0 0 00
0x2C 0 0 0 0 0 0 0 0 00
0x2D 0 0 0 0 0 0 0 0 00
0x2E 0 0 0 0 0 0 0 0 00
0x2F 0 0 0 0 0 0 0 0 00
0x30 0 0 0 0 0 0 0 0 00
0x31 0 0 0 0 0 0 0 0 00
0x32 0 0 0 0 0 0 0 0 00
0x33 0 0 0 0 0 0 0 0 00
0x34 0 1 0 0 0 1 1 0 46 PRIMCLK
0x35 0 1 0 1 0 1 0 1 55
SRC1[1:0] SM[1:0]SRC2[1:0]
OEM1[1;0] SLEW1[1:0]
CP1[3:0]_CONFIG3
A1[3:0]_CONFIG2
N1[7:0]_CONFIG1
N1[7:0]_CONFIG3
D1[7:0]_CONFIG0
N1[11:8]_CONFIG0
CP1[3:0]_CONFIG2
D1[7:0]_CONFIG3
N1[7:0]_CONFIG0
CZ1[3:0]_CONFIG3
D1[7:0]_CONFIG2
CZ1[3:0]_CONFIG2
D1[7:0]_CONFIG1
CP1[3:0]_CONFIG1 CZ1[3:0]_CONFIG1
RZ1[3:0]_CONFIG2
SRC6[1:0] SRC5[1:0] SRC4[1:0]
CP1[3:0]_CONFIG0
IP1[2:0]_CONFIG2
N1[11:8]_CONFIG2
A1[3:0]_CONFIG3 N1[11:8]_CONFIG3
A1[3:0]_CONFIG1 N1[11:8]_CONFIG1
CZ1[3:0]_CONFIG0
RZ1[3:0]_CONFIG0
RZ1[3:0]_CONFIG3
RZ1[3:0]_CONFIG1
SRC3[1:0]
N1[7:0]_CONFIG2
A1[3:0]_CONFIG0
IP1[2:0]_CONFIG0
IP1[2:0]_CONFIG1
IP1[2:0]_CONFIG3
Configuring Output OUT1
INV1=Output Inversion for OUT1 ("0"= Non-Invert (Default), "1"=Invert);
SLEW1=Slew Rate Settings for OUT1 output ("00"= 2.75V/ns (Default), "01"=2V/ns, "10"=1.25V/ns, "11"=0.7V/ns);
OEM1= Output Enable Mode for OUT1 output, when used with OE1 bit and SHUTDOWN/OE pin ("0x" = Tri-state (Default), "10"=Park
Low, "11"=Park High);
Address 0x1F, Bits 3, 1, 0 are reserved and should be set to "0"
PRIMCLK=Priority Selection for Input Clock ("0"=XTALIN/REF_IN becomes Primary (Default), "1"=CLK_IN becomes Primary);
SM = Switchover Mode ("0x"=Manual, "10"= Auto-NonRevertive, "11"=Auto-Revertive (Default));
Bit 3 is reserved and should be set to "0".
SRCx[1:0]=Input Source Selection for Output Dividers "Qx" blocks ("00"=Selected Input CLK, "01"=PLL0, "10"=PLL1, "11"=PLL2);
Default on SRC1 is the selected input clock. Default on SRC2-6 is PLL0 which will be powered down.
PLL1 LOOP FILTER SETTING
Loop Filter Values for PLL1 - For 4 Configurations (Default value is '0');
CONFIG0 will be selected if GINx are disabled and operating in MFC mode.
ODIV1_CONFIGx=Determines which one of the 2 "Qx-Divider" Configurations to use with, for any of the "Qx-Divider" block associated
with PLL1; Used in MFC mode; Default ODIV value is "0", and use CONFIG0 of Qx-Divider;
Resistor = 0.3KΩ + RZ1[3:0] * 1KΩ, 0.3 to 15.3kOhm with 1kOhm Step, ("0000"=0.3kOhm, "0001"=1.3kOhm, "0010"=2.3kOhm, ...);
Zero capacitor = 6pF + CZ1[3:0] * 27.2pF, 6pF to 414pF with 27.2pF Step, ("0000"=6pF, "0001"=33.2pF, "0010"=60.4pF", ...);
Pole capacitor = 1.3pF + CP1[3:0] * 0.75pF, 1.3pF to 12.55pF with 0.75pF Step, ("0000"=1.3pF, "0001"=2.05pF, "0010"=2.8pF, ...)
Charge pump current = 5 * 2^IP1[2:0] µA, 5uA to 640uA with 5, 10, 20, 40, ... binary step;
PLL1 INPUT DIVIDER D1 SETTING
PLL1 D-Divider Values (Prescaler) - For 4 Configurations (Default value is '0');
PLL1 MULTIPLIER SETTING
CONFIG0 will be selected if GINx are disabled and operating in MFC mode.
N1[11:0]_CONFIGx - Part of PLL1 M Integer Feedback Divider Values (see equation below) - For 4 Configurations (Default value is '0');
A1[3:0]_CONFIGx - Part of PLL1 M Integer Feedback Divider Values (see equation below) - For 4 Configurations (Default value is '0');
SSC_OFFSET1[5:0] - Spread Spectrum Fractional Multiplier Offset Value. See Spread Spectrum Settings in register address range
0x68-0x6F
Total Multiplier Value M1 = 2 * N1[11:0] + A1 + 1 + SS_OFFSET1 * 1/64
When A1[3:0] = 0 and spread spectrum disabled, M1= 2 * N1[11:0];
When A1[3:0] > 0 and spread spectrum disabled, M1 = 2 * N1[11:0] + A1 + 1 ;
(Note: A < N-1, i.e. valid M values are 2, 4, 6, 8, 9, 10, 11, 12, 13, ..., 4095 assuming within fPFD and fVCO spec);
0x36
0x37
0x38 0 0 0 0 0 0 0 0 00 ODIV2_CONFIG0
0x39 0 0 0 0 0 0 0 0 00 ODIV2_CONFIG1
0x3A 0 0 0 0 0 0 0 0 00 ODIV2_CONFIG2
0x3B 0 0 0 0 0 0 0 0 00 ODIV2_CONFIG3
0x3C 0 0 0 0 0 0 0 0 00
0x3D 0 0 0 0 0 0 0 0 00
0x3E 0 0 0 0 0 0 0 0 00
0x3F 0 0 0 0 0 0 0 0 00
CP2[3:0]_CONFIG2
CP2[3:0]_CONFIG1
IP2[2:0]_CONFIG0
RZ2[3:0]_CONFIG1IP2[2:0]_CONFIG1
RZ2[3:0]_CONFIG0
CZ2[3:0]_CONFIG1
IP2[2:0]_CONFIG3
IP2[2:0]_CONFIG2
RZ2[3:0]_CONFIG3
RZ2[3:0]_CONFIG2
CZ2[3:0]_CONFIG0
CZ2[3:0]_CONFIG2
CP2[3:0]_CONFIG0
CP2[3:0]_CONFIG3 CZ2[3:0]_CONFIG3
No Registers Exist
PLL2 LOOP FILTER SETTING
Loop Filter Values for PLL2 - For 4 Configurations (Default value is '0');
CONFIG0 will be selected if GINx are disabled and operating in MFC mode.
ODIV2_CONFIGx=Determines which one of the 2 "Qx-Divider" Configurations to use with, for any of the "Qx-Divider" block associated with
PLL2; Used in MFC mode; Default ODIV value is "0", and use CONFIG0 of Qx-Divider;
Resistor = 0.3KΩ + RZ2[3:0] * 1KΩ, 0.3 to 15.3kOhm with 1kOhm Step, ("0000"=0.3kOhm, "0001"=1.3kOhm, "0010"=2.3kOhm, ...);
Zero capacitor = 6pF + CZ2[3:0] * 27.2pF, 6pF to 414pF with 27.2pF Step, ("0000"=6pF, "0001"=33.2pF, "0010"=60.4pF", ...);
Pole capacitor = 1.3pF + CP2[3:0] * 0.75pF, 1.3pF to 12.55pF with 0.75pF Step, ("0000"=1.3pF, "0001"=2.05pF, "0010"=2.8pF, ...)
Charge pump current = 5 * 2^IP2[2:0] µA, 5uA to 640uA with 5, 10, 20, 40, ... binary step;
34
INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
RAM (PROGRAMMING REGISTER) TABLES
ADDR 7 6 5 4 3 2 1 0 Register
Hex Value 7 6 5 4 3 2 1 0
0x40 0 0 0 0 0 0 0 0 00
0x41 0 0 0 0 0 0 0 0 00
0x42 0 0 0 0 0 0 0 0 00
0x43 0 0 0 0 0 0 0 0 00
0x44 0 0 0 0 0 0 0 0 00
0x45 0 0 0 0 0 0 0 0 00
0x46 0 0 0 0 0 0 0 0 00
0x47 0 0 0 0 0 0 0 0 00
0x48 0 0 0 0 0 0 0 0 00
0x49 0 0 0 0 0 0 0 0 00
0x4A 0 0 0 0 0 0 0 0 00
0x4B 0 0 0 0 0 0 0 0 00
0x4C 0 0 0 0 0 0 0 0 00 INV2
0x4D 1 0 1 1 1 0 1 1 BB
0x4E 0 0 0 0 0 0 0 0 00
0x4F 0 0 0 0 0 0 0 0 00
0x50 0 0 0 0 0 0 0 0 00 INV 3
0x51 1 0 1 1 1 0 1 1 BB
0x52 0 0 0 0 0 0 0 0 00
0x53 0 0 0 0 0 0 0 0 00
BIT # BIT #
Q2[1:0]_CONFIG1
D2[7:0]_CONFIG1
Q2[9:2]_CONFIG0
D2[7:0]_CONFIG2
PM2[1:0]_CONFIG1 PM2[1:0]_CONFIG0
SLEW2[1:0]
N2[11:8]_CONFIG1
PM3[1:0]_CONFIG1 Q3[1:0]_CONFIG0 PM3[1:0]_CONFIG0
Q3[9:2]_CONFIG1
N2[11:8]_CONFIG3
N2[11:8]_CONFIG2
Q2[9:2]_CONFIG1
OEM2[1:0]
Q3[9:2]_CONFIG0
SLEW3[1:0]OEM3[1:0]
N2[11:8]_CONFIG0
N2[7:0]_CONFIG0
D2[7:0]_CONFIG3
N2[7:0]_CONFIG3
D2[7:0]_CONFIG0
N2[7:0]_CONFIG2
N2[7:0]_CONFIG1
Q2[1:0]_CONFIG0
Q3[1:0]_CONFIG1
0x54 0 0 0 0 1 1 0 0 0C INV4_1 INV 4_0
0x55 1 0 1 1 1 0 1 1 BB
0x56 0 0 0 0 0 0 0 0 00
0x57 0 0 0 0 0 0 0 0 00
0x58 0 0 0 0 1 1 0 0 0C INV5_1 INV 5_0
0x59 1 0 1 1 1 0 1 1 BB
0x5A 0 0 0 0 0 0 0 0 00
0x5B 0 0 0 0 0 0 0 0 00
0x5C 0 0 0 0 0 0 1 1 03 INV6
0x5D 1 0 1 1 1 0 1 1 BB
0x5E 0 0 0 0 0 0 0 0 00
0x5F 0 0 0 0 0 0 0 0 00
Q5[9:2]_CONFIG1
SLEW6[1:0]
Q6[9:2]_CONFIG1
PM6[1:0]_CONFIG0PM6[1:0]_CONFIG1Q6[1:0]_CONFIG1
Q5[1:0]_CONFIG0
Q6[9:2]_CONFIG0
OEM6[1:0]
PM5[1:0]_CONFIG1 PM5[1:0]_CONFIG0
Q5[9:2]_CONFIG0
Q5[1:0]_CONFIG1
Q6[1:0]_CONFIG0
SLEW5[1:0]OEM5[1:0]
Q4[9:2]_CONFIG0
LVL4[1:0]
LVL5[1:0]
Q4[9:2]_CONFIG1
PM4[1:0]_CONFIG1
SLEW4[1:0]
Q4[1:0]_CONFIG0
OEM4[1:0]
Q4[1:0]_CONFIG1 PM4[1:0]_CONFIG0
DES CR IPTION
P LL2 INPUT DIVIDER D2 SETTING
Configuring Output OUT3
IN V3=Output Inversion for OUT3 ("0"= Non-Invert (Default), "1"=Invert);
S LEW3=Slew Rate Settings for OUT3 output ("00"= 2.75V/ns (Default), "01"=2V/ns, "10"=1.25V/ns, "11"=0.7V/ns);
IN Vx PMx OEMx Qx SLEWx
Configuring Output OUT2
IN V2=Output Inversion for OUT2 ("0"= Non-Invert (Default), "1"=Invert);
S LEW2=Slew Rate Settings for OUT2 output ("00"= 2.75V/ns (Default), "01"=2V/ns, "10"=1.25V/ns, "11"=0.7V/ns);
IN V5_1=Output Inversion for /OUT5 ("0"= Invert, "1"=Non-Invert (Default));
IN V5_0=Output Inversion for OUT5 ("0"= Invert, "1"=Non-Invert (Default));
S LEW5=Slew rate settings for OUT5 output ("00"= 2.75V/ns (Defa ult), "0 1"=2V/ns, "10"=1.25V/ns, "11"=0.7V/ns);
OE M5= Output Enable Mode for OUT5 output, when used with OE5 bit and SHUTDOWN/OE pin ("0x" = Tri-state (Default), "10"=Park
Low, "11"=Park High);
LVL5=Output IO Standard Selection, ("00"=LVTTL (Default), "01"=LVDS, "10"=LVPECL, "11"=Reserved);
Q5[x:x]=Output Divider "Q5" Values (Default value is '2') - Support 2 output configurations when used in MFC mode;
P M5[x:x]=Divide Mode, ("00"=Divider Disabled;"01"=Divide by '1';"10"=Divide by 2; "11"=Divide by (Q+2) (Default));
(Note: To enable OUT5, PM5 register bit values for both CONFIG0 and CONFIG1 configurations must be non-zero.)
P LL2 MULTIPLIER SETTING
Total Multiplier Value
Configuring Output OUT5
IN V5_1=Output Inversion for /OUT5 ("0"= Invert, "1"=Non-Invert (Default));
IN V5_0=Output Inversion for OUT5 ("0"= Invert, "1"=Non-Invert (Default));
When using LVPECL or LVDS outputs, SLE W5 m ust be set to '00'.
Configuring Output OUT4
IN V4_1=Output Inversion for /OUT4 ("0"= Invert , "1"=Non-Invert (Default));
IN V4_0=Output Inversion for OUT4 ("0"= Invert , "1"=Non-Invert (Default));
35
INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
0x60 00000000 00
0x61 0 0 0 0 0 0 0 0 00 DITH0 X2_0
0x62 00000000 00
0x63 00000000 00
0x64 00000000 00
0x65 00000000 00
0x66 00000000 00
0x67 00000000 00
0x68 00000000 00
0x69 0 0 0 0 0 0 0 0 00 DITH1 X2_1
0x6A 00000000 00
0x6B 00000000 00
0x6C 00000000 00
0x6D 00000000 00
0x6E 00000000 00
0x6F 00000000 00
SD0[3:0][0]
SS_OFFSET1[5:0]
SD0[3:0][11]
SD0[3:0][1]
SD0[3:0][10]
SD0[3:0][3] SD0[3:0][2]
SD0[3:0][5]
SD0[3:0][6]
SD1[3:0][3]
NSSC0[3:0]TSSC0[3:0]
SD1[3:0][1]
TSSC1[3:0] NSSC1[3:0]
SD1[3:0][10]
SD1[3:0][9]
SD1[3:0][2]
SD0[3:0][4]
SD1[3:0][7]
SD0[3:0][7]
SD0[3:0][9]
SS_OFFSET0[5:0]
SD1[3:0][0]
SD0[3:0][8]
SD1[3:0][4]SD1[3:0][5]
SD1[3:0][8]
SD1[3:0][11]
SD1[3:0][6]
SPREAD SPRECTRUM SETTINGS FOR PLL0
SS_OFFSET0=SS Fractional Offset/ First Sample (Unsigned);
TSSC0=# of PFD Cycles Per SS Cycle Step, TSSC="0000" for SSC off (Default);
NSSC0=# of SS Samples to Use from SS Memory (Default is "0");
DITH0=LSB DITHER on Σ, ("1"=dither on, "0"=off (Default));
X2_0=Σ∆ output x2, ("1"=x2, "0"=normal (Default));
SD0=Delta-encoded samples (unsigned); Waveform start with SS_OFFSET0, then SS_OFFSET0+SD0[0], etc. (Default is "0");
SPREAD SPRECTRUM SETTINGS FOR PLL1
SS_OFFSET1=SS Fractional Offset/ First Sample (Unsigned);
TSSC1=# of PFD Cycles Per SS Cycle Step, TSSC="0000" for SSC off (Default);
NSSC1=# of SS Samples to Use from SS Memory (Default is "0");
DITH1=LSB DITHER on Σ∆, ("1"=dither on, "0"=off (Default));
X2_1=Σ∆ output x2, ("1"=x2, "0"=off (Default));
SD1=Delta-encoded samples (unsigned); Waveform start with SS_OFFSET1, then SS_OFFSET1+SD1[0], etc. (Default is "0");
RAM (PROGRAMMING REGISTER) TABLES
ADDR 7 6 5 4 3 2 1 0
Default
Register
Hex Value
7 6 5 4 3 2 1 0
BIT #
BIT #
(Default Settings)
DESCRIPTION
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
0x80
0x81 CERR
CRC error in EEPROM
CERR = CRC error bit indicator ("1`" = CRC error) Read-Only
No Registers Exist
36
INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
Package Outline and Package Dimensions (32-pin TQFP)
37
INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
RECOMMENDED LANDING PATTERN, 32-pin TQFP
38
INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
RECOMMENDED LANDING PATTERN, 28-pin VFQFPN
NL 28 pin
NOTE: All dimensions are in millimeters.
39
INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 clockhelp@idt.com
San Jose, CA 95138 fax: 408-284-2775
www.idt.com
Part Number Shipping Packaging Package Temperature
5V9885TPFGI Tubes 32-pin TQFP -40 to +85°C
5V9885TPFGI8 Tape and Reel 32-pin TQFP -40 to +85°C
5V9885TNLGI Tubes 28-pin VFQFPN -40 to +85°C
5V9885TNLGI8 Tape and Reel 28-pin VFQFPN -40 to +85°C
MARKING DIAGRAM (5V9885TPFGI)
MARKING DIAGRAM (5V9885TNLGI)
NOTES:
1. 'YYWW' is the date code.
2. '$' is the assembly mark code.
3. 'G' denotes RoHS compliant package.
4. 'I' denotes industrial temperature range.
5. Bottom marking: country of origin.
ORDERING INFORMATION
