Features
•Dual ADC with 8-bit Resolution
•500 Msps Sampling Rate per Channel, 1 Gsps in interleaved Mode
•Single or 1:2 Demultiplexed Output
•LVDS Output Format (100Ω)
•500 mVpp Analog Input (Differential Only)
•Differential or Single-ended 50Ω PECL/LVDS Compatible Clock Inputs
•Power Supply: 3.3V (Analog), 3.3V (Digital), 2.25V (Output)
•LQFP144 Package
•Temperature Range:
– 0°C < Tamb < 70°C (Commercial Grade)
– -40°C < Tamb < 85°C (Industrial Grade)
•3-wire Serial Interface
– 16-bit Data, 3-bit Address
– 1:2 or 1:1 Output Demultiplexer Ratio Selection
– Full or Partial Standby Mode
– Analog Gain (±1.5 dB) Digital Control
– Input Clock Selection
– Analog Input Switch Selection
– Binary or Gray Logical Outputs
– Synchronous Data Ready Reset
– Data Ready Delay Adjustable on Both Channels
– interleaving Functions:
Offset and Gain (Channel to Channel) Calibration
Digital Fine SDA (Fine Sampling Delay Adjust) on One Channel
– Internal Static or Dynamic Built-In Test (BIT)
Performance
•Low Power Consumption: 0.7W per Channel
•Power Consumption in Standby Mode: 120 mW
•1 GHz Full Power Input Bandwidth (-3 dB)
•SNR = 45 dB Typ (7.2 ENOB), THD = -53 dBc, SFDR = -56 dBc at Fs = 500 Msps
Fin = 250 MHz
•2-tone IMD3: -54 dBc (249 MHz, 251 MHz) at 500 Msps
•DNL = 0.25 LSB, INL = 0.5 LSB
•Low Bit Error Rate (10-18) at 500 Msps
Application
•Digital Oscilloscopes
•Communication Receivers (I/Q)
•Direct RF Down Conversion
•High Speed Data Acquisition
•Radar/ECM
Dual 8-bit
500 Msps ADC
AT84AD004B
Smart ADC™
5390B-BDC-02/06
2
5390B–BDC–02/06
AT84AD004B
1. Description
The AT84AD004B is a monolithic dual 8-bit analog-to-digital converter, offering low 1.4W power
consumption and excellent digitizing accuracy. It integrates dual on-chip track/holds that provide
an enhanced dynamic performance with a sampling rate of up to 500 Msps and an input fre-
quency bandwidth of 1 GHz. The dual concept, the integrated demultiplexer and the easy
interleaving mode make this device user-friendly for all dual channel applications, such as direct
RF conversion or data acquisition. The smart function of the 3-wire serial interface eliminates the
need for external components, which are usually necessary for gain and offset tuning and set-
ting of other parameters, leading to space and power reduction as well as system flexibility.
2. Functional Description
The AT84AD004B is a dual 8-bit 500 Msps ADC based on advanced high-speed
BiCMOS technology.
Each ADC includes a front-end analog multiplexer followed by a Sample and Hold (S/H), and an
8-bit flash-like architecture core analog-to-digital converter. The output data is followed by a
switchable 1:1 or 1:2 demultiplexer and LVDS output buffers (100Ω).
Two over-range bits are provided for adjustment of the external gain control on each channel.
A 3-wire serial interface (3-bit address and 16-bit data) is included to provide several
adjustments:
• Analog input range adjustment (±1.5 dB) with 8-bit data control using a 3-wire bus interface
(steps of 0.18 dB)
• Analog input switch: both ADCs can convert the same analog input signal I or Q
• Gray or binary encoder output. Output format: DMUX 1:1 or 1:2 with control of the output
frequency on the data ready output signal
• Partial or full standby on channel I or channel Q
• Clock selection:
– Two independent clocks: CLKI and CLKQ
– One master clock (CLKI) with the same phase for channel I and channel Q
– One master clock but with two phases (CLKI for channel I and CLKIB for channel Q)
• ISA: Internal Settling Adjustment on channel I and channel Q
• FiSDA: Fine Sampling Delay Adjustment on channel Q
• Adjustable Data Ready Output Delay on both channels
• Test mode: decimation mode (by 16), Built-in Test
A calibration phase is provided to set the two DC offsets of channel I and channel Q close to
code 127.5 and calibrate the two gains. The offset and gain error can also be set externally via
the 3-wire serial interface.
The AT84AD004B operates in fully differential mode from the analog inputs up to the digital out-
puts. The AT84AD004B features a full-power input bandwidth of 1 GHz.
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5390B–BDC–02/06
AT84AD004B
Figure 2-1. Simplified Block Diagram
DOIRI
DOIRIN
DOIRQ
DOIRQN
CLKI
Clock Buffer Divider
2 to16
DRDA
I
LVDS
Clock
Buffer
2CLKIO
DDRB
16 DOAI
DOAIN
8bit
ADC
I
DMUX
1:2
or
1:1
I
LVDS
Buffer
I
DoirI
INPUT
MUX
+
VINI
S/H 16 DOBI
DOBIN
VINIB 8
-2
Gain control I
Calibration
Gain/offset
ISA I DMUX control
BIT Data
Clock
Ldn
3-wire Serial Interface
3WSI
Input switch
Gain control Q
Calibration
Gain/offset
ISA Q & FiSDA
DMUX control Mode
2
DoirQ
LVDS
buffer
Q
8bit
ADC
Q
DMUX
1: 2
or
1: 1
Q
+
VINQ
S/H 16 DOAQ
DOAQN
VINQB
-816 DOBQ
DOBQN
CLKQ
Clock Buffer Divider
2 to 16
DRDA
Q
LVDS
Clock
Buffer
2CLKQO
DDRB
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5390B–BDC–02/06
AT84AD004B
3. Typical Applications
Figure 3-1. Satellite Receiver Application
Bandpass
Amplifier
11..12 GHz
Local Oscillator
Bandpass
Amplifier
1..2 GHz
Low Noise Converter
(Connected to the Dish)
090
Local Oscillator
Synthesizer
1.5 … 2.5 GHz
I
Q
AT84AD004
I
Q
Tunable
Band Filter
Control Functions:
Clock and Carrier
Recovery...
Clock
AGC
IF
Band Filter
Low Pass
Filter
Satellite Tuner
Demodulation
Dish
Satellite
Quadrature
I
Q
Q
5
5390B–BDC–02/06
AT84AD004B
Figure 3-2. Dual Channel Digital Oscilloscope Application
3.1 Absolute Maximum Ratings
Note: Absolute maximum ratings are limiting values (referenced to GND = 0V), to be applied individually, while other parameters are
within specified operating conditions. Long exposure to maximum ratings may affect device reliability.
Table 3-1. Absolute Maximum Ratings
Parameter Symbol Value Unit
Analog positive supply voltage VCCA 3.6 V
Digital positive supply voltage VCCD 3.6 V
Output supply voltage VCCO 3.6 V
Maximum difference between VCCA and VCCD VCCA to VCCD ± 0.8 V
Minimum VCCO VCCO 1.6 V
Analog input voltage VINI or VINIB
VINQ or VINQB
1/-1 V
Digital input voltage VD-0.3 to VCCD + 0.3 V
Clock input voltage VCLK or VCLKB -0.3 to VCCD + 0.3 V
Maximum difference between VCLK and VCLKB VCLK - VCLKB -2 to 2 V
Maximum junction temperature TJ125 °C
Storage temperature Tstg -65 to 150 °C
Lead temperature (soldering 10s) Tleads 300 °C
DAC
Gain
DAC
Offset
DAC
Offset
DAC
Gain
ADC B
ADC A
Timing
Circuit
FISO
RAM
Display
Analog Switch
Channel Mode
Selection
µP
Clock
Selection
DACs
DACs
Smart Dual
ADC
A
A
Channel B
Channel A
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5390B–BDC–02/06
AT84AD004B
3.2 Recommended Conditions of Use
4. Electrical Operating Characteristics
Unless otherwise specified:
•V
CCA = 3.3V; VCCD = 3.3V; VCCO = 2.25V
•V
INI - VINB or VINQ - VINQB = 500 mVpp full-scale differential input
• LVDS digital outputs (100Ω)
•T
amb (typical) = 25°C
• Full temperature range: 0°C < Tamb < 70°C (commercial grade)
Table 3-2. Recommended Conditions of Use
Parameter Symbol Comments Recommended Value Unit
Analog supply voltage VCCA 3.3 V
Digital supply voltage VCCD 3.3 V
Output supply voltage VCCO 2.25 V
Differential analog input voltage (full-scale) VINi -VIniB or
VINQ -VINQB
500 mVpp
Differential clock input level Vinclk 600 mVpp
Internal Settling Adjustment (ISA) with a 3-wire
serial interface for channel I and channel Q ISA 0 ps
Operating temperature range TAmbient
Commercial grade
Industrial grade
0 < Tamb < 70
-40 < Tamb < 85 °C
Table 4-1. Electrical Operating Characteristics in Nominal Conditions
Parameter Symbol Min Typ Max Unit
Resolution 8Bits
Power Requirements
Positive supply voltage
- Analog
- Digital
Output digital (LVDS) and serial interface
VCCA
VCCD
VCCO
3.15
3.15
2.0
3.3
3.3
2.25
3.45
3.45
2.5
V
V
V
Supply current (typical conditions)
- Analog
- Digital
- Output
ICCA
ICCD
ICCO
150
230
100
180
275
120
mA
mA
mA
Supply current (1:2 DMUX mode)
- Analog
- Digital
- Output
ICCA
ICCD
ICCO
150
260
175
180
310
210
mA
mA
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5390B–BDC–02/06
AT84AD004B
Supply current (2 input clocks, 1:2 DMUX mode)
- Analog
- Digital
- Output
ICCA
ICCD
ICCO
150
290
180
180
350
215
mA
Supply current
(1 channel only, 1:1 DMUX mode)
- Analog
- Digital
- Output
ICCA
ICCD
ICCO
80
160
55
95
190
65
mA
mA
mA
Supply current
(1 channel only, 1:2 DMUX mode)
- Analog
- Digital
- Output
ICCA
ICCD
ICCO
80
170
90
95
205
110
mA
mA
mA
Supply current (full standby mode)
- Analog
- Digital
- Output
ICCA
ICCD
ICCO
12
24
3
20
39
7
mA
mA
mA
Nominal dissipation
(1 clock, 1:1 DMUX mode, 2 channels) PD1.4 1.7 W
Nominal dissipation (full standby mode) stbpd 120 mW
Analog Inputs
Full-scale differential analog input voltage to
obtain full-scale with no gain adjust (mode 0)
VINi - VIniB
or
VINQ - VINQB
450 500 550
mV
mV
Analog input capacitance I and Q CIN 2pF
Full power input bandwidth (-3 dB) FPBW 1.0 GHz
Gain flatness (-0.5 dB) 400 MHz
Clock Input
Logic compatibility for clock inputs and DDRB
Reset (pins 124,125,126,127,128,129) PECL/ECL/LVDS
PECL/LVDS clock inputs and DDRB input
voltages (VCLKI/IN or VCLKQ/QN)
Differential logical level
VIL - VIH 600 mV
Clock input and DDRB input power level -9 0 6 dBm
Clock input capacitance 2 pF
Digital Outputs
Logic compatibility for digital outputs
(depending on the value of VCCO)LVDS
Differential output voltage swings
(assuming VCCO = 2.25V) VOD 220 270 350 mV
Table 4-1. Electrical Operating Characteristics in Nominal Conditions (Continued)
Parameter Symbol Min Typ Max Unit
8
5390B–BDC–02/06
AT84AD004B
Note: The gain setting is 0 dB, one clock input, no standby mode [full power mode], 1:1 DMUX, calibration off.
Note: The gain setting is 0 dB, two clock inputs, no standby mode [full power mode], 1:2 DMUX, calibration on.
Output levels (assuming VCCO = 2.25V)
100Ω differentially terminated
Logic 0 voltage
Logic 1 voltage
VOL
VOH
1.0
1.25
1.1
1.35
1.2
1.48
V
V
Output offset voltage (assuming VCCO = 2.25V)
100Ω differentially terminated VOS 1125 1250 1340 mV
Output impedance RO50 W
Output current (shorted output) 12 mA
Output current (grounded output) 30 mA
Output level drift with temperature 1.3 mV/°C
Digital Input (Serial Interface)
Maximum clock frequency (input clk) Fclk 50 MHz
Input logical level 0 (clk, mode, data, ldn) -0.4 0 0.4 V
Input logical level 1 (clk, mode, data, ldn) VCCO - 0.4 VCCO - 0.4 VCCO + 0.4 V
Output logical level 0 (cal) -0.4 0 0.4 V
Output logical level 1 (cal) VCCO - 0.4 VCCO VCCO + 0.4 V
Maximum output load (cal) 15 pF
Table 4-1. Electrical Operating Characteristics in Nominal Conditions (Continued)
Parameter Symbol Min Typ Max Unit
Table 4-2. Electrical Operating Characteristics
Parameter Symbol Min Typ Max Unit
DC Accuracy
No missing code Guaranteed over specified temperature range
Differential non-linearity DNL 0.25 0.6 LSB
Integral non-linearity INL 0.5 1 LSB
Gain error (single channel I or Q) with calibration -2 0 2 %
Input offset matching (single channel I or Q) with calibration -2 0 2 LSB
Gain error drift against temperature
Gain error drift against VCCA
0.062
0.064
LSB/°C
LSB/mV
Mean output offset code with calibration 126 127.5 129 LSB
Transient Performance
Bit Error Rate
Fs = 500 Msps
Fin = 250 MHz
BER 10-18 Error/
sample
ADC settling time channel I or Q
(between 10% - 90% of output response)
VIni -ViniB = 500 mVpp
TS 170 ps
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5390B–BDC–02/06
AT84AD004B
Notes: 1. Differential input [-1 dBFS analog input level], gain setting is 0 dB, two input clock signals, no standby mode,
1:1 DMUX, ISA = 0 ps.
2. Measured on the AT84AD004BTD-EB Evaluation Board
Table 4-3. AC Performance
Parameter Symbol Min Typ Max Unit
AC Performance
Signal-to-noise Ratio
Fs = 500 MspsFin = 20 MHz
SNR
44 46 dBc
Fs = 500 MspsFin = 250 MHz 43 45 dBc
Fs = 500 MspsFin = 500 MHz 42 44 dBc
Effective Number of Bits
Fs = 500 MspsFin = 20 MHz
ENOB
77.4 Bits
Fs = 500 MspsFin = 250 MHz 6.9 7.2 Bits
Fs = 500 MspsFin = 500 MHz 6.7 7.0 Bits
Total Harmonic Distortion (First 9 Harmonics)
Fs = 500 MspsFin = 20 MHz
|THD|
48 55 dBc
Fs = 500 MspsFin = 250 MHz 47 53 dBc
Fs = 500 MspsFin = 500 MHz 47 53 dBc
Spurious Free Dynamic Range
Fs = 500 MspsFin = 20 MHz
|SFDR|
50 57 dBc
Fs = 500 MspsFin = 250 MHz 49 56 dBc
Fs = 500 MspsFin = 500 MHz 49 56 dBc
Two-tone Inter-modulation Distortion (Single Channel)
FIN1 = 249 MHz , FIN2 = 251 MHz at Fs = 500 Msps IMD -54 dBc
Phase matching using auto-calibration and FiSDA
in interleaved mode (channel I and Q)
Fin = 250 MHz
Fs = 500 Msps
dϕ-0.7 0 0.7 °
Crosstalk channel I versus channel Q
Fin = 250 MHz, Fs = 500 Msps(2) Cr -55 dB
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5390B–BDC–02/06
AT84AD004B
Note: One analog input on both cores, clock I samples the analog input on the rising and falling edges. The calibration phase is nec-
essary. The gain setting is 0 dB, one input clock I, no standby mode, 1:1 DMUX, FiSDA adjustment.
Table 4-4. .AC Performances Over Full Industrial Temperature Range (-40°C < Tamb < 85° C)
Parameter Symbol Min Typ Max Unit
AC Performance
Signal-to-noise Ratio
Fs = 500 MspsFin = 500 MHz 41 44 dBc
Effective Number of Bits
Fs = 500 MspsFin = 500 MHz 6.5 7.0 Bits
Total Harmonic Distortion (First 9 Harmonics)
Fs = 500 MspsFin = 500 MHz 43 53 dBc
Spurious Free Dynamic Range
Fs = 500 MspsFin = 500 MHz 45 56 dBc
Table 4-5. AC Performances in Interleaved Mode
Parameter Symbol Min Typ Max Unit
Interleaved Mode
Maximum equivalent clock frequency Fint = 2 x Fs
Where Fs = external clock frequency Fint 1Gsps
Minimum clock frequency Fint 20 Msps
Differential non-linearity in interleaved mode intDNL 0.25 LSB
Integral non-linearity in interleaved mode intINL 0.5 LSB
Signal-to-noise Ratio in interleaved Mode
Fint = 1 GspsFin = 20 MHz iSNR 45 dBc
Fint = 1 GspsFin = 250 MHz 44 dBc
Effective Number of Bits in interleaved Mode
Fint = 1 GspsFin = 20 MHz iENOB 7.3 Bits
Fint = 1 GspsFin = 250 MHz 7.1 Bits
Total Harmonic Distortion in interleaved Mode
Fint = 1 GspsFin = 20 MHz |iTHD| 54 dBc
Fint = 1 GspsFin = 250 MHz 53 dBc
Spurious Free Dynamic Range in interleaved Mode
Fint = 1 GspsFin = 20 MHz |iSFDR| 56 dBc
Fint = 1 GspsFin = 250 MHz 55 dBc
Two-tone Inter-modulation Distortion (Single Channel) in interleaved Mode
FIN1 = 249 MHz , FIN2 = 251 MHz at Fint = 1 Gsps iIMD -54 dBc
11
5390B–BDC–02/06
AT84AD004B
Table 4-6. Switching Performances
Parameter Symbol Min Typ Max Unit
Switching Performance and Characteristics - See “Timing Diagrams” on page 12.
Maximum operating clock frequency FS500 Msps
Minimum clock frequency (no transparent mode) FS
10 Msps
Minimum clock frequency (with transparent mode) 1 Ksps
Minimum clock pulse width [high]
(No transparent mode) TC1 0.4 1 50 ns
Minimum clock pulse width [low]
(No transparent mode) TC2 0.4 1 50 ns
Aperture delay: nominal mode with ISA & FiSDA TA 1 ns
Aperture uncertainty Jitter 0.4 ps (rms)
Data output delay between input clock and data TDO 3.8 ns
Data Ready Output Delay TDR 3 ns
Data Ready Reset to Data Ready TRDR 2 ns
Data Output Delay with Data Ready TD2 1/2 Fs
+Tdrda ps
Data Ready (CLKO) Delay Adjust (140 ps steps) Tdrda range -560 to 420 ps
Output skew 50 100 ps
Output rise/fall time for DATA (20% - 80%) TR/TF 300 350 500 ps
Output rise/fall time for DATA READY (20% - 80%) TR/TF 300 350 500 ps
Data pipeline delay (nominal mode)
TPD
3 (port B)
3.5 (port A, 1:1 DMUX mode)
4 (port A, 1:2 DMUX mode) Clock cycles
Data pipeline delay (nominal mode) in S/H
transparent mode
2.5 (port B)
3 (port A, 1:1 DMUX mode)
3.5 (port A, 1:2 DMUX mode)
DDRB recommended pulse width 1 ns
12
5390B–BDC–02/06
AT84AD004B
Figure 4-1. Differential Inputs Voltage Span (Full-scale)
The analog input full-scale range is 0.5V peak-to-peak (Vpp), or -2 dBm into the 50Ω (100Ω dif-
ferential) termination resistor. In differential mode input configuration, which means 0.25V on
each input, or ±125 mV around common mode voltage.
4.1 Timing Diagrams
Figure 4-2. Timing Diagram, ADC I or ADC Q, 1:2 DMUX Mode, Clock I for ADC I, Clock Q for ADC Q
mV
+125
-125
500 mV
Full-scale
Analog Input
t
VIN VINB
+250 mV
-250 mV
0V
CLKOI or CLKOQ
(= CLKI/4)
CLKI or CLKQ
CLKOI or CLKOQ
(= CLKI/2)
Programmable delay
VIN
TA
N
N + 1 N + 2
N + 3
Pipeline delay = 4 clock cycles TDO
TD2
DOIA[0:7]
or DOQA[0:7]
N - 2
N - 4 N
DOIB[0:7]
or DOQB[0:7]
Pipeline delay = 3 clock cycles TDO
N - 3 N - 1 N +1
Address: D7 D6 D5 D4 D3 D2 D1 D0
1 1 X X 1 X 0 0
13
5390B–BDC–02/06
AT84AD004B
Figure 4-3. 1:1 DMUX Mode, Clock I = ADC I, Clock Q = ADC Q
Figure 4-4. 1:2 DMUX Mode, Clock I = ADC I, Clock I = ADC Q
CLKI or CLKQ
CLKOI or CLKOQ
VIN
TA
N
N + 1 N + 2 N + 3
Pipeline delay = 3.5 clock cycles TDO
DOIA[0:7]
or DOQA[0:7]
N - 1
N - 3 N + 1
N - 2 N
DOIB[0:7] and DOQB[0:7] are high impedance
Address: D7 D6 D5 D4 D3 D2 D1 D0
1 1 X X 0 X 0 0
CLKOI
(= CLKI/4)
CLKI
CLKOI
(= CLKI/2)
VIN
TA
N
N + 1 N + 2 N + 3
Pipeline delay = 4 clock cycles TDO
TD2
DOIA[0:7]
NI - 2
NI - 4 NI
DOIB[0:7]
Pipeline delay = 3 clock cycles TDO
NI - 3 NI - 1 NI +1
Address: D7 D6 D5 D4 D3 D2 D1 D0
1 0 X X 1 X 0 0
NQ - 4 NQ - 2 NQ
NQ - 3 NQ - 1 NQ +1
DOQA[0:7]
DOQB[0:7]
CLKOQ is high impedance
14
5390B–BDC–02/06
AT84AD004B
Figure 4-5. 1:1 DMUX Mode, Clock I = ADC I, Clock I = ADC Q
DOIB[0:7] and DOQB[0:7] are high impedance
CLKOQ is high impedance
CLKI
CLKOI
VIN
TA
N
N + 1 N + 2
N + 3
Pipeline delay = 3.5 clock cycles TDO
DOIA[0:7]
DOQA[0:7]
N - 1
N - 3 N + 1
N - 2 N
N - 1
N - 3 N + 1
N - 2 N
Address: D7 D6 D5 D4 D3 D2 D1 D0
1 0 X X 0 X 0 0
15
5390B–BDC–02/06
AT84AD004B
Figure 4-6. 1:2 DMUX Mode, Clock I = ADC I, Clock IN = ADC Q
CLKI
CLKOI
(= CLKI/2)
VIN
TA
NN + 1
N + 4 N + 6
Pipeline delay = 4 clock cycles TDO
TD2
DOQA[0:7]
N - 4
N - 8 N
DOQB[0:7]
Pipeline delay = 3 clock cycles TDO
N - 6 N - 2 N + 2
Address: D7 D6 D5 D4 D3 D2 D1 D0
0 X X X 1 X 0 0
N - 7 N - 3 N + 1
N - 5 N - 1 N + 3
DOIA[0:7]
DOIB[0:7]
CLKOQ is high impedance
CLKIN
Pipeline delay = 3.5 clock cycles TDO
N + 2
N + 3
N + 5
CLKOI
(= CLKI/4)
16
5390B–BDC–02/06
AT84AD004B
Figure 4-7. 1:1 DMUX Mode, Clock I = ADC I, Clock IN = ADC Q
Figure 4-8. 1:1 DMUX Mode, Decimation Mode Test (1:16 Factor)
Notes: 1. Frequency(CLKOI) = Frequency(Data) = Frequency(CLKI)/16.
CLKI
CLKOI
(= CLKI/2)
VIN
TA
NN + 1
N + 4 N + 6
Pipeline delay = 3.5 clock cycles TDO
DOQA[0:7]
Address: D7 D6 D5 D4 D3 D2 D1 D0
0 X X X 0 X 0 0
DOIA[0:7]
DOIB[0:7] and DOQB[0:7] are high impedance
CLKOQ is high impedance
CLKIN
N + 2
N + 3
N + 5
N - 2
N - 6 N + 2
N - 4 N
N - 1
N - 5 N + 3
N - 3 N + 1
Pipeline delay = 3 clock cycles TDO
VIN
N - 16 NN + 16 N + 32
CLKI
16 clock cycles
CLKOI
DOIA[0:7]
N + 16 N + 32 N + 48
N - 16 N
DOQA[0:7]
N + 16 N + 32 N + 48
N - 16 N
Address: D7 D6 D5 D4 D3 D2 D1 D0
1 0 X X 0 X 0 0
DOIB[0:7] and DOQB[0:7] are high impedance
CLKOQ is high impedance
17
5390B–BDC–02/06
AT84AD004B
Figure 4-9. Data Ready Reset
Figure 4-10. Data Ready Reset 1:1 DMUX Mode
Note: The Data Ready Reset is taken into account only 2 ns after it is asserted. The output clock first completes its cycle (if the reset
occurs when it is high, it goes low only when its half cycle is complete; if the reset occurs when it is low, it remains low) and then
only, remains in reset state (frozen to a low level in 1:1 DMUX mode). The next falling edge of the input clock after reset makes
the output clock return to normal mode (after TDR).
DDRB
CLKI or
CLKQ
500 ps
ALLOWED ALLOWED
FORBIDDENFORBIDDEN
1 ns min
500 ps
1 ns min
CLKI or
CLKQ
CLKOI or
CLKOQ
DOIA[0:7] or
DOQA[0:7]
VIN
TA
N
N
DDRB
2 ns
TDR
TDR
Pipeline Delay + TDO
Clock in
Reset
N + 1
18
5390B–BDC–02/06
AT84AD004B
Figure 4-11. Data Ready Reset 1:2 DMUX Mode
Notes: 1. In 1:2 DMUX, Fs/2 mode:
The Data Ready Reset is taken into account only 2 ns after it is asserted. The output clock first completes its cycle (if the
reset occurs when it is low, it goes high only when its half cycle is complete; if the reset occurs when it is high, it remains
high) and then only, remains in reset state (frozen to a high level in 1:2 DMUX Fs/2 mode). The next rising edge of the input
clock after reset makes the output clock return to normal mode (after TDR).
2. In 1:2 DMUX, Fs/4 mode:
The Data Ready Reset is taken into account only 2 ns after it is asserted. The output clock first completes its cycle (if the
reset occurs when it is high, it goes low only when its half cycle is complete; if the reset occurs when it is low, it remains low)
and then only, remains in reset state (frozen to a low level in 1:2 DMUX Fs/4 mode). The next rising edge of the input clock
after reset makes the output clock return to normal mode (after TDR).
CLKI or
CLKQ
CLKOI or CLKOQ
(= CLKI/2)
DOIA[0:7] or
DOQA[0:7]
VIN
TA
N
N
DDRB
Pipeline Delay + TDO
N + 1
2 ns
DOIB[0:7] or
DOQB[0:7]
N + 1
CLKOI or CLKOQ
(= CLKI/4)
1 ns min
TDR
TDR
TDR + 2 cycles
TDR + 2 cycles
Clock in
Reset
19
5390B–BDC–02/06
AT84AD004B
4.2 Functions Description
Table 4-7. Description of Functions
Name Function
VCCA Positive analog power supply
VCCD Positive digital power supply
VCCO Positive output power supply
GNDA Analog ground
GNDD Digital ground
GNDO Output ground
VINI, VINIB Differential analog inputs I
VINQ, VINQB Differential analog inputs Q
CLKOI, CLKOIN, CLKOQ,
CLKOQN
Differential output data ready I
and Q
CLKI, CLKIN, CLKQ, CLKQN Differential clock inputs I and Q
DDRB, DDRBN Synchronous data ready reset
I and Q
Mode Bit selection for 3-wire bus or
nominal setting
Clk Input clock for 3-wire bus
interface
Data Input data for 3-wire bus
Ldn Beginning and end of register
line for 3-wire bus interface
<D0AI0:DOAI7>
<D0AI0N:DOAI7N>
<D0BI0:DOBI7>
<D0BI0N:DOBI7N>
Differential output data port
channel I
<D0AQ0:DOAQ7>
<D0AQ0N:DOAQ7N>
<D0BQ0:DOBQ7>
<D0BQ0N:DOBQ7N>
Differential output data port
channel Q
DOIRI, DOIRIN DOIRQ,
DOIRQN
Differential output IN range
data I and Q
VtestQ Test voltage output for ADC Q
(to be left open)
VtestI Test voltage output for ADC I
(to be left open)
Cal Output bit status internal
calibration
Vdiode Test diode voltage for Tj
measurement
VINI
VINIB
CLKI
CLKIB
D0AI0
DOAI7
D0AI0N
DOAI7N
D0BI0
DOBI7
D0BI0N
DOBI7N
32
GNDD
VCCA = 3.3V
AT84AD004
GNDO
GNDA
VINQ
VINQB
VCCD = 3.3V VCCO = 2.25V
D0AQ0
DOAQ7
D0AQ0
DOAQ7
DOBQ0
DOQBQ7
DOBQ0N
DOQBQ7N
32
DOIRI, DOIRIN
DOIRQ, DOIRQN
4
CLOCKOI, CLOCKOIB
CLOCKOQ, CLOCKOQB
4
CLKQ
CLKQB
mode dataclk ldn
VtestI
VtestQ
2
Vdiode
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4.3 Digital Output Coding (Nominal Settings)
5. Pin Description
Table 4-8. Digital Output Coding (Nominal Setting)
Differential
Analog Input Voltage Level
Digital Output
I or Q (Binary Coding) Out-of-range Bit
> 250 mV > Positive full-scale + 1/2 LSB 1 1 1 1 1 1 1 1 1
250 mV
248 mV
Positive full-scale + 1/2 LSB
Positive full-scale - 1/2 LSB
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 0
0
0
1 mV
-1 mV
Bipolar zero + 1/2 LSB
Bipolar zero - 1/2 LSB
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
0
0
-248 mV
-250 mV
Negative full-scale + 1/2 LSB
Negative full-scale - 1/2 LSB
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
0
0
< -250 mV < Negative full-scale - 1/2 LSB 0 0 0 0 0 0 0 0 1
Table 5-1. AT84AD004B LQFP 144 Pin Description
Symbol Pin number Function
GNDA, GNDD, GNDO
10, 12, 22, 24, 36, 38, 40, 42, 44, 46, 51,
54, 59, 61, 63, 65, 67, 69, 85, 87, 97, 99,
109, 111, 130, 142, 144
Ground pins. To be connected to external
ground plane
VCCA 41, 43, 45, 60, 62, 64 Analog positive supply: 3.3V typical
VCCD
9, 21, 37, 39, 66, 68, 88, 100, 112, 123,
141 3.3V digital supply
VCCO 11, 23, 86, 98, 110, 143 2.25V output and 3-wire serial interface
supply
VINI 57, 58
In-phase (+) analog input signal of the
sample & hold differential preamplifier
channel I
VINIB 55, 56 Inverted phase (-) of analog input signal
(VINI)
VINQ 47, 48
In-phase (+) analog input signal of the
sample & hold differential preamplifier
channel Q
VINQB 49, 50 Inverted phase (-) of analog input signal
(VINQ)
CLKI 124 In-phase (+) clock input signal
CLKIN 125 Inverted phase (-) clock input signal
(CLKI)
CLKQ 129 In-phase (+) clock input signal
CLKQN 128 Inverted phase (-) clock input signal
(CLKQ)
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DDRB 126 Synchronous data ready reset I and Q
DDRBN 127 Inverted phase (-) of input signal (DDRB)
DOAI0, DOAI1, DOAI2, DOAI3, DOAI4,
DOAI5, DOAI6, DOAI7 117, 113, 105, 101, 93, 89, 81, 77
In-phase (+) digital outputs first phase
demultiplexer (channel I) DOAI0 is the
LSB. D0AI7 is the MSB
DOAI0N, DOAI1N, DOAI2N, DOAI3N,
DOAI4N, DOAI5N, DOAI6N, DOAI7N, 118, 114, 106, 102, 94, 90, 82, 78
Inverted phase (-) digital outputs first
phase demultiplexer (channel I) DOAI0N
is the LSB. D0AI7N is the MSB
DOBI0, DOBI1, DOBI2, DOBI3, DOBI4,
DOBI5, DOBI6, DOBI7 119, 115, 107, 103, 95, 91, 83, 79
In-phase (+) digital outputs second phase
demultiplexer (channel I) DOBI0 is the
LSB. D0BI7 is the MSB
DOBI0N, DOBI1N, DOBI2N, DOBI3N,
DOBI4N, DOBI5N, DOBI6N, DOBI7N 120, 116, 108, 104, 96, 92, 84, 80
Inverted phase (-) digital outputs second
phase demultiplexer (channel I) DOBI0N
is the LSB. D0BI7N is the MSB
DOAQ0, DOAQ1, DOAQ2, DOAQ3,
DOAQ4, DOAQ5, DOAQ6, DOAQ7 136, 140, 4, 8, 16, 20, 28, 32
In-phase (+) digital outputs first phase
demultiplexer (channel Q) DOAI0 is the
LSB. D0AQ7 is the MSB
DOAQ0N, DOAQ1N, DOAQ2N, DOAQ3N,
DOAQ4N, DOAQ5N, DOAQ6N, DOAQ7N 135, 139, 3, 7, 15, 19, 27, 31
Inverted phase (-) digital outputs first
phase demultiplexer (channel Q) DOAI0N
is the LSB. D0AQ7N is the MSB
DOBQ0, DOBQ1, DOBQ2, DOBQ3,
DOBQ4, DOBQ5, DOBQ6, DOBQ7 134, 138, 2, 6, 14, 18, 26, 30
In-phase (+) digital outputs second phase
demultiplexer (channel Q) DOBQ0 is the
LSB. D0BQ7 is the MSB
DOBQ0N, DOBQ1N, DOBQ2N,
DOBQ3N, DOBQ4N, DOBQ5N,
DOBQ6N, DOBQ7N
133, 137, 1 ,5, 13, 17, 25, 29
Inverted phase (-) digital outputs second
phase demultiplexer (channel Q)
DOBQ0N is the LSB. D0BQ7N is the MSB
DOIRI 75
In-phase (+) out-of-range bit input
(I phase) combined demultiplexer
out-of-range is high on the leading edge of
code 0 and code 256
DOIRIN 76 Inverted phase of output signal DOIRI
DOIRQ 34
In-phase (+) out-of-range bit input
(Q phase) combined demultiplexer
out-of-range is high on the leading edge of
code 0 and code 256
DOIRQN 33 Inverted phase of output signal DOIRQ
MODE 74 Bit selection for 3-wire bus interface or
nominal setting
CLK 73 Input clock for 3-wire bus interface
DATA 72 Input data for 3-wire bus
LND 71 Beginning and end of register line for
3- wire bus interface
CLKOI 121 Output clock in-phase (+) channel I
CLKOIN 122 Inverted phase (-) output clock channel I
Table 5-1. AT84AD004B LQFP 144 Pin Description (Continued)
Symbol Pin number Function
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5390B–BDC–02/06
AT84AD004B
Figure 5-1. AT84AD004B Pinout (Top View)
CLKOQ 132 Output clock in-phase (+) channel Q,
1/2 input clock frequency
CLKOQN 131 Inverted phase (-) output clock channel Q
VtestQ, VtestI 53, 52 Pins for internal test (to be left open)
Cal 70 Calibration output bit status
Vdiode 35 Positive node of diode used for die
junction temperature measurements
Table 5-1. AT84AD004B LQFP 144 Pin Description (Continued)
Symbol Pin number Function
LQFP 144
20 by 20 by 1.4 mm
Atmel - Dual 8-bit
Q
I
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6. Typical Characterization Results
Nominal conditions (unless otherwise specified):
•V
CCA = 3.3V; VCCD = 3.3V; VCCO = 2.25V
•V
INI - VINB or VINQ to VINQB = 500 mVpp full-scale differential input
• LVDS digital outputs (100Ω)
•T
amb (typical) = 25°C
• Full temperature range: 0 °C < Tamb < 70°C (commercial grade)
or - 40 °C < Tamb < 85°C (industrial grade)
6.1 Typical Full Power Input Bandwidth
• Fs = 500 Msps
• Pclock = 0 dBm
•Pin = -1 dBFS
• Gain flatness (±0.5 dB) from DC to > 350 MHz
• Full power input bandwidth at - 3 dB > 1 GHz
Figure 6-1. Full Power Input Bandwidth
-5.00
-4.00
-3.00
-2.00
-1.00
0.00
0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500
Fin (M Hz )
dBFS
-3 dB Bandwidth
Gain Flatness
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6.2 Typical Crosstalk
Figure 6-2. Crosstalk (Fs = 500 Msps)
Note: Measured on the AT84AD004BTD-EB Evaluation Board.
6.3 Typical DC, INL and DNL Patterns
1:2 DMUX mode, Fs/4 DR type
Figure 6-3. Typical INL (Fs = 50 Msps, Fin = 1 MHz, Saturated Input)
0.00
10.00
20.00
30.00
40.00
50.00
60.00
70.00
80.00
0 100 200 300 400 500 600 700 800 900 1000
Fin(MHz)
dBc
-0,6
-0,4
-0,2
0
0,2
0,4
0,6
1 16 31 46 61 76 91 106 121 136 151 166 181 196 211 226 241 256
Codes
INL (L sb)
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Figure 6-4. Typical DNL (Fs = 50 Msps, Fin = 1 MHz, Saturated Input)
6.4 Typical Dynamic Performances Versus Sampling Frequency
Figure 6-5. ENOB Versus Sampling Frequency in Nyquist Conditions (Fin = Fs/2)
Figure 6-6. SFDR Versus Sampling Frequency in Nyquist Conditions (Fin = Fs/2)
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
1 16 31 46 61 76 91 106 121 136 151 166 181 196 211 226 241 256
Codes
DNL (Lsb)
7.0
7.1
7.2
7.3
7.4
7.5
7.6
50 100 150 200 250 300
350
400 450 500 550
Fs (Msps)
ENOB ( Bit)
-68
-65
-62
-59
-56
50 100 150 200 250 300 350 400 450 500 550
Fs (Msps)
SF DR ( dBc )
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Figure 6-7. THD Versus Sampling Frequency in Nyquist Conditions (Fin = Fs/2)
Figure 6-8. SNR Versus Sampling Frequency in Nyquist Conditions (Fin = Fs/2)
6.5 Typical Dynamic Performances Versus Input Frequency
Figure 6-9. ENOB Versus Input Frequency (Fs = 500 Msps)
-60
-58
-56
-54
-52
-50
50 100 150 200 250 300 350 400 450 500 550
Fs (Msps)
THD (dBc)
44
45
46
47
50 100 150 200 250 300 350 400 450 500 550
Fs (Msps)
SNR (dBc)
6.8
6.9
7.0
7.1
7.2
7.3
7.4
7.5
7.6
0 100 200 300 400 500
Fin (MHz)
ENOB ( Bit)
Channel I Channel Q
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AT84AD004B
Figure 6-10. SFDR Versus Input Frequency (Fs = 500 Msps)
Figure 6-11. THD Versus Input Frequency (Fs = 500 Msps)
Figure 6-12. SNR Versus Input Frequency (Fs = 500 Msps)
-60
-59
-58
-57
-56
-55
-54
0 100 200 300 400 500
Fin (MHz)
SFDR (dBc)
Channel I Channel Q
-58
-57
-56
-55
-54
-53
-52
-51
-50
0 100 200 300 400 500
Fin (MHz)
THD (dBc)
Channel I Channel Q
42
43
44
45
46
47
0 100 200 300 400 500
Fin (MHz)
SNR (dBc)
Channel I Channel Q
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6.6 Typical Signal Spectrum
Figure 6-13. Fs = 500 Msps and Fin = 20 MHz (1:2 DMUX, Fs/4 DR Type
FiSDA = -35 ps, ISA = 0 ps)
Figure 6-14. Fs = 500 Msps and Fin = 250 MHz (1:2 DMUX, Fs/4 DR Type
FiSDA = -35 ps, ISA = 0 ps)
-120
-100
-80
-60
-40
-20
0
20
0 16 31 47 63 78 94 109 125 141 156 172 188 203 219 234
Fs (Msps)
dBc
H2 H3 H4
Fundamental: H1
SFDR = -60 dBc
-120
-100
-80
-60
-40
-20
0
20
0 16 31 47 63 78 94 109 125 141 156 172 188 203 219 234
Fs (Msps)
dBc
H2
H3
Fundamental : H1
SFDR = -58 dBc
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Figure 6-15. Fs = 500 Msps and Fin = 500 MHz (1:2 DMUX, Fs/4 DR Type
FiSDA = -35 ps, ISA = 0 ps)
Note: The spectra are given with respect to the output clock frequency observed by the acquisition sys-
tem (Figures 27 to 29).
Figure 6-16. Fs = 500 Msps and Fin = 250 MHz (Interleaving Mode Fint = 1 Gsps
1:1 DMUX, FiSDA = -35 ps, ISA = 0 ps)
-120
-100
-80
-60
-40
-20
0
20
0 16 31 47 63 78 94 109 125 141 156 172 188 203 219 234
Fs (Msps)
dBc
H3
H2
Fundamental: H1
SFDR = -57 dBc
-120
-100
-80
-60
-40
-20
0
20
0 62 125 187 249 311 374 436 498
Fs (Msps)
dBc
Fs
Fundamental H1
SFDR = -55 dBc
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6.7 Typical Performance Sensitivity Versus Power Supplies and Temperature
Figure 6-17. ENOB Versus VCCA (Fs = 500 Msps, Fin = 250 MHz, 1:2 DMUX,
Fs/4 DR Type, ISA = 0 ps)
Figure 6-18. SFDR Versus VCCA (Fs = 500 Msps, Fin = 250 MHz, 1:2 DMUX,
Fs/4 DR Type, ISA = 0 ps)
6.6
6.8
7.0
7.2
7.4
7.6
3.1 3.15 3.2 3.25 3.3 3.35 3.4 3.45 3.5
V
CCA
(V)
ENOB (Bit)
Channel I Channel Q
-62
-60
-58
-56
-54
-52
-50
-48
3.1 3.15 3.2 3.25 3.3 3.35 3.4 3.45 3.5
V
CCA
(V)
SF DR (dBc)
Channel I Channel Q
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Figure 6-19. THD Versus VCCA (Fs = 500 Msps, Fin = 250 MHz, 1:2 DMUX,
Fs/4 DR Type, ISA = 0 ps)
Figure 6-20. SNR Versus VCCA (Fs = 500 Msps, Fin = 250 MHz, 1:2 DMUX,
Fs/4 DR Type, ISA = 0 ps)
-58
-57
-56
-55
-54
-53
-52
-51
-50
-49
-48
3.1 3.15 3.2 3.25 3.3 3.35 3.4 3.45 3.5
VCCA (V
)
THD (dBc)
Channel I Channel Q
41.0
42.0
43.0
44.0
45.0
46.0
3.1 3.15 3.2 3.25 3.3 3.35 3.4 3.45 3.5
VCCA (V)
SNR (dBc)
Channel I Channel Q
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Figure 6-21. ENOB Versus Ambient Temperature (Fs = 500 Msps, Fin = 250 MHz,
1:2 DMUX, Fs/4 DR Type)
Figure 6-22. SFDR Versus Ambient Temperature (Fs = 500 Msps, Fin = 250 MHz,
1:2 DMUX, Fs/4 DR Type)
6.4
6.6
6.8
7.0
7.2
7.4
-40 -15 10 35 60 85
Tamb (˚C)
ENOB (Bit)
500 Msps 20 MHz
500 Msps 250 MHz
500 Msps 500 MHz
-62
-60
-58
-56
-54
-52
-50
-48
-46
-40 -15 10 35 60 85
Tamb (˚C)
SF DR (dBc)
500 Msps 20 MHz
500 Msps 250 MHz
500 Msps 500 MHz
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Figure 6-23. THD Versus Ambient Temperature (Fs = 500 Msps, Fin = 250 MHz,
1:2 DMUX, Fs/4 DR Type)
Figure 6-24. SNR Versus Ambient Temperature (Fs = 500 Msps, Fin = 250 MHz,
1:2 DMUX, Fs/4 DR Type)
-60
-58
-56
-54
-52
-50
-48
-40 -15 10 35 60 85
Tamb (˚C)
THD (dBc)
500 Msps 20 MHz
500 Msps 250 MHz
500 Msps 500 MHz
40
41
42
43
44
45
46
47
48
-40 -15 10 35 60 85
Tamb (˚C)
SNR (dBc)
500 Msps 20 MHz
500 Msps 250 MHz
500 Msps 500 MHz
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7. Test and Control Features
7.1 3-wire Serial Interface Control Setting
Table 7-1. 3-wire Serial Interface Control Settings
Mode Characteristics
Mode = 1 (2.25V) 3-wire serial bus interface activated
Mode = 0 (0V)
3-wire serial bus interface deactivated
Nominal setting:
Dual channel I and Q activated
One clock I
0 dB gain
DMUX mode 1:1
DRDA I & Q = 0 ps
ISA I & Q = 0 ps
FiSDA Q = 0 ps
Binary output
Decimation test mode OFF
Calibration setting OFF
Data Ready = Fs /2
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7.1.1 3-wire Serial Interface and Data Description
The 3-wire bus is activated with the control bit mode set to 1. The length of the word is 19 bits:
16 for the data and 3 for the address. The maximum clock frequency is
50 MHz.
Table 7-2. 3-wire Serial Interface Address Setting Description
Address Setting
000
Standby
Gray/binary mode
1:1 or 1:2 DMUX mode
Analog input MUX
Clock selection
Auto-calibration
Decimation test mode
Data Ready Delay Adjust
001
Analog gain adjustment
Data7 to Data0: gain channel I
Data15 to Data8: gain channel Q
Code 00000000: -1.5 dB
Code 10000000: 0 dB
Code 11111111: 1.5 dB
Steps: 0.011 dB
010
Offset compensation
Data7 to Data0: offset channel I
Data15 to Data8: offset channel Q
Data7 and Data15: sign bits
Code 11111111b: 31.75 LSB
Code 10000000b: 0 LSB
Code 00000000b: 0 LSB
Code 01111111b: -31.75 LSB
Steps: 0.25 LSB
Maximum correction: ±31.75 LSB
011
Gain compensation
Data6 to Data0: channel I/Q (Q is matched to I)
Code 11111111b: -0.315 dB
Code 10000000b: 0 dB
Code 0000000b: 0 dB
Code 0111111b: 0.315 dB
Steps: 0.005 dB
Data6: sign bit
100
Internal Settling Adjustment (ISA)
Data2 to Data0: channel I
Data5 to Data3: channel Q
Data15 to Data6: 1000010000
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Notes: 1. The Internal Settling Adjustment could change independently of the two analog sampling times (TA channels I and Q) of the
sample/hold (with a fixed digital sampling time) with steps of ±50 ps:
Nominal mode will be given by Data2…Data0 = 100 or Data5…Data3 = 100.
Data5…Data3 = 000 or Data2…Data0 = 000: sampling time is -200 ps compared to nominal.
Data2…Data0 = 111 or Data5…Data3 = 111: sampling time is 150 ps compared to nominal.
We recommend setting the ISA to 0 ps to optimize the ADC’s dynamic performances.
2. The Fine Sampling Delay Adjustment enables you to change the sampling time (steps of ±5 ps) on channel Q more pre-
cisely, particularly in the interleaved mode.
3. The “S/H transparent” mode (address 101, Data4) enables bypassing of the ADC’s track/hold. This function optimizes the
ADC’s performances at very low input frequencies (Fin < 50 MHz).
4. In the Gray mode, when the input signal is overflow (that is, the differential analog input is greater than 250 mV), the output
data must be corrected using the output DOIR:
If DOIR = 1: Data7 unchanged
Data6 = 0, Data5 = 0, Data4 = 0, Data3 = 0, Data2 = 0, Data1 = 0, Data0 = 0.
In 1:2 DMUX mode, only one out-of-range bit is provided for both A and B ports.
101
Testability
Data3 to Data0 = 0000
Mode S/H transparent OFF: Data4 = 0 ON: Data4 = 1
Data7 = 0
Data8 = 0
110
Built-In Test (BIT)
Data0 = 0 BIT Inactive Data0 = 1BIT Active
Data1 = 0 Static BIT Data1 = 1Dynamic BIT
If Data1 = 1, then Ports BI & BQ = Rising Ramp
Ports AI & AQ = Decreasing Ramp
If Data1 = 0, then Data2 to Data9 = Static Data for BIT
Ports BI & BQ = Data2 to Data9
Ports AI & AQ = NOT (Data2 to Data9)
111
Data Ready Delay Adjust (DRDA)
Data2 to Data0: clock I
Data5 to Data3: clock Q
Steps: 140 ps
000: -560 ps
100: 0 ps
111: 420 ps
Fine Sampling Delay Adjustment (FiSDA) on channel Q
Data10 to Data6: channel Q
Steps: 5 ps
Data4: sign bit
Code 11111: -75 ps
Code 10000: 0 ps
Code 00000: 0 ps
Code 01111: 75 ps
Table 7-2. 3-wire Serial Interface Address Setting Description (Continued)
Address Setting
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Table 7-3. 3-wire Serial Interface Data Setting Description
Setting for Address:
000 D15 D14 D13 D12 D11 D10 D9(1) D8 D7 D6 D5 D4 D3 D2 D1 D0
Full standby mode XXXXXX 0 XXXXXXX11
Standby channel I(2) XXXXXX 0 XXXXXXX01
Standby channel Q(3) XXXXXX 0 XXXXXXX10
No standby mode XXXXXX 0 XXXXXXX00
Binary output mode XXXXXX 0 XXXXXX1XX
Gray output mode XXXXXX 0 XXXXXX0XX
DMUX 1:2 mode XXXXXX 0 XXXXX1XXX
DMUX 1:1 mode XXXXXX 0 XXXXX0XXX
Analog selection mode
Input I → ADC I
Input Q → ADC Q
XXXXXX 0 XXX11XXXX
Analog selection mode
Input I → ADC I
Input I → ADC Q
XXXXXX 0 XXX10XXXX
Analog selection mode
Input Q → ADC I
Input Q → ADC Q
XXXXXX 0 XXX0XXXXX
Clock Selection mode
CLKI → ADC I
CLKQ → ADC Q
XXXXXX 0 X11XXXXXX
Clock selection mode
CLKI → ADC I
CLKI → ADC Q
XXXXXX 0 X10XXXXXX
Clock selection mode
CLKI → ADC I
CLKIN → ADC Q
XXXXXX 0 X0XXXXXXX
Decimation OFF modeXXXXXX 0 0XXXXXXXX
Decimation ON mode XXXXXX 0 1XXXXXXXX
Keep last calibration
calculated value(4)
No calibration phase
XXXX01 0 XXXXXXXXX
No calibration phase(5)
No calibration value XXXX0 0 0 XXXXXXXXX
Start a new calibration
phase XXXX11 0 XXXXXXXXX
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Notes: 1. D9 must be set to “0”
2. Mode standby channel I: use analog input I Vini, Vinib and Clocki.
3. Mode standby channel Q: use analog input Q Vinq, Vinqb and Clockq.
4. Keep last calibration calculated value - no calibration phase: D11 = 0 and D10 = 1. No new calibration is required. The val-
ues taken into account for the gain and offset are either from the last calibration phase or are default values (reset values).
5. No calibration phase - no calibration value: D11 = 0 and D10 = 0. No new calibration phase is required. The gain and offset
compensation functions can be accessed externally by writing in the registers at address 010 for the offset compensation
and at address 011 for the gain compensation.
6. The control wait bit gives the possibility to change the internal setting for the auto-calibration phase:
For high clock rates (= 500 Msps) use a = b = 1.
For clock rates > 250 Msps and < 500 Msps use a = 1 and b = 0.
For clock rates > 125 Msps and < 250 Msps use a = 0 and b = 1.
For low clock rates < 125 Msps use a = 0 and b = 0.
7.1.2 3-wire Serial Interface Timing Description
The 3-wire serial interface is a synchronous write-only serial interface made of three wires:
• sclk: serial clock input
• sldn: serial load enable input
• sdata: serial data input
The 3-wire serial interface gives write-only access to as many as 8 different internal registers of
up to 16 bits each. The input format is always fixed with 3 bits of register address followed by 16
bits of data. The data and address are entered with the Most Significant Bit (MSB) first.
The write procedure is fully synchronous with the rising clock edge of “sclk” and described in the
write chronogram (Figure 7-1 on page 39).
• “sldn” and “sdata” are sampled on each rising clock edge of “sclk” (clock cycle).
• “sldn” must be set to 1 when no write procedure is performed.
• A minimum of one rising clock edge (clock cycle) with “sldn” at 1 is required for a correct start
of the write procedure.
• A write starts on the first clock cycle with “sldn” at 0. “sldn” must stay at 0 during the complete
write procedure.
• During the first 3 clock cycles with “sldn” at 0, 3 bits of the register address from MSB (a[2]) to
LSB (a[0]) are entered.
• During the next 16 clock cycles with “sldn” at 0, 16 bits of data from MSB (d[15]) to LSB (d[0])
are entered.
Control wait bit
calibration(6) X X a b X X 0 XXXXXXXXX
In 1:2 DMUX
FDataReady
I & Q = Fs/2
X 0 X X X X 0 XXXXXXXXX
In 1:2 DMUX
FDataReady
I & Q = Fs/4
X 1 X X X X 0 XXXXXXXXX
Table 7-3. 3-wire Serial Interface Data Setting Description (Continued)
Setting for Address:
000 D15 D14 D13 D12 D11 D10 D9(1) D8 D7 D6 D5 D4 D3 D2 D1 D0
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5390B–BDC–02/06
AT84AD004B
• An additional clock cycle with “sldn” at 0 is required for parallel transfer of the serial data
d[15:0] into the addressed register with address a[2:0]. This yields 20 clock cycles with “sldn”
at 0 for a normal write procedure.
• A minimum of one clock cycle with “sldn” returned at 1 is requested to close the write
procedure and make the interface ready for a new write procedure. Any clock cycle where
“sldn” is at 1 before the write procedure is completed interrupts this procedure and no further
data transfer to the internal registers is performed.
• Additional clock cycles with “sldn” at 0 after the parallel data transfer to the register (done at
the 20th consecutive clock cycle with “sldn” at 0) do not affect the write procedure and are
ignored.
It is possible to have only one clock cycle with “sldn” at 1 between two following write
procedures.
• 16 bits of data must always be entered even if the internal addressed register has less than
16 bits. Unused bits (usually MSBs) are ignored. Bit signification and bit positions for the
internal registers are detailed in Table 7-2 on page 35.
To reset the registers, the Pin mode can be used as a reset pin for chip initialization, even when
the 3-wire serial interface is used.
Figure 7-1. Write Chronogram
Figure 7-2. Timing Definition
Reset Write procedure
a[2] a[1] a[0] d[15] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0]
12 345 1314151617181920
Reset setting
Mode
sclk
sldn
sdata
Internal register
value New d
Mode
sclk
sldn
sdata
Twlmode
Tdmode
Tssldn
Tssdata
Thsldn
Thsdata
Tdmode
Twsclk
Tsclk
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5390B–BDC–02/06
AT84AD004B
7.1.3 Calibration Description
The AT84AD004B offers the possibility of reducing offset and gain matching between the two
ADC cores. An internal digital calibration may start right after the 3-wire serial interface has been
loaded (using data D12 of the 3-wire serial interface with address 000).
The beginning of calibration disables the two ADCs and a standard data acquisition is per-
formed. The output bit CAL goes to a high level during the entire calibration phase. When this bit
returns to a low level, the two ADCs are calibrated with offset and gain and can be used again for
a standard data acquisition.
If only one channel is selected (I or Q) the offset calibration duration is divided by two and no
gain calibration between the two channels is necessary.
Figure 7-3. Internal Timing Calibration
The Tcal duration is a multiple of the clock frequency ClockI (master clock). Even if a dual clock
scheme is used during calibration, ClockQ will not be used.
The control wait bits (D13 and D14) give the possibility of changing the calibration’s setting
depending on the clock’s frequency:
• For high clock rates (= 500 Msps) use a = b = 1, Tcal = 10112 clock I periods.
• For clock rates > 250 Msps and < 500 Msps use a = 1, b = 0, Tcal = 6016 clock I periods.
• For clock rates > 125 Msps and < 250 Msps use a = 0, b = 1 ,Tcal = 3968 clock I periods.
• For low clock rates (< 125 Msps) use a = 0, b = 0 , Tcal = 2944 clock I periods.
Table 7-4. Timing Description
Name Parameter
Value
UnitMin Typ Max
Tsclk Sclk period 20 ns
Twsclk High or low time of sclk 5 ns
Tssldn Setup time of sldn before rising edge of sclk 4 ns
Thsldn Hold time of sldn after rising edge of sclk 2 ns
Tssdata Setup time of sdata before rising edge of sclk 4 ns
Thsdata Hold time of sdata after rising edge of sclk 2 ns
Twlmode Minimum low pulse width of mode 5 ns
Tdmode Minimum delay between an edge of mode and the
rising edge of sclk 10 ns
3-wire Serial Interface
LDN
CAL
Tcal
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5390B–BDC–02/06
AT84AD004B
The calibration phase is necessary when using the AT84AD004B in interleaved mode, where
one analog input is sampled at both ADC cores on the common input clock’s rising and falling
edges. This operation is equivalent to converting the analog signal at twice the clock frequency
During the ADC’s auto-calibration phase, the dual ADC is set with the following:
• Decimation mode ON
• 1:1 DMUX mode
• Binary mode
Any external action applied to any signal of the ADC’s registers is inhibited during the calibration
phase.
7.1.4 Gain and Offset Compensation Functions
It is also possible for the user to have external access to the ADC’s gain and offset compensa-
tion functions:
• Offset compensation between I and Q channels (at address 010)
• Gain compensation between I and Q channels (at address 011)
To obtain manual access to these two functions, which are used to set the offset to middle code
127.5 and to match the gain of channel Q with that of channel I (if only one channel is used, the
gain compensation does not apply), it is necessary to set the ADC to “manual” mode by writing 0
at bits D11 and D10 of address 000.
7.1.5 Built-in Test (BIT)
A Built-in Test (BIT) function is available to allow rapid testing of the device’s I/O by either apply-
ing a defined static pattern to the ADC or by generating a dynamic ramp at the ADC’s output.
This function is controlled via the 3-wire bus interface at address 101.
• The BIT is active when Data0 = 1 at address 110.
• The BIT is inactive when Data0 = 0 at address 110.
• The Data1 bit allows choosing between static mode (Data1 = 0) and dynamic mode (Data1 =
1).
When the static BIT is selected (Data1 = 0), it is possible to write any 8-bit pattern by defining the
Data9 to Data2 bits. Port B then outputs an 8-bit pattern equal to Data9 ... Data2, and Port A out-
puts an 8-bit pattern equal to NOT (Data9 ... Data2).
Table 7-5. Matching Between Channels
Parameter
Value
UnitMin Typ Max
Gain error (single channel I or Q) without calibration 0 %
Gain error (single channel I or Q) with calibration -2 0 2 %
Offset error (single channel I or Q) without calibration 0 LSB
Offset error (single channel I or Q) with calibration -2 0 2 LSB
Mean offset code without calibration (single channel I or Q) 127.5
Mean offset code with calibration (single channel I or Q) 126 127.5 129
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5390B–BDC–02/06
AT84AD004B
Example:
Address = 110
Data =
One should then obtain 01010101 on Port B and 10101010 on Port A.
When the dynamic mode is chosen (Data1 = 1) port B outputs a rising ramp while Port A outputs
a decreasing one.
Note: In dynamic mode, use the DRDA function to align the edges of CLKO with the middle of the data.
7.1.6 Decimation Mode
The decimation mode is provided to enable rapid testing of the ADC. In decimation mode, one
data out of 16 is output, thus leading to a maximum output rate of
31.25 Msps.
Note: Frequency (CLKO) = frequency (Data) = Frequency (CLKI)/16.
7.2 Die Junction Temperature Monitoring Function
A die junction temperature measurement setting is included on the board for junction tempera-
ture monitoring.
The measurement method forces a 1 mA current into a diode-mounted transistor.
Caution should be given to respecting the polarity of the current.
In any case, one should make sure the maximum voltage compliance of the current source is
limited to a maximum of 1V or use a resistor serial-mounted with the current source to avoid
damaging the transistor device (this may occur if the current source is reverse-connected).
The measurement setup is illustrated in Figure 7-4.
Figure 7-4. Die Junction Temperature Monitoring Setup
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
XXXXXX0101010101
1 mA
GNDD
(Pin 36)
VDiode (Pin 35)
Protection
Diodes
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5390B–BDC–02/06
AT84AD004B
The VBE diode’s forward voltage in relation to the junction temperature (in steady-state condi-
tions) is shown in Figure 7-5.
Figure 7-5. Diode Characteristics Versus TJ
7.3 VtestI, VtestQ
VtestI and VtestQ pins are for internal test use only. These two signals must be left open.
8. Equivalent Input/Output Schematics
Figure 8-1. Simplified Input Clock Model
620
640
660
680
700
720
740
760
780
800
820
840
860
-20-100 102030405060708090100110120
Junction Temperature (˚C)
Diode Voltage (mV)
VCCD/2
100Ω
VCCD
GNDD
CLK
CLKB
100Ω
50Ω
50Ω
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5390B–BDC–02/06
AT84AD004B
Figure 8-2. Simplified Data Ready Reset Buffer Model
Figure 8-3. Analog Input Model
VCCD/2
100Ω
VCCD
GNDD
DDRB
DDRBN
100Ω
50Ω
50Ω
GND
GND
Vcca
GND
Vcca
Sel Input I
GND
VinI
VinQ
Sel Input Q
VinQ Reverse
Termination
50Ω
ESD
ESD
VinQ
Double
Pad
VinI Double Pad
DC Coupling
(Common Mode = Ground = 0V)
GND – 0.4V
MAX
50ΩVinl Reverse
Termination
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5390B–BDC–02/06
AT84AD004B
Figure 8-4. Data Output Buffer Model
VCCO
GNDO
DOAIO, DOAI7
DOBIO, DOBI7
DOAION, DOAI7N
DOBION, DOBI7N
46
5390B–BDC–02/06
AT84AD004B
9. Definitions of Terms
Table 9-1. Definitions of Terms
Abbreviation Definition Description
BER Bit Error Rate The probability of an error occurring on the output at a maximum sampling rate.
DNL Differential
Non-Linearity
The differential non-linearity for an output code i is the difference between the measured step
size of code i and the ideal LSB step size. DNL (i) is expressed in LSBs. DNL is the
maximum value of all DNL (i). A DNL error specification of less than 1 LSB guarantees that
there are no missing output codes and that the transfer function is monotonic
ENOB Effective Number of
Bits
Where A is the actual input amplitude and Fs is
the full scale range of the ADC under test
FPBW Full Power Input
Bandwidth
The analog input frequency at which the fundamental component in the digitally
reconstructed output waveform has fallen by 3 dB with respect to its low frequency value
(determined by FFT analysis) for input at full-scale -1 dB (-1 dBFS)
IMD Inter-Modulation
Distortion
The two tones intermodulation distortion (IMD) rejection is the ratio of either of the two input
tones to the worst third order intermodulation products
INL Integral
Non-Linearity
The integral non-linearity for an output code i is the difference between the measured input
voltage at which the transition occurs and the ideal value of this transition. INL (i) is
expressed in LSBs and is the maximum value of all |INL (i)|
JITTER Aperture
uncertainty
The sample-to-sample variation in aperture delay. The voltage error due to jitters depends on
the slew rate of the signal at the sampling point
NPR Noise Power Ratio
The NPR is measured to characterize the ADC’s performance in response to broad
bandwidth signals. When applying a notch-filtered broadband white noise signal as the input
to the ADC under test, the Noise Power Ratio is defined as the ratio of the average out-of-
notch to the average in-notch power spectral density magnitudes for the FFT spectrum of the
ADC output sample test
ORT Overvoltage
Recovery Time
The time to recover a 0.2% accuracy at the output, after a 150% full-scale step applied on
the input is reduced to midscale
PSRR Power Supply
Rejection Ratio The ratio of input offset variation to a change in power supply voltage
SFDR Spurious Free
Dynamic Range
The ratio expressed in dB of the RMS signal amplitude, set at 1 dB below full-scale, to the
RMS value of the highest spectral component (peak spurious spectral component). The peak
spurious component may or may not be a harmonic. It may be reported in dB (related to the
converter -1 dB full-scale) or in dBc (related to the input signal level)
SINAD Signal to Noise and
Distortion Ratio
The ratio expressed in dB of the RMS signal amplitude, set to 1 dB below full-scale (-1 dBFS)
to the RMS sum of all other spectral components including the harmonics, except DC
SNR Signal to Noise
Ratio
The ratio expressed in dB of the RMS signal amplitude, set to 1 dB below full-scale, to the
RMS sum of all other spectral components excluding the first 9 harmonics
SSBW Small Signal Input
Bandwidth
The analog input frequency at which the fundamental component in the digitally
reconstructed output waveform has fallen by 3 dB with respect to its low frequency value
(determined by FFT analysis) for input at full-scale -10 dB (-10 dBFS)
TA Aperture delay The delay between the rising edge of the differential clock inputs (CLK, CLKB) [zero crossing
point] and the time at which VIN and VINB are sampled
TC Encoding Clock
period
TC1 = minimum clock pulse width (high)
TC = TC1 + TC2
TC2 = minimum clock pulse width (low)
ENOB SINAD 1,76–20 A
Fs/2
-----------
log+
6,02
-----------------------------------------------------------------------------=
47
5390B–BDC–02/06
AT84AD004B
TD1
Time Delay from
Data Transition to
Data Ready
The general expression is TD1 = TC1 + TDR - TDO with TC = TC1 + TC2 = 1 encoding clock
period
TD2
Time Delay from
Data Ready to
Data
The general expression is TD2 = TC2 + TDR - TDO with TC = TC1 + TC2 = 1 encoding clock
period
TDO Digital Data Output
Delay
The delay from the rising edge of the differential clock inputs (CLK, CLKB) [zero crossing
point] to the next point of change in the differential output data (zero crossing) with a
specified load
TDR Data Ready Output
Delay
The delay from the falling edge of the differential clock inputs (CLK, CLKB) [zero crossing
point] to the next point of change in the differential output data (zero crossing) with a
specified load
TF Fall Time The time delay for the output data signals to fall from 20% to 80% of delta between the low
and high levels
THD Total Harmonic
Distortion
The ratio expressed in dB of the RMS sum of the first 9 harmonic components to the RMS
input signal amplitude, set at 1 dB below full-scale. It may be reported in dB (related to the
converter -1 dB full-scale) or in dBc (related to the input signal level )
TPD Pipeline Delay The number of clock cycles between the sampling edge of an input data and the associated
output data made available (not taking into account the TDO)
TR Rise Time The time delay for the output data signals to rise from 20% to 80% of delta between the low
and high levels
TRDR Data Ready Reset
Delay
The delay between the falling edge of the Data Ready output asynchronous reset signal
(DDRB) and the reset to digital zero transition of the Data Ready output signal (DR)
TS Settling Time The time delay to rise from 10% to 90% of the converter output when a full-scale step
function is applied to the differential analog input
VSWR Voltage Standing
Wave Ratio
The VSWR corresponds to the ADC input insertion loss due to input power reflection. For
example, a VSWR of 1.2 corresponds to a 20 dB return loss (99% power transmitted and 1%
reflected)
Table 9-1. Definitions of Terms (Continued)
Abbreviation Definition Description
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AT84AD004B
10. Using the AT84AD004B Dual 8-bit 500 Msps ADC
10.1 Decoupling, Bypassing and Grounding of Power Supplies
The following figures show the recommended bypassing, decoupling and grounding schemes
for the dual 8-bit 500 Msps ADC power supplies.
Figure 10-1. VCCD and VCCA Bypassing and Grounding Scheme
Figure 10-2. VCCO Bypassing and Grounding Scheme
Note: L and C values must be chosen in accordance with the operating frequency of the application.
Figure 10-3. Power Supplies Decoupling Scheme
Note: The bypassing capacitors (1 µF and 100 pF) should be placed as close as possible to the board connectors, whereas the
decoupling capacitors (100 pF and 10 nF) should be placed as close as possible to the device.
1µF
L
PC Board 3.3V
PC Board GND
VCCD
L
CC
VCCA
100 pF
1µF
L
PC Board 2.25V
PC Board GND
VCCO
C
100 pF
VCCA
GNDA VCCO
GNDO
GNDA
GNDD
GNDO
VCCD
VCCA
VCCO
100 pF
100 pF 10 nF
10 nF
100 pF 10 nF
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5390B–BDC–02/06
AT84AD004B
10.2 Analog Input Implementation
The analog inputs of the dual ADC have been designed with a double pad implementation as
illustrated in Figure 10-4. The reverse pad for each input should be tied to ground via a 50Ω
resistor.
The analog inputs must be used in differential mode only.
Figure 10-4. Termination Method for the ADC Analog Inputs in DC Coupling Mode
Channel I
Channel Q
50Ω Source
VinI
VinIB
VinQ
VinQB
VinI
VinIB
VinQ
VinQB
Dual ADC
50Ω
50Ω
50Ω
50Ω
GND
GND
50Ω Source
GND
GND
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5390B–BDC–02/06
AT84AD004B
Figure 10-5. Termination Method for the ADC Analog Inputs in AC Coupling Mode
10.3 Clock Implementation
The ADC features two different clocks (I or Q) that must be implemented as shown in Figure
10-6. Each path must be AC coupled with a 100 nF capacitor.
Figure 10-6. Differential Termination Method for Clock I or Clock Q
Note: When only clock I is used, it is not necessary to add the capacitors on the CLKQ and CLKQN sig-
nal paths; they may be left floating.
DDRB may be implemented as described in the following figure. A pull-up resistor is imple-
mented to maintain the DDRB signal inactive in normal mode. The Data Ready Reset command
(it may be a pulse) is active on the high level.
Channel I
Channel Q
50Ω Source
VinI
VinIB
VinQ
VinQB
VinI
VinIB
VinQ
VinQB
Dual ADC
50Ω
50Ω
50Ω
50Ω
GND
GND
50Ω Source
GND
GND
ADC Package
VCCD/2
50Ω
50Ω
100 nF
100 nF
Differential Buffer
CLK
CLKB
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5390B–BDC–02/06
AT84AD004B
Figure 10-7. Single-ended Termination Method for Clock I or Clock Q
10.4 Reset Implementation
DDRB may be implemented as described in the following figure. A pull-up resistor is imple-
mented to maintain the DDRB signal inactive in normal mode. The Data Ready Reset command
(it might be a pulse) is active on the high level.
Figure 10-8. Reset Implementation
CLK
CLKB
50Ω
VCC
VCCD/2
AC coupling Capacitor
50Ω
Source
4.2 K
4.2 K
AC coupling Capacitor
50Ω
50Ω
DDRB
DDRBN
DDRB
VCCD
R = 1.5 K
R = 1.4 K
DDRBN
C = 100 nF
DDRB inactive
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5390B–BDC–02/06
AT84AD004B
10.5 Output Termination in 1:1 Ratio
When using the integrated DMUX in 1:1 ratio, the valid port is port A. Port B remains unused.
Port A functions in LVDS mode and the corresponding outputs (DOAI or DOAQ) have to be
100Ω differentially terminated as shown in Figure 10-9 on page 52.
The pins corresponding to Port B (DOBI or DOBQ pins) must be left floating (in high impedance
state).
Figure 10-9 on page 52 is an example of a 1:1 ratio of the integrated DMUX for channel I (the
same applies to channel Q).
Figure 10-9. Example of Termination for Channel I Used in DMUX 1:1 Ratio (Port B Unused)
Note: If the outputs are to be used in single-ended mode, it is recommended that the true and false signals be terminated with a 50Ω
resistor.
Port B
DOBI0 / DOBI0N
DOBI1 / DOBI1N
DOBI2 / DOBI2N
DOBI3 / DOBI3N
DOBI4 / DOBI4N
DOBI5 / DOBI5N
DOBI6 / DOBI6N
DOBI7 / DOBI7N
Floating (High Z)
Port A
DOAI0 / DOAI0N
DOAI1 / DOAI1N
DOAI2 / DOAI2N
DOAI3 / DOAI3N
DOAI4 / DOAI4N
DOAI5 / DOAI5N
DOAI6 / DOAI6N
DOAI7 / DOAI7N
VCCO
DOAI0
DOAI0N
Z0 = 50Ω
Z0 = 50Ω100Ω
LVDS In
LVDS In
Dual ADC Package
53
5390B–BDC–02/06
AT84AD004B
10.6 Using the Dual ADC With and ASIC/FPGA Load
Figure 10-10 on page 53 illustrates the configuration of the dual ADC (1:2 DMUX mode, inde-
pendent I and Q clocks) driving an LVDS system (ASIC/FPGA) with potential additional
DMUXes used to halve the speed of the dual ADC outputs.
Figure 10-10. Dual ADC and ASIC/FPGA Load Block Diagram
Port A
Channel I
Port A
Channel Q
Port B
Channel I
Port B
Channel Q
DEMUX
8:16
DMUX
8:16
DMUX
8:16
DMUX
8:16
CLKI/CLKIN @ FsI
CLKQ/CLKQN @ FsQ
Data rate = FsQ/2
Data rate = FsI/2
Data rate = FsQ/4
ASIC / FPGA
Dual 8-bit 1 Gsps ADC
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5390B–BDC–02/06
AT84AD004B
Note: The demultiplexers may be internal to the ASIC/FPGA system.
11. Thermal Characteristics
11.1 Simplified Thermal Model for LQFP 14420 x 20 x 1.4 mm
The following model has been extracted from the ANSYS FEM simulations.
Assumptions: no air, no convection and no board.
Figure 11-1. Simplified Thermal Model for LQFP Package
Note: The above are typical values with an assumption of uniform power dissipation over 2.5 x 2.5 mm2 of the top surface of the die.
11.1.0.1 Thermal Resistance from Junction to Bottom of Leads
Assumptions: no air, no convection and no board.
The thermal resistance from the junction to the bottom of the leads is 15.2°C/W typical.
11.1.0.2 Thermal Resistance from Junction to Top of Case
Assumptions: no air, no convection and no board.
The thermal resistance from the junction to the top of the case is 8.3°C/W typical.
355 µm silicon die
25 mm
λ
= 0.95W/cm/˚C
40 µm Epoxy/Ag glue
λ
= 0.02 W/cm/ ˚C
Copper paddle
λ
= 2.5W/cm/˚C
Aluminium paddle
λ
= 0.75W/ cm/ ˚C
Copper alloy leadframe
Package top
5.5˚C/watt
0.1˚C/watt
11.4˚C/watt
Package
bottom
4.3˚C/watt
1.5˚C/watt
λ
= 0.007W/cm/˚C
Silicon Junction
0.6˚C/watt
8.3˚C/watt
1.4˚C/watt
0.1˚C/watt
6.1˚C/watt 1.5˚C/watt
Leads tip
Assumptions:
Die 5.0 x 5.0 = 25 mm
40 µm thick Epoxy/Ag glue
2
Top of user board
Package bottom
connected to:
(user dependent)
Resin bottom
λ = 0.007W/cm/
˚C
2
Aluminium paddle Resin
Resin
λ
= 0.007W/cm/˚C
λ
= 25W/cm/˚C
100 µm air gap λ = 0.00027W/cm/
˚C
100 µm thermal grease gap diamater 12 mm
λ = 0.01W/cm/
˚C
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5390B–BDC–02/06
AT84AD004B
11.1.0.3 Thermal Resistance from Junction to Bottom of Case
Assumptions: no air, no convection and no board.
The thermal resistance from the junction to the bottom of the case is 6.4°C/W typical.
11.1.0.4 Thermal Resistance from Junction to Bottom of Air Gap
The thermal resistance from the junction to the bottom of the air gap (bottom of package) is
17.9°C/W typical.
11.1.0.5 Thermal Resistance from Junction to Ambient
The thermal resistance from the junction to ambient is 25.2°C/W typical.
Note: In order to keep the ambient temperature of the die within the specified limits of the device grade
(that is Tamb max = 70°C in commercial grade and 85°C in industrial grade) and the die junction
temperature below the maximum allowed junction temperature of 105°C, it is necessary to operate
the dual ADC in air flow conditions (1m/s recommended).
In still air conditions, the junction temperature is indeed greater than the maximum allowed TJ.
- TJ = 25.2°C/W x 1.4W + Tamb = 35.28 + 70 = 105.28°C for commercial grade devices
- TJ = 25.2°C/W x 1.4W + Tamb = 35.28 + 85 = 125.28°C for industrial grade devices
11.1.0.6 Thermal Resistance from Junction to Board
The thermal resistance from the junction to the board is 13°C/W typical.
12. Ordering Information
Part Number Package Temperature Range Screening Comments
AT84XAD004TD LQFP 144 Ambient Prototype Prototype version
Please contact your local Atmel sales office
AT84AD004BCTD LQFP 144 C grade
0°C < Tamb < 70°CStandard
AT84AD004BVTD LQFP 144 V grade
-40°C < Tamb < 85°CStandard
AT84AD004BCTDW LQFP 144 green
(RoHS compliant)
C grade
0°C < Tamb < 70°CStandard
AT84AD004BVTDW LQFP 144 green
(RoHS compliant)
V grade
-40°C < Tamb < 8 5°CStandard
AT84AD004BTD-EB LQFP 144 Ambient Prototype Evaluation kit
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5390B–BDC–02/06
AT84AD004B
13. Packaging Information
Figure 13-1. Package Type
Note: Thermally enhanced package: LQFP 144, 20 x 20 x 1.4 mm.
D
A1
A2
A
CC
0.25
0.17 max Lead coplanarity
Seating plane
Stand off
A1
b
Lccc c
ddd e cA-B e D e
6o+
-4o
0
0.20 RAD max.
0.20 RAD nom.
A
e
12 oTYP.
12 oTYP.
E1
N
1
E
B
D
D1
A
Notes: 1. All dimensions are in millimeters
2. Dimensions shown are nominal with tolerances as indicated
3. L/F: eftec 64T copper or equivalent
4. Foot length: "L" is measured at gauge plane
at 0.25 mm above the seating plane
Dims. Tols. Leads 144L
A max. 1.60
A1 0.05 min./0.15 max.
A2 +/- 0.05 1.40
D +/-0.20 22.00
D1 +/-0.10 20.00
E +/-0.20 22.00
E1 +/-0.10 20.00
L +0.15/-0.10 0.60
e basic 0.50
b +/-0.05 0.22
ddd 0.08
ccc max. 0.08
o 0 - 5
o
o
Body +2.00 mm footprint
Printed on recycled paper.
5390B–BDC–02/06
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5390B–BDC–02/06
AT84AD004B
i
5390B–BDC–02/06
AT84AD004B
Table of Contents
1 Description ............................................................................................... 2
2 Functional Description ............................................................................ 2
3 Typical Applications ................................................................................ 4
3.1 Absolute Maximum Ratings ...............................................................................5
3.2 Recommended Conditions of Use .....................................................................6
4 Electrical Operating Characteristics ...................................................... 6
4.1 Timing Diagrams .............................................................................................12
4.2 Functions Description ......................................................................................19
4.3 Digital Output Coding (Nominal Settings) ........................................................20
5 Pin Description ....................................................................................... 20
6 Typical Characterization Results ......................................................... 23
6.1 Typical Full Power Input Bandwidth ................................................................23
6.2 Typical Crosstalk .............................................................................................24
6.3 Typical DC, INL and DNL Patterns ..................................................................24
6.4 Typical Dynamic Performances Versus Sampling Frequency .........................25
6.5 Typical Dynamic Performances Versus Input Frequency ................................26
6.6 Typical Signal Spectrum ..................................................................................28
6.7 Typical Performance Sensitivity Versus Power Supplies and Temperature ....30
7 Test and Control Features .................................................................... 34
7.1 3-wire Serial Interface Control Setting .............................................................34
7.2 Die Junction Temperature Monitoring Function ...............................................42
7.3 VtestI, VtestQ ..................................................................................................43
8 Equivalent Input/Output Schematics ................................................... 43
9 Definitions of Terms .............................................................................. 46
10 Using the AT84AD004B Dual 8-bit 500 Msps ADC .............................. 48
10.1 Decoupling, Bypassing and Grounding of Power Supplies .............................48
10.2 Analog Input Implementation ...........................................................................49
10.3 Clock Implementation ......................................................................................50
10.4 Reset Implementation ......................................................................................51
10.5 Output Termination in 1:1 Ratio .......................................................................52
10.6 Using the Dual ADC With and ASIC/FPGA Load ............................................53
ii
5390B–BDC–02/06
AT84AD004B
11 Thermal Characteristics ........................................................................ 54
11.1 Simplified Thermal Model for LQFP 144
20 x 20 x 1.4 mm 54
12 Ordering Information ............................................................................. 55
13 Packaging Information .......................................................................... 56
Table of Contents....................................................................................... I
