LT3957
1
3957f
n Wide Input Voltage Range: 3V to 40V
n Single Feedback Pin for Positive or Negative
Output Voltage
n Internal 5A/40V Power Switch
n Current Mode Control Provides Excellent Transient
Response
n Programmable Operating Frequency (100kHz to
1MHz) with One External Resistor
n Synchronizable to an External Clock
n Low Shutdown Current < 1µA
n Internal 5.2V Low Dropout Voltage Regulator
n Programmable Input Undervoltage Lockout with
Hysteresis
n Programmable Soft-Start
n Thermally Enhanced QFN (5mm × 6mm) Package
TYPICAL APPLICATION
DESCRIPTION
Boost, Flyback, SEPIC and
Inverting Converter
with 5A, 40V Switch
The LT
®
3957 is a wide input range, current mode DC/DC
converter which is capable of generating either positive
or negative output voltages. It can be confi gured as either
a boost, fl yback, SEPIC or inverting converter. It features
an internal low side N-channel power MOSFET rated for
40V at 5A and driven from an internal regulated 5.2V
supply. The fi xed frequency, current-mode architecture
results in stable operation over a wide range of supply
and output voltages.
The operating frequency of LT3957 can be set with an
external resistor over a 100kHz to 1MHz range, and can
be synchronized to an external clock using the SYNC pin.
A minimum operating supply voltage of 3V, and a low
shutdown quiescent current of less than 1µA, make the
LT3957 ideally suited for battery-powered systems.
The LT3957 features soft-start and frequency foldback
functions to limit inductor current during start-up.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
No RSENSE and ThinSOT are trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Patents pending.
High Effi ciency Output Boost Converter
FEATURES
APPLICATIONS
n Automotive
n Telecom
n Industrial
Effi ciency vs Output Current
SENSE2
SENSE1
LT3957
10µH
VIN SW
GND
FBX
RT SS INTVCC
EN/UVLO
SYNC
SGND
95.3k
VC
3957 TA01a
200k
41.2k
300kHz 4.7µF
0.33µF 6.8k
22nF
226k
15.8k
10µF
s2
VOUT
24V
600mA
VIN
4.5V TO 16V
10µF
OUTPUT CURRENT (mA)
0
70
EFFICIENCY (%)
75
80
85
90
95
100
100 200 300 400 500
3957 TA01b
600
VIN = 12V
LT3957
2
3957f
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
VIN, EN/UVLO (Note 5), SW ......................................40V
INTVCC ......................................................VIN + 0.3V, 8V
SYNC ..........................................................................8V
VC, SS .........................................................................3V
RT ............................................................................................... 1.5V
SENSE1, SGND ..................Internally Connected to GND
SENSE2 ..................................................................±0.3V
FBX ................................................................. –6V to 6V
Operating Junction Temperature Range
(Note 2) .................................................. –40°C to 125°C
Maximum Junction Temperature .......................... 125°C
Storage Temperature Range .................. –65°C to 125°C
(Note 1)
12 13 14
TOP VIEW
SGND
37
SW
38
UHE PACKAGE
36-LEAD (5mm s 6mm) PLASTIC QFN
15 16 17
36 35 34 33 32 31 30
21
23
24
25
27
28
8
6
4
3
2
1NC
NC
SENSE2
SGND
SENSE1
SW
SW
NC
INTVCC
VIN
EN/UVLO
SGND
SGND
SW
SW
NC
NC
SYNC
RT
SS
FBX
VC
GND
GND
GND
GND
GND
GND
20
9
10
TJMAX = 125°C, θJA = 42°C/W, θJC = 3°C/W
EXPOSED PAD (PIN 37) IS SGND, MUST BE SOLDERED TO SGND PLANE
EXPOSED PAD (PIN 38) IS SW, MUST BE SOLDERED TO SW PLANE
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3957EUHE#PBF LT3957EUHE#TRPBF 3957 36-Lead (5mm × 6mm) Plastic QFN –40°C to 125°C
LT3957IUHE#PBF LT3957IUHE#TRPBF 3957 36-Lead (5mm × 6mm) Plastic QFN –40°C to 125°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
LT3957
3
3957f
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating temp-
erature range, otherwise specifi cations are at TA ≈ TJ = 25°C. VIN = 24V, EN/UVLO = 24V, SENSE2 = 0V, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Operating Range 340V
VIN Shutdown IQEN/UVLO = 0V
EN/UVLO = 1.15V
0.1 1
6
µA
µA
VIN Operating IQVC = 0.3V, RT = 41.2k 1.7 2.3 mA
VIN Operating IQ with Internal LDO Disabled VC = 0.3V, RT = 41.2k, INTVCC = 5.5V 350 400 µA
SW Pin Current Limit l5 5.9 6.8 A
SW Pin On Voltage ISW = 3A 100 mV
SENSE2 Input Bias Current Current Out of Pin –65 µA
Error Amplifi er
FBX Regulation Voltage (VFBX(REG)) FBX > 0V (Note 3)
FBX < 0V (Note 3)
l
l
1.569
–0.816
1.6
–0.800
1.631
–0.784
V
V
FBX Overvoltage Lockout FBX > 0V (Note 4)
FBX < 0V (Note 4)
6
7
8
11
10
14
%
%
FBX Pin Input Current FBX = 1.6V (Note 3)
FBX = –0.8V (Note 3) –10
70 100
10
nA
nA
Transconductance gm (ΔIVC /ΔFBX) (Note 3) 230 µS
VC Output Impedance (Note 3) 5 M
VFBX Line Regulation (ΔVFBX/[ΔVIN • VFBX(REG)]) FBX > 0V, 3V < VIN < 40V (Notes 3, 6)
FBX < 0V, 3V < VIN < 40V (Notes 3, 6)
0.04
0.03
0.06
0.06
%/V
%/V
VC Current Mode Gain (ΔVVC /ΔVSENSE)10 V/V
VC Source Current VC = 1.5V, FBX = 0V, Current Out of Pin –15 µA
VC Sink Current FBX = 1.7V
FBX = –0.85V
12
11
µA
µA
Oscillator
Switching Frequency RT = 140k to SGND, FBX = 1.6V, VC = 1.5V
RT = 41.2k to SGND, FBX = 1.6V, VC = 1.5V
RT = 10.5k to SGND, FBX = 1.6V, VC = 1.5V
80
270
850
100
300
1000
120
330
1200
kHz
kHz
kHz
RT Voltage FBX = 1.6V 1.2 V
SW Minimum Off-Time 220 275 ns
SW Minimum On-Time 240 320 ns
SYNC Input Low 0.4
SYNC Input High 1.5
SS Pull-Up Current SS = 0V, Current Out of Pin –10 µA
Low Dropout Regulator
INTVCC Regulation Voltage l5 5.2 5.45 V
INTVCC Undervoltage Lockout Threshold Falling INTVCC
UVLO Hysteresis
2.6 2.7
0.15
2.85 V
V
LT3957
4
3957f
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating temp-
erature range, otherwise specifi cations are at TA ≈ TJ = 25°C. VIN = 24V, EN/UVLO = 24V, SENSE2 = 0V, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
INTVCC Current Limit VIN = 40V
VIN = 15V
32 40
95
55 mA
mA
INTVCC Load Regulation (ΔVINTVCC /V
INTVCC)0 < IINTVCC < 20mA, VIN = 8V –1 –0.5 %
INTVCC Line Regulation (ΔVINTVCC /[ΔVIN • VINTVCC]) 6V < VIN < 40V 0.02 0.05 %/V
Dropout Voltage (VIN – VINTVCC)V
IN = 5V, IINTVCC = 20mA, VC = 0V 450 mV
INTVCC Current in Shutdown EN/UVLO = 0V, INTVCC = 6V 17 µA
INTVCC Voltage to Bypass Internal LDO 5.5 V
Logic Inputs
EN/UVLO Threshold Voltage Falling VIN = INTVCC = 6V l1.17 1.22 1.27 V
EN/UVLO Voltage Hysteresis 20 mV
EN/UVLO Input Low Voltage IVIN Drops Below 1µA 0.4 V
EN/UVLO Pin Bias Current Low EN/UVLO = 1.15V 1.7 2 2.5 µA
EN/UVLO Pin Bias Current High EN/UVLO = 1.33V 20 100 nA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3957E is guaranteed to meet performance specifi cations
from the 0°C to 125°C operating junction temperature. Specifi cations over
the –40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LT3957I is guaranteed over the full –40°C to 125°C operating junction
temperature range.
Note 3: The LT3957 is tested in a feedback loop which servos VFBX to the
reference voltages (1.6V and –0.8V) with the VC pin forced to 1.3V.
Note 4: FBX overvoltage lockout is measured at VFBX(OVERVOLTAGE) relative
to regulated VFBX(REG).
Note 5: For 3V ≤ VIN < 6V, the EN/UVLO pin must not exceed VIN.
Note 6: EN/UVLO = 1.33V when VIN = 3V.
TYPICAL PERFORMANCE CHARACTERISTICS
Positive Feedback Voltage
vs Temperature, VIN
Negative Feedback Voltage
vs Temperature, VIN
Quiescent Current
vs Temperature, VIN
TA ≈ TJ = 25°C, unless otherwise noted.
TEMPERATURE (°C)
–50
1580
REGULATED FEEDBACK VOLTAGE (mV)
1590
1600
1605
050 75
1585
–25 25 100 125
3957 G01
VIN = 40V
VIN = 24V
VIN = 8V
VIN = INTVCC = 3V,
SHDN/UVLO = 1.33V
TEMPERATURE (°C)
–50
–804
REGULATED FEEDBACK VOLTAGE (mV)
–802
–800
–796
–798
–794
–788
–790
050 75
–792
–25 25 100 125
3957 G02
VIN = 40V
VIN = 24V
VIN = 8V
VIN = INTVCC = 3V
SHDN/UVLO = 1.33V
TEMPERATURE (°C)
–50
1.4
QUIESCENT CURRENT (mA)
1.6
1.8
050 75
1.5
1.7
–25 25 100 125
3957 G03
VIN = 40V
VIN = 24V
VIN = INTVCC = 3V
LT3957
5
3957f
TYPICAL PERFORMANCE CHARACTERISTICS
TA ≈ TJ = 25°C, unless otherwise noted.
Dynamic Quiescent Current
vs Switching Frequency RT vs Switching Frequency
Normalized Switching
Frequency vs FBX
SWITCHING FREQUENCY (kHz)
100
0
IQ(mA)
4
6
12
300 500 600 700
2
8
10
200 400 900800 1000
3957 G04
SWITCHING FREQUENCY (kHz)
0
10
RT(k)
100
1000
300 500 600 700
100 200 400 900800 1000
3957 G05
FBX VOLTAGE (V)
–0.8
0
NORMALIZED FREQUENCY (%)
20
40
60
80
120
–0.4 0 0.4 0.8
3957 G06
1.2 1.6
100
Switching Frequency
vs Temperature
SW Pin Current Limit
vs Temperature
TEMPERATURE (°C)
–50
275
SWITCHING FREQUENCY (kHz)
280
285
290
295
300
305
310
325
–25 025 7550
3957 G07
100 125
315
320 RT = 41.2k
TEMPERATURE (°C)
–50
5.4
SW PIN CURRENT LIMIT (A)
6.0
5.8
6.2
6.4
6.6
050 75
5.6
–25 25 100 125
3957 G08
SW Pin Current Limit
vs Duty Cycle
DUTY CYCLE (%)
0
5.4
5.6
5.8
SW PIN CURRENT LIMIT (A)
6.2
20 40 8060
6.6
6.0
6.4
100
3957 G09
EN/UVLO Threshold
vs Temperature EN/UVLO Current vs Voltage
EN/UVLO Hysteresis Current
vs Temperature
TEMPERATURE (°C)
–50
1.18
1.22
1.24
1.28
050 75
1.20
–25 25 100 125
1.26
3957 G10
EN/UVLO VOLTAGE (V)
EN/UVLO RISING
EN/UVLO FALLING
EN/UVLO VOLTAGE (V)
0
0
EN/UVLO CURRENT (µA)
20
10 3020
40
10
30
40
3957 G11
TEMPERATURE (°C)
–50
1.6
IEN/UVLO (µA)
1.8
2.0
2.2
2.4
050 75
–25 25 100 125
3957 G12
LT3957
6
3957f
INTVCC Line Regulation
INTVCC Dropout Voltage
vs Current, Temperature
INTVCC vs Temperature
INTVCC Minimum Output
Current Limit vs VIN INTVCC Load Regulation
TYPICAL PERFORMANCE CHARACTERISTICS
TA ≈ TJ = 25°C, unless otherwise noted.
TEMPERATURE (°C)
–50
5.0
INTVCC (V)
5.1
5.2
5.3
5.4
050 75
–25 25 100 125
3957 G13
1
0
10
20
40
60
10 100
90
80
30
50
70
TJ = 125°C
INTVCC = 3V
VIN (V)
3957 G14
INTVCC CURRENT (mA)
INTVCC LOAD (mA)
0
4.8
5.0
5.1
5.2
5.3
30 50 60
4.9
10 20 40
3957 G15
INTVCC VOLTAGE (V)
VIN = 6V
VIN (V)
0
INTVCC VOLTAGE (V)
5.25
5.20
10 15 25
520 30 35 40
5.15
5.10
5.30
3957 G16 INTVCC LOAD (mA)
0
DROPOUT VOLTAGE (mV)
600
400
500
200
300
5 101520
100
0
700
3957 G17
125°C
25°C
0°C
–40°C
75°C
VIN = 5V
Internal Switch On-Resistance
vs Temperature
TEMPERATURE (°C)
–50
ON-RESISTANCE (mΩ)
35
40
45
30
25
–25 250 50 75 100 125
10
5
0
20
50
15
3957 G18
Internal Switch On-Resistance
vs INTVCC
SEPIC Typical Start-Up
Waveforms
SEPIC FBX Frequency Foldback
Waveforms During Overcurrent
INTVCC (V)
3
ON-RESISTANCE (mΩ)
27.8
28.0
27.6
27.4
27.2
45 768
27.0
26.8
26.6
28.2
3957 G19
5ms/DIV
SEE TYPICAL APPLICATION: 5V TO 16V INPUT,
12V OUTPUT SEPIC CONVERTER
VOUT
5V/DIV
IL1A + IL1B
2A/DIV
3957 G20
VIN = 12V
50µs/DIV
VOUT
10V/DIV
VSW
20V/DIV
IL1A + IL1B
5A/DIV
3957 G21
VIN = 12V
SEE TYPICAL APPLICATION: 5V TO 16V INPUT,
12V OUTPUT SEPIC CONVERTER
LT3957
7
3957f
PIN FUNCTIONS
NC (Pins 1, 2, 10, 35, 36): No Internal Connection. Leave
these pins open or connect them to the adjacent pins.
SENSE2 (Pin 3): The Current Sense Input for the Control
Loop. Connect this pin to SENSE1 pin directly or through
a low pass fi lter (connect this pin to SENSE1 pin through
a resistor, and to SGND through a capacitor).
SGND (Pins 4, 23, 24, Exposed Pad Pin 37): Signal
Ground. All small-signal components should connect to
this ground. SGND is connected to GND inside the IC to
ensure Kelvin connection for the internal switch current
sensing. Do not connect SGND and GND externally.
SENSE1 (Pin 6): The Current Sense Output of the Inter-
nal N-channel MOSFET. Connect this pin to SENSE2 pin
directly or through a low pass fi lter (connect this pin to
SENSE1 pin through a resistor, then connect SENSE2 to
SGND through a capacitor).
SW (Pins 8, 9, 20, 21, Exposed Pad Pin 38): Drain of
Internal Power N-channel MOSFET.
GND (Pins 12, 13, 14, 15, 16, 17): Ground. These pins
connect to the source terminal of internal power N-channel
MOSFET through an internal sense resistor. GND is con-
nected to SGND inside the IC to ensure Kelvin connection
for the internal switch current sensing. Do not connect
GND and SGND externally.
EN/UVLO (Pin 25): Shutdown and Undervoltage Detect
Pin. An accurate 1.22V (nominal) falling threshold with
externally programmable hysteresis detects when power
is okay to enable switching. Rising hysteresis is generated
by the external resistor divider and an accurate internal
2µA pull-down current. An undervoltage condition resets
soft-start. Tie to 0.4V, or less, to disable the device and
reduce VIN quiescent current below 1µA.
VIN (Pin 27): Input Supply Pin. The VIN pin can be locally
bypassed with a capacitor to GND (not SGND).
INTVCC (Pin 28): Regulated Supply for Internal Loads
and Gate Driver. Supplied from VIN and regulated to
5.2V (typical). INTVCC must be bypassed to SGND with a
minimum of 4.7µF capacitor placed close to pin. INTVCC
can be connected directly to VIN, if VIN is less than 8V.
INTVCC can also be connected to a power supply whose
voltage is higher than 5.5V, and lower than VIN, provided
that supply does not exceed 8V.
VC (Pin 30): Error Amplifi er Compensation Pin. Used to
stabilize the voltage loop with an external RC network.
Place compensation components between the VC pin
and SGND.
FBX (Pin 31): Positive and Negative Feedback Pin. Re-
ceives the feedback voltage from the external resistor
divider between the output and SGND. Also modulates the
switching frequency during start-up and fault conditions
when FBX is close to SGND.
SS (Pin 32): Soft-Start Pin. This pin modulates compen-
sation pin voltage (VC) clamp. The soft-start interval is
set with an external capacitor between SS pin and SGND.
The pin has a 10µA (typical) pull-up current source to
an internal 2.5V rail. The soft-start pin is reset to SGND
by an undervoltage condition at EN/UVLO, an INTVCC
undervoltage or overvoltage condition or an internal
thermal lockout.
RT (Pin 33): Switching Frequency Adjustment Pin. Set
the frequency using a resistor to SGND. Do not leave this
pin open.
SYNC (Pin 34): Frequency Synchronization Pin. Used to
synchronize the switching frequency to an outside clock.
If this feature is used, an RT resistor should be chosen
to program a switching frequency 20% slower than the
SYNC pulse frequency. Tie the SYNC pin to SGND if this
feature is not used. SYNC is bypassed when FBX is close
to SGND.
LT3957
8
3957f
BLOCK DIAGRAM
Figure 1. LT3957 Block Diagram Working as a SEPIC Converter
L1
R3R4
L2
1.22V
2.5V
D1
CDC
CIN
VOUT
COUT
CVCC
INTVCC
SENSE1
GND
SENSE2
M2
VIN
RSENSE
M1
VISENSE
•
VIN
IS1
2µA
27
SW
28
12, 13, 14,
15, 16, 17
25
EN/UVLO
INTERNAL
REGULATOR
AND UVLO
TLO
165˚C
A10
Q3
VC
2.7V
A8
UVLO
IS2
10µA
IS3
DRIVER
SLOPE
SENSE
48mV
SR1
+
–
CURRENT
LIMIT
RAMP
GENERATOR
5.2V LDO
•
+
–
RO
S
2.5V
RT
RT
SS
CSS
SYNC
1.28V
1.2V
1.6V
–0.8V
+
–
+
–
+
–
32
VC
30
FBX
31 34 33 SGND
4, 23,
24, 37
+
–
+
–
6
3
RAMP
PWM
COMPARATOR
FREQUENCY
FOLDBACK
100kHz-1MHz
OSCILLATOR
FREQ
PROG
CC2
CC1
3957 F01
–
+
+Q1
A1
A2
1.72V
–0.88V
+
–
+
–
A11
A12
A3
A4
A5
A6
G2
G5
G6
A7
Q2
G4
8, 9, 20,
21, 38
R1
R2
VOUT RC
G1
LT3957
9
3957f
APPLICATIONS INFORMATION
Main Control Loop
The LT3957 uses a fi xed frequency, current mode control
scheme to provide excellent line and load regulation. Op-
eration can be best understood by referring to the Block
Diagram in Figure 1.
The start of each oscillator cycle sets the SR latch (SR1)
and turns on the internal power MOSFET switch M1 through
driver G2. The switch current fl ows through the internal
current sensing resistor RSENSE and generates a voltage
proportional to the switch current. This current sense
voltage VISENSE (amplifi ed by A5) is added to a stabilizing
slope compensation ramp and the resulting sum (SLOPE)
is fed into the positive terminal of the PWM comparator A7.
When SLOPE exceeds the level at the negative input of A7
(VC pin), SR1 is reset, turning off the power switch. The
level at the negative input of A7 is set by the error amplifi er
A1 (or A2) and is an amplifi ed version of the difference
between the feedback voltage (FBX pin) and the reference
voltage (1.6V or –0.8V, depending on the confi guration).
In this manner, the error amplifi er sets the correct peak
switch current level to keep the output in regulation.
The LT3957 has a switch current limit function. The current
sense voltage is input to the current limit comparator A6.
If the SENSE2 pin voltage is higher than the sense current
limit threshold VSENSE(MAX) (48mV, typical), A6 will reset
SR1 and turn off M1 immediately.
The LT3957 is capable of generating either positive or
negative output voltage with a single FBX pin. It can be
confi gured as a boost, fl yback or SEPIC converter to gen-
erate positive output voltage, or as an inverting converter
to generate negative output voltage. When confi gured as
a SEPIC converter, as shown in Figure 1, the FBX pin is
pulled up to the internal bias voltage of 1.6V by a volt-
age divider (R1 and R2) connected from VOUT to SGND.
Comparator A2 becomes inactive and comparator A1
performs the inverting amplifi cation from FBX to VC.
When the LT3957 is in an inverting confi guration, the
FBX pin is pulled down to –0.8V by a voltage divider
connected from VOUT to SGND. Comparator A1 becomes
inactive and comparator A2 performs the noninverting
amplifi cation from FBX to VC.
The LT3957 has overvoltage protection functions to
protect the converter from excessive output voltage
overshoot during start-up or recovery from a short-circuit
condition. An overvoltage comparator A11 (with 20mV
hysteresis) senses when the FBX pin voltage exceeds the
positive regulated voltage (1.6V) by 8% and provides a
reset pulse. Similarly, an overvoltage comparator A12
(with 10mV hysteresis) senses when the FBX pin voltage
exceeds the negative regulated voltage (–0.8V) by 11%
and provides a reset pulse. Both reset pulses are sent to
the main RS latch (SR1) through G6 and G5. The power
MOSFET switch M1 is actively held off for the duration of
an output overvoltage condition.
Programming Turn-On and Turn-Off Thresholds with
the EN/UVLO Pin
The EN/UVLO pin controls whether the LT3957 is enabled
or is in shutdown state. A micropower 1.22V reference,
a comparator A10 and a controllable current source IS1
allow the user to accurately program the supply voltage
at which the IC turns on and off. The falling value can be
accurately set by the resistor dividers R3 and R4. When
EN/UVLO is above 0.4V, and below the 1.22V threshold,
the small pull-down current source IS1 (typical 2µA) is
active.
The purpose of this current is to allow the user to program
the rising hysteresis. The Block Diagram of the comparator
and the external resistors is shown in Figure 1. The typical
falling threshold voltage and rising threshold voltage can
be calculated by the following equations:
VVIN,FALLING =1.22 • (R3 +R4)
R4
VVIN,RISING =2µA • R3 +VIN,FALLING
For applications where the EN/UVLO pin is only used as
a logic input, the EN/UVLO pin can be connected directly
to the input voltage VIN for always-on operation.
LT3957
10
3957f
APPLICATIONS INFORMATION
INTVCC Regulator Bypassing and Operation
An internal, low dropout (LDO) voltage regulator produces
the 5.2V INTVCC supply which powers the gate driver, as
shown in Figure 1. The LT3957 contains an undervoltage
lockout comparator A8 for the INTVCC supply. The INTVCC
undervoltage (UV) threshold is 2.7V (typical), with 0.1V
hysteresis, to ensure that the internal MOSFET has suf-
fi cient gate drive voltage before turning on. When INTVCC
is below the UV threshold, the internal power switch will
be turned off and the soft-start operation will be triggered.
The logic circuitry within the LT3957 is also powered from
the internal INTVCC supply.
The INTVCC regulator must be bypassed to SGND imme-
diately adjacent to the IC pins with a minimum of 4.7µF
ceramic capacitor. Good bypassing is necessary to supply
the high transient currents required by the MOSFET gate
driver.
In an actual application, most of the IC supply current is
used to drive the gate capacitance of the internal power
MOSFET. The on-chip power dissipation can be signifi cant
when the internal power MOSFET is being driven at a high
frequency and the VIN voltage is high.
An effective approach to reduce the power consumption of
the internal LDO for gate drive and to improve the effi ciency
is to tie the INTVCC pin to an external voltage source high
enough to turn off the internal LDO regulator.
In SEPIC or fl yback applications, the INTVCC pin can be
connected to the output voltage VOUT through a blocking
diode, as shown in Figure 2, if VOUT meets the following
conditions:
1. VOUT < VIN (pin voltage)
2. VOUT < 8V
A resistor RVCC can be connected, as shown in Figure 2, to
limit the inrush current from VOUT. Regardless of whether
or not the INTVCC pin is connected to an external voltage
source, it is always necessary to have the driver circuitry
bypassed with a 4.7µF low ESR ceramic capacitor to ground
immediately adjacent to the INTVCC and SGND pins.
If LT3957 operates at a low VIN and high switching fre-
quency, the voltage drop across the drain and the source of
the LDO PMOS (M2 in Figure 1) could push INTVCC to be
below the UV threshold. To prevent this from happening,
the INTVCC pin can be shorted directly to the VIN pin. VIN
must not exceed the INTVCC Absolute Maximum Rating
(8V). In this condition, the internal LDO will be turned off
and the gate driver will be powered directly from VIN. It is
recommended that INTVCC pin be shorted to the VIN pin if
VIN is lower than 3.5V at 1MHz switching frequency, or VIN
is lower than 3.2V at 100kHz switching frequency. With
the INTVCC pin shorted to VIN, however, a small current
(around 16µA) will load the INTVCC in shutdown mode.
Figure 2. Connecting INTVCC to VOUT
CVCC
4.7µF
VOUT
3957 F02
INTVCC
SGND
LT3957
RVCC
DVCC
LT3957
11
3957f
APPLICATIONS INFORMATION
Operating Frequency and Synchronization
The choice of operating frequency may be determined by
on-chip power dissipation (a low switching frequency may
be required to ensure IC junction temperature does not
exceed 125°C), otherwise it is a trade-off between effi ciency
and component size. Low frequency operation improves
effi ciency by reducing gate drive current and MOSFET
and diode switching losses. However, lower frequency
operation requires a physically larger inductor. Switching
frequency also has implications for loop compensation.
The LT3957 uses a constant-frequency architecture that
can be programmed over a 100kHz to 1000kHz range
with a single external resistor from the RT pin to SGND,
as shown in Figure 1. A table for selecting the value of RT
for a given operating frequency is shown in Table 1.
Table 1. Timing Resistor (RT) Value
SWITCHING FREQUENCY (kHz) RT (kΩ)
100 140
200 63.4
300 41.2
400 30.9
500 24.3
600 19.6
700 16.5
800 14
900 12.1
1000 10.5
The operating frequency of the LT3957 can be synchronized
to an external clock source. By providing a digital clock
signal into the SYNC pin, the LT3957 will operate at the
SYNC clock frequency. The LT3957 detects the rising edge
of each clock cycle. If this feature is used, an RT resistor
should be chosen to program a switching frequency 20%
slower than SYNC pulse frequency. It is recommended that
the SYNC pin has a minimum pulse width of 200ns. Tie
the SYNC pin to SGND if this feature is not used.
Duty Cycle Consideration
Switching duty cycle is a key variable defi ning con-
verter operation. As such, its limits must be considered.
Minimum on-time is the smallest time duration that the
LT3957 is capable of turning on the power MOSFET. This
time is typically about 240ns (see Minimum On-Time in
the Electrical Characteristics table). In each switching
cycle, the LT3957 keeps the power switch off for at least
220ns (typical) (see Minimum Off-Time in the Electrical
Characteristics table).
The minimum on-time, minimum off-time and the switching
frequency defi ne the minimum and maximum switching
duty cycles a converter is able to generate:
Minimum duty cycle = minimum on-time • frequency
Maximum duty cycle = 1 – (minimum off-time • frequency)
Programming the Output Voltage
The output voltage VOUT is set by a resistor divider, as
shown in Figure 1. The positive and negative VOUT are set
by the following equations:
VOUT,POSITIVE =1.6V • 1+R2
R1
⎛
⎝
⎜⎞
⎠
⎟
VOUT,NEGATIVE =–0.8V • 1+R2
R1
⎛
⎝
⎜⎞
⎠
⎟
The resistors R1 and R2 are typically chosen so that
the error caused by the current fl owing into the FBX pin
during normal operation is less than 1% (this translates
to a maximum value of R1 at about 158k).
LT3957
12
3957f
APPLICATIONS INFORMATION
Soft-Start
The LT3957 contains several features to limit peak switch
currents and output voltage (VOUT) overshoot during
start-up or recovery from a fault condition. The primary
purpose of these features is to prevent damage to external
components or the load.
High peak switch currents during start-up may occur in
switching regulators. Since VOUT is far from its fi nal value,
the feedback loop is saturated and the regulator tries to
charge the output capacitor as quickly as possible, resulting
in large peak currents. A large surge current may cause
inductor saturation or power switch failure.
The LT3957 addresses this mechanism with the SS pin.
As shown in Figure 1, the SS pin reduces the power
MOSFET current by pulling down the VC pin through
Q2. In this way the SS allows the output capacitor to
charge gradually toward its fi nal value while limiting the
start-up peak currents. The typical start-up waveforms
are shown in the Typical Performance Characteristics
section. The inductor current IL slewing rate is limited by
the soft-start function.
Besides start-up (with EN/UVLO), soft-start can also be
triggered by the following faults:
1. INTVCC < 2.85V
2. Thermal lockout (TLO > 165°C)
Any of these three faults will cause the LT3957 to stop
switching immediately. The SS pin will be discharged by
Q3. When all faults are cleared and the SS pin has been
discharged below 0.2V, a 10µA current source IS2 starts
charging the SS pin, initiating a soft-start operation.
The soft-start interval is set by the soft-start capacitor
selection according to the equation:
TSS =CSS •1.25V
10µA
FBX Frequency Foldback
When VOUT is very low during start-up, or an output short-
circuit on a SEPIC, an inverting, or a fl yback converter, the
switching regulator must operate at low duty cycles to keep
the power switch current below the current limit, since
the inductor current decay rate is very low during switch
off time. The minimum on-time limitation may prevent the
switcher from attaining a suffi ciently low duty cycle at the
programmed switching frequency. So, the switch current
may keep increasing through each switch cycle, exceed-
ing the programmed current limit. To prevent the switch
peak currents from exceeding the programmed value, the
LT3957 contains a frequency foldback function to reduce
the switching frequency when the FBX voltage is low (see
the Normalized Switching Frequency vs FBX graph in the
Typical Performance Characteristics section).
During frequency foldback, external clock synchroniza-
tion is disabled to prevent interference with frequency
reducing operation.
Loop Compensation
Loop compensation determines the stability and transient
performance. The LT3957 uses current mode control to
regulate the output which simplifi es loop compensation.
The optimum values depend on the converter topology, the
component values and the operating conditions (including
the input voltage, load current, etc.). To compensate the
feedback loop of the LT3957, a series resistor-capacitor
network is usually connected from the VC pin to SGND.
Figure 1 shows the typical VC compensation network.
For most applications, the capacitor should be in the
range of 470pF to 22nF, and the resistor should be in the
range of 5k to 50k. A small capacitor is often connected
in parallel with the RC compensation network to attenu-
ate the VC voltage ripple induced from the output voltage
ripple through the internal error amplifi er. The parallel
capacitor usually ranges in value from 10pF to 100pF. A
practical approach to design the compensation network
is to start with one of the circuits in this data sheet that
is similar to your application, and tune the compensation
network to optimize the performance. Stability should
then be checked across all operating conditions, including
load current, input voltage and temperature. Application
Note 76 is a good reference on loop compensation.
LT3957
13
3957f
APPLICATIONS INFORMATION
The Internal Power Switch Current
For control and protection, the LT3957 measures the
internal power MOSFET current by using a sense resistor
(RSENSE) between GND and the MOSFET source. Figure 3
shows a typical waveform of the internal switch current
(ISW).
Due to the current limit (minimum 5A) of the internal power
switch, the LT3957 should be used in the applications
that the switch peak current ISW(PEAK) during steady state
normal operation is lower than 5A by a suffi cient margin
(10% or higher is recommended).
The LT3957 switching controller incorporates 100ns
timing interval to blank the ringing on the current sense
signal across RSENSE immediately after M1 is turned on.
This ringing is caused by the parasitic inductance and
capacitance of the PCB trace, the sense resistor, the diode,
and the MOSFET. The 100ns timing interval is adequate
for most of the LT3957 applications. In the applications
that have very large and long ringing on the current sense
signal, a small RC fi lter can be added to fi lter out the excess
ringing. Figure 4 shows the RC fi lter on the SENSE1 and
SENSE2 pins. It is usually suffi cient to choose 22 for
RFLT and 2.2nF to 10nF for CFLT. Keep RFLT’s resistance
low. Remember that there is 65µA (typical) fl owing out of
the SENSE2 pin. Adding RFLT will affect the internal power
switch current limit threshold:
ISW _ILIM =1−65µA •RFLT
48mV
⎛
⎝
⎜⎞
⎠
⎟•5A
On-Chip Power Dissipation and Thermal Lockout (TLO)
The on-chip power dissipation of LT3957 can be estimated
using the following equation:
P
IC ≈ I2SW • D • RDS(ON) + V2PEAK • ISW • ƒ • 200pF/A +
V
IN • (1.6mA + ƒ • 10nC)
where RDS(ON) is the internal switch on-resistance which
can be obtained from the Typical Performance Characteris-
tics section. VSW(PEAK) is the peak switch off-state voltage.
The maximum power dissipation PIC(MAX) can be obtained
by comparing PIC across all the VIN range at the maximum
output current . The highest junction temperature can be
estimated using the following equation:
T
J(MAX) ≈ TA + PIC(MAX) • 42°C/W
It is recommended to measure the IC temperature in steady
state to verify that the junction temperature limit is not
exceeded. A low switching frequency may be required to
ensure TJ(MAX) does not exceed 125°C.
If LT3957 die temperature reaches thermal lockout
threshold at 165°C (typical), the IC will initiate several
protective actions. The power switch will be turned off.
A soft-start operation will be triggered. The IC will be en-
abled again when the junction temperature has dropped
by 5°C (nominal).
Figure 3. The Switch Current During a Switching Cycle
3957 F03
ISW(PEAK)
$ISW
ISW
t
DTS
TS
Figure 4. The RC Filter on SENSE1 Pin and SENSE2 Pin
3957 F04
LT3957
RFLT
CFLT
SENSE2
SGND
SENSE1
LT3957
14
3957f
APPLICATIONS INFORMATION
APPLICATION CIRCUITS
The LT3957 can be confi gured as different topologies. The
fi rst topology to be analyzed will be the boost converter,
followed by the fl yback, SEPIC and inverting converters.
Boost Converter: Switch Duty Cycle and Frequency
The LT3957 can be confi gured as a boost converter for
the applications where the converter output voltage is
higher than the input voltage. Remember that boost con-
verters are not short-circuit protected. Under a shorted
output condition, the inductor current is limited only by
the input supply capability. For applications requiring a
step-up converter that is short-circuit protected, please
refer to the Applications Information section covering
SEPIC converters.
The conversion ratio as a function of duty cycle is
VOUT
VIN
=1
1−D
in continuous conduction mode (CCM).
For a boost converter operating in CCM, the duty cycle
of the main switch can be calculated based on the output
voltage (VOUT) and the input voltage (VIN). The maximum
duty cycle (DMAX) occurs when the converter has the
minimum input voltage:
DMAX =VOUT −VIN(MIN)
VOUT
Discontinuous conduction mode (DCM) provides higher
conversion ratios at a given frequency at the cost of reduced
effi ciencies and higher switching currents.
Boost Converter: Maximum Output Current Capability
and Inductor Selection
For the boost topology, the maximum average inductor
current is:
IL(MAX)= IO(MAX) •1
1−DMAX
Due to the current limit of its internal power switch, the
LT3957 should be used in a boost converter whose maxi-
mum output current (IO(MAX)) is less than the maximum
output current capability by a suffi cient margin (10% or
higher is recommended):
IO(MAX) <VIN(MIN)
VOUT
•5A−0.5 • ΔISW
(
)
The inductor ripple current ΔISW has a direct effect on the
choice of the inductor value and the converter’s maximum
output current capability. Choosing smaller values of
ΔISW increases output current capability, but requires
large inductances and reduces the current loop gain (the
converter will approach voltage mode). Accepting larger
values of ΔISW provides fast transient response and
allows the use of low inductances, but results in higher
input current ripple and greater core losses, and reduces
output current capability.
Given an operating input voltage range, and having chosen
the operating frequency and ripple current in the inductor,
the inductor value of the boost converter can be determined
using the following equation:
L=VIN(MIN)
ΔISW •ƒ•D
MAX
The peak inductor current is the switch current limit (5.9A
typical), and the RMS inductor current is approximately
equal to IL(MAX). The user should choose the inductors
having suffi cient saturation and RMS current ratings.
Boost Converter: Output Diode Selection
To maximize effi ciency, a fast switching diode with low
forward drop and low reverse leakage is desirable. The
peak reverse voltage that the diode must withstand is
equal to the regulator output voltage plus any additional
ringing across its anode-to-cathode during the on-time.
The average forward current in normal operation is equal
to the output current.
It is recommended that the peak repetitive reverse voltage
rating VRRM is higher than VOUT by a safety margin (a 10V
safety margin is usually suffi cient).
LT3957
15
3957f
APPLICATIONS INFORMATION
The power dissipated by the diode is:
P
D = IO(MAX) • VD
where VD is diode’s forward voltage drop, and the diode
junction temperature is:
T
J = TA + PD • RθJA
The RθJA to be used in this equation normally includes the
RθJC for the device plus the thermal resistance from the board
to the ambient temperature in the enclosure. TJ must not
exceed the diode maximum junction temperature rating.
Boost Converter: Output Capacitor Selection
Contributions of ESR (equivalent series resistance), ESL
(equivalent series inductance) and the bulk capacitance
must be considered when choosing the correct output
capacitors for a given output ripple voltage. The effect of
these three parameters (ESR, ESL and bulk C) on the output
voltage ripple waveform for a typical boost converter is
illustrated in Figure 5.
The choice of component(s) begins with the maximum
acceptable ripple voltage (expressed as a percentage of
the output voltage), and how this ripple should be divided
between the ESR step ΔVESR and the charging/discharg-
ing ΔVCOUT. For the purpose of simplicity, we will choose
2% for the maximum output ripple, to be divided equally
between ΔVESR and ΔVCOUT. This percentage ripple will
change, depending on the requirements of the application,
and the following equations can easily be modifi ed. For a
1% contribution to the total ripple voltage, the ESR of the
output capacitor can be determined using the following
equation:
ESRCOUT ≤0.01• VOUT
ID(PEAK)
For the bulk C component, which also contributes 1% to
the total ripple:
COUT ≥IO(MAX)
0.01• VOUT •ƒ
The output capacitor in a boost regulator experiences high
RMS ripple currents, as shown in Figure 5. The RMS ripple
current rating of the output capacitor can be determined
using the following equation:
IRMS(COUT) ≥IO(MAX) •DMAX
1−DMAX
Multiple capacitors are often paralleled to meet ESR require-
ments. Typically, once the ESR requirement is satisfi ed, the
capacitance is adequate for fi ltering and has the required
RMS current rating. Additional ceramic capacitors in par-
allel are commonly used to reduce the effect of parasitic
inductance in the output capacitor, which reduces high
frequency switching noise on the converter output.
Boost Converter: Input Capacitor Selection
The input capacitor of a boost converter is less critical
than the output capacitor, due to the fact that the inductor
is in series with the input, and the input current wave-
form is continuous. The input voltage source impedance
determines the size of the input capacitor, which is typi-
cally in the range of 1µF to 100µF. A low ESR capacitor
is recommended, although it is not as critical as for the
output capacitor.
The RMS input capacitor ripple current for a boost con-
verter is:
I
RMS(CIN) = 0.3 • ΔIL
Figure 5. The Output Ripple Waveform of a Boost Converter
VOUT
(AC)
tON
$VESR
RINGING DUE TO
TOTAL INDUCTANCE
(BOARD + CAP)
$VCOUT
3957 F05
tOFF
LT3957
16
3957f
APPLICATIONS INFORMATION
Figure 7 shows the waveforms of the fl yback converter
in discontinuous mode operation. During each switching
period TS, three subintervals occur: DTS, D2TS, D3TS.
During DTS, M is on, and D is reverse-biased. During
D2TS, M is off, and LS is conducting current. Both LP and
LS currents are zero during D3TS.
FLYBACK CONVERTER APPLICATIONS
The LT3957 can be confi gured as a fl yback converter for the
applications where the converters have multiple outputs,
high output voltages or isolated outputs. Due to the 40V
rating of the internal power switch, LT3797 should be used
in low input voltage fl yback converters. Figure 6 shows a
simplifi ed fl yback converter.
The fl yback converter has a very low parts count for mul-
tiple outputs, and with prudent selection of turns ratio, can
have high output/input voltage conversion ratios with a
desirable duty cycle. However, it has low effi ciency due to
the high peak currents, high peak voltages and consequent
power loss. The fl yback converter is commonly used for
an output power of less than 50W.
The fl yback converter can be designed to operate either
in continuous or discontinuous mode. Compared to con-
tinuous mode, discontinuous mode has the advantage of
smaller transformer inductances and easy loop compen-
sation, and the disadvantage of higher peak-to-average
current and lower effi ciency.
Figure 7. Waveforms of the Flyback Converter
in Discontinuous Mode Operation
3957 F07
ISW
VSW
ID
t
DTSD2TSD3TS
ISW(MAX)
ID(MAX)
TS
Figure 6. A Simplifi ed Flyback Converter
NP:NS
VIN
CIN CSN
VSN
LP
D
SUGGESTED
RCD SNUBBER
ID
ISW
3957 F06
GND
SW
LT3957
LS
+
–
RSN
DSN
+
–
+
VOUT
COUT
+
Flyback Converter: Switch Duty Cycle and Turns Ratio
The fl yback converter conversion ratio in the continuous
mode operation is:
VOUT
VIN
=NS
NP
•D
1−D
where NS/NP is the second to primary turns ratio. D is
duty cycle.
The fl yback converter conversion ratio in the discontinu-
ous mode operation is:
VOUT
VIN
=NS
NP
•D
D2
According to Figure 6, the peak SW voltage is:
V
SW(PEAK) = VIN(MAX) + VSN
where VSN is the snubber capacitor voltage. A smaller VSN
results in a larger snubber loss. A reasonable VSN is 1.5
to 2 times of the refl ected output voltage:
VSN =k•VOUT •N
P
NS
k = 1.5 ~ 2
LT3957
17
3957f
APPLICATIONS INFORMATION
According to the Absolute Maximum Ratings table, the SW
voltage Absolute Maximum value is 40V. Therefore, the
maximum primary to secondary turns ratio (for both the
continuous and the discontinuous operation) should be.
NP
NS
≤40V −VIN(MAX)
k•V
OUT
According to the preceding equations, the user has relative
freedom in selecting the switch duty cycle or turns ratio to
suit a given application. The selections of the duty cycle
and the turns ratio are somewhat iterative processes, due
to the number of variables involved. The user can choose
either a duty cycle or a turns ratio as the start point. The
following trade-offs should be considered when select-
ing the switch duty cycle or turns ratio, to optimize the
converter performance. A higher duty cycle affects the
fl yback converter in the following aspects:
• Lower MOSFET RMS current ISW(RMS), but higher
MOSFET VSW peak voltage
• Lower diode peak reverse voltage, but higher diode
RMS current ID(RMS)
• Higher transformer turns ratio (NP/NS)
It is recommended to choose a duty cycle between 20%
and 80%.
Flyback Converter: Maximum Output Current
Capability and Transformer Design
The maximum output current capability and transformer
design for continuous conduction mode (CCM) is chosen
as presented here.
The maximum duty cycle (DMAX) occurs when the converter
has the minimum VIN:
DMAX =
VOUT •NP
NS
⎛
⎝
⎜⎞
⎠
⎟
VOUT •NP
NS
⎛
⎝
⎜⎞
⎠
⎟+VIN(MIN)
Due to the current limit of its internal power switch, the
LT3957 should be used in a fl yback converter whose maxi-
mum output current (IO(MAX)) is less than the maximum
output current capability by a suffi cient margin (10% or
higher is recommended):
IO(MAX) <VIN(MIN)
VOUT
•D
MAX •5A−0.5 • ΔISW
(
)
The transformer ripple current ΔISW has a direct effect on
the design/choice of the transformer and the converter’s
output current capability. Choosing smaller values of
ΔISW increases the output current capability, but requires
large primary and secondary inductances and reduce the
current loop gain (the converter will approach voltage
mode). Accepting larger values of ΔISW allows the use
of low primary and secondary inductances, but results
in higher input current ripple, greater core losses, and
reduces the output current capability.
Given an operating input voltage range, and having chosen
the operating frequency and ripple current in the primary
winding, the primary winding inductance can be calculated
using the following equation:
L=VIN(MIN)
ΔISW •ƒ•D
MAX
The primary winding peak current is the switch current
limit (typical 5.9A). The primary and secondary maximum
RMS currents are:
ILP(RMS) ≈ POUT(MAX)
DMAX •V
IN(MIN) •η
ILS(RMS) ≈ IOUT(MAX)
1−DMAX
where η is the converter effi ciency.
Based on the preceding equations, the user should de-
sign/choose the transformer having suffi cient saturation
and RMS current ratings.
Flyback Converter: Snubber Design
Transformer leakage inductance (on either the primary or
secondary) causes a voltage spike to occur after the MOS-
FET turn-off. This is increasingly prominent at higher load
currents, where more stored energy must be dissipated.
LT3957
18
3957f
APPLICATIONS INFORMATION
In some cases a snubber circuit will be required to avoid
overvoltage breakdown at the MOSFET’s drain node. There
are different snubber circuits (such as RC snubber, RCD
snubber, Zener clamp, etc.), and Application Note 19 is a
good reference on snubber design. An RC snubber circuit
can be connected between SW and GND to damp the
ringing on SW pins. The snubber resistor values should
be close to the impedance of the parasitic resonance. The
snubber capacitor value should be larger than the circuit
parasitic capacitance, but be small enough to keep the
snubber resistor power dissipation low.
If the RC snubber is insuffi cient to prevent SW pins over-
voltage, the RCD snubber can be used to limit the peak
voltage on the SW pins, which is shown in Figure 6.
The snubber resistor value (RSN) can be calculated by the
following equation:
RSN =2•
V2SN −VSN •V
OUT •NP
NS
I2SW(PEAK) •LLK •ƒ
LLK is the leakage inductance of the primary winding,
which is usually specifi ed in the transformer character-
istics. LLK can be obtained by measuring the primary
inductance with the secondary windings shorted. The
snubber capacitor value (CSN) can be determined using
the following equation:
CCN =VSN
ΔVSN •RSN •ƒ
where ΔVSN is the voltage ripple across CSN. A reasonable
ΔVSN is 5% to 10% of VSN. The reverse voltage rating of
DSN should be higher than the sum of VSN and VIN(MAX).
A Zener clamp can also be connected between SW and
GND to ensure SW voltage does not exceed 40V.
Flyback Converter: Output Diode Selection
The output diode in a fl yback converter is subject to large
RMS current and peak reverse voltage stresses. A fast
switching diode with a low forward drop and a low reverse
leakage is desired. Schottky diodes are recommended if
the output voltage is below 100V.
Approximate the required peak repetitive reverse voltage
rating VRRM using:
VRRM >NS
NP
•V
IN(MAX) +VOUT
The power dissipated by the diode is:
P
D = IO(MAX) • VD
and the diode junction temperature is:
T
J = TA + PD • RθJA
The RθJA to be used in this equation normally includes the
RθJC for the device, plus the thermal resistance from the board
to the ambient temperature in the enclosure. TJ must not
exceed the diode maximum junction temperature rating.
Flyback Converter: Output Capacitor Selection
The output capacitor of the fl yback converter has a similar
operation condition as that of the boost converter. Refer to
the Boost Converter: Output Capacitor Selection section
for the calculation of COUT and ESRCOUT.
The RMS ripple current rating of the output capacitors
in continuous operation can be determined using the
following equation:
IRMS(COUT),CONTINUOUS ≈IO(MAX) •DMAX
1−DMAX
Flyback Converter: Input Capacitor Selection
The input capacitor in a fl yback converter is subject to
a large RMS current due to the discontinuous primary
current. To prevent large voltage transients, use a low
ESR input capacitor sized for the maximum RMS current.
The RMS ripple current rating of the input capacitors in
continuous operation can be determined using the fol-
lowing equation:
IRMS(CIN),CONTINUOUS ≈POUT(MAX)
VIN(MIN) •η•1−DMAX
DMAX
LT3957
19
3957f
APPLICATIONS INFORMATION
SEPIC CONVERTER APPLICATIONS
The LT3957 can be confi gured as a SEPIC (single-ended
primary inductance converter), as shown in Figure 1. This
topology allows for the input to be higher, equal, or lower
than the desired output voltage. The conversion ratio as
a function of duty cycle is:
VOUT +VD
VIN
=D
1−D
in continuous conduction mode (CCM).
In a SEPIC converter, no DC path exists between the input
and output. This is an advantage over the boost converter
for applications requiring the output to be disconnected
from the input source when the circuit is in shutdown.
Compared to the fl yback converter, the SEPIC converter
has the advantage that both the power MOSFET and the
output diode voltages are clamped by the capacitors (CIN,
CDC and COUT), therefore, there is less voltage ringing
across the power MOSFET and the output diodes. The
SEPIC converter requires much smaller input capacitors
than those of the fl yback converter. This is due to the fact
that, in the SEPIC converter, the current through inductor
L1 (which is series with the input) is continuous.
SEPIC Converter: Switch Duty Cycle and Frequency
For a SEPIC converter operating in CCM, the duty cycle
of the main switch can be calculated based on the output
voltage (VOUT), the input voltage (VIN) and the diode
forward voltage (VD).
The maximum duty cycle (DMAX) occurs when the converter
has the minimum input voltage:
DMAX =VOUT +VD
VIN(MIN) +VOUT +VD
SEPIC Converter: The Maximum Output Current
Capability and Inductor Selection
As shown in Figure 1, the SEPIC converter contains two
inductors: L1 and L2. L1 and L2 can be independent, but
can also be wound on the same core, since identical volt-
ages are applied to L1 and L2 throughout the switching
cycle.
For the SEPIC topology, the current through L1 is the
converter input current. Based on the fact that, ideally, the
output power is equal to the input power, the maximum
average inductor currents of L1 and L2 are:
IL1(MAX) =IIN(MAX) =IO(MAX) •DMAX
1−DMAX
IL2(MAX) =IO(MAX)
Due to the current limit of its internal power switch,
the LT3957 should be used in a SEPIC converter whose
maximum output current (IO(MAX)) is less than the output
current capability by a suffi cient margin (10% or higher
is recommended):
IO(MAX) <1−DMAX
(
)
•5A−0.5 • ΔISW
(
)
The inductor ripple currents ΔIL1 and ΔIL2 are identical:
ΔIL1 = ΔIL2 = 0.5 • ΔISW
The inductor ripple current ΔISW has a direct effect on the
choice of the inductor value and the converter’s maximum
output current capability. Choosing smaller values of ΔISW
requires large inductances and reduces the current loop
gain (the converter will approach voltage mode). Accepting
larger values of ΔISW allows the use of low inductances,
but results in higher input current ripple and greater core
losses and reduces output current capability.
Given an operating input voltage range, and having chosen
the operating frequency and ripple current in the induc-
tor, the inductor value (L1 and L2 are independent) of the
SEPIC converter can be determined using the following
equation:
L1 = L2 = VIN(MIN)
0.5 • ΔISW •ƒ•D
MAX
For most SEPIC applications, the equal inductor values
will fall in the range of 1µH to 100µH.
LT3957
20
3957f
APPLICATIONS INFORMATION
By making L1 = L2, and winding them on the same core, the
value of inductance in the preceding equation is replaced
by 2L, due to mutual inductance:
L=VIN(MIN)
ΔISW •ƒ•D
MAX
This maintains the same ripple current and energy storage
in the inductors. The peak inductor currents are:
I
L1(PEAK) = IL1(MAX) + 0.5 • ΔIL1
I
L2(PEAK) = IL2(MAX) + 0.5 • ΔIL2
The maximum RMS inductor currents are approximately
equal to the maximum average inductor currents.
Based on the preceding equations, the user should choose
the inductors having suffi cient saturation and RMS cur-
rent ratings.
SEPIC Converter: Output Diode Selection
To maximize effi ciency, a fast switching diode with a low
forward drop and low reverse leakage is desirable. The
average forward current in normal operation is equal to
the output current.
It is recommended that the peak repetitive reverse voltage
rating VRRM is higher than VOUT + VIN(MAX) by a safety
margin (a 10V safety margin is usually suffi cient).
The power dissipated by the diode is:
P
D = IO(MAX) • VD
where VD is diode’s forward voltage drop, and the diode
junction temperature is:
T
J = TA + PD • RθJA
The RθJA used in this equation normally includes the RθJC
for the device, plus the thermal resistance from the board,
to the ambient temperature in the enclosure. TJ must not
exceed the diode maximum junction temperature rating.
SEPIC Converter: Output and Input Capacitor Selection
The selections of the output and input capacitors of the
SEPIC converter are similar to those of the boost converter.
Please refer to the Boost Converter: Output Capacitor
Selection and Boost Converter: Input Capacitor Selection
sections.
SEPIC Converter: Selecting the DC Coupling Capacitor
The DC voltage rating of the DC coupling capacitor (CDC,
as shown in Figure 1) should be larger than the maximum
input voltage:
V
CDC > VIN(MAX)
CDC has nearly a rectangular current waveform. During
the switch off-time, the current through CDC is IIN, while
approximately –IO fl ows during the on-time. The RMS
rating of the coupling capacitor is determined by the fol-
lowing equation:
IRMS(CDC) >IO(MAX) •VOUT +VD
VIN(MIN)
A low ESR and ESL, X5R or X7R ceramic capacitor works
well for CDC.
INVERTING CONVERTER APPLICATIONS
The LT3957 can be confi gured as a dual-inductor inverting
topology, as shown in Figure 8. The VOUT to VIN ratio is:
VOUT −VD
VIN
=− D
1−D
in continuous conduction mode (CCM).
Figure 8. A Simplifi ed Inverting Converter
CDC
VIN
CIN
L1
D1
COUT VOUT
3757 F10
+
GND
LT3957
SW
L2
+
–
+–
+
LT3957
21
3957f
APPLICATIONS INFORMATION
Inverting Converter: Switch Duty Cycle and Frequency
For an inverting converter operating in CCM, the duty cycle
of the main switch can be calculated based on the negative
output voltage (VOUT) and the input voltage (VIN).
The maximum duty cycle (DMAX) occurs when the converter
has the minimum input voltage:
DMAX =VOUT −VD
VOUT −VD−VIN(MIN)
Inverting Converter: Output Diode and Input Capacitor
Selections
The selections of the inductor, output diode and input
capacitor of an inverting converter are similar to those
of the SEPIC converter. Please refer to the corresponding
SEPIC converter sections.
Inverting Converter: Output Capacitor Selection
The inverting converter requires much smaller output
capacitors than those of the boost, fl yback and SEPIC
converters for similar output ripples. This is due to the fact
that, in the inverting converter, the inductor L2 is in series
with the output, and the ripple current fl owing through the
output capacitors are continuous. The output ripple voltage
is produced by the ripple current of L2 fl owing through the
ESR and bulk capacitance of the output capacitor:
ΔVOUT(P–P) =ΔIL2 •ESR
COUT +1
8•ƒ•C
OUT
⎛
⎝
⎜⎞
⎠
⎟
After specifying the maximum output ripple, the user can
select the output capacitors according to the preceding
equation.
The ESR can be minimized by using high quality X5R or
X7R dielectric ceramic capacitors. In many applications,
ceramic capacitors are suffi cient to limit the output volt-
age ripple.
The RMS ripple current rating of the output capacitor
needs to be greater than:
I
RMS(COUT) > 0.3 • ΔIL2
Inverting Converter: Selecting the DC Coupling Capacitor
The DC voltage rating of the DC coupling capacitor
(CDC, as shown in Figure 10) should be larger than the
maximum input voltage minus the output voltage (nega-
tive voltage):
V
CDC > VIN(MAX) – VOUT
CDC has nearly a rectangular current waveform. During
the switch off-time, the current through CDC is IIN, while
approximately –IO fl ows during the on-time. The RMS
rating of the coupling capacitor is determined by the fol-
lowing equation:
IRMS(CDC) >IO(MAX) •DMAX
1−DMAX
A low ESR and ESL, X5R or X7R ceramic capacitor works
well for CDC.
Board Layout
The high power and high speed operation of the LT3957
demands careful attention to board layout and component
placement. Careful attention must be paid to the internal
power dissipation of the LT3957 at high input voltages,
high switching frequencies, and high internal power switch
currents to ensure that a junction temperature of 125°C is
not exceeded. This is especially important when operating
at high ambient temperatures. Exposed pads on the bot-
tom of the package are SGND and SW terminals of the IC,
and must be soldered to a SGND ground plane and a SW
plane respectively. It is recommended that multiple vias
in the printed circuit board be used to conduct heat away
from the IC and into the copper planes with as much as
area as possible.
To prevent radiation and high frequency resonance
problems, proper layout of the components connected
to the IC is essential, especially the power paths with
higher di/dt. The following high di/dt loops of different
topologies should be kept as tight as possible to reduce
inductive ringing:
• In boost confi guration, the high di/dt loop contains the
output capacitor, the internal power MOSFET and the
Schottky diode.
LT3957
22
3957f
APPLICATIONS INFORMATION
• In fl yback confi guration, the high di/dt primary loop
contains the input capacitor, the primary winding, the
internal power MOSFET. The high di/dt secondary loop
contains the output capacitor, the secondary winding
and the output diode.
• In SEPIC confi guration, the high di/dt loop contains
the internal power MOSFET, output capacitor, Schottky
diode and the coupling capacitor.
• In inverting confi guration, the high di/dt loop contains
internal power MOSFET, Schottky diode and the coupling
capacitor.
Check the stress on the internal power MOSFET by measur-
ing the SW-to-GND voltage directly across the IC terminals.
Make sure the inductive ringing does not exceed the
maximum rating of the internal power MOSFET (40V).
The small-signal components should be placed away from
high frequency switching nodes. For optimum load regula-
tion and true remote sensing, the top of the output voltage
sensing resistor divider should connect independently to
the top of the output capacitor (Kelvin connection), staying
away from any high dV/dt traces. Place the divider resis-
tors near the LT3957 in order to keep the high impedance
FBX node short.
Figure 9 shows the suggested layout of the 4.5V to16V
input, 24V output boost converter in the Typical Applica-
tion section.
3958 F09
LT3957
37
38
12 13 14 15 16 17
36 35 34 33 32 31 30
21
23
24
25
27
28
8
6
4
3
2
1
20
9
10
VIA TO VOUT
R1
R2
CSS
RTRCCC
CVCC
R3
R4
D1
L1
COUT
COUT
CIN
GND VOUT
VIN
VIA TO VOUT
VIAS TO SGND GROUND PLANE
VIAS TO SW PLANE
Figure 9. Suggested Layout of the 4.5V to 16V Input. 24V Output Boost Converter in the Typical Application Section
LT3957
23
3957f
APPLICATIONS INFORMATION
Table 2. Recommended Component Manufacturers
VENDOR COMPONENTS WEB ADDRESS
AVX Capacitors avx.com
BH Electronics Inductors,
Transformers
bhelectronics.com
Coilcraft Inductors coilcraft.com
Cooper Bussmann Inductors bussmann.com
Diodes, Inc Diodes diodes.com
General Semiconductor Diodes generalsemiconductor.
com
International Rectifi er Diodes irf.com
Kemet Tantalum Capacitors kemet.com
Magnetics Inc Toroid Cores mag-inc.com
Microsemi Diodes microsemi.com
Murata-Erie Inductors, Capacitors murata.co.jp
Nichicon Capacitors nichicon.com
On Semiconductor Diodes onsemi.com
Panasonic Capacitors panasonic.com
Pulse Inductors pulseeng.com
Sanyo Capacitors sanyo.co.jp
Sumida Inductors sumida.com
Taiyo Yuden Capacitors t-yuden.com
TDK Capacitors, Inductors component.tdk.com
Thermalloy Heat Sinks aavidthermalloy.com
Tokin Capacitors nec-tokinamerica.com
Toko Inductors tokoam.com
United Chemi-Con Capacitors chemi-com.com
Vishay Inductors vishay.com
Würth Elektronik Inductors we-online.com
Vishay/Sprague Capacitors vishay.com
Zetex Small-Signal Discretes zetex.com
Recommended Component Manufacturers
Some of the recommended component manufacturers
are listed in Table 2.
LT3957
24
3957f
TYPICAL APPLICATIONS
4.5V to 16V Input, 24V Output Boost Converter
Effi ciency vs Output Current
SENSE2
SENSE1
LT3957
L1
10µH
VIN SW
GND
FBX
RT SS INTVCC
EN/UVLO
SYNC
SGND
R4
95.3k
VC
3957 TA02a
D1
R3
200k
RT
41.2k
300kHz
CVCC
4.7µF
10V
X5R
CSS
0.33µF
RC
6.8k
CC
22nF
R2
226k
R1
15.8k
COUT
10µF
50V
X5R
s2
VOUT
24V
600mA
VIN
4.5V TO 16V CIN
10µF
25V
X5R
CIN: MURATA GRM31ER61H106KA12
COUT: TAIYO YUDEN UMK325BJ106MM
D1: VISHAY SILICONIX 10BQ040
L1: VISHAY SILICONIX IHLP-5050CE-1
OUTPUT CURRENT (mA)
0
70
EFFICIENCY (%)
75
80
85
90
95
100
100 200 300 400 500
3957 TA02b
600
VIN = 12V
LT3957
25
3957f
TYPICAL APPLICATIONS
5V to 16V Input, 12V Output SEPIC Converter
Effi ciency vs Output Current Load Step Waveforms
Start-Up Waveforms
Frequency Foldback Waveforms
When Output Short-Circuit
SENSE2
SENSE1
LT3957
L1A
L1B
VIN SW
GND
FBX
RT SS INTVCC
EN/UVLO
SYNC
SGND
82.5k
VC
3957 TA03a
D1
200k
41.2k
300kHz
CVCC
4.7µF
10V
X5R
0.47µF 10k
10nF
105k
15.8k
CDC
4.7µF, 25V
X5R VOUT
12V
1A
VIN
5V TO 16V CIN
4.7µF
25V
X5R
COUT
22µF
16V
X5R
s2
•
•
CIN, CDC: MURATA GRM21BR61E475KA12L
COUT: MURATA GRM32ER61C226KE20
D1: VISHAY SILICONIX 30BQ040
L1A, L1B: COILTRONICS DRQ127-100
OUTPUT CURRENT (mA)
0
50
EFFICIENCY (%)
65
60
55
70
75
80
85
90
95
100
200 400 600 800
3957 TA03b
1000
VIN = 12V
500µs/DIV
VOUT
0.5V/DIV
(AC)
IOUT
0.5A/DIV
0.8A
0.2A
3957 TA03c
VIN = 12V
5ms/DIV
VOUT
5V/DIV
IL1A + IL1B
2A/DIV
3957 TA03d
VIN = 12V
50µs/DIV
VOUT
10V/DIV
VSW
20V/DIV
IL1A + IL1B
5A/DIV
3957 TA03e
VIN = 12V
LT3957
26
3957f
TYPICAL APPLICATIONS
5V to 16V Input, –12V Output Inverting Converter
Effi ciency vs Output Current Load Step Waveforms
Start-Up Waveforms
Frequency Foldback Waveforms
When Output Short-Circuit
SENSE2
SENSE1
LT3957
L1A L1B
VIN SW
GND
FBX
RT SS INTVCC
EN/UVLO
SYNC
SGND
82.5k
VC
3957 TA04a
D1
200k
41.2k
300kHz
CVCC
4.7µF
10V
X5R
0.47µF 10k
10nF
105k
7.5k
CDC
4.7µF, 50V
X7R VOUT
–12V
1A
VIN
5V TO 16V CIN
4.7µF
25V
X5R
COUT
22µF
16V
X5R
s2
•
•
CIN: MURATA GRM21BR61E475KA12L
CDC: TAIYO YUDEN UMK316BJ475KL
COUT: MURATA GRM32ER61C226KE20
D1: VISHAY SILICONIX 30BQ040
L1A, L1B: COILTRONICS DRQ127-100
OUTPUT CURRENT (mA)
0
50
EFFICIENCY (%)
65
60
55
70
75
80
85
90
95
100
200 400 600 800
3957 TA04b
1000
VIN = 12V
500µs/DIV
VOUT
1V/DIV
(AC)
IOUT
0.5A/DIV
0.8A
0.2A
3957 TA04c
VIN = 12V
5ms/DIV
VOUT
5V/DIV
IL1A + IL1B
2A/DIV
3957 TA04d
VIN = 12V
50µs/DIV
VOUT
10V/DIV
VSW
20V/DIV
IL1A + IL1B
5A/DIV
3957 TA04e
VIN = 12V
LT3957
27
3957f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
UHE Package
Variation: UHE28MA
36-Lead Plastic QFN (5mm × 6mm)
(Reference LTC DWG # 05-08-1836 Rev B)
5.00 p 0.10
6.00 p 0.10
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 p 0.10
1
363530 31 32 33 34
28
20
21
23
24
25
27 2
3
4
6
8
9
10
121314151617
BOTTOM VIEW—EXPOSED PAD
2.00 REF
1.50 REF
0.75 p 0.05
R = 0.125
TYP
R = 0.10
TYP
PIN 1 NOTCH
R = 0.30 OR
0.35 s 45o
CHAMFER
0.25 p 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UHE28MA) QFN 0409 REV B
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 p0.05
4.10 p 0.05
5.50 p 0.05
PACKAGE OUTLINE
1.88 p 0.10
1.53 p 0.10
2.00 REF
1.50 REF
5.10 p 0.05
6.50 p 0.05
3.00 p 0.10
3.00 p 0.10
0.12
p 0.10
1.88
p 0.05
1.53
p 0.05
3.00 p 0.05 3.00 p 0.05
0.48 p 0.05
0.12
p 0.05
0.48 p 0.10
0.25 p0.05
0.50 BSC
1012 34 6 89
17
20212324252728
30
31
32
33
34
35
36
12
13
14
15
16
LT3957
28
3957f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2010
LT 0610 • PRINTED IN USA
TYPICAL APPLICATIONS
PART NUMBER DESCRIPTION COMMENTS
LT3958 High Input Voltage, Boost, Flyback, SEPIC and
Inverting Converter with 3.5A/80V Switch
5V ≤ VIN < 80V, Current Mode Control, 100kHz to 1MHz Programmable
Operation Frequency, 5mm × 6mm QFN-36 Package
LT3580 Boost/Inverting DC/DC Converter with 2A Switch, Soft-
Start and Synchronization
2.5V ≤ VIN ≤ 32V, Current Mode Control, 200kHz to 2.5MHz, 3mm × 3mm
DFN-8, MSOP-8E
LT3573 Isolated Flyback Converter with 1.25A/60V Integrated
Switch
3V ≤ VIN ≤ 40V, No Opto-Isolator or "Third Winding" Required, Up to 7W,
MSOP-16E
LT3574 Isolated Flyback Converter with 0.65A/60V Integrated
Switch
3V ≤ VIN ≤ 40V, No Opto-Isolator or “Third Winding” Required, Up to 3W,
MSOP-16
LT3757 Boost, Flyback, SEPIC and Inverting Controller 2.9V ≤ VIN ≤ 40V, Current Mode Control, 100kHz to 1MHz Programmable
Operation Frequency, 3mm × 3mm DFN-10 and MSOP-10E Package
LT3758 Boost, Flyback, SEPIC and Inverting Controller 5.5V ≤ VIN ≤ 100V, Current Mode Control, 100kHz to 1MHz Programmable
Operation Frequency, 3mm × 3mm DFN-10 and MSOP-10E Package
LTC1871/LTC1871-1/
LTC1871-7
Wide Input Range, No RSENSE™ Low Quiescent Current
Flyback, Boost and SEPIC Controller
Adjustable Switching Frequency, 2.5V ≤ VIN ≤ 36V, Burst Mode Operation
at Light Load
LTC3803/LTC3803-3/
LTC3803-5
200kHz/300kHz Flyback DC/DC Controller VIN and VOUT Limited Only by External Components, ThinSOT™ Package
RELATED PARTS
4V to 6V Input, 180V Output Flyback Converter
SENSE2
FBX
SENSE1
LT3957
T1
1:10
VIN SW GND
RT SS INTVCC
EN/UVLO
SYNC
SGND
37.4k
VC
3957 TA05
D1
D2
DANGER! HIGH VOLTAGE!
75k
22Ω 220pF
140k
100kHz
4.7µF
10V
X5R
10nF
0.1µF 10k
10nF
100pF
22Ω
15.8k
1.80M
COUT
68nF
s2
VOUT
180V
15mA
VIN
4V TO 6V
CIN
100µF
6.3V
s2
T1: TDK DCT15EFD-U44S003
CIN: GRM31CR60J107ME39L
COUT: GRM43QR72J683KW01L
D1: VISHAY SILICONIX GSD2004S DUAL DIODE CONNECTED IN SERIES
D2: DIODES MMSZ5258B
•
•
