Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks Revision History Rev. No. History Issue Date 1.0 Initial issue Apr. 07, 2005 1.1 Revised DC/AC characteristics Nov. 22, 2006 1 Remark Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks DESCRIPTION The CS56A12863 is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 2,097,152x16x4 (word x bit x bank). Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable device to be useful for a variety of high bandwidth, high performance memory system applications. FEATURES JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency (2 & 3 ) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst Read single write operation DQM for masking Auto & self refresh 64ms refresh period (4K cycle) Product Family Part No. Operating Temp ( oC) Vcc. Range (V) Speed (ns) 3.0~3.6 6 / 7.5 0~70oC CS56A12863 -40~85oC 2 Package Type Dice 54 TSOP 2 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks PIN ASSIGNMENT - 54L TSOP 2- 400mil FUNCTIONAL BLOCK DIAGRAM 3 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks PIN FUNCTION DESCRIPTION PIN NAME INPUT CLK System Clock /CS Chip Select FUNCTION Active on the positive going edge to sample all inputs Disables or enables device operation by masking or enabling all inputs except CLK , CKE and L(U)DQM Masks system clock to freeze operation from the next clock cycle. CKE CKE Clock Enable should be enabled at least one cycle prior new command. Disable input buffers for power down in standby. Row / column address are multiplexed on the same pins. A0 ~ A11 Address A12, A13 Bank Select Address /RAS Row Address Strobe /CAS Column Address Strobe /WE Write Enable L (U) DQM Data Input / Output Mask DQ0 ~ DQ15 Data Input / Output Data inputs / outputs are multiplexed on the same pins. VDD / VSS Power Supply / Ground Power and ground for the input buffers and the core logic. VDDQ / VSSQ Data Output Power / Ground NC No Connection Row address : RA0~RA11, column address : CA0~CA8 Selects bank to be activated during row address latch time. Selects bank for read / write during column address latch time. Latches row addresses on the positive going edge of the CLK with /RAS low. (Enables row access & precharge.) Latches column address on the positive going edge of the CLK with /CAS low. (Enables column access.) Enables write operation and row precharge. Latches data in starting from /CAS , /WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when L(U)DQM active. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device. SIMPLIFIED TRUTH TABLE COMMAND Register Mode Register set Auto Refresh Refresh Self Refresh Entry Exit Bank Active & Row Addr. CKE CKE n-1 n H X H H L L H H X A13 A10 A11 A12 /AP A9~A0 /CS /RAS /CAS /WE DQM L L L L X OP CODE L L L H X X L H H H X H X X X X L L H H X 4 1,2 3 3 3 X V Note 3 Row Address Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks COMMAND CKE CKE n-1 n /CS /RAS /CAS /WE DQM A13 A10 A11 A12 /AP A9~A0 L Column Auto Precharge Read & Disable Column Auto Precharge Address H X L H L H X V Enable Auto Precharge Write & Disable Column Auto Precharge Address H X L H L L X Burst Stop X L H H L X H X L L H L X Entry H L H X X X L V V V Exit L H X X X X Entry H L H X X X L H H H H X X X L V V V Bank Selection Precharge All Banks Clock Suspend or Active Power Down Precharge Power Down Mode Exit H (A0~A8) 4,5 L Column 4 Address (A0~A8) H H L DQM H No Operating Command (NOP) H H X X H X X X L H H H X V L X H X X X X X X X V X X X 7 Note: 1. OP Code : Operating Code A0~A11 & A13~A12 : Program keys. (@ MRS) MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge of command is meant by "Auto". Auto/self refresh can be issued only at all banks idle state. 4. A13~A12 : Bank select addresses. If A13 and A12 are "Low" at read ,write , row active and precharge ,bank A is selected. If A13 is "Low" and A12 is "High" at read ,write , row active and precharge ,bank B is selected. If A13 is "High" and A12 is "Low" at read ,write , row active and precharge ,bank C is selected. If A13 and A12 are "High" at read ,write , row active and precharge ,bank D is selected If A10/AP is "High" at row precharge , A13 and A12 is ignored and all banks are selected. 5 4,5 6 (V = Valid , X = Don't Care. H = Logic High , L = Logic Low ) 2. 4 Address V Enable Note Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks 5. During burst read or write with auto precharge. new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2) MODE REGISTER TABLE TO PROGRAM MODES Register Programmed with MRS Address A13~A12 A11~A10/AP A9 Function RFU RFU W.B.L. Test Mode A8 A7 A8 A7 A6 Test Mode CAS Latency A5 A4 CAS Latency A3 A2 Burst Type Burst Type A1 A0 Burst Length Burst Length Type A6 A5 A4 Latency A3 Type A2 A1 A0 BT=0 BT=1 0 0 Mode Register Set 0 0 0 Reserved 0 Sequential 0 0 0 1 1 0 1 Reserved 0 0 1 Reserved 1 Interleave 0 0 1 2 2 1 0 Reserved 0 1 0 2 0 1 0 4 4 1 1 Reserved 0 1 1 3 0 1 1 8 8 1 0 0 Reserved 1 0 0 Reserved Reserved 1 0 1 Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved 1 1 0 Reserved Reserved 1 1 1 Reserved 1 1 1 Full Page Reserved Full Page Length: 512 (for 8M x16 device). POWER UP SEQUENCE 1. Apply power and start clock, Attempt to maintain CKE = "H", DQM = "H" and the other pin are NOP condition at the inputs. 2. Maintain stable power , stable clock and NOP input condition for a minimum of 200us. 3. Issue precharge commands for all banks of the devices. 4. Issue 2 or more auto-refresh commands. 5. Issue mode register set command to initialize the mode register. cf.) Sequence of 4 & 5 is regardless of the order. The device is now ready for normal operation. Note: 1. RFU (Reserved for future use) should stay "0" during MRS cycle. 2. If A9 is high during MRS cycle, " Burst Read single write" function will be enabled. 6 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks BURST SEQUENCE (BURST LENGTH = 4) Initial Address Sequential Interleave A1 A0 0 0 0 1 2 3 0 1 2 3 0 1 1 2 3 0 1 0 3 2 1 0 2 3 0 1 2 3 0 1 1 1 3 0 1 2 3 2 1 0 BURST SEQUENCE (BURST LENGTH = 8) Initial Address Sequential Interleave A2 A1 A0 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 DEVICE OPERATION Clock (CLK) The clock input is used as the reference for all SDRAM operations. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between VIL and VIH. During operation with CKE high all inputs are assumed to be in valid state (low or high) for the duration of setup and hold time around positive edge of the clock for proper functionality and ICC specifications. Clock Enable (CKE) The clock enable (CKE) gates the clock onto SDRAM. If CKE goes low synchronously with clock (set-up and hold time same as other inputs), the internal clock suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. All other inputs are ignored from the next clock cycle after CKE goes low. When all banks are in the idle state and CKE goes low synchronously with clock, the SDRAM enters the power down mode from the next clock cycle. The SDRAM remains in the power down mode ignoring the other inputs as long as CKE remains low. The power down exit is synchronous as the internal clock is suspended. When CKE goes high at least "1CLK + tSS" before the high going edge of the clock, then the SDRAM becomes active from the same clock edge accepting all the input commands. 7 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks Bank Addresses (A13~A12) This SDRAM is organized as four independent banks of 2,097,152 words x 16 bits memory arrays. The A13~A12 inputs are latched at the time of assertion of /RAS and /CAS to select the bank to be used for the operation. The banks addressed A13~A12 are latched at bank active, read, write, mode register set and precharge operations. Address Inputs (A0~A11) The 21 address bits are required to decode the 2,097,152 word locations are multiplexed into 12 address input pins (A0~A11). The 12 row addresses are latched along with /RAS and A13~A12 during bank active command. The 9 bit column addresses are latched along with /CAS , /WE and A13~A12 during read or with command. NOP and Device Deslect When /RAS , /CAS and /WE are high , The SDRAM performs no operation (NOP). NOP does not initiate any new operation, but is needed to complete operations which require more than single clock cycle like bank activate, burst read, auto refresh, etc. The device deselect is also a NOP and is entered by asserting /CS high. /CS high disables the command decoder so that /RAS , /CAS , /WE and all the address inputs are ignored. Power-up 1. Apply power and start clock, Attempt to maintain CKE = "H", DQM = "H" and the other pins are NOP condition at the inputs. 2. Maintain stable power, stable clock and NOP input condition for minimum of 200us. 3. Issue precharge commands for both banks of the devices. 4. Issue 2 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. cf.) Sequence of 4 & 5 is regardless of the order. The device is now ready for normal operation. Mode Register Set (MRS) The mode register stores the data for controlling the various operating modes of SDRAM. It programs the CAS latency, burst type, burst length, test mode and various vendor specific options to make SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after power up to operate the SDRAM. The mode register is written by asserting low on /CS , /RAS , /CAS and /WE (The SDRAM should be in active mode with CKE already high prior to writing the mode register). The state of address pins A0~A11 and A13~A12 in the same cycle as /CS , /RAS , /CAS and /WE going low is the data written in the mode register. Two clock cycles is required to complete the write in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields into depending 8 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks on functionality. The burst length field uses A0~A2, burst type uses A3, CAS latency (read latency from column address) use A4~A6, vendor specific options or test mode use A7~A8, A10/AP~A11 and A13~A12. The write burst length is programmed using A9. A7~A8, A10/AP~A11 and A13~A12 must be set to low for normal SDRAM operation. Refer to the table for specific codes for various burst length, burst type and CAS latencies. Bank Activate The bank activate command is used to select a random row in an idle bank. By asserting low on /RAS and /CS with desired row and bank address, a row access is initiated. The read or write operation can occur after a time delay of tRCD(min) from the time of bank activation. tRCD is the internal timing parameter of SDRAM, therefore it is dependent on operating clock frequency. The minimum number of clock cycles required between bank activate and read or write command should be calculated by dividing tRCD(min) with cycle time of the clock and then rounding of the result to the next higher integer. The SDRAM has four internal banks in the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the activation of four banks simultaneously. Also the noise generated during sensing of each bank of SDRAM is high requiring some time for power supplies to recover before another bank can be sensed reliably. tRRD(min) specifies the minimum time required between activating different bank. The number of clock cycles required between different bank activation must be calculated similar to tRCD specification. The minimum time required for the bank to be active to initiate sensing and restoring the complete row of dynamic cells is determined by tRAS(min). Every SDRAM bank activate command must satisfy tRAS(min) specification before a precharge command to that active bank can be asserted. The maximum time any bank can be in the active state is determined by tRAS (max) and tRAS(max) can be calculated similar to tRCD specification. Burst Read The burst read command is used to access burst of data on consecutive clock cycles from an active row in an active bank The burst read command is issued by asserting low on /CS and /RAS with /WE being high on the positive edge of the clock. The bank must be active for at least tRCD(min) before the burst read command is issued. The first output appears in CAS latency number of clock cycles after the issue of burst read command. The burst length, burst sequence and latency from the burst read command is determined by the mode register which is already programmed. The burst read can be initiated on any column address of the active row. The address wraps around if the initial address does not start from a boundary such that number of outputs from each I/O are equal to the burst length programmed in the mode register. The output goes into high-impedance at the end of burst, unless a new burst read was initiated to keep the data output gapless. The burst read can be terminated by issuing another burst read or burst write in the same bank or the other active bank or a precharge command to the same bank. The burst stop command is valid at every page burst length. 9 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks Burst Write The burst write command is similar to burst read command and is used to write data into the SDRAM on consecutive clock cycles in adjacent addresses depending on burst length and burst sequence. By asserting low on /CS , /CAS and /WE with valid column address, a write burst is initiated. The data inputs are provided for the initial address in the same clock cycle as the burst write command. The input buffer is deselected at the end of the burst length, even though the internal writing can be completed yet. The writing can be complete by issuing a burst read and DQM for blocking data inputs or burst write in the same or another active bank. The burst stop command is valid at every burst length. The write burst can also be terminated by using DQM for blocking data and precharge the bank tRDL after the last data input to be written into the active row. See DQM OPERATION also. DQM Operation The DQM is used mask input and output operations. It works similar to /OE during operation and inhibits writing during write operation. The read latency is two cycles from DQM and zero cycle for write, which means DQM masking occurs two cycles later in read cycle and occurs in the same cycle during write cycle. DQM operation is synchronous with the clock. The DQM signal is important during burst interrupts of write with read or precharge in the SDRAM. Due to asynchronous nature of the internal write, the DQM operation is critical to avoid unwanted or incomplete writes when the complete burst write is required. Please refer to DQM timing diagram also. Precharge The precharge is performed on an active bank by asserting low on clock cycles required between bank activate and clock cycles required between bank activate and /CS , /RAS , /WE and A10/AP with valid A13~A12 of the bank to be procharged. The precharge command can be asserted anytime after tRAS(min) is satisfy from the bank active command in the desired bank. tRP is defined as the minimum number of clock cycles required to complete row precharge is calculated by dividing tRP with clock cycle time and rounding up to the next higher integer. Care should be taken to make sure that burst write is completed or DQM is used to inhibit writing before precharge command is asserted. The maximum time any bank can be active is specified by tRAS(max). Therefore, each bank has to be precharge with tRAS(max) from the bank activate command. At the end of precharge, the bank enters the idle state and is ready to be activated again. Entry to power-down, Auto refresh, Self refresh and Mode register set etc. is possible only when all banks are in idle state. Auto Precharge The precharge operation can also be performed by using auto precharge. The SDRAM internally generates the timing to satisfy tRAS(min) and "tRP" for the programmed burst length and CAS latency. The auto precharge command is issued at the same time as burst write by asserting high on A10/AP, the bank is precharge command is asserted. Once auto precharge command is given, no new commands are possible to that particular bank until the bank achieves idle state. 10 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks Four Banks Precharge Four banks can be precharged at the same time by using Precharge all command. Asserting low on /CS , /RAS , and /WE with high on A10/AP after all banks have satisfied tRAS(min) requirement, performs precharge on all banks. At the end of tRP after performing precharge all, all banks are in idle state. Auto Refresh The storage cells of SDRAM need to be refreshed every 64ms to maintain data. An auto refresh cycle accomplishes refresh of a single row of storage cells. The internal counter increments automatically on every auto refresh cycle to refresh all the rows. An auto refresh command is issued by asserting low on /CS , /RAS and /CAS with high on CKE and /WE . The auto refresh command can only be asserted with all banks being in idle state and the device is not in power down mode (CKE is high in the previous cycle). The time required to complete the auto refresh operation is specified by tRFC(min). The minimum number of clock cycles required can be calculated by driving tRFC with clock cycle time and them rounding up to the next higher integer. The auto refresh command must be followed by NOP's until the auto refresh operation is completed. The auto refresh is the preferred refresh mode when the SDRAM is being used for normal data transactions. The auto refresh cycle can be performed once in 15.6us. Self Refresh The self refresh is another refresh mode available in the SDRAM. The self refresh is the preferred refresh mode for data retention and low power operation of SDRAM. In self refresh mode, the SDRAM disables the internal clock and all the input buffers except CKE. The refresh addressing and timing is internally generated to reduce power consumption. The self refresh mode is entered from all banks idle state by asserting low on /CS , /RAS , /CAS and CKE with high on /WE . Once the self refresh mode is entered, only CKE state being low matters, all the other inputs including clock are ignored to remain in the refresh. The self refresh is exited by restarting the external clock and then asserting high on CKE. This must be followed by NOP's for a minimum time of tRFC before the SDRAM reaches idle state to begin normal operation. It is recommended to use burst 4096 auto refresh cycles immediately before and after self refresh. 11 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks COMMANDS Mode register set command ( /CS , /RAS , /CAS , /WE = Low) The CS56A12863 has a mode register that defines how the device operates. In this command, A0 through A13 are the data input pins. After power on, the mode register set command must be executed to initialize the device. The mode register can be set only when all banks are in idle state. During 2CLK following this command, the CS56A12863 cannot accept any other commands. Activate command ( /CS , /RAS = Low, /CAS , /WE = High) The CS56A12863 has four banks, each with 4,096 rows. This command activates the bank selected by A12 and A13 (BS) and a row address selected by A0 through A11. This command corresponds to a conventional DRAM's /RAS falling. Precharge command ( /CS , /RAS , /WE = Low, /CAS = High ) This command begins precharge operation of the bank selected by A12 and A13 (BS). When A10 is High, all banks are precharged, regardless of A12 and A13. When A10 is Low, only the bank selected by A12 and A13 is precharged. After this command, the CS56A12863 can't accept the activate command to the precharging bank during tRP (precharge to activate command period). This command corresponds to a conventional DRAM's /RAS rising. 12 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks Write command ( /CS , /CAS , /WE = Low, /RAS = High) If the mode register is in the burst write mode, this command sets the burst start address given by the column address to begin the burst write operation. The first write data in burst can be input with this command with subsequent data on following clocks. Read command ( /CS , /CAS = Low, /RAS , /WE = High) Read data is available after /CAS latency requirements have been met. This command sets the burst start address given by the column address. CBR (auto) refresh command ( /CS , /RAS , /CAS = Low, /WE , CKE = High) This command is a request to begin the CBR refresh operation. The refresh address is generated internally. Before executing CBR refresh, all banks must be precharged. After this cycle, all banks will be in the idle (precharged) state and ready for a row activate command. During tRC period (from refresh command to refresh or activate command), the CS56A12863 can not accept any other command. 13 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks Self refresh entry command ( /CS , /RAS , /CAS , CKE = Low , /WE = High) After the command execution, self refresh operation continues while CKE remains low. When CKE goes to high, the CS56A12863 exits the self refresh mode. During self refresh mode, refresh interval and refresh operation are performed internally, so there is no need for external control. Before executing self refresh, all banks must be precharged. Burst stop command ( /CS , /WE = Low, /RAS , /CAS = High) This command terminates the current burst operation. Burst stop is valid at every burst length. No operation ( /CS = Low , /RAS , /CAS , /WE = High) This command is not a execution command. No operations begin or terminate by this command. Note: 1. All input expect CKE & DQM can be don't care when /CS is high at the CLK high going edge. 2. Bank active @ read/write are controlled by A13~A12. A13 A12 Active & Read/Write 0 0 Bank A 0 1 Bank B 1 0 Bank C 1 1 Bank D 14 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks 3. Enable and disable auto precharge function are controlled by A10/AP in read/write command A10/AP 0 1 A12 A13 Operating 0 0 Disable auto precharge, leave A bank active at end of burst. 0 1 Disable auto precharge, leave B bank active at end of burst. 1 0 Disable auto precharge, leave C bank active at end of burst. 1 1 0 0 Enable auto precharge , precharge bank A at end of burst. 0 1 Enable auto precharge , precharge bank B at end of burst. 1 0 Enable auto precharge , precharge bank C at end of burst. 1 1 Enable auto precharge , precharge bank D at end of burst. Disable auto precharge, leave D bank active at end of burst. 4. A10/AP and A13~A12 control bank precharge when precharge is asserted. A10/AP A12 A13 Precharge 0 0 0 Bank A 0 0 1 Bank B 0 1 0 Bank C 0 1 1 Bank D 1 X X All Banks 15 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks STATE DIAGRAM (Simplified for Single BANK Operation State Diagram) 16 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks BASIC FEATURE AND FUNCTION DESCRIPTIONS 1. CLOCK Suspend 2. DQM Operation 17 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks Note: 1. CKE to CLK disable/enable = 1CLK. 2. DQM masks data out Hi-Z after 2CLKs which should masked by CKE "L". 3. DQM masks both data-in and data-out. 3. CAS Interrupt (I) Note: 1. By "interrupt" is meant to stop burst read/write by external before the end of burst. By " /CAS interrupt ", to stop burst read/write by /CAS access ; read and write. 2. tCCD : /CAS to /CAS delay. (=1CLK) 3. tCDL : Last data in to new column address delay. (=1CLK) 18 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks 4. /CAS Interrupt (II) : Read Interrupted by Write & DQM Note: To prevent bus contention, there should be at least one gap between data in and data out. 5. Write Interrupted by Precharge & DQM Note: 1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out. 2. To inhibit invalid write, DQM should be issued. 3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only another bank precharge of four banks operation. 19 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks 6. Precharge 7. Auto Precharge Note: 1. tRDL : Last data in to row precharge delay. 2. Number of valid output data after row precharge : 1,2 for CAS Latency = 2,3 respectively. 3. The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of other activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal. 20 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks 8. Burst Stop & Interrupted by Precharge 9. MRS Note: 1. tBDL : 1 CLK ; Last data in to burst stop delay. Read or write burst stop command is valid at every burst length. 2. Number of valid output data after burst stop : 1,2 for CAS latency = 2,3 respectiviely. 3. Write burst is terminated. tBDL determinates the last data write. 4. DQM asserted to prevent corruption of locations D2 and D3. 5. Precharge can be issued here or earlier (satisfying tRAS min delay) with DQM. 6. PRE : All banks precharge, if necessary. MRS can be issued only at all banks precharge state. 21 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks 10. Clock Suspend Exit & Power Down Exit 11. Auto Refresh & Self Refresh Note: 1. Active power down : one or more banks active state. 2. Precharge power down : all banks precharge state. 3. The auto refresh is the same as CBR refresh of conventional DRAM. No precharge commands are required after auto refresh command. During tRFC from auto refresh command, any other command can not be accepted. 4. Before executing auto/self refresh command, all banks must be idle state. 5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry. 6. During self refresh entry, refresh interval and refresh operation are performed internally. After self refresh entry, self refresh mode is kept while CKE is low. During self refresh entry, all inputs expect CKE will be 22 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks don't cared, and outputs will be in Hi-Z state. For the time interval of tRFC from self refresh exit command, any other command can not be accepted. Before/After self refresh mode, burst auto refresh (4096 cycles) is recommended. 12. About Burst Type Control Sequential Counting Basic Mode Interleave Counting Random Mode Random Column Access tCCD = 1 CLK At MRS A3 = "0". See the BURST SEQUENCE TABLE. (BL = 4,8) BL = 1, 2, 4, 8 and full page. At MRS A3 = "1". See the BURST SEQUENCE TABLE. (BL = 4,8) BL = 4, 8 At BL =1, 2 interleave Counting = Sequential Counting Every cycle Read/Write Command with random column address can realize Random Column Access. That is similar to Extended Data Out (EDO) Operation of conventional DRAM. 13. About Burst Length Control 1 2 Basic Mode At MRS A210 = "000" At auto precharge . tRAS should not be violated. At MRS A210 = "001" At auto precharge . tRAS should not be violated. 4 At MRS A210 = "010" 8 At MRS A210 = "011" Full Page At MRS A210 = "111" At the end of the burst length , burst is warp-around. At MRS A9 = "1" Special Mode BRSW Read burst = 1,2,4,8, full page write burst =1 At auto precharge of write, tRAS should not be violated. Random Mode Burst Stop tBDL = 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively. Using burst stop command, any burst length control is possible. Before the end of burst. Row precharge command of the same bank stops read /write burst with auto precharge. /RAS Interrupt tRDL = 1 with DQM , Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 (Interrupted by Precharge) respectively. Interrupt Mode During read/write burst with auto precharge, /RAS interrupt can not be issued. Before the end of burst, new read/write stops read/write burst and starts new /CAS Interrupt read/write burst. During read/write burst with auto precharge, /CAS interrupt can not be issued. 23 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks FUNCTION TURTH TABLE (TABLE 1) Current State IDLE /CS /RAS /CAS /WE BA ADDR ACTION H X X X X X NOP L H H H X X NOP L H H L X X ILLEGAL 2 L H L X BA CA, A10/AP ILLEGAL 2 L L H H BA RA L L H L BA A10/AP L L L H X X Row (&Bank) Active ; Latch RA NOP 4 Auto Refresh or Self Refresh 5 Mode Register Access 5 L L L L OP code OP code H X X X X X NOP L H H H X X NOP L H H L X X ILLEGAL Row L H L H BA CA, A10/AP Begin Read ; latch CA ; determine AP Active L H L L BA CA, A10/AP Begin Write ; latch CA ; determine AP L L H H BA RA ILLEGAL L L H L BA A10/AP Precharge Read Write Read with Auto Precharge Note L L L X X X ILLEGAL H X X X X X NOP (Continue Burst to EndRow Active) L H H H X X NOP (Continue Burst to EndRow Active) L H H L X X Term burstRow active L H L H BA CA, A10/AP Term burst, New Read, Determine AP L H L L BA CA, A10/AP Term burst, New Write, Determine AP L L H H BA RA L L H L BA A10/AP 2 2 3 ILLEGAL 2 Term burst, Precharge timing for Reads L L L X X X ILLEGAL H X X X X X NOP (Continue Burst to EndRow Active) L H H H X X NOP (Continue Burst to EndRow Active) L H H L X X Term burstRow active L H L H BA CA, A10/AP Term burst, New Read, Determine AP 3 L H L L BA CA, A10/AP Term burst, New Write, Determine AP 3 L L H H BA RA L L H L BA A10/AP ILLEGAL 2 Term burst, Precharge timing for Writes 3 L L L X X X ILLEGAL H X X X X X NOP (Continue Burst to EndRow Active) L H H H X X NOP (Continue Burst to EndRow Active) L H H L X X ILLEGAL L H L X BA L L H X BA RA,RA10 ILLEGAL L L L X X X ILLEGAL CA, A10/AP ILLEGAL 24 2 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks Current /CS /RAS /CAS /WE BA ADDR H X X X X X NOP (Continue Burst to EndRow Active) L H H H X X NOP (Continue Burst to EndRow Active) L H H L X X ILLEGAL L H L X BA L L H X BA RA,RA10 ILLEGAL L L L X X X ILLEGAL H X X X X X NOPIdle after tRP L H H H X X NOPIdle after tRP L H H L X X ILLEAGL 2 L H L X BA CA ILLEAGL 2 L L H H BA RA ILLEAGL 2 L L H L BA A10/AP NOPIdle after tRPL 4 L L L X X X ILLEAGL H X X X X X NOPRow Active after tRCD L H H H X X NOPRow Active after tRCD Row L H H L X X ILLEAGL 2 Activating L H L X BA CA ILLEAGL 2 L L H H BA RA ILLEAGL 2 L L H L BA A10/AP ILLEAGL 2 L L L X X X ILLEAGL H X X X X X NOPIdle after tRFC L H H X X X NOPIdle after tRFC L H L X X X ILLEGAL State Wriye with Auto Precharge Read with Auto Precharge Refreshing ACTION Note CA, A10/AP ILLEGAL L L H X X X ILLEGAL L L L X X X ILLEGAL H X X X X X NOPIdle after 2colcks Mode L H H H X X NOPIdle after 2colcks Register L H H L X X ILLEGAL Accessing L H L X X X ILLEGAL L L X X X X ILLEAGL 2 Abbreviations: RA = Row Address, BA = Bank Address, NOP = No Operation Command, CA = Column Address, AP = Auto Precharge Note: 1. All entries assume the CKE was active (High) during the precharge clock and the current clock cycle. 2. Illegal to bank in specified state ; Function may be legal in the bank indicated by BA, depending on the state of the bank. 3. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 4. NOP to bank precharge or in idle state. May precharge bank indicated by BA (and A10/AP). 5. Illegal if any bank is not idle. 25 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks FUNCTION TRUTH TABLE (TABLE2) Current CKE CKE State n-1 n H Self Refresh /CS /RAS /CAS /WE ADDR ACTION Note X X X X X X Invalid L H H X X X X Exit Self RefreshIdle after tRDC(ABI) 6 L H L H H H X Exit Self RefreshIdle after tRDC(ABI) 6 L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP(Maintain Self Refresh) H X X X X X X Invalid All L H H X X X X Exit Self RefreshABI 7 Banks L H L H H H X Exit Self RefreshABI 7 Precharge L H L H H L X ILLEGAL Power L H L H L X X ILLEGAL down L H L L X X X ILLEGAL L L X X X X X NOP(Maintain Low Power Mode) H H X X X X X Refer to Table 1 H L H X X X X Enter Power Down 8 H L L H H H X Enter Power Down 8 H L L H H L X ILLEGAL H L L H L X X ILLEGAL H L L L H H RA H L L L H H X NOP H L L L L L X Enter Self Refresh All Banks Idle Row(&Bank) Active 8 H L L L L L OP Mode L L X X X X X NOP Mode Register Access Any State H H X X X X X Refer to Operations in Table 1 other than H L X X X X X Begin Clock Suspend next cycle 9 Listed L H X X X X X Exit Clock Suspend next cycle 9 above L L X X X X X Maintain Clock Suspend Abbreviations: ABI = All Banks Idle, RA = Row Address Note: 6. CKE low to high transition is asynchronous. 7. CKE low to high transition is asynchronous if restart internal clock. A minimum setup time 1CLK + tSS must be satisfy before any command other than exit. 8. Power down and self refresh can be entered only from the all banks idle state. 9. Must be a legal command. 26 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks Single Bit Read-Write-Read Cycle(Same Page) @ CAS Latency = 3,Burst Length = 1 27 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL VALUE UNIT Voltage on any pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD supply relative to VSS VDD, VDDQ -1.0 ~ 4.6 V TSTG -55 ~ +150 Power dissipation PD 1 W Short circuit current IOS 50 mA Storage temperature Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITION Recommended operating condition s (Voltage referenced to VSS = 0V, TA = 0 to 70 C ) PARAMETER SYMBOL MIN TYP MAX UNIT VDD, VDDQ 3.0 3.3 3.6 V Input logic high voltage VIH 2.0 3.0 VDD+0.3 V 1 Input logic low voltage VIL -0.3 0 0.8 V 2 Output logic high voltage VOH 2.4 - - V IOH = -2mA Output logic low voltage VOL - - 0.4 V IOL = 2mA Input leakage current IIL -5 - 5 A 3 Output leakage current IOL -5 - 5 A 4 Supply voltage NOTE Note: 1. VIH(max) = 4.6V AC for pulse width 10ns acceptable. 2. VIL(min) = -1.5V AC for pulse width 10ns acceptable. 3. Any input 0V VIN VDD + 0.3V, all other pins are not under test = 0V. 4. Dout is disabled, 0V VOUT VDD. CAPACITANCE (VDD = 3.3V, TA = 25 C , f = 1MHZ) PARAMETER Input capacitance (A0 ~ A11, A13 ~ A12) Input capacitance (CLK, CKE, /CS , /RAS , /CAS , /WE &L(U)DQM) Data input/output capacitance (DQ0 ~ DQ15) SYMBOL MIN MAX UNIT CIN1 2.5 4 pF CIN2 2.5 4 pF COUT 2 6.5 pF 28 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks DC CHARACTERISTICS Recommended operating condition unless otherwise notedTA = 0 to 70 PARAMETER SYMBOL Operating Current ICC1 (One Bank Active) Precharge Standby Current in power-down mode Precharge Standby Active Current in power-down mode Active Current Standby in power-down non 160 140 2 ICC2PS CKE & CLK VIL(max), tcc = 2 2 45 45 ICC2N CKE VIH(min), /CS VIH(min), tCC = tck(min), Input signals are changed one time during 2tck CKE VIH(min), CLK VIL(max), tCC = input signals are stable UNIT NOTE mA 1,2 mA mA 25 25 ICC3P CKE VIL(max), tcc = tck(min) 6 6 ICC3PS CKE & CLK VIL(max), tCC = 6 6 55 55 mA CKE VIH(min), /CS VIH(min), tCC = tck(min), ICC3N Input signals are changed one time during 2tck ICC3NS Operating Current IOL = 0 mA 7.5 2 mode (One Bank Active) Burst Length = 1, tRC tRC(min), 6 CKE VIL(max), tcc = tck(min) ICC2NS Standby Latency ICC2P Current in non power - down mode Speed CAS TEST CONDITION mA CKE VIH(min), CLK VIL(max), tCC = input signals are stable 35 35 ICC4 IOL = 0 mA, Page Burst, 2 Banks active 210 180 mA Refresh Current ICC5 tRC tRC(min) 210 180 mA Self Refresh Current ICC6 CKE 0.2V 2 2 mA (Burst Mode) Note: 1,2 1. Measured with outputs open. 2. Input signals are changed one time during 2 CLKS. AC OPERATING TEST CONDITIONS (VDD = 3.3V 0.3V PARAMETER Input levels (VIH/VIL) Input timing measurement reference level Input rise and fall-time Output timing measurement reference level Output load condition TA = 0 to 70 C) VALUE UNIT 2.4/0.4 V 1.4 V tr/tf = 1/1 ns 1.4 V See Fig. 2 29 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks Asynchronous Characteristics (AC operating conditions unless otherwise noted) PARAMETER SPEED SYMBOL 6 7.5 UNIT NOTE Row active to row active delay tRRD(min) 12 14 ns 1 /RAS to /CAS delay tRCD(min) 18 20 ns 1 Row precharge time tRP(min) 18 20 ns 1 Row active time tRAS(min) 40 42 ns 1 100 tRAS(max) Row cycle time us @ Operating tRC(min) 58 63 ns 1 @ Auto refresh tRFC(min) 60 70 ns 1,5 ea 4 Number of valid Ouput data CAS latency=3 2 CAS latency=2 1 Col. Address to col. delay tCCD(min) 1 tCK 3 Last data in to col. address delay tCDL(min) 1 tCK 2 Last data in to row percharge tRDL(min) 2 tCK 2 Last data in to burst stop tBDL(min) 1 tCK 2 Refresh period(4096 rows) tBEF(max) 64 ms 6 Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. A new command may be given tRFC after self refresh exit. 6. A maximum of eight consecutive AUTO REFRESH commands (with tRFC(min)) can be posted to any given SDRAM, and the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8x15.6 s.) 30 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks Synchronous Characteristics (AC operating condition unless otherwise noted) PARAMATER CLK cycle time CAS latency = 3 CAS latency = 2 CLK to valid CAS latency = 3 output delay CAS latency = 2 Output data CAS latency = 3 hold time CAS latency = 2 SYMBOL tCC tSAC tOH 6 MIN 6 10 7.5 MAX MIN 1000 7.5 10 MAX 1000 - 5.4 - 5.4 - 6 - 6 2.5 - 2.5 - 2.5 - 2.5 - UNIT NOTE ns 1 ns 1, 2 ns 2 CLK high pulse width tCH 2.5 - 2.5 - ns 3 CLK low pulse width tCL 2.5 - 2.5 - ns 3 Input setup time tSS 1.5 - 1.5 - ns 3 Input hold time tSH 1 - 1 - ns 3 CLK to output in Low-Z tSLZ 1 - 1 - ns 2 - 5.4 - 5.4 - 6 - 6 CLK to output CAS latency = 3 in Hi-Z CAS latency = 2 tSHZ ns Note: 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns. (tr/2 - 0.5) ns should be considered. 3. Assumed input rise and fall time (tr & tf) =1ns. If tr & tf is longer than 1ns. transient time compensation should be considered. i.e., [(tr + tf)/2 - 1] ns should be added to the parameter. 31 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks Power Up Sequence 32 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks Read & Write Cycle at Same Bank @ Burst Length = 4 Note: 1. Minimum row cycle times is required to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row precharge. Last valid output will be Hi-Z (tSHZ) after the clock. 3. Output will be Hi-Z after the end of burst. (1,2,4,8 & Full page bit burst) 33 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks Page Read & Write Cycle at Same Bank @ Burst Length = 4 Note: 1. To Write data before burst read ends. DQM should be asserted three cycle prior to write command to avoid bus contention. 2. Row precharge will interrupt writing. Last data input , tRDL before row precharge , will be written. 3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 34 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks Page Read Cycle at Different Bank @ Burst Length = 4 Note: 1. /CS can be don't cared when /RAS , /CAS and /WE are high at the clock high going edge. 2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same. 35 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks Page Write Cycle at Different Bank @ Burst Length = 4 Note: 1. To interrupt burst write by Row precharge , DQM should be asserted to mask invalid input data. 2. To interrupt burst write by Row precharge , both the write and the precharge banks must be the same. 36 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks Read & Write Cycle at Different Bank @ Burst Length = 4 Note: 1. tCDL should be met to complete write. 37 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks Read & Write cycle with Auto Precharge @ Burst Length = 4 38 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks Clock Suspension & DQM Operation Cycle @ CAS Letency = 2 , Burst Length = 4 Note: 1. DQM is needed to prevent bus contention 39 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks Read interrupted by Precharge Command & Read Burst Stop Cycle @ Burst Length = Full page Note: 1. About the valid DQs after burst stop, it is same as the case of /RAS interrupt. Both cases are illustrated above timing diagram. See the label 1,2 on them. But at burst write, Burst stop and /RAS interrupt should be compared carefully. Refer the timing diagram of "Full page write burst stop cycles". 2. Burst stop is valid at every burst length. 40 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks Write interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length = Full page Note: 1. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of tRDL. DQM at write interrupted by precharge command is needed to prevent invalid write. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 2. Burst stop is valid at every burst length. 41 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks Active/Precharge Power Down Mode @ CAS Latency = 2, Burst Length = 4 Note: 1. Both banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at least 1CLK + tSS prior to Row active command. 3. Can not violate minimum refresh specification. 42 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks Self Refresh Entry & Exit Cycle Note: TO ENTER SELF REFRESH MODE 1. /CS , /RAS & /CAS with CKE should be low at the same clock cycle. 2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE. 3. The device remains in self refresh mode as long as CKE stays "Low". cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh. TO EXIT SELF REFRESH MODE 1. System clock restart and be stable before returning CKE high. 2. /CS starts from high. 3. Minimum tRFC is required after CKE going high to complete self refresh exit. 4. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh. 43 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks Mode Register Set Cycle Auto Refresh Cycle All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle. Note: MODE REGISTER SET CYCLE 1. /CS , /RAS , /CAS , & /WE activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new /RAS activation. 3. Please refer to Mode Register Set table. 44 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks ORDER INFORMATION Note: Package material code "R" meets ROHS 45 Rev. 1.1 Chiplus reserves the right to change product or specification without notice.