Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
1 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
Revision History
Rev. No. History Issue Date Remark
1.0 Initial issue Apr. 07, 2005
1.1 Revised DC/AC characteristics Nov. 22, 2006
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
2 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
DESCRIPTION
The CS56A12863 is 134,217,728 bits synchronous high data rate Dynamic RAM organized as
2,097,152x16x4 (word x bit x bank). Synchronous design allows precise cycle controls with the use of system
clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst
length and programmable device to be useful for a variety of high bandwidth, high performance memory system
applications.
FEATURES
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency (2 & 3 )
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system clock
Burst Read single write operation
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
Product Family
Part No. Operating Temp ( oC) Vcc. Range (V) Speed (ns) Package Type
0~70oC
CS56A12863
-40~85oC
3.0~3.6 6 / 7.5 Dice
54 TSOP 2
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
3 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
PIN ASSIGNMENT - 54L TSOP 2- 400mil
FUNCTIONAL BLOCK DIAGRAM
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
4 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
PIN FUNCTION DESCRIPTION
PIN NAME INPUT FUNCTION
CLK System Clock Active on the positive going edge to sample all inputs
/CS Chip Select Disables or enables device operation by masking or enabling all inputs
except CLK , CKE and L(U)DQM
CKE Clock Enable
Masks system clock to freeze operation from the next clock cycle. CKE
should be enabled at least one cycle prior new command. Disable input
buffers for power down in standby.
A0 ~ A11 Address Row / column address are multiplexed on the same pins.
Row address : RA0~RA11, column address : CA0~CA8
A12, A13 Bank Select Address Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
/RAS Row Address Strobe Latches row addresses on the positive going edge of the CLK with /RAS
low. (Enables row access & precharge.)
/CAS Column Address Strobe Latches column address on the positive going edge of the CLK with /CAS
low. (Enables column access.)
/WE Write Enable Enables write operation and row precharge.
Latches data in starting from /CAS , /WE active.
L (U) DQM Data Input / Output Mask Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
DQ0 ~ DQ15 Data Input / Output Data inputs / outputs are multiplexed on the same pins.
VDD / VSS Power Supply / Ground Power and ground for the input buffers and the core logic.
VDDQ / VSSQ Data Output Power / Ground Isolated power supply and ground for the output buffers to provide improved
noise immunity.
NC No Connection This pin is recommended to be left No Connection on the device.
SIMPLIFIED TRUTH TABLE
COMMAND
CKE
n-1
CKE
n
/CS /RAS /CAS /WE DQM
A13
A12
A10
/AP
A11
A9~A0
Note
Register Mode Register set H X L L L L X OP CODE 1,2
Auto Refresh H 3
Entry
H
L
L L L H X X
3
L H H H X 3
Refresh Self
Refresh Exit L H
H X X X X
X
3
Bank Active & Row Addr. H X L L H H X V Row Address
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
5 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
COMMAND
CKE
n-1
CKE
n
/CS /RAS /CAS /WE DQM
A13
A12
A10
/AP
A11
A9~A0
Note
Auto Precharge
Disable
L 4 Read &
Column
Address
Auto Precharge
Enable
H X L H L H X V
H
Column
Address
(A0~A8) 4,5
Auto Precharge
Disable
L 4 Write &
Column
Address
Auto Precharge
Enable
H X L H L L X V
H
Column
Address
(A0~A8) 4,5
Burst Stop H X L H H L X X 6
Bank Selection V L
Precharge
All Banks
H X L L H L X
X H
X
H X X X
Entry H L
L V V V
X
Clock Suspend or
Active Power Down
Exit L H X X X X X
X
H X X X
Entry H L
L H H H
X
H X X X
Precharge Power
Down Mode
Exit L H
L V V V
X
X
DQM H X V X 7
H X X X
No Operating Command (NOP) H X
L H H H
X X
(V = Valid , X = Don’t Care. H = Logic High , L = Logic Low )
Note:
1. OP Code : Operating Code A0~A11 & A13~A12 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of
MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row
precharge of command is meant by “Auto”. Auto/self refresh can be issued only at all banks idle state.
4. A13~A12 : Bank select addresses.
If A13 and A12 are “Low” at read ,write , row active and precharge ,bank A is selected.
If A13 is “Low” and A12 is “High” at read ,write , row active and precharge ,bank B is selected.
If A13 is “High” and A12 is “Low” at read ,write , row active and precharge ,bank C is selected.
If A13 and A12 are “High” at read ,write , row active and precharge ,bank D is selected
If A10/AP is “High” at row precharge , A13 and A12 is ignored and all banks are selected.
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
6 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
5. During burst read or write with auto precharge. new read/write command can not be issued. Another bank
read/write command can be issued after the end of burst. New row active of the associated bank can be
issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)
MODE REGISTER TABLE TO PROGRAM MODES
Register Programmed with MRS
Address A13~A12 A11~A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Function RFU RFU W.B.L. Test Mode CAS Latency Burst Type Burst Length
Test Mode CAS Latency Burst Type Burst Length
A8 A7 Type A6 A5 A4 Latency A3 Type A2 A1 A0 BT=0 BT=1
0 0 Mode Register Set 0 0 0 Reserved 0 Sequential 0 0 0 1 1
0 1 Reserved 0 0 1 Reserved 1 Interleave 0 0 1 2 2
1 0 Reserved 0 1 0 2 0 1 0 4 4
1 1 Reserved 0 1 1 3 0 1 1 8 8
1 0 0 Reserved 1 0 0 Reserved Reserved
1 0 1 Reserved 1 0 1 Reserved Reserved
1 1 0 Reserved 1 1 0 Reserved Reserved
1 1 1 Reserved 1 1 1 Full Page Reserved
Full Page Length: 512 (for 8M ×16 device).
POWER UP SEQUENCE
1. Apply power and start clock, Attempt to maintain CKE = ”H”, DQM = ”H” and the other pin are NOP condition
at the inputs.
2. Maintain stable power , stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 is regardless of the order.
The device is now ready for normal operation.
Note: 1. RFU (Reserved for future use) should stay “0” during MRS cycle.
2. If A9 is high during MRS cycle, “ Burst Read single write” function will be enabled.
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
7 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
BURST SEQUENCE (BURST LENGTH = 4)
Initial Address
A1 A0
Sequential Interleave
0 0 0 1 2 3 0 1 2 3
0 1 1 2 3 0 1 0 3 2
1 0 2 3 0 1 2 3 0 1
1 1 3 0 1 2 3 2 1 0
BURST SEQUENCE (BURST LENGTH = 8)
Initial Address
A2 A1 A0
Sequential Interleave
0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6
0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5
0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4
1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3
1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2
1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1
1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0
DEVICE OPERATION
Clock (CLK)
The clock input is used as the reference for all SDRAM operations. All operations are synchronized to the
positive going edge of the clock. The clock transitions must be monotonic between VIL and VIH. During operation
with CKE high all inputs are assumed to be in valid state (low or high) for the duration of setup and hold time
around positive edge of the clock for proper functionality and ICC specifications.
Clock Enable (CKE)
The clock enable (CKE) gates the clock onto SDRAM. If CKE goes low synchronously with clock (set-up and
hold time same as other inputs), the internal clock suspended from the next clock cycle and the state of output
and burst address is frozen as long as the CKE remains low. All other inputs are ignored from the next clock cycle
after CKE goes low. When all banks are in the idle state and CKE goes low synchronously with clock, the SDRAM
enters the power down mode from the next clock cycle. The SDRAM remains in the power down mode ignoring
the other inputs as long as CKE remains low. The power down exit is synchronous as the internal clock is
suspended. When CKE goes high at least “1CLK + tSS” before the high going edge of the clock, then the SDRAM
becomes active from the same clock edge accepting all the input commands.
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
8 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
Bank Addresses (A13~A12)
This SDRAM is organized as four independent banks of 2,097,152 words x 16 bits memory arrays. The
A13~A12 inputs are latched at the time of assertion of /RAS and /CAS to select the bank to be used for the
operation. The banks addressed A13~A12 are latched at bank active, read, write, mode register set and
precharge operations.
Address Inputs (A0~A11)
The 21 address bits are required to decode the 2,097,152 word locations are multiplexed into 12 address
input pins (A0~A11). The 12 row addresses are latched along with /RAS and A13~A12 during bank active
command. The 9 bit column addresses are latched along with /CAS , /WE and A13~A12 during read or with
command.
NOP and Device Deslect
When /RAS , /CAS and /WE are high , The SDRAM performs no operation (NOP). NOP does not initiate any
new operation, but is needed to complete operations which require more than single clock cycle like bank activate,
burst read, auto refresh, etc. The device deselect is also a NOP and is entered by asserting /CS high. /CS high
disables the command decoder so that /RAS , /CAS , /WE and all the address inputs are ignored.
Power-up
1. Apply power and start clock, Attempt to maintain CKE = “H”, DQM = “H” and the other pins are NOP condition
at the inputs.
2. Maintain stable power, stable clock and NOP input condition for minimum of 200us.
3. Issue precharge commands for both banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 is regardless of the order. The device is now ready for normal operation.
Mode Register Set (MRS)
The mode register stores the data for controlling the various operating modes of SDRAM. It programs the
CAS latency, burst type, burst length, test mode and various vendor specific options to make SDRAM useful for
variety of different applications. The default value of the mode register is not defined, therefore the mode register
must be written after power up to operate the SDRAM. The mode register is written by asserting low on /CS ,
/RAS , /CAS and /WE (The SDRAM should be in active mode with CKE already high prior to writing the mode
register). The state of address pins A0~A11 and A13~A12 in the same cycle as /CS , /RAS , /CAS and /WE going
low is the data written in the mode register. Two clock cycles is required to complete the write in the mode register.
The mode register contents can be changed using the same command and clock cycle requirements during
operation as long as all banks are in the idle state. The mode register is divided into various fields into depending
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
9 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
on functionality. The burst length field uses A0~A2, burst type uses A3, CAS latency (read latency from column
address) use A4~A6, vendor specific options or test mode use A7~A8, A10/AP~A11 and A13~A12. The write
burst length is programmed using A9. A7~A8, A10/AP~A11 and A13~A12 must be set to low for normal SDRAM
operation. Refer to the table for specific codes for various burst length, burst type and CAS latencies.
Bank Activate
The bank activate command is used to select a random row in an idle bank. By asserting low on /RAS and
/CS with desired row and bank address, a row access is initiated. The read or write operation can occur after a
time delay of tRCD(min) from the time of bank activation. tRCD is the internal timing parameter of SDRAM, therefore it
is dependent on operating clock frequency. The minimum number of clock cycles required between bank activate
and read or write command should be calculated by dividing tRCD(min) with cycle time of the clock and then rounding
of the result to the next higher integer. The SDRAM has four internal banks in the same chip and shares part of
the internal circuitry to reduce chip area, therefore it restricts the activation of four banks simultaneously. Also the
noise generated during sensing of each bank of SDRAM is high requiring some time for power supplies to recover
before another bank can be sensed reliably. tRRD(min) specifies the minimum time required between activating
different bank. The number of clock cycles required between different bank activation must be calculated similar
to tRCD specification. The minimum time required for the bank to be active to initiate sensing and restoring the
complete row of dynamic cells is determined by tRAS(min). Every SDRAM bank activate command must satisfy
tRAS(min) specification before a precharge command to that active bank can be asserted. The maximum time any
bank can be in the active state is determined by tRAS (max) and tRAS(max) can be calculated similar to tRCD
specification.
Burst Read
The burst read command is used to access burst of data on consecutive clock cycles from an active row in an
active bank The burst read command is issued by asserting low on /CS and /RAS with /WE being high on the
positive edge of the clock. The bank must be active for at least tRCD(min) before the burst read command is issued.
The first output appears in CAS latency number of clock cycles after the issue of burst read command. The burst
length, burst sequence and latency from the burst read command is determined by the mode register which is
already programmed. The burst read can be initiated on any column address of the active row. The address
wraps around if the initial address does not start from a boundary such that number of outputs from each I/O are
equal to the burst length programmed in the mode register. The output goes into high-impedance at the end of
burst, unless a new burst read was initiated to keep the data output gapless. The burst read can be terminated by
issuing another burst read or burst write in the same bank or the other active bank or a precharge command to the
same bank. The burst stop command is valid at every page burst length.
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
10 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
Burst Write
The burst write command is similar to burst read command and is used to write data into the SDRAM on
consecutive clock cycles in adjacent addresses depending on burst length and burst sequence. By asserting low
on /CS , /CAS and /WE with valid column address, a write burst is initiated. The data inputs are provided for the
initial address in the same clock cycle as the burst write command. The input buffer is deselected at the end of the
burst length, even though the internal writing can be completed yet. The writing can be complete by issuing a
burst read and DQM for blocking data inputs or burst write in the same or another active bank. The burst stop
command is valid at every burst length. The write burst can also be terminated by using DQM for blocking data
and precharge the bank tRDL after the last data input to be written into the active row. See DQM OPERATION also.
DQM Operation
The DQM is used mask input and output operations. It works similar to /OE during operation and inhibits
writing during write operation. The read latency is two cycles from DQM and zero cycle for write, which means
DQM masking occurs two cycles later in read cycle and occurs in the same cycle during write cycle. DQM
operation is synchronous with the clock. The DQM signal is important during burst interrupts of write with read or
precharge in the SDRAM. Due to asynchronous nature of the internal write, the DQM operation is critical to avoid
unwanted or incomplete writes when the complete burst write is required. Please refer to DQM timing diagram
also.
Precharge
The precharge is performed on an active bank by asserting low on clock cycles required between bank
activate and clock cycles required between bank activate and /CS , /RAS , /WE and A10/AP with valid A13~A12 of
the bank to be procharged. The precharge command can be asserted anytime after tRAS(min) is satisfy from the
bank active command in the desired bank. tRP is defined as the minimum number of clock cycles required to
complete row precharge is calculated by dividing tRP with clock cycle time and rounding up to the next higher
integer. Care should be taken to make sure that burst write is completed or DQM is used to inhibit writing before
precharge command is asserted. The maximum time any bank can be active is specified by tRAS(max). Therefore,
each bank has to be precharge with tRAS(max) from the bank activate command. At the end of precharge, the bank
enters the idle state and is ready to be activated again. Entry to power-down, Auto refresh, Self refresh and Mode
register set etc. is possible only when all banks are in idle state.
Auto Precharge
The precharge operation can also be performed by using auto precharge. The SDRAM internally generates
the timing to satisfy tRAS(min) and “tRP” for the programmed burst length and CAS latency. The auto precharge
command is issued at the same time as burst write by asserting high on A10/AP, the bank is precharge command
is asserted. Once auto precharge command is given, no new commands are possible to that particular bank until
the bank achieves idle state.
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
11 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
Four Banks Precharge
Four banks can be precharged at the same time by using Precharge all command. Asserting low on /CS ,
/RAS , and /WE with high on A10/AP after all banks have satisfied tRAS(min) requirement, performs precharge on all
banks. At the end of tRP after performing precharge all, all banks are in idle state.
Auto Refresh
The storage cells of SDRAM need to be refreshed every 64ms to maintain data. An auto refresh cycle
accomplishes refresh of a single row of storage cells. The internal counter increments automatically on every auto
refresh cycle to refresh all the rows. An auto refresh command is issued by asserting low on /CS , /RAS and /CAS
with high on CKE and /WE . The auto refresh command can only be asserted with all banks being in idle state and
the device is not in power down mode (CKE is high in the previous cycle). The time required to complete the auto
refresh operation is specified by tRFC(min). The minimum number of clock cycles required can be calculated by
driving tRFC with clock cycle time and them rounding up to the next higher integer. The auto refresh command must
be followed by NOP’s until the auto refresh operation is completed. The auto refresh is the preferred refresh mode
when the SDRAM is being used for normal data transactions. The auto refresh cycle can be performed once in
15.6us.
Self Refresh
The self refresh is another refresh mode available in the SDRAM. The self refresh is the preferred refresh
mode for data retention and low power operation of SDRAM. In self refresh mode, the SDRAM disables the
internal clock and all the input buffers except CKE. The refresh addressing and timing is internally generated to
reduce power consumption. The self refresh mode is entered from all banks idle state by asserting low on /CS ,
/RAS , /CAS and CKE with high on /WE . Once the self refresh mode is entered, only CKE state being low matters,
all the other inputs including clock are ignored to remain in the refresh. The self refresh is exited by restarting the
external clock and then asserting high on CKE. This must be followed by NOP’s for a minimum time of tRFC before
the SDRAM reaches idle state to begin normal operation. It is recommended to use burst 4096 auto refresh cycles
immediately before and after self refresh.
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
12 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
COMMANDS
Mode register set command
( /CS , /RAS , /CAS , /WE = Low)
The CS56A12863 has a mode register that defines how the device operates. In this
command, A0 through A13 are the data input pins. After power on, the mode register
set command must be executed to initialize the device.
The mode register can be set only when all banks are in idle state.
During 2CLK following this command, the CS56A12863 cannot accept any other
commands.
Activate command
( /CS , /RAS = Low, /CAS , /WE = High)
The CS56A12863 has four banks, each with 4,096 rows.
This command activates the bank selected by A12 and A13 (BS) and a row address
selected by A0 through A11.
This command corresponds to a conventional DRAM’s /RAS falling.
Precharge command
( /CS , /RAS , /WE = Low, /CAS = High )
This command begins precharge operation of the bank selected by A12 and A13 (BS).
When A10 is High, all banks are precharged, regardless of A12 and A13. When A10 is
Low, only the bank selected by A12 and A13 is precharged.
After this command, the CS56A12863 can’t accept the activate command to the
precharging bank during tRP (precharge to activate command period).
This command corresponds to a conventional DRAM’s /RAS rising.
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
13 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
Write command
( /CS , /CAS , /WE = Low, /RAS = High)
If the mode register is in the burst write mode, this command sets the burst start
address given by the column address to begin the burst write operation. The first write
data in burst can be input with this command with subsequent data on following clocks.
Read command
( /CS , /CAS = Low, /RAS , /WE = High)
Read data is available after /CAS latency requirements have been met.
This command sets the burst start address given by the column address.
CBR (auto) refresh command
( /CS , /RAS , /CAS = Low, /WE , CKE = High)
This command is a request to begin the CBR refresh operation. The refresh address is
generated internally.
Before executing CBR refresh, all banks must be precharged.
After this cycle, all banks will be in the idle (precharged) state and ready for a row
activate command.
During tRC period (from refresh command to refresh or activate command), the
CS56A12863 can not accept any other command.
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
14 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
Self refresh entry command
( /CS , /RAS , /CAS , CKE = Low , /WE = High)
A
fter the command execution, self refresh operation continues while CKE remains low.
When CKE goes to high, the CS56A12863 exits the self refresh mode.
During self refresh mode, refresh interval and refresh operation are performed
internally, so there is no need for external control. Before executing self refresh, all
banks must be precharged.
Burst stop command
( /CS , /WE = Low, /RAS , /CAS = High)
This command terminates the current burst operation.
Burst stop is valid at every burst length.
No operation
( /CS = Low , /RAS , /CAS , /WE = High)
This command is not a execution command. No operations begin or terminate by this
command.
Note:
1. All input expect CKE & DQM can be don’t care when /CS is high at the CLK high going edge.
2. Bank active @ read/write are controlled by A13~A12.
A13 A12 Active & Read/Write
0 0 Bank A
0 1 Bank B
1 0 Bank C
1 1 Bank D
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
15 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
3. Enable and disable auto precharge function are controlled by A10/AP in read/write command
4. A10/AP and A13~A12 control bank precharge when precharge is asserted.
A10/AP A12 A13 Precharge
0 0 0 Bank A
0 0 1 Bank B
0 1 0 Bank C
0 1 1 Bank D
1 X X All Banks
A10/AP A12 A13 Operating
0 0 Disable auto precharge, leave A bank active at end of burst.
0 1 Disable auto precharge, leave B bank active at end of burst.
1 0 Disable auto precharge, leave C bank active at end of burst.
0
1 1 Disable auto precharge, leave D bank active at end of burst.
0 0 Enable auto precharge , precharge bank A at end of burst.
0 1 Enable auto precharge , precharge bank B at end of burst.
1 0 Enable auto precharge , precharge bank C at end of burst.
1
1 1 Enable auto precharge , precharge bank D at end of burst.
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
16 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
STATE DIAGRAM (Simplified for Single BANK Operation State Diagram)
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
17 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
BASIC FEATURE AND FUNCTION DESCRIPTIONS
1. CLOCK Suspend
2. DQM Operation
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
18 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
Note:
1. CKE to CLK disable/enable = 1CLK.
2. DQM masks data out Hi-Z after 2CLKs which should masked by CKE ”L”.
3. DQM masks both data-in and data-out.
3. CAS Interrupt (I)
Note:
1. By “interrupt” is meant to stop burst read/write by external before the end of burst. By ” /CAS interrupt ”, to
stop burst read/write by /CAS access ; read and write.
2. tCCD : /CAS to /CAS delay. (=1CLK)
3. tCDL : Last data in to new column address delay. (=1CLK)
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
19 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
4. /CAS Interrupt (II) : Read Interrupted by Write & DQM
Note: To prevent bus contention, there should be at least one gap between data in and data out.
5. Write Interrupted by Precharge & DQM
Note:
1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and
data out.
2. To inhibit invalid write, DQM should be issued.
3. This precharge command and burst write command should be of the same bank, otherwise it is not
precharge interrupt but only another bank precharge of four banks operation.
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
20 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
6. Precharge
7. Auto Precharge
Note:
1. tRDL : Last data in to row precharge delay.
2. Number of valid output data after row precharge : 1,2 for CAS Latency = 2,3 respectively.
3. The row active command of the precharge bank can be issued after tRP from this point. The new
read/write command of other activated bank can be issued from this point. At burst read/write with auto
precharge, CAS interrupt of the same/another bank is illegal.
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
21 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
8. Burst Stop & Interrupted by Precharge
9. MRS
Note:
1. tBDL : 1 CLK ; Last data in to burst stop delay. Read or write burst stop command is valid at every burst
length.
2. Number of valid output data after burst stop : 1,2 for CAS latency = 2,3 respectiviely.
3. Write burst is terminated. tBDL determinates the last data write.
4. DQM asserted to prevent corruption of locations D2 and D3.
5. Precharge can be issued here or earlier (satisfying tRAS min delay) with DQM.
6. PRE : All banks precharge, if necessary. MRS can be issued only at all banks precharge state.
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
22 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
10. Clock Suspend Exit & Power Down Exit
11. Auto Refresh & Self Refresh
Note:
1. Active power down : one or more banks active state.
2. Precharge power down : all banks precharge state.
3. The auto refresh is the same as CBR refresh of conventional DRAM. No precharge commands are
required after auto refresh command. During tRFC from auto refresh command, any other command can
not be accepted.
4. Before executing auto/self refresh command, all banks must be idle state.
5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.
6. During self refresh entry, refresh interval and refresh operation are performed internally. After self refresh
entry, self refresh mode is kept while CKE is low. During self refresh entry, all inputs expect CKE will be
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
23 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
don’t cared, and outputs will be in Hi-Z state. For the time interval of tRFC from self refresh exit command,
any other command can not be accepted. Before/After self refresh mode, burst auto refresh (4096 cycles)
is recommended.
12. About Burst Type Control
Sequential Counting
At MRS A3 = “0”. See the BURST SEQUENCE TABLE. (BL = 4,8) BL = 1, 2,
4, 8 and full page.
Basic Mode
Interleave Counting
At MRS A3 = “1”. See the BURST SEQUENCE TABLE. (BL = 4,8) BL = 4, 8
At BL =1, 2 interleave Counting = Sequential Counting
Random Mode
Random Column Access
tCCD = 1 CLK
Every cycle Read/Write Command with random column address can realize
Random Column Access. That is similar to Extended Data Out (EDO)
Operation of conventional DRAM.
13. About Burst Length Control
1
At MRS A210 = “000”
At auto precharge . tRAS should not be violated.
2
At MRS A210 = “001”
At auto precharge . tRAS should not be violated.
4 At MRS A210 = “010”
8 At MRS A210 = “011”
Basic Mode
Full Page
At MRS A210 = “111”
At the end of the burst length , burst is warp-around.
Special Mode BRSW
At MRS A9 = “1”
Read burst = 1,2,4,8, full page write burst =1
At auto precharge of write, tRAS should not be violated.
Random Mode Burst Stop
tBDL = 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
Using burst stop command, any burst length control is possible.
/RAS Interrupt
(Interrupted by Precharge)
Before the end of burst. Row precharge command of the same bank stops
read /write burst with auto precharge.
tRDL = 1 with DQM , Valid DQ after burst stop is 1, 2 for CAS latency 2, 3
respectively.
During read/write burst with auto precharge, /RAS interrupt can not be
issued.
Interrupt Mode
/CAS Interrupt
Before the end of burst, new read/write stops read/write burst and starts new
read/write burst. During read/write burst with auto precharge, /CAS interrupt
can not be issued.
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
24 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
FUNCTION TURTH TABLE (TABLE 1)
Current
State /CS /RAS /CAS /WE BA ADDR ACTION Note
H X X X X X NOP
L H H H X X NOP
L H H L X X ILLEGAL 2
L H L X BA CA, A10/AP ILLEGAL 2
L L H H BA RA Row (&Bank) Active ; Latch RA
L L H L BA A10/AP NOP 4
L L L H X X Auto Refresh or Self Refresh 5
IDLE
L L L L OP code OP code Mode Register Access 5
H X X X X X NOP
L H H H X X NOP
L H H L X X ILLEGAL 2
L H L H BA CA, A10/AP Begin Read ; latch CA ; determine AP
L H L L BA CA, A10/AP Begin Write ; latch CA ; determine AP
L L H H BA RA ILLEGAL 2
L L H L BA A10/AP Precharge
Row
Active
L L L X X X ILLEGAL
H X X X X X NOP (Continue Burst to End→Row Active)
L H H H X X NOP (Continue Burst to End→Row Active)
L H H L X X Term burst→Row active
L H L H BA CA, A10/AP Term burst, New Read, Determine AP
L H L L BA CA, A10/AP Term burst, New Write, Determine AP 3
L L H H BA RA ILLEGAL 2
L L H L BA A10/AP Term burst, Precharge timing for Reads
Read
L L L X X X ILLEGAL
H X X X X X NOP (Continue Burst to End→Row Active)
L H H H X X NOP (Continue Burst to End→Row Active)
L H H L X X Term burst→Row active
L H L H BA CA, A10/AP Term burst, New Read, Determine AP 3
L H L L BA CA, A10/AP Term burst, New Write, Determine AP 3
L L H H BA RA ILLEGAL 2
L L H L BA A10/AP Term burst, Precharge timing for Writes 3
Write
L L L X X X ILLEGAL
H X X X X X NOP (Continue Burst to End→Row Active)
L H H H X X NOP (Continue Burst to End→Row Active)
L H H L X X ILLEGAL
L H L X BA CA, A10/AP ILLEGAL
L L H X BA RA,RA10 ILLEGAL 2
Read with
Auto
Precharge
L L L X X X ILLEGAL
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
25 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
Current
State /CS /RAS /CAS /WE BA ADDR ACTION Note
H X X X X X NOP (Continue Burst to End→Row Active)
L H H H X X NOP (Continue Burst to End→Row Active)
L H H L X X ILLEGAL
L H L X BA CA, A10/AP ILLEGAL
L L H X BA RA,RA10 ILLEGAL 2
Wriye with
Auto
Precharge
L L L X X X ILLEGAL
H X X X X X NOP→Idle after tRP
L H H H X X NOP→Idle after tRP
L H H L X X ILLEAGL 2
L H L X BA CA ILLEAGL 2
L L H H BA RA ILLEAGL 2
Read with
Auto
Precharge
L L H L BA A10/AP NOP→Idle after tRPL 4
L L L X X X ILLEAGL
H X X X X X NOP→Row Active after tRCD
L H H H X X NOP→Row Active after tRCD
L H H L X X ILLEAGL 2
L H L X BA CA ILLEAGL 2
L L H H BA RA ILLEAGL 2
L L H L BA A10/AP ILLEAGL 2
Row
Activating
L L L X X X ILLEAGL
H X X X X X NOP→Idle after tRFC
L H H X X X NOP→Idle after tRFC
L H L X X X ILLEGAL
L L H X X X ILLEGAL
Refreshing
L L L X X X ILLEGAL
H X X X X X NOP→Idle after 2colcks
L H H H X X NOP→Idle after 2colcks
L H H L X X ILLEGAL
L H L X X X ILLEGAL
Mode
Register
Accessing
L L X X X X ILLEAGL
Abbreviations: RA = Row Address, BA = Bank Address, NOP = No Operation Command,
CA = Column Address, AP = Auto Precharge
Note:
1. All entries assume the CKE was active (High) during the precharge clock and the current clock cycle.
2. Illegal to bank in specified state ; Function may be legal in the bank indicated by BA, depending on the
state of the bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharge or in idle state. May precharge bank indicated by BA (and A10/AP).
5. Illegal if any bank is not idle.
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
26 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
FUNCTION TRUTH TABLE (TABLE2)
Current
State
CKE
n-1
CKE
n /CS /RAS /CAS /WE ADDR ACTION Note
H X X X X X X Invalid
L H H X X X X Exit Self Refresh→Idle after tRDC(ABI) 6
L H L H H H X Exit Self Refresh→Idle after tRDC(ABI) 6
L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
L H L L X X X ILLEGAL
Self
Refresh
L L X X X X X NOP(Maintain Self Refresh)
H X X X X X X Invalid
L H H X X X X Exit Self Refresh→ABI 7
L H L H H H X Exit Self Refresh→ABI 7
L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
L H L L X X X ILLEGAL
All
Banks
Precharge
Power
down
L L X X X X X NOP(Maintain Low Power Mode)
H H X X X X X Refer to Table 1
H L H X X X X Enter Power Down 8
H L L H H H X Enter Power Down 8
H L L H H L X ILLEGAL
H L L H L X X ILLEGAL
H L L L H H RA Row(&Bank) Active
H L L L H H X NOP
H L L L L L X Enter Self Refresh 8
H L L L L L OP Mode Mode Register Access
All
Banks
Idle
L L X X X X X NOP
H H X X X X X Refer to Operations in Table 1
H L X X X X X Begin Clock Suspend next cycle 9
L H X X X X X Exit Clock Suspend next cycle 9
Any State
other than
Listed
above L L X X X X X Maintain Clock Suspend
Abbreviations: ABI = All Banks Idle, RA = Row Address
Note:
6. CKE low to high transition is asynchronous.
7. CKE low to high transition is asynchronous if restart internal clock. A minimum setup time 1CLK + tSS
must be satisfy before any command other than exit.
8. Power down and self refresh can be entered only from the all banks idle state.
9. Must be a legal command.
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
27 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
Single Bit Read-Write-Read Cycle(Same Page) @ CAS Latency = 3,Burst Length = 1
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
28 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL VALUE UNIT
Voltage on any pin relative to VSS V
IN, VOUT -1.0 ~ 4.6 V
Voltage on VDD supply relative to VSS V
DD, VDDQ -1.0 ~ 4.6 V
Storage temperature TSTG -55 ~ +150 ℃
Power dissipation PD 1 W
Short circuit current IOS 50 mA
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITION
Recommended operating condition s (Voltage referenced to VSS = 0V, TA = 0 to 70 C °)
PARAMETER SYMBOL MIN TYP MAX UNIT NOTE
Supply voltage VDD, VDDQ 3.0 3.3 3.6 V
Input logic high voltage VIH 2.0 3.0 VDD+0.3 V 1
Input logic low voltage VIL -0.3 0 0.8 V 2
Output logic high voltage VOH 2.4 - - V IOH = -2mA
Output logic low voltage VOL - - 0.4 V IOL = 2mA
Input leakage current IIL -5 - 5 µA 3
Output leakage current IOL -5 - 5 µA 4
Note:
1. VIH(max) = 4.6V AC for pulse width ≤10ns acceptable.
2. VIL(min) = -1.5V AC for pulse width ≤10ns acceptable.
3. Any input 0V ≤VIN ≤VDD + 0.3V, all other pins are not under test = 0V.
4. Dout is disabled, 0V ≤VOUT ≤VDD.
CAPACITANCE (VDD = 3.3V, TA = 25 C °, f = 1MHZ)
PARAMETER SYMBOL MIN MAX UNIT
Input capacitance (A0 ~ A11, A13 ~ A12) CIN1 2.5 4 pF
Input capacitance
(CLK, CKE, /CS , /RAS , /CAS , /WE &L(U)DQM)
CIN2 2.5 4 pF
Data input/output capacitance (DQ0 ~ DQ15) COUT 2 6.5 pF
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
29 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
DC CHARACTERISTICS
Recommended operating condition unless otherwise noted，TA = 0 to 70℃
Speed
PARAMETER SYMBOL TEST CONDITION
CAS
Latency 6 7.5
UNIT NOTE
Operating Current
(One Bank Active)
ICC1
Burst Length = 1, tRC ≥tRC(min),
IOL = 0 mA
160 140 mA 1,2
ICC2P CKE ≤VIL(max), tcc = tck(min) 2 2 Precharge Standby
Current in
power-down mode
ICC2PS CKE & CLK ≤VIL(max), tcc = ∞ 2 2
mA
ICC2N
CKE ≥VIH(min), /CS ≤VIH(min), tCC = tck(min), Input
signals are changed one time during 2tck
45 45 Precharge Standby
Current in non power
- down mode ICC2NS
CKE ≥VIH(min), CLK ≤VIL(max), tCC = ∞
input signals are stable
25 25
mA
ICC3P CKE ≤VIL(max), tcc = tck(min) 6 6 Active Standby
Current in
power-down mode
ICC3PS CKE & CLK ≤VIL(max), tCC =∞ 6 6
mA
ICC3N
CKE ≥VIH(min), /CS ≥VIH(min), tCC = tck(min),
Input signals are changed one time during
2tck
55 55
Active Standby
Current in non
power-down mode
(One Bank Active) ICC3NS
CKE ≥VIH(min), CLK ≤VIL(max), tCC = ∞
input signals are stable
35 35
mA
Operating Current
(Burst Mode)
ICC4 I
OL = 0 mA, Page Burst, 2 Banks active 210 180 mA 1,2
Refresh Current ICC5 t
RC ≥tRC(min) 210 180 mA
Self Refresh Current ICC6 CKE ≤0.2V 2 2 mA
Note: 1. Measured with outputs open.
2. Input signals are changed one time during 2 CLKS.
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V ，TA = 0 to 70 °C)
PARAMETER VALUE UNIT
Input levels (VIH/VIL) 2.4/0.4 V
Input timing measurement reference level 1.4 V
Input rise and fall-time tr/tf = 1/1 ns
Output timing measurement reference level 1.4 V
Output load condition See Fig. 2
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
30 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
Asynchronous Characteristics (AC operating conditions unless otherwise noted)
SPEED
PARAMETER SYMBOL
6 7.5
UNIT NOTE
Row active to row active delay tRRD(min) 12 14 ns 1
/RAS to /CAS delay tRCD(min) 18 20 ns 1
Row precharge time tRP(min) 18 20 ns 1
tRAS(min) 40 42 ns 1 Row active time
tRAS(max) 100 us
@ Operating tRC(min) 58 63 ns 1 Row cycle time
@ Auto refresh tRFC(min) 60 70 ns 1,5
CAS latency=3 2
Number of valid Ouput data
CAS latency=2 1
ea 4
Col. Address to col. delay tCCD(min) 1 tCK 3
Last data in to col. address delay tCDL(min) 1 tCK 2
Last data in to row percharge tRDL(min) 2 tCK 2
Last data in to burst stop tBDL(min) 1 tCK 2
Refresh period(4096 rows) tBEF(max) 64 ms
6
Note:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. A new command may be given tRFC after self refresh exit.
6. A maximum of eight consecutive AUTO REFRESH commands (with tRFC(min)) can be posted to any given SDRAM,
and the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH
command is 8x15.6 µ s.)
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
31 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
Synchronous Characteristics (AC operating condition unless otherwise noted)
6 7.5
PARAMATER SYMBOL
MIN MAX MIN MAX
UNIT NOTE
CAS latency = 3 6 7.5 CLK cycle time
CAS latency = 2 tCC
10 1000
10
1000 ns 1
CAS latency = 3 - 5.4 - 5.4 CLK to valid
output delay CAS latency = 2
tSAC
- 6 - 6
ns 1, 2
CAS latency = 3 2.5 - 2.5 - Output data
hold time CAS latency = 2 tOH
2.5 - 2.5 -
ns 2
CLK high pulse width tCH 2.5 - 2.5 - ns 3
CLK low pulse width tCL 2.5 - 2.5 - ns 3
Input setup time tSS 1.5 - 1.5 - ns 3
Input hold time tSH 1 - 1 - ns 3
CLK to output in Low-Z tSLZ 1 - 1 - ns 2
CAS latency = 3 - 5.4 - 5.4
CLK to output
in Hi-Z CAS latency = 2 tSHZ
- 6 - 6
ns
Note:
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns. (tr/2 - 0.5) ns should be considered.
3. Assumed input rise and fall time (tr & tf) =1ns.
If tr & tf is longer than 1ns. transient time compensation should be considered.
i.e., [(tr + tf)/2 – 1] ns should be added to the parameter.
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
32 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
Power Up Sequence
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
33 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
Read & Write Cycle at Same Bank @ Burst Length = 4
Note:
1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row
precharge. Last valid output will be Hi-Z (tSHZ) after the clock.
3. Output will be Hi-Z after the end of burst. (1,2,4,8 & Full page bit burst)
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
34 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
Page Read & Write Cycle at Same Bank @ Burst Length = 4
Note:
1. To Write data before burst read ends. DQM should be asserted three cycle prior to write command to avoid bus
contention.
2. Row precharge will interrupt writing. Last data input , tRDL before row precharge , will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
35 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
Page Read Cycle at Different Bank @ Burst Length = 4
Note:
1. /CS can be don’t cared when /RAS , /CAS and /WE are high at the clock high going edge.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
36 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
Page Write Cycle at Different Bank @ Burst Length = 4
Note:
1. To interrupt burst write by Row precharge , DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge , both the write and the precharge banks must be the same.
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
37 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
Read & Write Cycle at Different Bank @ Burst Length = 4
Note:
1. tCDL should be met to complete write.
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
38 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
Read & Write cycle with Auto Precharge @ Burst Length = 4
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
39 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
Clock Suspension & DQM Operation Cycle @ CAS Letency = 2 , Burst Length = 4
Note:
1. DQM is needed to prevent bus contention
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
40 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
Read interrupted by Precharge Command & Read Burst Stop Cycle @ Burst Length = Full
page
Note:
1. About the valid DQs after burst stop, it is same as the case of /RAS interrupt.
Both cases are illustrated above timing diagram. See the label 1,2 on them.
But at burst write, Burst stop and /RAS interrupt should be compared carefully.
Refer the timing diagram of “Full page write burst stop cycles”.
2. Burst stop is valid at every burst length.
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
41 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
Write interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length = Full
page
Note:
1. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined
by AC parameter of tRDL.
DQM at write interrupted by precharge command is needed to prevent invalid write.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.
2. Burst stop is valid at every burst length.
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
42 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
Active/Precharge Power Down Mode @ CAS Latency = 2, Burst Length = 4
Note:
1. Both banks should be in idle state prior to entering precharge power down mode.
2. CKE should be set high at least 1CLK + tSS prior to Row active command.
3. Can not violate minimum refresh specification.
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
43 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
Self Refresh Entry & Exit Cycle
Note:
TO ENTER SELF REFRESH MODE
1. /CS , /RAS & /CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays “Low”.
cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
1. System clock restart and be stable before returning CKE high.
2. /CS starts from high.
3. Minimum tRFC is required after CKE going high to complete self refresh exit.
4. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst
refresh.
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
44 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
Mode Register Set Cycle Auto Refresh Cycle
All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
Note: MODE REGISTER SET CYCLE
1. /CS , /RAS , /CAS , & /WE activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new /RAS activation.
3. Please refer to Mode Register Set table.
Synchronous DRAM
2M Word x 16 Bit x 4 Banks CS56A12863
45 Rev. 1.1
Chiplus reserves the right to change product or specification without notice.
ORDER INFORMATION
Note: Package material code “R” meets ROHS
