UCC28220-Q1 www.ti.com SLUS789 - MARCH 2008 INTERLEAVED DUAL PWM CONTROLLER WITH PROGRAMMABLE MAXIMUM DUTY CYCLE FEATURES APPLICATIONS * Qualified for Automotive Applications * 2-MHz High-Frequency Oscillator With 1-MHz Operation Per Channel * Matched Internal Slope Compensation Circuits * Programmable Maximum Duty Cycle Clamp 60% to 90% Per Channel * Peak Current Mode Control With Cycle-by-Cycle Current Limit * Current Sense Discharge Transistor for Improved Noise Immunity * Accurate Line Undervoltage and Overvoltage Sense With Programmable Hysteresis * Opto-Coupler Interface * Operates From 12-V Supply * Programmable Soft-Start * 1 2 * * * High Output Current (50 A to 100 A) Converters Maximum Power Density Designs High-Efficiency 48-V Input with Low-Output Ripple Converters High-Power Offline, Telecom, and Datacom Power Supplies DESCRIPTION The UCC28220 is a BiCMOS interleaved dual-channel PWM controller. Peak current mode control is used to ensure current sharing between the two channels. A precise maximum duty cycle clamp can be set to any value between 60% and 90% duty cycle per channel. UCC28220 has an UVLO turn-on threshold of 10 V for use in 12-V supplies. It has 8-V turn-off threshold. Additional features include a programmable internal slope compensation with a special circuit that ensures exactly the same slope is added to each channel. The UCC28220 is available in a 16-pin low-profile TSSOP package. TYPICAL APPLICATION VIN (48 V) CS1 UCC28220 1 LINEOV N/C 16 Bias 2 LINE HYS LINEUV 15 3 VDD REF 14 4 CS1 OUT1 13 5 SLOPE OUT2 12 VOUT 1/2 UCC27324 6 CS2 GND 11 7 SS CHG 10 CS2 REF 8 CTRL DISCHG 9 1/2 UCC27324 E/A 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2008, Texas Instruments Incorporated UCC28220-Q1 www.ti.com SLUS789 - MARCH 2008 ORDERING INFORMATION (1) TA = TJ UVLO THRESHOLDS -40C to 125C 10 V On / 8 V Off (1) (2) ORDERABLE PART NUMBER PACKAGE (2) TSSOP-16 - PW Reel of 2000 UCC28220QPWRQ1 TOP-SIDE MARKING U28220Q For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. ABSOLUTE MAXIMUM RATINGS (1) (2) over operating free-air temperature (unless otherwise noted) VDD Supply voltage IOUT(dc) Output current, dc IREF 15 V OUT1, OUT2 10 mA OUT1/ OUT2 capacitive load 200 pF REF output current 10 mA Current sense inputs CS1, CS2 CHG, DISCHG, SLOPE, REF, CNTRL Analog inputs SS, LINEOV, LINEUV, LINEHYS -1 V to 2 V -0.3 V to 3.6 V -0.3 V to 7 V PD Power dissipation at TA = 25C TJ Virtual-junction operating temperature range -55C to 150C Tstg Storage temperature range -65C to 150C Tlead Lead temperature (soldering, 10 seconds) (1) (2) 400 mW 300C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. Currents are positive into and negative out of the specified terminal. RECOMMENDED OPERATING CONDITIONS VIN High-voltage start-up input voltage VDD Supply voltage 2 Submit Documentation Feedback MIN MAX 36 76 UNIT V 8 14.5 V Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): UCC28220-Q1 UCC28220-Q1 www.ti.com SLUS789 - MARCH 2008 ELECTRICAL CHARACTERISTICS VDD = 12 V, 0.1-F capacitor from VDD to GND, 0.1-F capacitor from REF to GND, fOSC = 1 MHz, TA = -40C to 125C, TA = TJ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Overall Operating VDD 8.5 14 Quiescent current SS = 0 V, No switching, fosc = 1 MHz 1.5 3 4 Operating current Outputs switching, fosc = 1 MHz 1.6 3.5 6 V mA Startup Section Startup current VDD < (UVLO - 0.8) 200 A UVLO start threshold 9.5 10 10.5 V UVLO stop threshold 7.6 8 8.4 V UVLO hysteresis 1.8 2 2.2 V 3.15 3.3 3.45 Reference Output voltage 8.5 V < VDD < 14 V, ILOAD = 0 mA to -10 mA Output current Outputs not switching, CNTRL = 0 V Output short-circuit current VREF = 0 V VREF UVLO 10 V mA -40 -20 -10 mA 2.55 3 3.25 V -60 -100 -130 A A Soft Start (SS) SS charge current RCHG = 10.2 k, SS = 0 V SS discharge current RCHG = 10.2 k, SS = 2 V 60 100 130 SS initial voltage LINEOV = 2 V, LINEUV = 0 V 0.5 1 1.5 SS voltage at 0% dc Point at which output starts switching 0.5 1.2 1.8 75 90 100 % 3 3.5 4 V SS voltage ratio SS maximum voltage LINEOV = 0 V, LINEUV = 2 V V Oscillator and PWM Output frequency RCHG = 10.2 k, RDISCHG = 10.2 k 400 500 550 kHz Oscillator frequency RCHG = 10.2 k, RDISCHG = 10.2 k 900 1000 1100 kHz Output maximum duty cycle RCHG = 10.2 k, RDISCHG = 10.2 k, Measured at OUT1 and OUT2 73 75 77 CHG voltage 1.5 2.5 3 DISCHG voltage 1.5 2.5 3 140 200 260 mV/s 0 10 % nA % V Slope Compensation Slope RSLOPE = 75 k, RCHG = 66 k, RDISCHG = 44 k, CSx = 0 V to 0.5 V Channel matching RSLOPE = 75 k, CSx = 0 V Current Sense CS1, CS2 bias current CS1 = 0, CS2 = 0 Prop delay CSx to OUTx CSx input 0 V to 1.5 V step CS1, CS2 sink current CSx = 2 V -500 2.3 0 500 40 85 ns 4.5 7 mA CNTRL Section Resistor ratio (1) 0.6 CTRL input current CTRL = 0 V and 3.3 V CTRL voltage at 0% dc CSx = 0 V, Point at which output starts switching (checks resistor ratio) (1) -100 0 100 nA 0.5 1.2 1.8 V Specified by design Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): UCC28220-Q1 3 UCC28220-Q1 www.ti.com SLUS789 - MARCH 2008 ELECTRICAL CHARACTERISTICS (continued) VDD = 12 V, 0.1-F capacitor from VDD to GND, 0.1-F capacitor from REF to GND, fOSC = 1 MHz, TA = -40C to 125C, TA = TJ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Output Section (OUT1, OUT2) Low level IOUT = 10 mA 0.4 1 High level IOUT = -10 mA, VREF - VOUT 0.4 1 V V Rise time CLOAD = 50 pF 10 20 ns Fall time CLOAD = 50 pF 10 20 ns Line-Sense Section LINEOV threshold LINEUV threshold TA = 25C 1.24 1.26 1.28 TA = -40C to 125C 1.23 1.26 1.29 TA = 25C 1.24 1.26 1.28 TA = -40C to 125C 1.23 1.26 1.29 3.25 3.4 V V V LINEHYST pull up voltage LINEOV = 2 V, LINEUV = 2 V 3.1 LINEHYST off leakage LINEOV = 0 V, LINEUV = 2 V -500 0 500 nA LINEHYS pullup resistance I = -20 A 100 500 LINEHYS pulldown resistance I = 20 A 100 500 LINEOV bias current LINEOV = 1.25 V -900 900 nA LINEUV bias current LINEUV = 1.25 V -500 500 nA 4 Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): UCC28220-Q1 UCC28220-Q1 www.ti.com SLUS789 - MARCH 2008 FUNCTIONAL BLOCK DIAGRAM REF RUN REFERENCE 14 16 NC UVLO CONTROL 2 CHG 10 T OSC DISCHG 9 CLK1 Q FF + 4 VDD CLK2 Q CS1 3 CLK1 + R 0.5 V VREF S Q LATCH 13 OUT1 Q RUN 11 SLOPE COMPENSATION 0.5 V 6 + CS2 CLK2 + VREF S Q LATCH R GND 12 OUT2 Q RUN SLOPE 5 CTRL 8 + + - 20 kW 1 LINEOV 30 kW 1 pF LINE OV/UV 2 LINEHYS 15 LINEUV Soft-Start SS 7 RUN Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): UCC28220-Q1 5 UCC28220-Q1 www.ti.com SLUS789 - MARCH 2008 PW PACKAGE (TOP VIEW) LINEOV 1 16 NC LINEHYS 2 15 LINEUV VDD 3 14 REF CS1 4 13 OUT1 SLOPE 5 12 OUT2 CS2 6 11 GND SS 7 10 CHG CTRL 8 9 DISCHG NC - No internal connection TERMINAL FUNCTIONS TERMINAL 6 I/O FUNCTION NO. NAME 1 LINEOV I Input for line overvoltage comparator 2 LINEHYS I Sets line comparator hysteresis 3 VDD I Device supply input 4 CS1 I Channel 1 current sense input 5 SLOPE I Sets slope compensation 6 CS2 I Channel 2 current sense input 7 SS I Soft-start input 8 CTRL I Feedback control input 9 DISCHG I Sets oscillator discharge current 10 CHG I Sets oscillator charge current 11 GND 12 OUT2 O PWM output from channel 2 13 OUT1 O PWM output from channel 1 14 REF O Reference voltage output 15 LINEUV I Input for line undervoltage comparator 16 NC Device ground No connection Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): UCC28220-Q1 UCC28220-Q1 www.ti.com SLUS789 - MARCH 2008 TERMINAL DESCRIPTIONS VDD: VDD supplies power to the device and is monitored by the UVLO circuit, which ensures glitch-free startup. Until VDD reaches its UVLO threshold, the device remains in low-power mode, drawing approximately 150 A of current and forcing pins SS, CS1, CS2, OUT1, and OUT2 to logic 0 states. If VDD falls below 8 V after reaching the turn-on threshold, the device returns to the low-power state. The UVLO turn-on threshold is 10 V, and the turn-off threshold is 8 V. CS1 and CS2: These two pins are the current-sense inputs to the device. The signals are internally level shifted by 0.5 V before the signal reaches the PWM comparator. Internally, the slope compensation ramp is added to this signal. The linear operating range on this input is 0 to 1.5 V. Also, this pin is pulled to ground each time its respective output goes low (i.e., OUT1 or OUT2). SLOPE: This pin sets up a current used for the slope compensation ramp. A resistor to ground sets up a current, which is internally divided by 25 and applied to an internal 10-pF capacitor. Under normal operation, the dc voltage on this pin is 2.5 V. SS: A capacitor to ground sets up the soft-start time for the open-loop soft-start function. The source and sink current from this pin is equal to 3/7 of the oscillator charge current set by the resistor on the CHG pin. The soft-start capacitor is held low during UVLO and during a line overvoltage or undervoltage condition. Once an overvoltage or undervoltage fault occurs, the soft-start capacitor is discharged by a current equal to its charging current. The capacitor does not quickly discharge during faults. In this way, the controller has the ability to recover quickly from very short line transients. This pin can also be used as an enable/disable function. CHG: A resistor from this pin to GND sets up the charging current of the internal CT capacitor used in the oscillator. This resistor, in conjunction with the resistor on the DISCHG pin, sets the operating frequency and maximum duty cycle. Under normal operation, the dc voltage on this pin is 2.5 V. DISCHG: A resistor from this pin to GND sets the discharge current of the internal CT capacitor used in the oscillator. This resistor, in conjunction with the resistor on the CHG pin, sets the operating frequency and maximum duty cycle. Under normal operation, the dc voltage on this pin is 2.5 V. OUT1 and OUT2: These output buffers are intended to interface with high-current MOSFET drivers. The output drive capability is approximately 33 mA and has an output impedance of 100 . The outputs swing between GND and REF. LINEOV: This pin is connected to a comparator and used to monitor the line voltage for an overvoltage condition. The typical threshold is 1.26 V. LINEUV: This pin is connected to a comparator and used to monitor the line voltage for an undervoltage condition. The typical threshold is 1.26 V. LINEHYST: This pin is controlled by both the LINEOV and LINEUV pins. It controls the hysteresis values for both the overvoltage and undervoltage line detectors. REF: REF is a 3.3-V output used primarily as a source for the output buffers and other internal circuits. It is protected from accidental shorts to ground. For improved noise immunity, it is recommended that the reference pin be bypassed with a minimum of 0.1-F of capacitance to GND. Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): UCC28220-Q1 7 UCC28220-Q1 www.ti.com SLUS789 - MARCH 2008 APPLICATION INFORMATION General The device is composed of several housekeeping blocks, as well as two slope-compensated PWM channels that are interleaved. The circuit is intended to run from an external VDD supply voltage between 8 V and 14 V. Other functions contained in the device are supply UVLO, 3.3-V reference, accurate line overvoltage and undervoltage functions, a high speed programmable oscillator for both frequency and duty cycle, programmable slope compensation, and programmable soft-start functions. The UCC28220 is a primary-side controller for a two-channel interleaved power converter. The device is compatible with forward or flyback converters, as long as a duty cycle clamp between 60% and 90% is required. Therefore, the active clamp forward and flyback converters, as well as the RCD and resonant reset forward converters, are compatible with this device. To ensure the two channels share the total converter output current, current-mode control with internal slope compensation is used. Slope compensation is user programmable via a dedicated pin and can be set over a 50:1 range, ensuring good small-signal stability over a wide range of applications. Line Overvoltage and Undervoltage Three pins are provided to turn off the output drivers and reset the soft-start capacitor when the converter input voltage is outside a prescribed range. The undervoltage set point and undervoltage hysteresis are accurately set via external resistors. The overvoltage set point is also accurately set via a resistor ratio, but the hysteresis is fixed by the same resistor that sets the undervoltage hysteresis. Figure 1 and Figure 2 show a detailed functional diagram and operation of the undervoltage lockout (UVLO) overvoltage lockout (OVLO) features. The equations for setting the thresholds defined in Figure 2 are: R1 V1 + 1.26 ) 1.26 (R2 ) R3) (R1 ) Rx) V2 + 1.26 , where Rx + R4 (R2 ) R3) Rx (R1 ) R2 ) R3) V4 + 1.26 R3 V3 + V4 * 1.26 R1 R4 and (1) (2) (3) (4) The UVLO hysteresis and the OVLO hysteresis can then be calculated as V2 - V1 and V4 - V3, respectively. By examining the design equations it becomes apparent that the value of R4 sets the amount of hysteresis at both thresholds. By realizing this fact, the designer can then set the value of R4 based on the most critical hysteresis specification either at high line or at low line. In most designs, the value of R4 is determined by the desired amount of hysteresis around the UVLO threshold. As an example, consider a telecom power supply with the following input UVLO and OVLO design specifications: * V1 = 32.0 V * V2 = 34.0 V * V3 = 83.0 V * V4 = 84.7 V then * R1 = 976 k * R2 = 24.9 k * R3 = 15.0 k and * R4 = 604 k 8 Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): UCC28220-Q1 UCC28220-Q1 www.ti.com SLUS789 - MARCH 2008 Input Voltage R1 UV 15 + 1.26 V 1.26 V + S1 OPEN HYS 2 R4 S2 CLOSED LINE_GOOD R2 OV 1 + R3 1.26 V Figure 1. Line UVLO and OVLO Functional Diagram ENABLE LINE_GOOD OFF V1 V2 V3 V4 Figure 2. Line UVLO and OVLO Operation VDD Because the driver output impedance is high, the energy storage requirements on the VDD capacitor is low. For improved noise immunity, it is recommended that the VDD pin be bypassed with a minimum of 0.1 F of capacitance to GND. In most typical applications, the bias voltage for the MOSFET drivers is also used as the VDD supply voltage for the chip. In the aforementioned applications, it is beneficial to add a low-value resistor between the bulk-storage capacitor of the driver and the VDD capacitor for the UCC28220. By adding a resistor in series with the bias supply, any noise that is present on the bias supply is filtered out before getting to the VDD pin of the controller. Reference For improved noise immunity, it is recommended that the reference pin (REF) be bypassed with a minimum of 0.1 F of capacitance to GND. Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): UCC28220-Q1 9 UCC28220-Q1 www.ti.com SLUS789 - MARCH 2008 Oscillator Operation and Maximum Duty Cycle Setpoint The oscillator uses an internal capacitor to generate the time base for both PWM channels. The oscillator is programmable over a 200-kHz to 2-MHz frequency range with 20% to 80% maximum duty cycle range. Both the dead time and the frequency of the oscillator are divided by two to generate the PWM clock and off-time information for each of the outputs. In this way, a 20% oscillator duty cycle corresponds to a 60% maximum duty cycle at each output, where an 80% oscillator duty cycle yields a 90% duty cycle clamp at each output. The design equations for the oscillator and maximum duty cycle set point are given by: F OSC + 2 F OUT D MAX(osc) + 1 * 2 R CHG + KOSC R DISCHG + KOSC 1 * DMAX(out) (5) (6) DMAX(osc) F OSC (7) 1 * DMAX(osc) F OSC (8) Where KOSC = 2.04 x 1010 [/s] FOUT = Switching frequency at the outputs of the chip (Hz) DMAX(out) = Maximum duty cycle limit at the outputs of the chip DMAX(osc) = Maximum duty cycle of the Oscillator for the desired maximum duty cycle at the outputs FOSC = Oscillator frequency for desired output frequency (Hz) RCHG = External oscillator resistor which sets the charge current () RDISCHG = External oscillator resistor which sets the discharge current () Soft Start A current is forced out of the SS pin, equal to 3/7 of the current set by RCHG, to provide a controlled ramp voltage. The current set by the RCHG resistor is equal to 2.5 V divided by RCHG. This ramp voltage overrides the duty cycle on the CTRL pin, allowing a controlled startup. Assuming the UCC28220 is biased on the primary side, the soft start should be quite quick to allow the secondary bias to be generated, and the secondary side control can then take over. Once the soft-start time interval is complete, a closed-loop soft-start on the secondary side can be executed. 2.5 ISS + 3 7 RCHG (9) Where ISS = current which is sourced out of the SS pin during the soft-start time (A) Current Sense The current sense signals CS1 and CS2 are level shifted by 0.5 V and have the slope compensation ramps added to them before being compared to the control voltage at the input of the PMW comparators. The amplitude of the current sense signal at full load should be selected such that it is very close to the maximum control voltage, in order to limit the peak output current during short-circuit operation. Output Drivers The UCC28220 is intended to interface with the UCC27323/4/5 family of MOSFET drivers. As such, the output drive capability is low (effectively 100 ), and the driver outputs swing between GND and REF. 10 Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): UCC28220-Q1 UCC28220-Q1 www.ti.com SLUS789 - MARCH 2008 Slope Compensation The slope compensation circuit in the UCC28220 operates on a cycle-by-cycle basis. The two channels have separate slope compensation circuits. These are fabricated in precisely the same way so as current sharing is unaffected by the slope compensation circuit. For each channel, an internal capacitor is reset whenever that channel's output is off. At the beginning of the PWM cycle, a current is mirrored off the SLOPE pin into the capacitor, developing an independent ramp. Since the two channel's ramps start when the channel's output changes from a low to high state, the ramps are thus interleaved. These internal ramps are added to the voltages on the current sense pins (CS1 and CS2) and the result forms an input to the PWM comparators. REF SLOPE (5) 2.5/(25*R_SLOPE) = I_SC R_SLOPE PWM TO RESET of PWM LATCH CTRL (8) + + 0.5V C_SC OUT 1 ON S1 10 pF OFF CS1 (4) S2 Figure 3. Slope Compensation Detail for Channel 1 (Duplicate Matched Circuitry for Channel 2) To ensure stability, the slope compensation circuit must add between 1/5 and 1 times the inductor downslope to each of the current sense signals prior to being applied to the PWM comparator's input. Determining the value for the slope compensation resistor: Design Example NCT(p) = 1 NCT(s) = 50 VOUT = 12 LOUT = 3.2 x 10 -6 Np = 7 RSENSE = 5.23 Ns = 5 VEA(cl) = 1.98 FS(out) = 500000 Where NCT(p) = Number of primary turns on the Current Transformer (Turns) NCT(s) = Number of Secondary turns on the current transformer (Turns) VOUT = Nominal output voltage of the converter (V) LOUT = Inductance value of each output inductor (H) NP = Number of primary turns on the main transformer (Turns) NS = Number of secondary turns on the main transformer (Turns) RSENSE = Value of current sense resistor on secondary of current sense transformer () VEA(cl) = Maximum value of the E/A output voltage (V) FS(out) = Switching frequency of each output (Hz) Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): UCC28220-Q1 11 UCC28220-Q1 www.ti.com SLUS789 - MARCH 2008 Determine the correct value for the slope resistor, RSLOPE, to provide the desired amount of slope compensation. NCT(p) N CT + , Current Transformer Turns Ratio N CT(s) (10) 1. Transform the secondary inductor downslope to the primary V Ns S L(prime) + OUT , S L(prime) + 2.679 Ams L OUT Np (11) 2. Calculate the transformed slope voltage at sense resistor VS L(prime) + SL(prime) NCT RSENSE, VS L(prime) + 2.281 Vms (12) 3. Calculate the RSLOPE value to give a compensating ramp equal to the transformed slope voltage given in Equation 12 M + 1.0 (13) The desired ratio between the compensating ramp and the output inductor downslope ramp, transformed to the primary sense resistor, is shown in Equation 14. 10 4 R SLOPE + , RSLOPE + 35.556 kW M VS L(prime) 10 *6 (14) VIN CS1 1 UCC28220 OV N/C 16 2 HYS UV 15 3 VDD REF 14 Bias VOUT 1/2 UCC27424 4 CS1 OUT1 13 5 SLOPE OUT2 12 6 CS2 GND 11 7 SS CHG 10 8 CTRL CS2 DISCHG 9 1/2 UCC27424 REF E/A Figure 4. Interleaved Flyback Application Circuit 12 Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): UCC28220-Q1 UCC28220-Q1 www.ti.com SLUS789 - MARCH 2008 VIN CS1 UCC28220 1 OV 2 HYS N/C 16 UV 15 Bias 1/2 UCC27424 3 VDD REF 14 4 CS1 OUT1 13 5 SLOPE OUT2 12 VOUT CS2 6 CS2 GND 11 7 SS CHG 10 8 CTRL DISCHG 9 1/2 UCC27424 E/A Figure 5. Interleaved Boost Application Circuit Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): UCC28220-Q1 13 UCC28220-Q1 www.ti.com SLUS789 - MARCH 2008 TYPICAL CHARACTERISTICS UVLO THRESHOLDS vs TEMPERATURE QUIESCENT CURRENT vs SUPPLY VOLTAGE 4.0 13.5 3.5 IDD - Quiescent Current - mA VUVLO - UVLO Thresholds - V 12.5 11.5 10.5 UVLO on threshold 9.5 3.0 2.5 2.0 1.5 1.0 8.5 0.5 UVLO off threshold 0.0 7.5 -50 -25 0 25 50 75 TJ - Temperature - C 100 2 4 6 8 10 12 VDD - Supply Voltage - V 14 Figure 6. Figure 7. REFERENCE VOLTAGE vs TEMPERATURE LINEOV AND LINEUV THRESHOLDS vs TEMPERATURE 3.45 16 1.270 1.265 3.40 LINEOV 1.260 Vth - Trip Threshold - V VREF - Reference Voltage - V 0 125 3.35 3.30 No load 3.25 Load 1.255 1.250 LINEUV 1.245 1.240 3.20 1.235 3.15 -50 1.230 -25 0 25 50 75 TJ - Temperature - C 100 125 -50 -25 Figure 8. 14 0 25 50 75 TJ - Temperature - C 100 125 Figure 9. Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): UCC28220-Q1 UCC28220-Q1 www.ti.com SLUS789 - MARCH 2008 TYPICAL CHARACTERISTICS (continued) SLOPE COMPENSATION vs TEMPERATURE PROGRAMMING RESISTOR vs SLOPE COMPENSATION 6 230 RSLOPE - Slope Programming Resistor - W 225 SLOPE - Slope Compensation - mV/s 10 RSLOPE = 75 kW 220 215 210 205 CS1 = 0 V 200 195 CS1 = 0.5 V 190 185 180 5 10 104 175 170 -50 -25 0 25 50 75 TJ - Temperature - C 100 103 10 125 Figure 10. Figure 11. CHANNEL 1 AND CHANNEL 2 SLOPE MATCHING vs TEMPERATURE RISE AND FALL TIME vs TEMPERATURE (CL = 50 pF 10 RSLOPE = 75 kW CS0 = 0 V CS1 = 0 V tr and tf - Rise and Fall Times - ns 8 6 4 Mismatch - % 100 SLOPE - Slope Compensation - mV/s 2 0 -2 -4 -6 -8 -10 -50 -25 0 25 50 75 TJ - Temperature - C 100 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -50 1000 Fall Time Rise Time -25 125 Figure 12. 0 25 50 75 TJ - Temperature - C 100 125 Figure 13. Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): UCC28220-Q1 15 UCC28220-Q1 www.ti.com SLUS789 - MARCH 2008 TYPICAL CHARACTERISTICS (continued) VOH AND VOL vs TEMPERATURE SOFT-START CHARGE CURRENT vs TEMPERATURE -70 IOUT = 10 mA RCHG = 10.2 kW ISSCH - Charge Current - A VO - Output Voltage - V -80 VREF - VOUT (VOH) VOL -90 -100 -110 -120 -50 -25 0 25 50 75 TJ - Temperature - C 100 -130 -50 125 -25 0 25 50 75 TJ - Temperature - C Figure 14. Figure 15. SOFT-START DISCHARGE CURRENT vs TEMPERATURE PROGRAMMING RESISTORS vs SWITCHING FREQUENCY 130 100 125 1M RCHRG, RDISRG - Resistance - W ISSdis - Charge Current - A 120 110 100 90 RCHRG = RDISRG DMAX = 75% 100k 10k 80 70 -50 -25 0 25 50 75 TJ - Temperature - C 100 125 1k 10k Figure 16. 16 100k 1M 10M fS - Switching Frequency - Hz Figure 17. Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): UCC28220-Q1 UCC28220-Q1 www.ti.com SLUS789 - MARCH 2008 TYPICAL CHARACTERISTICS (continued) OSCILLATOR FREQUENCY vs TEMPERATURE PROGRAMMABLE MAX DUTY CYCLE vs TEMPERATURE 77 550 RCHRG = RDISRG = 10.2 kW RCHRG = RDISRG = 10.2 kW 530 76 520 DC - Duty Cycle - % fs - Oscillator Frequency - kHz 540 510 500 490 480 75 74 470 460 73 -50 450 -50 -25 0 25 75 50 100 125 -25 0 TJ - Temperature - C 25 50 75 TJ - Temperature - C Figure 18. 100 125 Figure 19. CSx TO OUTx DELAY vs CSx PEAK VOLTAGE 100 90 CSx to OUTx Delay - ns 80 105C 70 60 25C 50 40 -40C 30 20 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 CSx - Peak Voltage - V Figure 20. Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): UCC28220-Q1 17 UCC28220-Q1 www.ti.com SLUS789 - MARCH 2008 Related Products DEVICE DESCRIPTION PACKAGE OPTIONS UCC27323/4/5 Dual 4-A High-Speed Low-Side MOSFET Drivers SOIC-8, PowerPADTM MSOP-8, PDIP-8 UCC27423/4/5 Dual 4-A High-Speed Low-Side MOSFET Drivers with Enable SOIC-8, PowerPAD MSOP-8, PDIP-8 TPS2811/12/13 Dual 2.4-A High-Speed Low-Side MOSFET Drivers SOIC-8, TSSOP-8, PDIP-8 UC3714/15 Dual 2.4-A High-Speed Low-Side MOSFET Drivers SOIC-8, PowerSOIC-14, PDIP-8 18 Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): UCC28220-Q1 PACKAGE OPTION ADDENDUM www.ti.com 2-Jul-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty UCC28220QDRQ1 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC28220QPWRQ1 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF UCC28220-Q1 : * Catalog: UCC28220 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant UCC28220QDRQ1 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 UCC28220QPWRQ1 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC28220QDRQ1 SOIC D 16 2500 367.0 367.0 38.0 UCC28220QPWRQ1 TSSOP PW 16 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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