1
FEATURES APPLICATIONS
DESCRIPTION
TYPICAL APPLICATION
UCC28220
3
7
6
4
5
1
8
15
11
12
14
13
9
10
VDD
CS1
SLOPE
CS2
SS
CTRL
LINEOV
LINEUV
OUT1
OUT2
CHG
DISCHG
Bias
E/A
2
16
LINE
N/C
VIN
(48 V)
REF
GND
CS1
VOUT
REF
1/2 UCC27324
1/2 UCC27324
CS2
HYS
UCC28220-Q1
SLUS789 – MARCH 2008www.ti.com
INTERLEAVED DUAL PWM CONTROLLERWITH PROGRAMMABLE MAXIMUM DUTY CYCLE
•High Output Current (50 A to 100 A)2
•Qualified for Automotive Applications
Converters•2-MHz High-Frequency Oscillator With 1-MHz
•Maximum Power Density DesignsOperation Per Channel
•High-Efficiency 48-V Input with Low-Output•Matched Internal Slope Compensation Circuits
Ripple Converters•Programmable Maximum Duty Cycle Clamp
•High-Power Offline, Telecom, and Datacom60% to 90% Per Channel
Power Supplies•Peak Current Mode Control WithCycle-by-Cycle Current Limit•Current Sense Discharge Transistor for
The UCC28220 is a BiCMOS interleavedImproved Noise Immunity
dual-channel PWM controller. Peak current mode•Accurate Line Undervoltage and Overvoltage
control is used to ensure current sharing between thetwo channels. A precise maximum duty cycle clampSense With Programmable Hysteresis
can be set to any value between 60% and 90% duty•Opto-Coupler Interface
cycle per channel. UCC28220 has an UVLO turn-on•Operates From 12-V Supply
threshold of 10 V for use in 12-V supplies. It has 8-V•Programmable Soft-Start
turn-off threshold.
Additional features include a programmable internalslope compensation with a special circuit that ensuresexactly the same slope is added to each channel.The UCC28220 is available in a 16-pin low-profileTSSOP package.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains
Copyright © 2008, Texas Instruments IncorporatedPRODUCTION DATA information current as of publication date.Products conform to specifications per the terms of TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
(1) (2)
RECOMMENDED OPERATING CONDITIONS
UCC28220-Q1
SLUS789 – MARCH 2008
ORDERING INFORMATION
(1)
UVLO ORDERABLE PART TOP-SIDET
A
= T
J
PACKAGE
(2)THRESHOLDS NUMBER MARKING
– 40 °C to 125 °C 10 V On / 8 V Off TSSOP-16 – PW Reel of 2000 UCC28220QPWRQ1 U28220Q
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com .(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .
over operating free-air temperature (unless otherwise noted)
V
DD
Supply voltage 15 VI
OUT(dc)
Output current, dc OUT1, OUT2 ± 10 mAOUT1/ OUT2 capacitive load 200 pFI
REF
REF output current 10 mACurrent sense inputs CS1, CS2 – 1 V to 2 VCHG, DISCHG, SLOPE, REF, CNTRL – 0.3 V to 3.6 VAnalog inputs
SS, LINEOV, LINEUV, LINEHYS – 0.3 V to 7 VP
D
Power dissipation at T
A
= 25 °C 400 mWT
J
Virtual-junction operating temperature range – 55 °C to 150 °CT
stg
Storage temperature range – 65 °C to 150 °CT
lead
Lead temperature (soldering, 10 seconds) 300 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltages are with respect to GND. Currents are positive into and negative out of the specified terminal.
MIN MAX UNIT
V
IN
High-voltage start-up input voltage 36 76 VV
DD
Supply voltage 8 14.5 V
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ELECTRICAL CHARACTERISTICS
UCC28220-Q1
SLUS789 – MARCH 2008
V
DD
= 12 V, 0.1- µF capacitor from VDD to GND, 0.1- µF capacitor from REF to GND, f
OSC
= 1 MHz, T
A
= – 40 °C to 125 °C,T
A
= T
J
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Overall
Operating VDD 8.5 14 VQuiescent current SS = 0 V, No switching, f
osc
= 1 MHz 1.5 3 4
mAOperating current Outputs switching, f
osc
= 1 MHz 1.6 3.5 6
Startup Section
Startup current VDD < (UVLO – 0.8) 200 µAUVLO start threshold 9.5 10 10.5 VUVLO stop threshold 7.6 8 8.4 VUVLO hysteresis 1.8 2 2.2 V
Reference
Output voltage 8.5 V < VDD < 14 V, I
LOAD
= 0 mA to – 10 mA 3.15 3.3 3.45 VOutput current Outputs not switching, CNTRL = 0 V 10 mAOutput short-circuit current V
REF
= 0 V – 40 – 20 – 10 mAV
REF
UVLO 2.55 3 3.25 V
Soft Start (SS)
SS charge current R
CHG
= 10.2 k Ω, SS = 0 V – 60 – 100 – 130 µASS discharge current R
CHG
= 10.2 k Ω, SS = 2 V 60 100 130 µASS initial voltage LINEOV = 2 V, LINEUV = 0 V 0.5 1 1.5
VSS voltage at 0% dc Point at which output starts switching 0.5 1.2 1.8SS voltage ratio 75 90 100 %SS maximum voltage LINEOV = 0 V, LINEUV = 2 V 3 3.5 4 V
Oscillator and PWM
Output frequency R
CHG
= 10.2 k Ω, R
DISCHG
= 10.2 k Ω400 500 550 kHzOscillator frequency R
CHG
= 10.2 k Ω, R
DISCHG
= 10.2 k Ω900 1000 1100 kHzR
CHG
= 10.2 k Ω, R
DISCHG
= 10.2 k Ω,Output maximum duty cycle 73 75 77 %Measured at OUT1 and OUT2CHG voltage 1.5 2.5 3
VDISCHG voltage 1.5 2.5 3
Slope Compensation
R
SLOPE
= 75 k Ω, R
CHG
= 66 k Ω, R
DISCHG
= 44 k Ω,Slope 140 200 260 mV/ µsCSx = 0 V to 0.5 VChannel matching R
SLOPE
= 75 k Ω, CSx = 0 V 0 10 %
Current Sense
CS1, CS2 bias current CS1 = 0, CS2 = 0 – 500 0 500 nAProp delay CSx to OUTx CSx input 0 V to 1.5 V step 40 85 nsCS1, CS2 sink current CSx = 2 V 2.3 4.5 7 mA
CNTRL Section
Resistor ratio
(1)
0.6CTRL input current CTRL = 0 V and 3.3 V – 100 0 100 nACSx = 0 V, Point at which output starts switchingCTRL voltage at 0% dc 0.5 1.2 1.8 V(checks resistor ratio)
(1) Specified by design
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UCC28220-Q1
SLUS789 – MARCH 2008
ELECTRICAL CHARACTERISTICS (continued)V
DD
= 12 V, 0.1- µF capacitor from VDD to GND, 0.1- µF capacitor from REF to GND, f
OSC
= 1 MHz, T
A
= – 40 °C to 125 °C,T
A
= T
J
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Output Section (OUT1, OUT2)
Low level I
OUT
= 10 mA 0.4 1 VHigh level I
OUT
= – 10 mA, V
REF
– V
OUT
0.4 1 VRise time C
LOAD
= 50 pF 10 20 nsFall time C
LOAD
= 50 pF 10 20 ns
Line-Sense Section
T
A
= 25 °C 1.24 1.26 1.28LINEOV threshold VT
A
= – 40 °C to 125 °C 1.23 1.26 1.29T
A
= 25 °C 1.24 1.26 1.28LINEUV threshold VT
A
= – 40 °C to 125 °C 1.23 1.26 1.29LINEHYST pull up voltage LINEOV = 2 V, LINEUV = 2 V 3.1 3.25 3.4 VLINEHYST off leakage LINEOV = 0 V, LINEUV = 2 V – 500 0 500 nALINEHYS pullup resistance I = – 20 µA 100 500 Ω
LINEHYS pulldown resistance I = 20 µA 100 500 Ω
LINEOV bias current LINEOV = 1.25 V – 900 900 nALINEUV bias current LINEUV = 1.25 V – 500 500 nA
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14
REF
10
CHG
9
DISCHG
8
CTRL
4
CS1
6
CS2
5
SLOPE
2LINEHYS
12 OUT2
11 GND
13 OUT1
7
SS
3VDD
16 NC
SLOPE
COMPENSATION
S Q
QR
+
CLK1
S Q
QR
+
CLK2
OSC
20 kW
30 kW1 pF
REFERENCE UVLO
CONTROL
RUN
Soft-Start
VREF
VREF
T Q
Q
CLK1
CLK2
+
+
-1LINEOV
15 LINEUV
LINE OV/UV
RUN
LATCH
LATCH
+
+
0.5 V
0.5 V
RUN
RUN
2
FF
UCC28220-Q1
SLUS789 – MARCH 2008
FUNCTIONAL BLOCK DIAGRAM
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1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
PW PACKAGE
(TOP VIEW)
NC
LINEUV
REF
OUT1
OUT2
GND
CHG
DISCHG
LINEOV
LINEHYS
VDD
CS1
SLOPE
CS2
SS
CTRL
NC – No internal connection
UCC28220-Q1
SLUS789 – MARCH 2008
TERMINAL FUNCTIONS
TERMINAL
I/O FUNCTIONNO. NAME
1 LINEOV I Input for line overvoltage comparator2 LINEHYS I Sets line comparator hysteresis3 VDD I Device supply input4 CS1 I Channel 1 current sense input5 SLOPE I Sets slope compensation6 CS2 I Channel 2 current sense input7 SS I Soft-start input8 CTRL I Feedback control input9 DISCHG I Sets oscillator discharge current10 CHG I Sets oscillator charge current11 GND Device ground12 OUT2 O PWM output from channel 213 OUT1 O PWM output from channel 114 REF O Reference voltage output15 LINEUV I Input for line undervoltage comparator16 NC No connection
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TERMINAL DESCRIPTIONS
UCC28220-Q1
SLUS789 – MARCH 2008
VDD: VDD supplies power to the device and is monitored by the UVLO circuit, which ensures glitch-free startup.Until VDD reaches its UVLO threshold, the device remains in low-power mode, drawing approximately 150 µA ofcurrent and forcing pins SS, CS1, CS2, OUT1, and OUT2 to logic 0 states. If VDD falls below 8 V after reachingthe turn-on threshold, the device returns to the low-power state. The UVLO turn-on threshold is 10 V, and theturn-off threshold is 8 V.
CS1 and CS2: These two pins are the current-sense inputs to the device. The signals are internally level shiftedby 0.5 V before the signal reaches the PWM comparator. Internally, the slope compensation ramp is added tothis signal. The linear operating range on this input is 0 to 1.5 V. Also, this pin is pulled to ground each time itsrespective output goes low (i.e., OUT1 or OUT2).
SLOPE: This pin sets up a current used for the slope compensation ramp. A resistor to ground sets up a current,which is internally divided by 25 and applied to an internal 10-pF capacitor. Under normal operation, the dcvoltage on this pin is 2.5 V.
SS: A capacitor to ground sets up the soft-start time for the open-loop soft-start function. The source and sinkcurrent from this pin is equal to 3/7 of the oscillator charge current set by the resistor on the CHG pin. Thesoft-start capacitor is held low during UVLO and during a line overvoltage or undervoltage condition. Once anovervoltage or undervoltage fault occurs, the soft-start capacitor is discharged by a current equal to its chargingcurrent. The capacitor does not quickly discharge during faults. In this way, the controller has the ability torecover quickly from very short line transients. This pin can also be used as an enable/disable function.
CHG: A resistor from this pin to GND sets up the charging current of the internal C
T
capacitor used in theoscillator. This resistor, in conjunction with the resistor on the DISCHG pin, sets the operating frequency andmaximum duty cycle. Under normal operation, the dc voltage on this pin is 2.5 V.
DISCHG: A resistor from this pin to GND sets the discharge current of the internal C
T
capacitor used in theoscillator. This resistor, in conjunction with the resistor on the CHG pin, sets the operating frequency andmaximum duty cycle. Under normal operation, the dc voltage on this pin is 2.5 V.
OUT1 and OUT2: These output buffers are intended to interface with high-current MOSFET drivers. The outputdrive capability is approximately 33 mA and has an output impedance of 100 Ω. The outputs swing betweenGND and REF.
LINEOV: This pin is connected to a comparator and used to monitor the line voltage for an overvoltage condition.The typical threshold is 1.26 V.
LINEUV: This pin is connected to a comparator and used to monitor the line voltage for an undervoltagecondition. The typical threshold is 1.26 V.
LINEHYST: This pin is controlled by both the LINEOV and LINEUV pins. It controls the hysteresis values for boththe overvoltage and undervoltage line detectors.
REF: REF is a 3.3-V output used primarily as a source for the output buffers and other internal circuits. It isprotected from accidental shorts to ground. For improved noise immunity, it is recommended that the referencepin be bypassed with a minimum of 0.1- µF of capacitance to GND.
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APPLICATION INFORMATION
General
Line Overvoltage and Undervoltage
V1 +1.26 R1
(R2 )R3))1.26
(1)
V2 +1.26 (R1 )Rx)
Rx , where Rx +R4 Ŧ(R2 )R3)
(2)
V4 +1.26 (R1 )R2 )R3)
R3
(3)
V3 +V4 *1.26 ǒR1
R4Ǔ
(4)
UCC28220-Q1
SLUS789 – MARCH 2008
The device is composed of several housekeeping blocks, as well as two slope-compensated PWM channels thatare interleaved. The circuit is intended to run from an external VDD supply voltage between 8 V and 14 V. Otherfunctions contained in the device are supply UVLO, 3.3-V reference, accurate line overvoltage and undervoltagefunctions, a high speed programmable oscillator for both frequency and duty cycle, programmable slopecompensation, and programmable soft-start functions.
The UCC28220 is a primary-side controller for a two-channel interleaved power converter. The device iscompatible with forward or flyback converters, as long as a duty cycle clamp between 60% and 90% is required.Therefore, the active clamp forward and flyback converters, as well as the RCD and resonant reset forwardconverters, are compatible with this device. To ensure the two channels share the total converter output current,current-mode control with internal slope compensation is used. Slope compensation is user programmable via adedicated pin and can be set over a 50:1 range, ensuring good small-signal stability over a wide range ofapplications.
Three pins are provided to turn off the output drivers and reset the soft-start capacitor when the converter inputvoltage is outside a prescribed range. The undervoltage set point and undervoltage hysteresis are accurately setvia external resistors. The overvoltage set point is also accurately set via a resistor ratio, but the hysteresis isfixed by the same resistor that sets the undervoltage hysteresis.
Figure 1 and Figure 2 show a detailed functional diagram and operation of the undervoltage lockout (UVLO) andovervoltage lockout (OVLO) features. The equations for setting the thresholds defined in Figure 2 are:
The UVLO hysteresis and the OVLO hysteresis can then be calculated as V2 – V1 and V4 – V3, respectively. Byexamining the design equations it becomes apparent that the value of R4 sets the amount of hysteresis at boththresholds. By realizing this fact, the designer can then set the value of R4 based on the most critical hysteresisspecification either at high line or at low line. In most designs, the value of R4 is determined by the desiredamount of hysteresis around the UVLO threshold. As an example, consider a telecom power supply with thefollowing input UVLO and OVLO design specifications:•V1 = 32.0 V•V2 = 34.0 V•V3 = 83.0 V•V4 = 84.7 V
then
•R1 = 976 k Ω
•R2 = 24.9 k Ω
•R3 = 15.0 k Ω
and
•R4 = 604 k Ω
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V1 V2 V3 V4
LINE_GOOD
ENABLE
OFF
VDD
Reference
UCC28220-Q1
SLUS789 – MARCH 2008
Figure 1. Line UVLO and OVLO Functional Diagram
Figure 2. Line UVLO and OVLO Operation
Because the driver output impedance is high, the energy storage requirements on the VDD capacitor is low. Forimproved noise immunity, it is recommended that the VDD pin be bypassed with a minimum of 0.1 µF ofcapacitance to GND. In most typical applications, the bias voltage for the MOSFET drivers is also used as theVDD supply voltage for the chip. In the aforementioned applications, it is beneficial to add a low-value resistorbetween the bulk-storage capacitor of the driver and the VDD capacitor for the UCC28220. By adding a resistorin series with the bias supply, any noise that is present on the bias supply is filtered out before getting to theVDD pin of the controller.
For improved noise immunity, it is recommended that the reference pin (REF) be bypassed with a minimum of0.1 µF of capacitance to GND.
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Oscillator Operation and Maximum Duty Cycle Setpoint
FOSC +2 FOUT
(5)
DMAX(osc) +1*2 ǒ1*DMAX(out)Ǔ
(6)
RCHG +KOSC DMAX(osc)
FOSC
(7)
RDISCHG +KOSC ǒ1*DMAX(osc)Ǔ
FOSC
(8)
Soft Start
ISS +3
7 2.5
RCHG
(9)
Current Sense
Output Drivers
UCC28220-Q1
SLUS789 – MARCH 2008
The oscillator uses an internal capacitor to generate the time base for both PWM channels. The oscillator isprogrammable over a 200-kHz to 2-MHz frequency range with 20% to 80% maximum duty cycle range. Both thedead time and the frequency of the oscillator are divided by two to generate the PWM clock and off-timeinformation for each of the outputs. In this way, a 20% oscillator duty cycle corresponds to a 60% maximum dutycycle at each output, where an 80% oscillator duty cycle yields a 90% duty cycle clamp at each output.
The design equations for the oscillator and maximum duty cycle set point are given by:
Where
K
OSC
= 2.04 ×10
10
[Ω/s]F
OUT
= Switching frequency at the outputs of the chip (Hz)D
MAX(out)
= Maximum duty cycle limit at the outputs of the chipD
MAX(osc)
= Maximum duty cycle of the Oscillator for the desired maximum duty cycle at the outputsF
OSC
= Oscillator frequency for desired output frequency (Hz)R
CHG
= External oscillator resistor which sets the charge current ( Ω)R
DISCHG
= External oscillator resistor which sets the discharge current ( Ω)
A current is forced out of the SS pin, equal to 3/7 of the current set by R
CHG
, to provide a controlled rampvoltage. The current set by the R
CHG
resistor is equal to 2.5 V divided by R
CHG
. This ramp voltage overrides theduty cycle on the CTRL pin, allowing a controlled startup. Assuming the UCC28220 is biased on the primaryside, the soft start should be quite quick to allow the secondary bias to be generated, and the secondary sidecontrol can then take over. Once the soft-start time interval is complete, a closed-loop soft-start on the secondaryside can be executed.
Where
ISS = current which is sourced out of the SS pin during the soft-start time (A)
The current sense signals CS1 and CS2 are level shifted by 0.5 V and have the slope compensation rampsadded to them before being compared to the control voltage at the input of the PMW comparators. The amplitudeof the current sense signal at full load should be selected such that it is very close to the maximum controlvoltage, in order to limit the peak output current during short-circuit operation.
The UCC28220 is intended to interface with the UCC27323/4/5 family of MOSFET drivers. As such, the outputdrive capability is low (effectively 100 Ω), and the driver outputs swing between GND and REF.
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Slope Compensation
PWM
CS1
(4)
+
-
REF
CTRL
(8)
+
SLOPE
(5)
C_SC
OUT 1
TO RESET
of
PWM LATCH
ON OFF
2.5/(25*R_SLOPE) = I_SC
R_SLOPE
0.5V
10 pF
S1
S2
UCC28220-Q1
SLUS789 – MARCH 2008
The slope compensation circuit in the UCC28220 operates on a cycle-by-cycle basis. The two channels haveseparate slope compensation circuits. These are fabricated in precisely the same way so as current sharing isunaffected by the slope compensation circuit. For each channel, an internal capacitor is reset whenever thatchannel's output is off. At the beginning of the PWM cycle, a current is mirrored off the SLOPE pin into thecapacitor, developing an independent ramp. Since the two channel's ramps start when the channel's outputchanges from a low to high state, the ramps are thus interleaved. These internal ramps are added to the voltageson the current sense pins (CS1 and CS2) and the result forms an input to the PWM comparators.
Figure 3. Slope Compensation Detail for Channel 1 (Duplicate Matched Circuitry for Channel 2)
To ensure stability, the slope compensation circuit must add between 1/5 and 1 times the inductor downslope toeach of the current sense signals prior to being applied to the PWM comparator's input.
Determining the value for the slope compensation resistor:
Design Example
N
CT(p)
= 1 V
OUT
= 12 Np = 7 R
SENSE
= 5.23 F
S(out)
= 500000N
CT(s)
= 50 L
OUT
= 3.2 x 10
-6
Ns = 5 V
EA(cl)
= 1.98
Where
N
CT(p)
= Number of primary turns on the Current Transformer (Turns)N
CT(s)
= Number of Secondary turns on the current transformer (Turns)V
OUT
= Nominal output voltage of the converter (V)L
OUT
= Inductance value of each output inductor (H)N
P
= Number of primary turns on the main transformer (Turns)N
S
= Number of secondary turns on the main transformer (Turns)R
SENSE
= Value of current sense resistor on secondary of current sense transformer ( Ω)V
EA(cl)
= Maximum value of the E/A output voltage (V)F
S(out)
= Switching frequency of each output (Hz)
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NCT +
NCT(p)
NCT(s), Current Transformer Turns Ratio
(10)
SL(prime) +VOUT
LOUT Ns
Np, SL(prime) +2.679 Ańms
(11)
VSL(prime) +SL(prime) NCT RSENSE, VSL(prime) +2.281 Vńms
(12)
M+1.0
(13)
RSLOPE +104
ǒM VSL(prime) 10*6Ǔ, RSLOPE +35.556 kW
(14)
UCC28220
3
7
6
4
5
1
8
15
11
12
14
13
9
10
VDD
CS1
SLOPE
CS2
SS
CTRL
OV
UV
OUT1
OUT2
CHG
DISCHG
Bias
E/A
2
16
HYS
N/C
REF
GND
REF
1/2 UCC27424
1/2 UCC27424
CS1
CS2
VIN
VOUT
UCC28220-Q1
SLUS789 – MARCH 2008
Determine the correct value for the slope resistor, R
SLOPE
, to provide the desired amount of slope compensation.
1. Transform the secondary inductor downslope to the primary
2. Calculate the transformed slope voltage at sense resistor
3. Calculate the R
SLOPE
value to give a compensating ramp equal to the transformed slope voltage given inEquation 12
The desired ratio between the compensating ramp and the output inductor downslope ramp, transformed to theprimary sense resistor, is shown in Equation 14 .
Figure 4. Interleaved Flyback Application Circuit
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UCC28220
3
7
6
4
5
1
8
15
11
12
14
13
9
10
VDD
CS1
SLOPE
CS2
SS
CTRL
OV
UV
OUT1
OUT2
CHG
DISCHG
Bias
E/A
2
16
HYS
N/C
REF
GND
1/2 UCC27424
1/2 UCC27424
CS2
CS1
VIN
VOUT
UCC28220-Q1
SLUS789 – MARCH 2008
Figure 5. Interleaved Boost Application Circuit
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TYPICAL CHARACTERISTICS
T – Temperature – °C
J
-50 -25 0 25 50 75 100 125
V – UVLO Thresholds – V
UVLO
UVLO on threshold
UVLO off threshold
13.5
12.5
11.5
10.5
9.5
8.5
7.5
I– Quiescent Current – mA
DD
02 4 6 8 10 12 14
0.0
0.5
1.0
1.5
2.0
2.5
3.0
16
3.5
4.0
VDD – Supply Voltage – V
T – Temperature – °C
J
V – Reference Voltage – V
REF
No load
Load
-50 -25 0 25 50 75 100 125
3.45
3.40
3.35
3.30
3.25
3.20
3.15
V – T
th rip Threshold – V
-50 -25 0 25 50 75 100
1.230
1.235
1.240
1.245
1.250
1.255
1.260
125
1.265
1.270
LINEOV
LINEUV
T – Temperature – °C
J
UCC28220-Q1
SLUS789 – MARCH 2008
UVLO THRESHOLDS QUIESCENT CURRENTvs vsTEMPERATURE SUPPLY VOLTAGE
Figure 6. Figure 7.
REFERENCE VOLTAGE LINEOV AND LINEUV THRESHOLDSvs vsTEMPERATURE TEMPERATURE
Figure 8. Figure 9.
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SLOPE – Slope Compensation – mV/µs
R – Slope Programming Resistor –
SLOPE W
106
105
104
103
10 100 1000
SLOPE – Slope Compensation – mV/µs
R = 75 k
SLOPE W
T – Temperature – °C
J
-50 -25 0 25 50 75 100 125
CS1 = 0 V
CS1 = 0.5 V
230
225
220
215
210
205
200
195
190
185
180
175
170
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Fall Time
Rise Time
tand t – Rise and Fall Times – ns
r f
T – Temperature – °C
J
-50 -25 0 25 50 75 100 125
-10
-8
-6
-4
-2
0
2
4
6
8
10
-50 -25 0 25 50 75 100 125
T – Temperature – °C
J
Mismatch – %
R = 75 k
CS0 = 0 V
CS1 = 0 V
SLOPE W
UCC28220-Q1
SLUS789 – MARCH 2008
TYPICAL CHARACTERISTICS (continued)
SLOPE COMPENSATION PROGRAMMING RESISTORvs vsTEMPERATURE SLOPE COMPENSATION
Figure 10. Figure 11.
CHANNEL 1 AND CHANNEL 2 SLOPE MATCHING RISE AND FALL TIMEvs vsTEMPERATURE TEMPERATURE (C
L
= 50 pF
Figure 12. Figure 13.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): UCC28220-Q1
www.ti.com
T – Temperature – °C
J
-50 -25 0 25 50 75 100 125
V – Output Voltage – V
O
I = 10 mA
OUT
V – V (V )
REF OUT OH
VOL
R = 10.2 k
CHG W
T – Temperature – °C
J
I – Charge Current – µA
SSCH
-50 -25 0 25 50 75 100 125
-70
-80
-90
-100
-110
-120
-130
70
80
90
100
110
120
130
I – Charge Current –
SSdis µA
T – Temperature – °C
J
-50 -25 0 25 50 75 100 125
R ,
CHRG R – Resistance –
DISRG W
fS– Switching Frequency – Hz
10k 100k 1M
1k
10k
100k
10M
1M
R = R
CHRG DISRG
DMAX = 75%
UCC28220-Q1
SLUS789 – MARCH 2008
TYPICAL CHARACTERISTICS (continued)
V
OH
AND V
OL
SOFT-START CHARGE CURRENTvs vsTEMPERATURE TEMPERATURE
Figure 14. Figure 15.
SOFT-START DISCHARGE CURRENT PROGRAMMING RESISTORSvs vsTEMPERATURE SWITCHING FREQUENCY
Figure 16. Figure 17.
16 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): UCC28220-Q1
www.ti.com
T – Temperature – °C
J
DC – Duty Cycle – %
R = R = 10.2 k
CHRG DISRG W
-50 -25 0 25 50 75 100 125
77
76
75
74
73
T – Temperature – °C
J
-50 -25 0 25 50 75 100 125
f – Oscillator Frequency – kHz
s
550
540
530
520
510
500
490
480
470
460
450
R = R = 10.2 k
CHRG DISRG W
CSx – Peak Voltage – V
0 0.2 0.4 0.6 0.8 1.0 1.2
0
10
20
30
40
50
60
1.4
70
80
90
100
1.6 1.8
105°C
25°C
–40°C
CSx to OUTx Delay – ns
UCC28220-Q1
SLUS789 – MARCH 2008
TYPICAL CHARACTERISTICS (continued)
OSCILLATOR FREQUENCY PROGRAMMABLE MAX DUTY CYCLEvs vsTEMPERATURE TEMPERATURE
Figure 18. Figure 19.
CSx TO OUTx DELAY
vsCSx PEAK VOLTAGE
Figure 20.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): UCC28220-Q1
www.ti.com
Related Products
UCC28220-Q1
SLUS789 – MARCH 2008
DEVICE DESCRIPTION PACKAGE OPTIONS
UCC27323/4/5 Dual 4-A High-Speed Low-Side MOSFET Drivers SOIC-8, PowerPAD™ MSOP-8, PDIP-8UCC27423/4/5 Dual 4-A High-Speed Low-Side MOSFET Drivers with Enable SOIC-8, PowerPAD MSOP-8, PDIP-8TPS2811/12/13 Dual 2.4-A High-Speed Low-Side MOSFET Drivers SOIC-8, TSSOP-8, PDIP-8UC3714/15 Dual 2.4-A High-Speed Low-Side MOSFET Drivers SOIC-8, PowerSOIC-14, PDIP-8
18 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): UCC28220-Q1
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
UCC28220QDRQ1 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC28220QPWRQ1 ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UCC28220-Q1 :
•Catalog: UCC28220
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
PACKAGE OPTION ADDENDUM
www.ti.com 2-Jul-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
UCC28220QDRQ1 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
UCC28220QPWRQ1 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UCC28220QDRQ1 SOIC D 16 2500 367.0 367.0 38.0
UCC28220QPWRQ1 TSSOP PW 16 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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