Rev. 4235C–8051–08/03
1
Features
•80C52 Compatible
– 8051 Instruction Compatible
– Six 8-bit I/O Ports (64 Pins or 68 Pins Versions)
– Four 8-bit I/O Ports (44 Pins Version)
– Three 16-bit T ime r/ Counte rs
– 256 Bytes Scratch Pad RAM
– 9 Interrupt Sources with 4 Priority Levels
•Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply
•ISP (In-System Programming) Using Standard VCC Power Supply
•Boot ROM Contains Low Level Flash Programming Routines and a Default Serial
Loader
•High-speed Architecture
–In Standard Mode:
40 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)
60 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
–In X2 mode (6 Clocks/machine cycle)
20 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)
30 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
•64K Bytes On-chip Flash Program/Data Memory
–Byte and Page (128 Bytes) Erase and Write
–100k Write Cycles
•On-chip 1792 bytes Expanded RAM (XRAM)
–Software Selectable Size (0, 256, 512, 768, 1024, 1792 Bytes)
–768 Bytes Selected at Reset for T89C51RD2 Compatibility
•On-chip 2048 Bytes EEPROM Block for Data Storage (AT89C51ED2 Only)
–100K W rite Cycles
•Dual Data Pointer
•Variable Length MOVX for Slow RAM/Peripherals
•Improved X2 Mode with Independent Selection for CPU and Each Peripheral
•Keyboard Interrupt Interface on Port 1
•SPI Interface (Master/Slave Mode)
•8-bit Clock Prescaler
•16-bit Programma ble Counte r Array
–High Speed Output
–Compare/Capture
–Pulse Width Modulator
–Watchdog Timer Capabilities
•Asynchronous Port Reset
•Full-duplex Enhanced UART with Dedicated Internal Baud Rate Generator
•Low EMI (Inhibit ALE)
•Hardware Watchdog Timer (One-time Enabled with Reset-Out), Power-off Flag
•Power Control Modes: Idle Mode, Power-down Mode
•Single Range Power Supply: 2.7V to 5.5V
•Industrial Temperature Range (-40 to +85°C)
•Packages: PLCC44, VQFP44, PLCC68, VQFP64, DIL40, PDIL40
Description
AT89C51RD2/ED2 is high performance CMOS Flash version of the 80C51 CMOS sin-
gle chip 8-bit microcontroller . It contains a 64-Kbyte Flash memory block for code and
for data.
The 64- Kbytes F lash memo ry can be program med eith er in parall el mode or in serial
mode with the ISP capability or with software. The programming voltage is internally
generated from the standard VCC pin .
8-bit Flash
Microcontroller
AT89C51RD2
AT89C51ED2
2AT89C51RD2/ED2 4235C–8051–08/03
The AT89C51RD2/ED2 retains all of the features of the Atmel 80C52 with 256 bytes of internal RAM, a 9-source 4-level
interrupt controller and three timer/counters.
The AT89C51ED2 provides 2048 bytes of EEPROM for nonvolatile data storage.
3
AT89C51RD2/ED2
4235C–8051–08/03
In addition, the AT89C51RD2/ED2 has a Programmable Counter Array, an XRAM of
1792 bytes, a Hardware Watchdog Timer, SPI interface, Keyboard, a more versatile
serial channel that fac ilitates m ultiproce ssor com munication (EUART) and a sp eed
improvement mechanism (X2 Mode).
The ful ly static de sign of the AT8 9C51RD2/ ED2 allows to r educe syst em power con-
sumption by bring ing the c lock freque ncy do wn to any value, inc luding DC, wi thout lo ss
of data.
The AT89C51RD2/ED2 has 2 software-selectable modes of reduced activity and an 8-
bit clock prescaler for further reduction in power consumption. In the Idle mode the CPU
is frozen whi le the peri phe ra ls and th e int erru pt s ystem are still operating. In the Power-
down mode the RAM is saved and all other functions are inoperative.
The add ed features of the A T89C51RD2/E D2 make it more po werful for a pplications
that need pulse wi dth modulation, high spee d I/O and counting cap abilities such as
alarms, motor control, corded phones, and smart card readers.
Table 1. Memory Size and I/O Pins
Note: 1. For PLCC68, VQFP64 and DIL40 packages, please contact Atmel sales office for
availability.
Package Flash (Bytes) XRAM (Bytes) Total RAM (Bytes) I/O
PLCC44/VQFP44/DIL40 64K 1792 2048 34
PLCC68/VQFP64(1) 64K 1792 2048 50
4AT89C51RD2/ED2 4235C–8051–08/03
Block Diagram
Figure 1. Block Diagram
Time r 0 INT
RAM
256x8
T0
T1 RxD
TxD
WR
RD
EA
PSEN
ALE/
XTALA2
XTALA1 EUART
CPU
Time r 1
INT1
Ctrl
INT0
(2)
(2)
C51
CORE
(2) (2) (2) (2)
Port 0
P0
Port 1
Port 2
Port 3
P1
P2
P3
XRAM
1792 x 8
IB-bus
PCA
RESET
PROG
Watch
-dog
PCA
ECI
VSS
VCC
(2)(2) (1)
(1): Alternate function of Port 1
(2): Alternate function of Port 3
(1)
Timer2
T2EX
T2
(1) (1)
Flash
64K x 8
Keyboard
(1)
Keyboard
MISO
MOSI
SCK
SS
Port4
P4
(1) (1)(1)(1)
BOOT
2K x 8
ROM
Regulator
POR / PFD
Port 5
P5
Parallel I/O Ports &
External Bus SPI
EEPROM*
2K x 8
(AT89C51ED2)
5
AT89C51RD2/ED2
4235C–8051–08/03
SFR Mapping The Special Function Registers (SFRs) of the AT89C51RD2/ED2 fall into the following
categories:
•C51 core registers: ACC, B, DPH, DPL, PSW, SP
•I/O port registers: P0, P1, P2, P3, PI2
•Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2,
RCAP2L, RCAP2H
•Serial I/O port registers: SADDR, SADEN, SBUF, SCON
•PCA (Programmable Counter Array) registers: CCON, CCAPMx, CL, CH, CCAPxH,
CCAPxL (x: 0 to 4)
•Power and clock control registers: PCON
•Hardware Watchdog Timer registe rs: WDTR ST, WDTPRG
•Interrupt system registers: IE0, IPL0, IPH0, IE1, IPL1, IPH1
•Keyboard Interface registers: KBE, KBF, KBLS
•SPI registers: SPCON, SPSTR, SPDAT
•BRG (Baud Rate Generator) registers: BRL, BDRCON
•Clock Prescaler register: CKRL
•Others: AUXR, AUXR1, CKCON0, CKCON1
6AT89C51RD2/ED2 4235C–8051–08/03
Table 2. C51 Core SFRs
Mnemonic AddName 76543210
ACC E0h Accumulator
BF0h B Register
PSW D0h Program St atus Word CY AC F0 RS1 RS0 OV F1 P
SP 81h St ack Pointer
DPL 82h Data Pointer Low Byte
DPH 83h Data Pointer High Byte
Table 3. System Management SFRs
Mnemonic AddName 76543210
PCON 87h P ower Control SMOD1 SMOD0 - - GF1 GF0 PD IDL
AUXR 8Eh Auxiliary Register 0 DPU - M0 XRS2 XRS1 XRS0 EXTRAM AO
AUXR1 A2h Auxiliary Register 1 - - ENBOOT -GF30 -DPS
CKRL97hClock Reload Register --------
Table 4. In terr upt S FRs
Mnemonic AddName 76543210
IEN0 A8h Interrupt Enab le Control 0 EA EC ET2 ES ET1 EX1 ET0 EX0
IEN1 B1hInterrupt Enable Control 1 -----ESPI KBD
IPH0 B7h Interrupt Priority Control High 0 - P PCH PT2H PHS PT1H PX 1H PT0H PX0H
IPL0 B8h Interrupt Priority Control Low 0 - PPCL PT2L PLS PT1L PX1L PT0L PX0L
IPH1 B3hInterrupt Priority Control High 1-----SPIH KBDH
IPL1 B2hInterrupt Priority Control Low 1-----SPIL KBDL
Table 5. Port SFRs
Mnemonic AddName 76543210
P0 80h 8-bit Port 0
P1 90h 8-bit Port 1
P2 A0h 8 -bit Port 2
P3 B0h 8 -bit Port 3
P4 C0h 8-bit Port 4
P5 D8h 4-bit Port 5
7
AT89C51RD2/ED2
4235C–8051–08/03
Table 6. Timer SFRs
Mnemonic AddName 76543210
TCON 88h Timer/Counter 0 and 1 Control T F1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
TMOD 89h Timer/Counter 0 and 1 Modes GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00
TL0 8Ah Timer/Counter 0 Low Byte
TH0 8Ch Timer/Counter 0 High Byte
TL1 8Bh Timer/Counter 1 Low Byte
TH1 8Dh T imer/Counter 1 High Byte
WDTRST A6h WatchDog Timer Reset
WDTPRGA7hWatchDog Timer Program -----WTO2WTO1WTO0
T2CON C8h Timer/Counter 2 control TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#
T2MOD C9h Timer/Counter 2 Mode ------T2OEDCEN
RCAP2H CBh Ti mer/Counter 2 Reload/Capture
High Byte
RCAP2L CAh Ti mer/Counter 2 Reload/Capture
Low Byte
TH2 CDh Timer/Counter 2 High Byte
TL2 CCh Timer/Counter 2 Low Byte
Table 7. P C A SFR s
Mnemo
-nicAddName 76543210
CCON D8h PCA Timer/Counter Control CF CR CCF4 CCF3 CCF2 CCF1 CCF0
CMOD D9h PCA Timer/Counter Mode CIDL W DT E CPS1 CPS0 ECF
CL E9h PCA Timer/Counter Low Byte
CH F9h PCA Timer/Counter High Byte
CCAPM0
CCAPM1
CCAPM2
CCAPM3
CCAPM4
DAh
DBh
DCh
DDh
DEh
PCA Timer/Counter Mode 0
PCA Timer/Counter Mode 1
PCA Timer/Counter Mode 2
PCA Timer/Counter Mode 3
PCA Timer/Counter Mode 4
ECOM0
ECOM1
ECOM2
ECOM3
ECOM4
CAPP0
CAPP1
CAPP2
CAPP3
CAPP4
CAPN0
CAPN1
CAPN2
CAPN3
CAPN4
MAT0
MAT1
MAT2
MAT3
MAT4
TOG0
TOG1
TOG2
TOG3
TOG4
PWM0
PWM1
PWM2
PWM3
PWM4
ECCF0
ECCF1
ECCF2
ECCF3
ECCF4
CCAP0H
CCAP1H
CCAP2H
CCAP3H
CCAP4H
FAh
FBh
FCh
FDh
FEh
PCA Compare Capture Module 0 H
PCA Compare Capture Module 1 H
PCA Compare Capture Module 2 H
PCA Compare Capture Module 3 H
PCA Compare Capture Module 4 H
CCAP0H7
CCAP1H7
CCAP2H7
CCAP3H7
CCAP4H7
CCAP0H6
CCAP1H6
CCAP2H6
CCAP3H6
CCAP4H6
CCAP0H5
CCAP1H5
CCAP2H5
CCAP3H5
CCAP4H5
CCAP0H4
CCAP1H4
CCAP2H4
CCAP3H4
CCAP4H4
CCAP0H3
CCAP1H3
CCAP2H3
CCAP3H3
CCAP4H3
CCAP0H2
CCAP1H2
CCAP2H2
CCAP3H2
CCAP4H2
CCAP0H1
CCAP1H1
CCAP2H1
CCAP3H1
CCAP4H1
CCAP0H0
CCAP1H0
CCAP2H0
CCAP3H0
CCAP4H0
CCAP0L
CCAP1L
CCAP2L
CCAP3L
CCAP4L
EAh
EBh
ECh
EDh
EEh
PCA Compare Capture Mod ule 0 L
PCA Compare Capture Mod ule 1 L
PCA Compare Capture Mod ule 2 L
PCA Compare Capture Mod ule 3 L
PCA Compare Capture Mod ule 4 L
CCAP0L7
CCAP1L7
CCAP2L7
CCAP3L7
CCAP4L7
CCAP0L6
CCAP1L6
CCAP2L6
CCAP3L6
CCAP4L6
CCAP0L5
CCAP1L5
CCAP2L5
CCAP3L5
CCAP4L5
CCAP0L4
CCAP1L4
CCAP2L4
CCAP3L4
CCAP4L4
CCAP0L3
CCAP1L3
CCAP2L3
CCAP3L3
CCAP4L3
CCAP0L2
CCAP1L2
CCAP2L2
CCAP3L2
CCAP4L2
CCAP0L1
CCAP1L1
CCAP2L1
CCAP3L1
CCAP4L1
CCAP0L0
CCAP1L0
CCAP2L0
CCAP3L0
CCAP4L0
8AT89C51RD2/ED2 4235C–8051–08/03
Table 8. Serial I/O Port SFRs
Mnemonic AddName 76543210
SCON 98h Serial Control FE/SM0 SM1 SM2 REN TB8 RB8 TI RI
SBUF 99h Serial Data Buffer
SADEN B9h Slave Address Mask
SADDR A9h Slave Address
BDRCON 9Bh Baud Rate Control BRR TBCK RBCK SPD SRC
BRL 9Ah Baud Rate Reload
Table 9. S PI Contro ll er SFRs
Mnemonic AddName 76543210
SPCON C3h SPI Control SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0
SPSTA C4h SPI Status SPIF WCOL SSERR MODF
SPDAT C5h SPI Data SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0
Table 10. Keyboard Interface SFRs
Mnemonic AddName 76543210
KBLS 9Ch Keyboard Level Selector KBLS7 KBLS6 KBLS5 KBLS4 KBLS3 KBLS2 KBLS1 KBLS0
KBE 9Dh Keyboard Input Enable KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0
KBF 9Eh Keyboard Flag Register KBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBF0
Table 11. EEPROM data Memory SFR (AT89C51ED2 only)
Mnemonic AddName 76543210
EECON EEPROM Data Control EEE EEBUSY
9
AT89C51RD2/ED2
4235C–8051–08/03
Table 12 shows all SFRs with their address and their reset value.
Table 12. SFR Mapping
Bit
Addressable Non Bit Addressable
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
F8h PI2
XXXX XX11 CH
0000 0000 CCAP0H
XXXX XXXX CCAP1H
XXXX XXXX CCAP2H
XXXX XXXX CCAP3H
XXXX XXXX CCAP4H
XXXX XXXX FFh
F0h B
0000 0000 F7h
E8h P5 bit
addressable
1111 1111
CL
0000 0000 CCAP0L
XXXX XXXX CCAP1L
XXXX XXXX CCAP2L
XXXX XXXX CCAP3L
XXXX XXXX CCAP4L
XXXX XXXX EFh
E0h ACC
0000 0000 E7h
D8h CCON
00X0 0000 CMOD
00XX X000 CCAPM0
X000 0000 CCAPM1
X000 0000 CCAPM2
X000 0000 CCAPM3
X000 0000 CCAPM4
X000 0000 DFh
D0h PSW
0000 0000 FCON
XXXX 0000 EECON
xxxx xx00 D7h
C8h T2CON
0000 0000 T2MOD
XXXX XX00 RCAP2L
0000 0000 RCAP2H
0000 0000 TL2
0000 0000 TH2
0000 0000 CFh
C0h P4
1111 1111 SPCON
0001 0100 SPSTA
0000 0000 SPDAT
XXXX XXXX
P5 byte
Addressable
1111 1111 C7h
B8h IPL0
X000 000 SADEN
0000 0000 BFh
B0h P3
1111 1111 IEN1
XXXX X000 IPL1
XXXX X000 IPH1
XXXX X111 IPH0
X000 0000 B7h
A8h IEN0
0000 0000 SADDR
0000 0000 CKCON1
XXXX XXX0 AFh
A0h P2
1111 1111 AUXR1
0XXX X0X0 WDTRST
XXXX XXXX WDTPRG
XXXX X000 A7h
98h SCON
0000 0000 SBUF
XXXX XXXX BRL
0000 0000 BDRCON
XXX0 0000 KBLS
0000 0000 KBE
0000 0000 KBF
0000 0000 9Fh
90h P1
1111 1111 CKRL
1111 1111 97h
88h TCON
0000 0000 TMOD
0000 0000 TL0
0000 0000 TL1
0000 0000 TH0
0000 0000 TH1
0000 0000 AUXR
XX00 1000 CKCON0
0000 0000 8Fh
80h P0
1111 1111 SP
0000 0111 DPL
0000 0000 DPH
0000 0000 PCON
00X1 0000 87h
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
reserved
10 AT89C51RD2/ED2 4235C–8051–08/03
Pin Configurations
Figure 2. Pin Configurations
43 42 41 40 3944 38 37 36 35 34
P1.4/CEX1
P1.0/T2
P1.1/T2EX/SS
P1.3/CEX0
P1.2/ECI
VCC
P0.0/AD0
P0.2/AD2
P0.3/AD3
P0.1/AD1
P0.4/AD4
P0.6/AD6
P0.5/AD5
P0.7/AD7
ALE/PROG
PSEN
EA
P2.7/A15
P2.5/A13
P2.6/A14
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P1.7/CEX4/MOSI
RST
P3.0/RxD
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
NIC*
1213 17161514 201918 2122
33
32
31
30
29
28
27
26
25
24
23
AT89C51RD2/ED2
1
2
3
4
5
6
7
8
9
10
11
VQFP44 1.4
NIC*
NIC*
NIC*
PLCC44
AT89C51RD2/ED2
NIC*
NIC*
NIC*
PDIL40
P1.7CEX4/MOSI
P1.4/CEX1
RST
P3.0/RxD
P3.1/TxD
P1.3CEX0
1
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS P2.0/AD8
P2.1/AD9
P2.2/AD10
P2.3/AD11
P2.4/AD12
P0.4/AD4
P0.6/AD6
P0.5/AD5
P0.7/AD7
ALE/PROG
PSEN
EA
P2.7/AD15
P2.5/AD13
P2.6/AD14
P1.0/T2
P1.2/ECI
P1.1/T2EX/SS VCC
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
AT89C51ED2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
18 19 23222120 262524 27 28
5 4 3 2 1 6 44 43 42 41 40
P1.4/CEX1
P1.0/T2
P1.1/T2EX/SS
P1.3/CEX0
P1.2/ECI
VCC
P0.0/AD0
P0.2/AD2
P0.1/AD1
P0.4/AD4
P0.6/AD6
P0.5/AD5
P0.7/AD7
ALE/PROG
PSEN
EA
P2.7/A15
P2.5/A13
P2.6/A14
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P1.7/CEx4/MOSI
RST
P3.0/RxD
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P0.3/AD3
NIC*
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
11
AT89C51RD2/ED2
4235C–8051–08/03
50
49
48
47
44
45
46
P4.5
P3.7/RD
XTAL2
XTAL1
P4.4
P3.6/WR
P4.3
NIC
NIC
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
37
38
39
40
41
42
43
AT89C51RD2/ED2
PLCC68
P0.4/AD4
P5.4
P5.3
P0.5/AD5
P0.6/AD6
NIC
P0.7/AD7
EA
NIC
ALE
P1.6/CEX3/SCK
P1.7/CEX4/MOSI
RST
NIC
NIC
NIC
P3.0/RxD
NIC
NIC
P1.5/CEX2/MISO
60
59
58
57
56
55
54
53
51
52
10
11
12
13
14
15
16
17
19
18
27
28
29
30
31
32
33
34
35
36
9
8
7
6
5
3
2
1
68
P5.0
P2.4/A12
P2.3/A11
P4.7
P2.2/A10
P4.6
P2.0/A8
P2.1/A9
NIC
VSS
P5.5
P0.3/AD3
P0.2/AD2
P5.6
P0.1/AD1
P0.0/AD0
P5.7
VCC
NIC
P1.0/T2
4
PSEN
NIC
P2.7/A15
P2.6/A14
P5.2
P5.1
P2.5/A13
67
65
64
63
62
61
66
20
21
22
23
26
25
24
P4.0
P1.1/T2EX/SS
P1.2/ECI
P1.3/CEX0
P4.1
P1.4/CEX1
P4.2
NIC: Not Internaly Connected
54
53
52
51
50
49
AT89C51RD2/ED2
VQFP64
P0.4/AD4
P5.4
P5.3
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
NIC
ALE
PSEN#
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P1.7/A17/CEX4/MOSI
RST
NIC
NIC
NIC
P3.0/RxD
NIC
P4.2
48
47
46
45
44
43
42
41
39
40
1
2
3
4
5
6
7
8
10
9
17
18
19
20
21
22
23
24
25
26
64
63
62
61
60
59
58
57
56
55
P2.4/A12
P2.3/A11
P4.7
P2.2/A10
P2.1/A9
NIC
P4.6
P2.0/A8
VSS
P4.5
P5.5
P0.3/AD3
P0.2/AD2
P5.6
P0.1/AD1
P0.0/AD0
P5.7
VCC
NIC
P1.0/T2 11
12
13
16
15
14
P4.0
P1.1/T2EX/SS
P1.2/ECI
P1.3/CEX0
P4.1
P1.4/CEX1
38
37
36
33
34
35 P3.7/RD
XTAL2
XTAL1
P4.4
P3.6/WR
P4.3
NIC
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
27
28
29
30
31
32
P2.7/A15
P2.6/A14
P5.2
P5.1
P2.5/A13
P5.0
12 AT89C51RD2/ED2 4235C–8051–08/03
Table 13. Pin Description
Mnemonic
Pin Number Type Na m e a n d Func tionPLCC44 VQFP44 PLCC68 VQFP64 PDIL40
VSS 22 16 51 40 20 I Ground: 0V reference
VCC 44 38 17 8 40 I Power Supply: This is the power supply voltage for normal, idle and
power-down operation
P0.0 - P0.7 43 - 36 37 - 30 15, 14,
12, 11,
9,6, 5, 3
6, 5, 3,
2, 64,
61,60,59 I/O
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that
have 1s written to them float and can be used as high impedance inputs.
Port 0 must be polarized to VCC or VSS in order to prevent any parasitic
current consumption. Port 0 is also the multiplexed low-order address
and data bus during access to external program and data memory . In this
application, it uses strong internal pull-up when emitting 1s. Port 0 also
inputs the code bytes during EPROM programming. External pull-ups are
required during program verification during which P0 outputs the code
bytes.
32-39
P1.0 - P1.7 2 - 9 40 - 44
1 - 3
19, 21,
22, 23,
25, 27,
28, 29
10, 12,
13, 14,
16, 18,
19, 20
1-8 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1
pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 1 pins that are externally
pulled low will source current because of the int ernal pull-ups. Port 1 also
receives the low-order address byte during memory program ming and
verification.
Alternate functions for AT89C51RD2/ED2 Port 1 include:
2401910 1I/OP1.0: Input/Output
I/O T2 (P1.0): Ti mer/Counter 2 external count input/Clockout
3412112 2I/OP1.1: Input/Output
IT2EX: Timer/Counter 2 Reload/Capture/Direction Control
ISS: SPI Slave Select
4422213 3I/OP1.2: Input/Output
IECI: External Clock for the PCA
5432314 4I/OP1.3: Input/Output
I/O CEX0: Capture/Compare External I/O for PCA module 0
6442516 5I/OP1.4: Input/Output
I/O CEX1: Capture/Compare External I/O for PCA module 1
7 1 27 18 6 I/O P1.5: Input/Output
I/O CEX2: Capture/Compare External I/O for PCA module 2
I/O MISO: SPI Master Input Slave Output line
When SPI is in master mode, MISO receives data from the slave periph-
eral. When SPI is in slave mode, MISO outputs data to the master con-
troller.
8 2 28 19 7 I/O P1.6: Input/Output
I/O CEX3: Capture/Compare External I/O for PCA module 3
I/O SCK: SPI Seri a l Cloc k
13
AT89C51RD2/ED2
4235C–8051–08/03
9 3 29 20 8 I/O P1.7: Input/Output:
I/O CEX4: Capture/Compare External I/O for PCA module 4
I/O MOSI: SPI Master Output Slave Input line
When SPI is in master mode, MOSI outputs data to the slave peripheral.
When SPI is in slave mode, MOSI receives data from the master control-
ler.
XTALA1 21 15 49 38 19 I XTALA 1: Input to the inverting oscillator amplifier and input to the inter-
nal clock generator circuits.
XTALA2 20 14 48 37 18 O XTALA 2: Output from the inverting oscillator amplifier
P2.0 - P2.7 24 - 31 18 - 25
54, 55,
56, 58,
59, 61,
64, 65
43, 44,
45, 47,
48, 50,
53, 54
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2
pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 2 pins that are externally
pulled low will source current because of the internal pull-ups. Port 2
emits the high-order address byte during fetches from external program
memory and during accesses to external data memory that use 16-bit
addresses (MOVX @DPTR).In this application, it uses strong internal
pull-ups emitting 1s. During accesses to external data memory that use
8-bit addresses (MOVX @R i), port 2 emits the contents of the P2 SFR.
21-28
P3.0 - P3.7 11 ,
13 - 19 5,
7 - 13
34, 39,
40, 41,
42, 43,
45, 47
25, 28,
29, 30,
31, 32,
34, 36
10-17 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 3 pins that are externally
pulled low will source current because of the int ernal pull-ups. Port 3 also
serves the special features of the 80C51 family, as listed below.
11 5 34 25 10 I RXD (P3.0): Serial input port
13 7 39 28 11 O TXD (P3. 1): Serial output port
14 8 40 29 12 I INT0 (P3.2): Ex te r nal inte r rupt 0
15 9 41 30 13 I INT1 (P3.3): Ex te r nal inte r rupt 1
16 10 42 31 14 I T0 (P3.4): Ti mer 0 external input
17 11 43 32 15 I T1 (P3.5): Timer 1 external input
18 12 45 34 16 O WR (P3.6): External data mem ory write strobe
19 13 47 36 17 O RD (P3.7): External data memory read st robe
P4.0 - P4.7 --
20, 24,
26, 44,
46, 50,
53, 57
11, 15,
17,33,
35,39,
42, 46
-I/O
Port 4: Port 4 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 3 pins that are externally
pulled low will source current because of the internal pull-ups.
P5.0 - P5.7 --
60, 62,
63, 7, 8,
10, 13,
16
49, 51,
52, 62,
63, 1, 4,
7
-I/O
Port 5: Port 5 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 3 pins that are externally
pulled low will source current because of the internal pull-ups.
RST 10 4 30 21 9 I
Reset: A high on this pin for two machine cycles while the oscillator is
running, resets the device. An internal diffused resistor to VSS permits a
power-on reset using only an external capacitor to VCC. This pin is an out-
put when the hardware watchdog forces a system rese t.
Table 13. Pin Description (Continued)
Mnemonic
Pin Number Type Na m e a n d Func tionPLCC44 VQFP44 PLCC68 VQFP64 PDIL40
14 AT89C51RD2/ED2 4235C–8051–08/03
ALE/PRO
G33 27 68 56 30 O (I) Address Latch Enable/Program Pulse: Output pulse for latching the
low byte of the address during an access to external memory. In normal
operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the
oscillator frequency, and can be used for external timing or clocking. Note
that one ALE pulse is skipped during each access to external data mem-
ory. This pin is also the program pulse input (PROG) during Flash pro-
gramming. ALE can be disabled by setting SFR’s AUXR.0 bit. With this
bit set, ALE will be inactive during internal fetches.
PSEN 32 26 67 55 29 O Program Strobe ENable: The read strobe to external program memory.
When executing code from the external program memory, PSEN i s a cti -
vated twice each machine cycle, except that two PSEN activations are
skipped during each access to external data memory. PSEN is not acti-
vated during fetches from internal program memory.
EA 35 29 2 58 31 I External Access Enable: EA must be externally held low to enable the
device to fetch code from external program memory locations 0000H to
FFFFH. If security level 1 is programmed, EA will be internally latched on
Reset.
Table 13. Pin Description (Continued)
Mnemonic
Pin Number Type Na m e a n d Func tionPLCC44 VQFP44 PLCC68 VQFP64 PDIL40
15
AT89C51RD2/ED2
4235C–8051–08/03
Port Types AT89C51RD2/ED2 I/O ports (P1, P2, P3, P4, P5) implement the quasi-bidirectional out-
put that is common on the 80C51 and most of its derivatives. This output typ e can be
used as both an input and output without the need to reconfigure the port. This is possi-
ble becau se when the por t outputs a logic hi gh, it i s weakly driven, allowi ng an ex ternal
device to pull the pin low. When the pin is pulled low, it is driven strongly and able to sink
a fairly large current. These features are somewhat similar to an open drain output
except that there are three pull-up transistors in the quasi-bidirectional output that serve
differe nt purposes . One of these pu ll-ups, c alled the "wea k" pull-u p, is turned on wh en-
ever th e port latch fo r the pin c ontains a lo gic 1 . The weak p ull-up sour ces a very smal l
current that will pull the pin high if it is left floating. A second pull-up, called the "medium"
pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is
also at a l ogic 1 leve l. This pul l-up pro vides the pr imary s ource curr ent for a quas i-bidi-
rectional pin that is outputting a 1. If a pin that has a logic 1 on it is pulled low by an
exter nal devic e, the med ium pull -up turn s off, an d only the wea k pull-u p remai ns on. In
order to pull the pin low under these c onditions, the ex ternal devic e has to sink enoug h
current to overpower the medium pull-up and take the voltage on the port pin below its
input thres hol d.
The third pull-up is referred to as the "strong" pull-up. This pull-up is used to speed up
low-to-high transitions on a quasi-bidirectional port pin when the port latch changes from
a log ic 0 to a log ic 1. W hen thi s o ccur s, t he str ong pul l-up tur ns on f or a bri ef tim e, two
CPU clocks, in order to pull the port pin high quickly. Then it turns off again.
The DPU bit ( bit 7 in A UX R regis te r) al lo ws to dis ab le t he pe rm ane nt wea k p ull up of all
ports when latch data is logical 0.
The quasi-b idi rec tio nal port con fig ur ation is shown in Figu re 3.
Figure 3. Quasi-Bidirectional Output
2 CPU
Input
Pin
Strong Medium
N
Weak
P
Clock Delay
Port Latch
Data
Data
DPU
AUXR.7
PP
16 AT89C51RD2/ED2 4235C–8051–08/03
Oscillator To optimiz e the power consumption and execution time needed for a specific task, an
interna l presc aler featu re has be en impl emented between th e oscill ator a nd the CP U
and peripherals.
Registers Table 14. CKRL Register
CKRL – Clock Reload Register ( 97h)
Reset Value = 1111 1111b
Not bit address ab le
Table 15. PCON Register
PCON – Power Control Register (87h)
Reset Value = 00X1 0000b Not bit addressable
76543210
CKRL7 CKRL6 CKRL5 CKRL4 CKRL3 CKRL2 CKRL1 CKRL0
Bit Number Mnemonic Descriptio n
7:0 CKRL Clock Reload Register
Prescaler value
76543210
SMOD1 SMOD0 - POF GF1 GF0 PD IDL
Bit Number Bit Mnemonic Description
7SMOD1
Serial Port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
6SMOD0
Serial Port Mode bit 0
Cleared to select SM0 bit in SCON register .
Set to sele ct FE bit in SCO N register.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4POF
Power-off Flag
Cleared by software to recognize thenext reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can
also be set by software.
3GF1
Gene r a l - p urpo s e Fl a g
Cleared by software for general-purpose usage.
Set by software for general-purpose usage.
2GF0
Gene r a l - p urpo s e Fl a g
Cleared by software for general-purpose usage.
Set by software for general-purpose usage.
1PD
Power-do wn Mod e bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
0IDL
Idle Mode bit
Cleared by hardware when interrupt or reset occurs.
Set to enter idle mode.
17
AT89C51RD2/ED2
4235C–8051–08/03
Functional Block Diagram
Figure 4. Functional Oscillator Block Diagram
Prescaler Divider •A hardw are RESET puts the prescaler divider in t he following state:
•CKRL = FFh: FCLK CPU = FCLK PERIPH = FOSC/2 (Standard C51 feature)
•Any value between FFh down to 00h can be written by software into CKRL register
in order to divide frequency of the selected oscillator:
•CKRL = 00h: minimum frequency
FCLK CPU = FCLK PERIPH = FOSC/1020 (Standard Mode)
FCLK CPU = FCLK PERIPH = FOSC/ 510 (X2 Mode)
•CKRL = FFh: maximum frequency
FCLK CPU = FCLK PERIPH = FOSC/2 (Standard Mode)
FCLK CPU = FCLK PERIPH = FOSC (X2 Mode)
FCLK CPU and FCLK PERIPH
In X2 Mode, for CKRL<>0xFF:
In X1 Mode, for CKRL<>0xFF then:
Xtal2
Xtal1
Osc
CLK
Idle
CPU Clock
CKRL
Reload
8-bit
Prescaler-Divider
Reset
Peripheral Clock
:2
X2
0
1
FOSC
CKCON0
CLK
Periph
CPU
CKRL = 0xFF?
0
1
FCPU F=CLKPERIPH FOSC
2 255 CKRL–()×
-----------------------------------------------=
FCPU F=CLKPERIPH FOSC
4 255 CKRL–()×
-----------------------------------------------=
18 AT89C51RD2/ED2 4235C–8051–08/03
Enhanced Features In compa ris on to the original 80C5 2, the A T89C51 RD2/ED2 impl eme nts some new fea-
tures, which are:
• X2 option
• Dual Data Pointer
• Extended RAM
• Programmable Counter Array (PCA)
• Hardware Watchdog
• SPI interfa ce
• 4-level interrupt priority system
• Power-off flag
• ONCE mode
• ALE disabl ing
•Some enhanced features are also located in the UART and the Timer 2
X2 Feature The AT89C51RD2/ED2 core needs only 6 clock periods per machine cycle. This feature
called ‘X2’ provides the followi ng adv ant age s:
•Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
•Save power consumption while keeping same CPU power (oscillator power saving).
•Save power consumption by dividing dynamically the operating frequency by 2 in
operating and idle modes.
•Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the ori ginal C51 com patibili ty, a divider by 2 is inser ted between th e
XTAL1 signal and the main clock input of the core (phase generator). This divider may
be disabled by software.
Description The cl ock fo r the whole c ircuit and periph erals is first div ided by two befor e being use d
by the CPU core and the peripherals.
This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is
bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%.
Figure 5 shows the clock generation block diagram. X2 bit is validated on the rising edge
of the XTAL1 ÷ 2 to avoid glitches when switching from X2 to STD mode. Figure 6
shows the switching mode waveforms.
Figure 5. Clock Generation Diagram
XTAL1 2
CKCON0
X2
8-bit Prescaler
FOSC
FXTAL 0
1
XTAL1:2 FCLK CPU
FCLK PERIPH
CKRL
19
AT89C51RD2/ED2
4235C–8051–08/03
Figure 6. Mode Switching Waveforms
The X2 bit in the CKCON0 register (see Table 16) allows a switch from 12 clock periods
per inst ructio n to 6 c lock peri ods an d vice v ersa. A t rese t, the s peed is s et acc ording to
X2 bit of Hardware Security Byte (HSB). By default, Standard mode is active. Setting the
X2 bit activates the X2 feature (X2 mode).
The T0X2 , T1X 2, T2X2, UartX 2, PcaX2 , and W dX2 bi ts in the CKCON 0 regis ter (Tabl e
16) and SPIX2 bit in the CKCON1 register (see Table 17) allows a switch from standard
peripheral speed (12 clock periods per peripheral clock cycle) to fast peripheral speed (6
clock periods per peripheral clock cycle). These bits are active only in X2 mode.
XTAL1:2
XTAL1
CPU Clock
X2 Bi t
X2 ModeSTD Mode STD Mode
FOSC
20 AT89C51RD2/ED2 4235C–8051–08/03
Table 16. CKCON0 Register
CKCON0 - Clock Control Register (8Fh)
Reset Value = 0000 000’HSB. X2’b (See “Hardware Security Byte”)
Not bit address ab le
76543210
- WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2
Bit
Number Bit
Mnemonic Description
7Reserved The values for this bit are indeterminite. Do not set this bit.
6WDX2
Wa tchdog Clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low , this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
5PCAX2
Programmable Counter Array Clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low , this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
4SIX2
Enhanced UART Clock (Mode 0 and 2)
(This control bit is validated when the CPU clock X2 is set; when X2 is low , this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
3T2X2
Timer2 Clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low , this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
2T1X2
Timer1 Clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low , this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
1T0X2
Timer0 Clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low , this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
0X2
CPU Clock
Cleared to select 12 clock periods per machine cycle (STD mode) for CPU and
all the peripherals. Set to select 6 clock periods per machine cycle (X2 mode)
and to enable the individual peripherals’X2’ bits. Programmed by hardware after
Power-up regarding Hardware Securit y Byte (HSB) , Default setting, X2 is
cleared.
21
AT89C51RD2/ED2
4235C–8051–08/03
Table 17. CKCON1 Register
CKCON1 - Clock Control Register (AFh)
Reset Val ue = XXXX XXX 0b
Not bit address ab le
76543210
-------SPIX2
Bit
Number Bit
Mnemonic Description
7-Reserved
6-Reserved
5-Reserved
4-Reserved
3-Reserved
2-Reserved
1-Reserved
0 SPIX2
SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low,
this bit has no effect).
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
22 AT89C51RD2/ED2 4235C–8051–08/03
Dual Data Pointer
Register (DPTR) The additional data pointer can be used to speed up code execution and reduce code
size.
The dual DPTR structure is a way by which the chip will specify the address of an exter-
nal data memory location. There are two 16-bit DPTR registers that address the external
memory, and a single bit called DPS = AUXR1.0 (see Table 18) that allows the program
code to switch between them (Refer to Figure 7).
Figure 7. Use of Dual Pointer Ext e rn a l D a ta M e mo ry
AUXR1(A2H)
DPS
DPH(83H) DPL(82H)
07
DPTR0
DPTR1
23
AT89C51RD2/ED2
4235C–8051–08/03
Table 18. AUXR1 Register
AUXR1- Auxiliary Register 1(0A2h)
Reset Value = XXXX XX0X0b
Not bit address ab le
Note: 1. Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3.
ASSEMBLY LANG U A G E
; Block move using dual data pointers
; Modifies DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2 AUXR1 EQU 0A2H
;
0000 909000MOV DPTR,#SOURCE ; address of SOURCE
0003 05A2 INC AUXR1 ; switch data pointers
0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers
000A E0 MOVX A,@DPTR ; get a byte from SOURCE
000B A3 INC DPTR ; increment SOURCE address
000C 05A2 INC AUXR1 ; switch data pointers
000E F0 MOVX @DPTR,A ; write the byte to DEST
000F A3 INC DPTR ; increment DEST address
0010 70F6JNZ LOOP ; check for 0 terminator
0012 05A2 INC AUXR1 ; (optional) restore DPS
76543210
- - ENBOOT - GF3 0 - DPS
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5ENBOOT
Enable Boot Flash
Cleared to disable boot ROM.
Set to map the boot ROM between F800h - 0FFFFh.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3GF3This bit is a general-purpose user flag.(1)
20Always cleared
1-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0DPS
Data Pointer Selection
Cleared to select DPTR0.
Set to select DPTR1.
24 AT89C51RD2/ED2 4235C–8051–08/03
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1
SFR. However, note that the INC instruction does not directly force the DPS bit to a par-
ticul ar state , but sim ply toggle s it. In simp le rout ines, s uch as the bl ock move e xample ,
only the fa ct t hat DP S i s togg led in th e pr op er se quence matt er s, n ot i ts a ctu al value. In
other words, the block move ro utine wo rks the same whe ther DPS is ’0’ or ’1’ on entr y.
Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in
the opposite state.
25
AT89C51RD2/ED2
4235C–8051–08/03
Expanded RAM
(XRAM) The AT89C51RD2/ED2 provides additional on-chip random access memory (RAM)
space for increased data parameter handling and high level language usage.
AT89C51RD2/ED2 device haS expanded RAM in external data space configurable up
to 1792 bytes (see Table 19).
The AT89C51RD2/ED2 internal data memory is mapped into four separate segments.
The four segments are:
1. The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly
addressable.
2. The Upper 128 bytes of RAM (addresses 80h to FFh) are indirectly addressable
only.
3. The Special Function Registers, SFRs, (addresses 80h to FFh) are directly
addressable only.
4. The expanded RAM bytes are indirectly accessed by MOVX instructions, and
with the EXTRAM bit cleared in the AUXR register (see Table 19).
The lower 128 bytes can be accessed by either direct or indirect addressing. The Upper
128 bytes ca n be access ed by indirect ad dressing only. T he Upper 128 bytes occupy
the same add r ess spa ce as th e S FR. T ha t m eans t hey ha ve the s ame ad dr ess, but ar e
physically separate from SFR space.
Figure 8. Internal and External Data Memory Address
When an instru ction a ccesse s an inte rnal lo cation above ad dress 7Fh , the CPU knows
whether the access is to the upper 128 bytes of data RAM or to SFR space by the
addressing mode used in the instruction.
•Instructions that use direct addressing access SFR space. For example: MOV
0A0H, # data, accesses the SFR at location 0A0h (which is P2).
•Instructions that use indirect addressing access the Upper 128 bytes of data RAM.
For example: MOV @R0, # data where R0 contains 0A0h, accesses the data byte
at address 0A0h, rather than P2 (whose address is 0A0h).
•The XRAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared
and MOVX instructions. This part of memory which is physically located on-chip,
logically occupies the first bytes of external data memory. The bits XRS0 and XRS1
are used to hide a part of the available XRAM as explained in Table 19. This can be
XRAM
Upper
128 Bytes
Internal
RAM
Lower
128 Bytes
Internal
RAM
Special
Function
Register
80h 80h
00
0FFh or 6FFh 0FFh
00
0FFh
External
Data
Memory
0000
00FFh up to 06FFh
0FFFFh
Indirect Accesses Di rec t Accesses
Direct or Indirect
Accesses
7Fh
26 AT89C51RD2/ED2 4235C–8051–08/03
useful if external peripherals are mapped at addresses already used by the internal
XRAM.
•With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in
combination with any of the registers R0, R1 of the selected bank or DPTR. An
access to XRAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For
example, with EXTRAM = 0, MOVX @R0, # data where R0 contains 0A0H,
accesses the XRAM at address 0A0H rather than external memory. An access to
external data memory locations higher than the accessible size of the XRAM will be
performed with the MOVX DPTR instructions in the same way as in the standard
80C51, with P0 and P2 as data/address busses, and P3.6 and P3.7 as write and
read timing signals. Accesses to XRAM above 0FFH can only be done by the use of
DPTR.
•With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard
80C51.MOVX @ Ri will provide an eight-bit address multiplexed with data on Port0
and any output port pins can be used to output higher order address bits. This is to
provide the external paging capability. MOVX @DPTR will generate a sixteen-bit
address. Port2 outputs the high-order eight address bits (the contents of DPH) while
Port0 multiplexes the low-order eight address bits (DPL) with data. MOVX @ Ri and
MOVX @DPTR will generate either read or write signals on P3.6 (WR) and P3.7
(RD).
The s tack point er (SP) ma y be loc ated any where in the 256 byt es RAM (l ower and
upper RAM) internal data memory. The stack may not be located in the XRAM.
The M0 bit allows to stretch the XRAM timings; if M0 is set, the read and write pulses
are extended from 6 to 30 clock periods. This is useful to access external slow
peripherals.
27
AT89C51RD2/ED2
4235C–8051–08/03
Registers Table 19. AUXR Register
AUXR - Auxiliary Register (8Eh)
Reset Value = 0X00 10’HSB. XRAM’0b
Not bit address ab le
76543210
DPU - M0 XRS2 XRS1 XRS0 EXTRAM AO
Bit
Number Bit
Mnemonic Description
7DPU
Disable Weak Pull-up
Cleared by software to activate the permanent weak pull-up (default)
Set by software to disable the weak pull-up (reduce power consumpt ion)
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5M0
Pulse length
Cleared to stretch MOVX control: the RD and the WR pulse length is 6 clock
periods (default).
Set to stret c h MO VX con tr ol : the RD and the WR pulse length is 30 clock
periods.
4XRS2XRAM Size
XRS2 XRS1 XRS0 XRAM size
0 0 0 256 bytes
0 0 1 512 bytes
0 1 0 768 bytes(default)
0 1 1 1024 bytes
1 0 0 1792 bytes
3XRS1
2XRS0
1EXTRAM
EXTRAM bit
Cleared to access internal XRAM using movx @ Ri/ @ DPTR.
Set to access external memory.
Programmed by hardware after Powe r-up regarding Hardware Sec urity Byte
(HSB), default setting, XRAM selected.
0AO
ALE Output bi t
Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if
X2 mode is used). (default) Set, ALE is active only during a MOVX or MOVC
instruction is used.
28 AT89C51RD2/ED2 4235C–8051–08/03
Reset
Introduction The reset s ources are : Power Manag ement, Har dware Wa tchdog , PCA Watc hdog an d
Reset input.
Figure 9. Reset schematic
Reset Input The Reset input can be used to force a reset pulse longer than the internal reset con-
trolled by the Po wer M onitor. RST input has a pull-down resistor allowing power -on
reset by simply connecting an external capacitor to VCC as shown in Figure 10. Resistor
value an d input cha racteri stics are discu ssed in th e Sectio n “DC Characteristics” of the
AT89C51RD2/E D2 data sheet.
Figure 10. Reset Circuitry and Power-On Reset
Power
Monitor
Hardware
Watchdog
PCA
Watchdog
RST
Internal Reset
RST
R
RST
VSS
To internal reset
RST
VDD
+
b. Power-on Reseta. RST input circuitry
29
AT89C51RD2/ED2
4235C–8051–08/03
Reset Output
As detailed in Section “Hardware Watchdog Timer”, pag e 87, the WD T gener ates a 96-
clock period pulse on the RST pin. In order to properly propagate this pulse to the rest of
the application in case of external capacitor or power-supply supervisor circuit, a 1 kΩ
resistor must be added as shown Figure 11.
Figure 11. Recommended Reset Output Schematic
RST
VDD
+
VSS
VDD
RST
1K
To other
on-board
circuitry
AT89C51XD2
30 AT89C51RD2/ED2 4235C–8051–08/03
Power Monitor The POR/PFD function monitors the internal power-supply of the CPU core memories
and the peripherals, and if needed, suspends their activity when the internal power sup-
ply falls below a safety threshold. This is achieved by applying an internal reset to them.
By generating the Reset the Power Monitor insures a correct start up when
AT89C51RD2/ED2 is powered up.
Description In order to startup and maintain the microcontroller in correct operating mode, VCC has
to be stabi lized in the VCC opera ting rang e and the oscil lator has to be stabilize d with a
nominal amplitude compatible with logic level VIH/VIL.
These parameters are controlled during the three phases: power-up, normal operation
and power going down. See Figure 12.
Figure 12. Power Monitor Block Diagram
Note: 1. Once XTAL1 High and low levels reach above and below VIH/VIL. a 1024 clock
period delay will extend the reset coming from the Power Fail Detect. If the power
falls below the Power Fail Detect threshold level, the Reset will be applied
immediately.
The Voltag e r egu la tor gen erate s a re gulate d i nter na l sup ply fo r t he CPU c or e th e m em-
ories an d the peripherals. Spikes on the exte rnal Vcc are smoothed by the voltage
regulator.
VCC
Power On Reset
Power Fail Detect
Voltage Regulator
XTAL1 (1)
CPU core
Memories
Peripherals
Regulated
Supply
RST pin
Hardware
Watchdog
PCA
Watchdog
Internal Reset
31
AT89C51RD2/ED2
4235C–8051–08/03
The Powe r fail d etect mo nitor the s upply gener ated by th e volta ge regula tor and g ener-
ate a reset if this supply falls below a safety threshold as illustrated in the Figure 13
below.
Figure 13. Power Fail Detect
When the powe r is applied, the Power Mo nitor immediately a sserts a re set. Once the
internal supply after the voltage regulator reach a safety level, the power monitor then
looks a t the X T AL cl oc k input. The in ter nal res et wi ll re mai n ass er ted unti l th e X tal 1 le v-
els are above and below VIH and VIL. F ur the r more. An internal counte r wil l count 1024
clock periods before the reset is de-asserted.
If the internal power supply falls below a safety level, a reset is immediately asserted.
.
Vcc
t
Reset
Vcc
32 AT89C51RD2/ED2 4235C–8051–08/03
Timer 2 The Timer 2 in the AT89C51RD2/ED2 is the standard C52 Timer 2. It is a 16-bit
timer/coun ter : the coun t is mainta ine d by two eight- bi t timer regi ste r s, TH 2 and TL2 ar e
cascad ed. It is co ntr ol led by T2 CO N (Ta ble 20) and T 2M OD (T ab le 21) regi ste r s. Ti mer
2 operati on is similar to Timer 0 and Time r 1. C/T2 selects FOSC/12 (timer op eration) or
external pin T2 (counter operation) as the timer clock input. Setting TR2 allows TL2 to
increment by the selected input.
Timer 2 has 3 ope ratin g mode s: c aptur e, au toreload and B aud R ate Genera tor. These
modes are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON).
Refer to the Atmel 8-bit Mic rocont roll er Hardwa re Manual for the descripti on of Capt ure
and Baud Rate Generator Modes.
Timer 2 includes the following enhancements:
•Auto-reload mode with up or down counter
•Programmable clock-output
Auto-reload Mode The auto-reload mode configures Timer 2 as a 16-bit timer or event counter with auto-
matic reload. If DCEN bit in T2MOD is cleared, Timer 2 behaves as in 80C52 (refer to
the Atmel C51 Mic roc ontrol le r Ha rdwar e Ma nual) . If DCEN bit is se t, Tim er 2 acts as an
Up/down timer/counter as shown in F igure 14. In this mode the T2E X pin controls the
direction of count.
When T2EX is high, Timer 2 counts up. Time r overflow occurs at FFFFh which sets the
TF2 fl ag a nd g ener ates an interr upt requ est. T he overfl ow a lso cau ses th e 16 -bit valu e
in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2.
When T2EX is low, Timer 2 counts down. Timer underflow occurs when the count in the
timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers.
The underflow sets TF2 flag and reloads FFFFh into the timer registers.
The EXF2 bit toggles when Timer 2 overflows or underflows according to the direction of
the count. EX F2 does not gener ate any interru pt. This bit can be used to provide 17-bit
resolution.
33
AT89C51RD2/ED2
4235C–8051–08/03
Figure 14. Auto-reload Mode Up/Down Counter (DCEN = 1)
Programmable
Clock-output In the clock-out mode, Timer 2 operates as a 50% duty-cycle, programmable clock gen-
erato r (See Figu re 15) . The inpu t clock i ncremen ts TL2 at frequenc y FCLK PERIPH/2. The
timer repe atedly coun ts to overfl ow from a loade d value. At ov erflow, the co ntents of
RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, Timer 2
overflows do not generate interrupts. The formula gives the clock-out frequency as a
function of the system oscillator frequency and the value in the RCAP2H and RCAP2L
registers:
For a 16 MHz system clock, Timer 2 has a programmable frequency range of 61 Hz
(FCLK PERI PH/216) to 4 MHz (FCLK PE RIP H/4). The generated clock signal is brought out to
T2 pin (P1.0).
Timer 2 is programmed for the clock-out mode as follows:
•Set T2OE bit in T2MOD register.
•Clear C/T2 bit in T2CON register.
•Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L
registers.
•Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the
reload value or a different one depending on the application.
•To start the timer, set TR2 run control bit in T2CON register.
It is possible to use Timer 2 as a baud rate generator and a clock generator simulta-
neously. For this configuration, the baud rates and clock frequencies are not
independent since both functions use the values in the RCAP2H and RCAP2L registers.
(DOWN COUNTING RELOAD VALUE)
C/T2
TF2
TR2
T2
EXF2
TH2
(8-bit)
TL2
(8-bit)
RCAP2H
(8-bit)
RCAP2L
(8-bit)
FFh
(8-bit) FFh
(8-bit)
TOGGLE
(UP COUNTING RELOAD VALUE)
TIMER 2
INTERRUPT
FCLK PERIPH 0
1
T2CON T2CON
T2CON
T2CON
T2EX:
If DCEN = 1, 1 = UP
If DCEN = 1, 0 = DOWN
If DCEN = 0, up counting
:6
Clock O–utFrequency FCLKPERIPH
4 65536 RCAP2H RCAP2L⁄)–(×
---------------------------------------------------------------------------------------------
=
34 AT89C51RD2/ED2 4235C–8051–08/03
Figure 15. Clock-out Mode C/T2 = 0
:6
EXF2
TR2
OVER-
FLOW
T2EX
TH2
(8-bit)
TL2
(8-bit)
TIMER 2
RCAP2H
(8-bit)
RCAP2L
(8-bit)
T2OE
T2
FCLK PERIPH
T2CON
T2CON
T2CON
T2MOD
INTERRUPT
QD
Toggle
EXEN2
35
AT89C51RD2/ED2
4235C–8051–08/03
Registers Table 20. T2CON Register
T2CON - Timer 2 Control Register (C8h)
Reset Value = 0000 0000b
Bit addressable
76543210
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#
Bit
Number Bit
Mnemonic Description
7TF2
Timer 2 overflow Flag
Must be cleared by software.
Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0.
6EXF2
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if
EXEN2 = 1.
When set, causes the CPU to vector to T imer 2 interrupt routine when Timer 2
interrupt is enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down
counter mode (DCEN = 1).
5 RCLK Receive Clock bit
Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3.
4TCLK
Transmit Clock bit
Cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3.
3EXEN2
Timer 2 External Enable bit
Cleared to ignore events on T2EX pin for Timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is
detected, if Tim er 2 is not used to clock the serial port.
2TR2
Timer 2 Run control bit
Cleared to turn off Timer 2.
Set to tur n on Timer 2.
1C/T2#
Timer/Counter 2 select bit
Cleared for timer operation (input from internal clock system: FCLK PERIPH).
Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0
for clock out mode.
0 CP/RL2#
Timer 2 Capture/Reload bit
If RCLK = 1 or TCLK = 1, CP/RL2# is ignored and timer is forced to auto-reload
on Timer 2 overflow.
Cleared to auto-reload on Timer 2 overflows or negative transitions on T2EX pin
if EXEN2= 1.
Set to capture on negative transitions on T2EX pin if EXEN2 = 1.
36 AT89C51RD2/ED2 4235C–8051–08/03
Table 21. T2MOD Register
T2MOD - Timer 2 Mode Control Register (C9h)
Reset Val ue = XXXX XX00 b
Not bit address ab le
76543210
------T2OEDCEN
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1T2OE
Timer 2 Output Enable bit
Cleared to program P1.0/T2 as clock input or I/O port.
Set to program P1.0/T2 as clock output.
0 DCEN Down Counter Enable bit
Cleared to disable Timer 2 as up/down counter.
Set to enable Ti mer 2 as up/down counter.
37
AT89C51RD2/ED2
4235C–8051–08/03
Programmable
Counter Array (PCA) The PCA provides more timing capabilities with less CPU intervention than the standard
timer/counters. Its advantages include reduced software overhead and improved accu-
racy. T he PCA co nsists of a dedic ated timer /counte r which se rves as the time ba se for
an arra y of fiv e compar e/ca pture m odules . Its cl ock inp ut can be progra mmed to count
any one of the following signals:
•Peripheral clock frequency (FCLK PERIPH) ÷ 6
•Peripheral clock frequency (FCLK PERIPH) ÷ 2
•Timer 0 overflow
•External input on ECI (P1.2)
Each compare/capture module can be programmed in any one of the following modes:
•Rising and/or falling edge capture
•Software timer
•High-speed output
•Pulse width modulator
Module 4 can also be programmed as a watchdog timer (see Section "PCA Watchdog
Timer", page 48).
When the compare/capture modules are programmed in the capture mode, software
timer, or hig h speed ou tpu t mode, an in terrupt c an be gene rated when the modu le exe-
cutes it s function. All five modules plus the PCA timer overflow share one interrupt
vector.
The PCA timer/counter and compare/capture modules share Port 1 for external I/O.
Thes e pins ar e liste d belo w. If one or seve ral bit s in the port are not use d for th e PCA,
they can still be used for standard I/O.
The PCA timer is a common time base for all five modules (see Figure 16). The timer
count source is determined from the CPS1 and CPS0 bits in the CMOD register
(Table 22) and can be programmed to run at:
•1/6 the peripheral clock frequency (FCLK PERIPH)
•1/2 the peripheral clock frequency (FCLK PERIPH)
•The Timer 0 overflow
•The input on the ECI pin (P1.2)
PCA Component External I/O Pin
16-bit Counter P1.2/ECI
16-bit Module 0 P1.3/CEX0
16-bit Module 1 P1.4/CEX1
16-bit Module 2 P1.5/CEX2
16-bit Module 3 P1.6/CEX3
38 AT89C51RD2/ED2 4235C–8051–08/03
The CMOD register includes three additional bits associated with the PCA (See
Figure 16 and Table 22).
•The CIDL bit which allows the PCA to stop during idle mode.
•The WDTE bit which enables or disables the watchdog function on module 4.
•The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in
the CCON SFR) to be set when the PCA timer overflows.
Figure 16. PCA Timer/Counter
CIDL CPS1 CPS0 ECF
IT
CH CL
16 Bit Up/Down Counter
To PCA
Modules
FCLK PERIPH/6
FCLK PERIPH/2
T0 OVF
P1.2
Idle
CMOD
0xD9
WDTE
CF CR CCON
0xD8
CCF4 CCF3 CCF2 CCF1 CCF0
Overflow
39
AT89C51RD2/ED2
4235C–8051–08/03
Table 22. CMOD Register
CMOD - PCA Counter Mode Register (D9h)
Reset Val ue = 00XX X00 0b
Not bit address ab le
The CCON registe r contains the run c ontrol bit for the P CA and the flags for the PCA
timer (CF) and each module (Refer to Table 23).
•Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by
clearing this bit.
•Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an
interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can
only be cleared by software.
•Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1,
etc.) and are set by hardware when either a match or a capture occurs. These flags
also can only be cleared by software.
76543210
CIDL WDTE - - - CPS1 CPS0 ECF
Bit
Number Bit
Mnemonic Description
7CIDL
Counter Idle Control
Cleared to program the PCA Counter to continue functioning during idle Mode.
Set to program PCA to be gated off during idle.
6WDTE
Watchdog Timer Enable
Cleared to disable W atchdog Timer function on PCA Module 4.
Set to enable Watchdog Timer function on PCA Module 4.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2CPS1PCA Count Pulse Select
CPS1 CPS0 Selected PCA input
0 0 Internal clock FCLK PERIPH/6
0 1 Internal clock FCLK PERIPH/2
1 0 Timer 0 Overflow
1 1 External clock at ECI/P1.2 pin (max rate = FCLK PERIPH/4)
1CPS0
0ECF
PCA Enable Counter Overflow Interrupt
Cleared to disable CF bit in CCON to inhibit an interrupt.
Set to enable CF bit in CCON to generate an interrupt.
40 AT89C51RD2/ED2 4235C–8051–08/03
Table 23. CCON Register
CCON - PCA Counter Control Register (D8h)
Reset Value = 00X0 0000b
Not bit address ab le
The watchdog timer function is implemented in Module 4 (See Figure 19).
The PCA interrupt system is shown in Figure 17.
76543210
CF CR - CCF4 CCF3 CCF2 CCF1 CCF0
Bit
Number Bit
Mnemonic Description
7CF
PCA Counter Overflow flag
Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in
CMOD is set. CF
may be set by either hardware or software but can only be cleared by software.
6CR
PCA Counter Run control bit
Must be cleared by software to turn the PCA counter off.
Set by software to turn the PCA counter on.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 CCF4 P CA Mo dule 4 interrupt flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
3 CCF3 P CA Mo dule 3 interrupt flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
2 CCF2 P CA Mo dule 2 interrupt flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
1 CCF1 P CA Mo dule 1 interrupt flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
0 CCF0 P CA Mo dule 0 interrupt flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
41
AT89C51RD2/ED2
4235C–8051–08/03
Figure 17. PCA Interrupt System
PCA Modules: each one of t he five compa re/captur e modul es has si x poss ible fun c-
tions. It can perform:
•16-bit Capture, positive-edge triggered
•16-bit Capture, negative-edge triggered
•16-bit Capture, both positive and negative-edge triggered
•16-bit Sof tware Timer
•16-bit High Speed Output
•8-bit Pulse Width Modulator
In addition, Module 4 can be used as a Watchdog Timer.
Each mod ule in the PCA has a s pecial function r egis ter ass ociated wi th it. The se r egis-
ters are: CCAPM0 for Module 0, CCAPM1 for Module 1, etc. (See Table 24). The
registers contain the bits that control the mode that each module will operate in.
•The ECCF bit (CCAPMn.0 where n = 0, 1, 2, 3, or 4 depending on the module)
enables the CCF flag in the CCON SFR to generate an interrupt when a match or
compare occurs in the associated module.
•PWM (CCAPMn.1) enables the pulse width modulation mode.
•The TOG bit (CCAPMn.2) when set causes the CEX output associated with the
module to toggle when there is a match between the PCA counter and the modules
captur e/com par e re giste r.
•The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON
register to be set when there is a match between the PCA counter and the modules
captur e/compare regis te r.
•The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge
that a capture input will be active on. The CAPN bit enables the negative edge, and
the CAPP bit enables the positive edge. If both bits are set both edges will be
enabled and a capture will occur for either transition.
•The last bit in the register ECOM (CCAPMn.6) when set enables the comparator
function.
CF CR CCON
0xD8
CCF4 CCF3 CCF2 CCF1 CCF0
Module 4
Module 3
Module 2
Module 1
Module 0
ECF
PCA Timer/Counter
ECCFn CCAPMn.0CMOD.0 IE.6 IE.7
To Interrupt
Priority Decoder
EC EA
42 AT89C51RD2/ED2 4235C–8051–08/03
Table 24 shows the CCAPMn settings for the various PCA functions.
Table 24. CCAPMn Registers (n = 0-4)
CCAPM0 - PCA Module 0 Compare/Capture Control Register (0DAh)
CCAPM1 - PCA Module 1 Compare/Capture Control Register (0DBh)
CCAPM2 - PCA Module 2 Compare/Capture Control Register (0DCh)
CCAPM3 - PCA Module 3 Compare/Capture Control Register (0DDh)
CCAPM4 - PCA Module 4 Compare/Capture Control Register (0DEh)
Reset Value = X000 0000b
Not bit address ab le
76543210
- ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6ECOMn
Enable Comparator
Cleared to disable the comparator function.
Set to enable the comparator function.
5 CAPPn Capture Positive
Cleared to disable positive edge capture.
Set to enable positive edge capture.
4CAPNn
Capture Negative
Cleared to disable negative edge capture.
Set to enable negative edge capture.
3MATn
Match
When MAT n = 1, a match of the PCA counter with this module’s
compare/capture register causes the CCFn bit in CCON to be set, flagging an
interrupt.
2TOGn
Toggle
When TOGn = 1, a match of the PCA counter with this module’s
compare/capture register causes the CEXn pin to toggle.
1PWMn
Pulse Width Modulation Mode
Cleared to disable the CEXn pin to be used as a pulse width modulated output.
Set to enable the CEXn pin to be used as a pulse width modulated output.
0 CCF0
Enable CCF interrupt
Cleared to disable compare/capture flag CCFn in the CCON register to generate
an interrupt.
Set to enable compare/capture flag CCFn in the CCON register to generate an
interrupt.
43
AT89C51RD2/ED2
4235C–8051–08/03
Table 25. PCA Module Modes (CCAPMn Registers)
There are two additional registers associated with each of the PCA modules. They are
CCAPnH and CCAPnL and thes e are the register s that store the 16-bit count when a
capture occurs or a compare should occur. When a module is used in the PWM mode
these registers are used to control the duty cycle of the output (See Table 26 &
Table 27).
Table 26. CCAPnH Registers (n = 0 - 4)
CCAP0H - PCA Module 0 Compare/Capture Control Register High (0FAh)
CCAP1H - PCA Module 1 Compare/Capture Control Register High (0FBh)
CCAP2H - PCA Module 2 Compare/Capture Control Register High (0FCh)
CCAP3H - PCA Module 3 Compare/Capture Control Register High (0FDh)
CCAP4H - PCA Module 4 Compare/Capture Control Register High (0FEh)
Reset Value = 0000 0000b
Not bit address ab le
ECOMn CAPPn CAPNn MATn TOGn PWMm ECCFn Module Function
0000000 No Operation
X10000X
16-bit capture by a positive-edge
trigger on CEXn
X01000X
16-bit capture by a negative trigger
on CEXn
X11000X
16-bit capture by a transition on
CEXn
100100X
16-bit Software Timer/Compare
mode.
100110X16-bit High Speed Output
10000108-bit PWM
1001X0XWatchdog Timer (module 4 only)
76543210
--------
Bit
Number Bit
Mnemonic Description
7 - 0 - PCA Module n Compare/Capture Control
CCAPnH Value
44 AT89C51RD2/ED2 4235C–8051–08/03
Table 27. CCAPnL Registers (n = 0 - 4)
CCAP0L - PCA Module 0 Compare/Capture Control Register Low (0EAh)
CCAP1L - PCA Module 1 Compare/Capture Control Register Low (0EBh)
CCAP2L - PCA Module 2 Compare/Capture Control Register Low (0ECh)
CCAP3L - PCA Module 3 Compare/Capture Control Register Low (0EDh)
CCAP4L - PCA Module 4 Compare/Capture Control Register Low (0EEh)
Reset Value = 0000 0000b
Not bit address ab le
Table 28. CH Register
CH - PCA Counter Register High (0F9h)
Reset Value = 0000 0000b
Not bit address ab le
Table 29. CL Register
CL - PCA Counter Register Low (0E9h)
Reset Value = 0000 0000b
Not bit address ab le
76543210
--------
Bit
Number Bit
Mnemonic Description
7 - 0 - PCA Module n Compare/Capture Control
CCAPnL Value
76543210
--------
Bit
Number Bit
Mnemonic Description
7 - 0 - PCA counter
CH Value
76543210
--------
Bit
Number Bit
Mnemonic Description
7 - 0 - PCA Counter
CL Value
45
AT89C51RD2/ED2
4235C–8051–08/03
PCA Capture Mode To use one of the P CA modu les in th e captur e mode ei ther one or both of the CCAPM
bits CAP N a nd CAPP f or tha t mo dule m us t be s et. The exte rn al CEX i nput for th e m od-
ule (on port 1) is sampled for a transition. When a valid transition occurs the PCA
hardware loads the value of the PCA counter registers (CH and CL) into the module’s
capture register s (CCAPnL and CCA PnH). If the CC Fn bit for the modul e in the CCON
SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated
(Refer to Figure 18).
Figure 18. PCA Capture Mode
16-bit Softwar e Timer/
Compare Mode The PCA mod ules can be us ed as software tim ers by settin g both the ECOM and MAT
bits in the mod ules CCAPMn regi ster. The PCA timer will be compar ed to the module’s
capture registers and when a match occurs an interrupt will occur if the CCFn (CCON
SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (See Figure 19).
CF CR CCON
0xD8
CH CL
CCAPnH CCA PnL
CCF4 CCF3 CCF2 CCF1 CCF0
PCA IT
PCA Counter /Timer
ECOMn CCA PMn, n= 0 to 4
0xDA to 0xDE
CAPNn MATn TOGn PWMn ECCFnCAPPn
Cex.n
Capture
46 AT89C51RD2/ED2 4235C–8051–08/03
Figure 19. PCA Compare Mode and PCA Watchdog Timer
Before e nab li ng E CO M bi t, CCA PnL a nd CCAPnH s hou ld be s et wi th a non ze ro va lu e,
otherwise an unwanted match could happen. Writing to CCAPnH will set the ECOM bit.
Once ECOM is set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t
occur while mo difying the compare value. Writing to CCAPnH will set ECOM. For this
reason, user software should write CCAPnL first, and then CCAPnH. Of course, the
ECOM bit can still be controlled by accessing to CCAPMn register.
High Speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle
each time a match occurs between the PCA counter and the modules capture registers.
To activate this mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR
must be set (See Figu re 20).
A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit.
CH CL
CCAPnH CCAPnL
ECOMn CCAPMn, n = 0 to 4
0xDA to 0xDE
CAPNn MATn TOGn PWMn ECCFnCAPPn
16 bit comparator Match
CCON
0xD8
PCA IT
Enable
PCA cou nte r/ ti mer
RESET *
CIDL CPS1 CPS0 ECF CMOD
0xD9
WDTE
Reset
Write to
CCAPnL
Write to
CCAPnH
CF CCF2 CCF1 CCF0
CR CCF3CCF4
10
47
AT89C51RD2/ED2
4235C–8051–08/03
Figure 20. PCA High Speed Output Mode
Before e nab li ng E CO M bi t, CCA PnL a nd CCAPnH s hou ld be s et wi th a non ze ro va lu e,
otherwise an unwanted match could happen.
Once ECOM is set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t
occur while mo difying the compare value. Writing to CCAPnH will set ECOM. For this
reason, user software should write CCAPnL first, and then CCAPnH. Of course, the
ECOM bit can still be controlled by accessing to CCAPMn register.
Pulse Width Modulator
Mode All of the P CA mod ule s can b e used as P WM out puts. F igure 21 shows the PW M func-
tion. T he frequen cy of t he output depends on the source for the P CA time r. All o f the
module s will h ave the sam e freque ncy of ou tput beca use they all shar e the PCA ti mer.
The duty cycle of each module is independently variable using the modules capture reg-
ister CCAPLn. When the value of the PCA CL SFR is less than the value in the modules
CCAPLn SFR the output will be low, when it is equal to or greater than the output will be
high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn.
This allows updating the PWM without glitches. The PWM and ECOM bits in the mod-
ule's CCAPMn register must be set to enable the PWM mode.
CH CL
CCAPnH CCAPnL
ECOMn CCAPMn , n = 0 to 4
0xDA to 0xDE
CAPNn MATn TOGn PWMn ECCFnCAPPn
16 bit comparator Match
CF CR CCON
0xD8
CCF4 CCF3 CCF2 CCF1 CCF0
PC A IT
Enable
CEXn
PCA c ounter /timer
Write to
CCAPnH
Reset
Wr i te to
CCAPnL
10
48 AT89C51RD2/ED2 4235C–8051–08/03
Figure 21. PCA PWM Mode
PCA Wa tchdog Timer An on- board watchdog timer is a vailable with the PCA to improve the r eliability of the
system without increasing chip count. Watchdog timers are useful for systems that are
susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only
PCA module that can be programmed as a watchdog. However, this module can still be
used for othe r mode s i f the watc hd og i s n ot ne eded . Fig ur e 19 shows a di agram of how
the watchdog works. The user pre-load s a 16-bit v alue in the compare registers. Jus t
like the other compare modes, this 16-bit value is compared to the PCA timer value. If a
match is allowed to occu r, an internal r eset will be genera ted. This will not c ause the
RST pin to be driven high.
In order to hold off the reset, the user has three options:
1. Periodically change the compare value so it will never match the PCA timer.
2. Periodically change the PCA timer value so it will never match the compare
values.
3. Disable the watchdog by clearing the WDTE bit before a match occurs and then
re-enable it.
The first two options ar e more r el iable bec aus e the watc hdog tim er is never disabl ed as
in option #3. If the program c ounter ever goes astray, a mat ch will eve ntually occu r and
cause an in ter nal r es et. The second o pti on i s a lso n ot r ec omm end ed i f ot her P CA m od-
ules are being used. Remember, the PCA timer is the time base for all modules;
changing the time base for other modules would not be a good idea. Thus, in most appli-
cations the first solution is the best option.
This watchdog timer won’t generate a reset out on the reset pin.
CL
CCAPnH
CCAPnL
ECOMn CCAPMn, n= 0 to 4
0xDA to 0xDE
CAPNn MATn TOGn PWMn ECCFnCAPPn
8-bit Comparator CEXn
“0”
“1”
Enable
PCA Counter/Timer
Overflow
49
AT89C51RD2/ED2
4235C–8051–08/03
Seria l I/ O P o rt The serial I/O port in the AT89 C51RD2/ED2 is com patib le with the seri al I/O port in the
80C52.
It provides both synchronous and asynchronous communication modes. It operates as a
Universal Async hronous Receiver and Transmitter (UART) in three full-duplex modes
(Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously
and at different baud rates
Serial I/O port includes the following enhancements:
•Framing error detection
•Automatic address recognition
Framing Error Detection Framing bit error detection is provided for the three asynchronous modes (modes 1, 2
and 3). To enable the framin g bi t erro r de tec tio n feat ur e, se t SMO D0 bit in PCO N regi s-
ter (See Figure 22).
Figure 22. Framing Error Block Diagram
When this feature is enabled, the receiver checks each incoming data frame for a valid
stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous
transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in
SCON registe r (See Ta bl e 33) bit is set.
Software may examine F E bit after each reception to c heck for data errors. Once set,
only software or a reset can clear FE bit. Subsequently received frames with valid stop
bits c annot clear FE b it. When FE feature is enable d, RI r ise s on stop bit i nstead of th e
last data bit (See Figure 23 and Figur e 24).
Figure 23. UART Timings in Mode 1
RITIRB8TB8RENSM2SM1SM0/FE
IDLPDGF0GF1POF-SMOD0SMOD1
To UART Framing Error Control
SM0 to UART Mode Control (SMOD0 = 0)
Set FE Bit if Stop Bit Is 0 (Framing Error) (SMOD0 = 1)
SCON (98h)
PCON (87h)
Data Byte
RI
SMOD0 = X
Stop
Bit
Start
Bit
RXD D7D6D5D4D3D2D1D0
FE
SMOD0 = 1
50 AT89C51RD2/ED2 4235C–8051–08/03
Figure 24. UART Timings in Modes 2 and 3
Automatic Addres s
Recognition The aut oma tic a ddr es s r ec ogn iti on feat ure i s en abl ed when th e m ul tiproce ss or c om mu-
nication feature is enabled (SM2 bit in SCON register is set).
Imple mente d in hard ware, automati c addre ss rec ogniti on enha nces th e multip roces sor
communication feature by allowing the serial port to examine the address of each
inco ming command frame. O nly when the seri al port recogni zes its own addres s, the
receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU
is not interrupted by command frames addressed to other devices.
If desired, the user ma y enabl e the autom atic ad dress r ecogn ition feat ure in Mode 1. In
this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when
the received command frame address matches the device’s address and is terminated
by a valid stop bit.
To supp ort automatic a ddr es s recognitio n, a dev ic e i s ide nti fie d by a given addre ss an d
a broadcast address.
Note: The multiprocessor communication and automatic address recognition features cannot
be enabled in Mode 0 (i. e. setting SM2 bit in SCON register in Mode 0 has no effect).
Given Address Each devi ce h as an indiv idua l ad dress that is specif ie d in SADD R regis ter; t he SADEN
register is a mask byte that contains don’t care bits (defined by zeros) to form the
device’s given address. The don’t care bits provide the flexibility to address one or more
slaves at a time. The following example illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask byte must be 1111
1111b.
For example:
SADDR0101 0110b
SADEN1111 1100b
Given0101 01XXb
The following is an example of how to use given addresses to address different slaves:
Slave A:SADDR1111 0001b
SADEN1111 1010b
Given1111 0X0Xb
Slave B:SADDR1111 0011b
SADEN1111 1001b
Given1111 0XX1b
Slave C:SADDR1111 0010b
SADEN1111 1101b
Given1111 00X1b
RI
SMOD0 = 0
Data Byte Ninth
Bit Stop
Bit
Start
Bit
RXD D8D7D6D5D4D3D2D1D0
RI
SMOD0 = 1
FE
SMOD0 = 1
51
AT89C51RD2/ED2
4235C–8051–08/03
The SADEN byte is selected so that each slave may be addressed separately.
For slave A, bit 0 (the LSB) is a don’t care bit; for slaves B and C, bit 0 is a 1.To commu-
nica te with sla ve A only, th e master m ust send an address where bit 0 is c lear (e. g.
1111 0000b).
For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with
slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both
set (e. g. 1111 0011b).
To communicate with slaves A, B and C, the master must send an address with bit 0 set,
bit 1 clear, and bit 2 clear (e. g. 1111 0001b).
Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers
with zeros defined as don’t care bits, e. g. :
SADDR 0101 0110b
SADEN 1111 1100b
Broadcast = SADDR OR SADEN1111 111Xb
The use of don’t care bits provides flexibility in defining the broadcast address, however
in most applications, a broadcast address is FFh. The following is an example of using
broadcast addresses:
Slave A:SADDR1111 0001b
SADEN1111 1010b
Broadcast1111 1X11b,
Slave B:SADDR1111 0011b
SADEN1111 1001b
Broadcast1111 1X11B,
Slave C:SADDR = 1111 0010b
SADEN1111 1101b
Broadcast1111 1111b
For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with
all of the s lave s, the ma ster mus t send a n add ress F Fh. To com mun icate with slav es A
and B, but not slave C, the master can send and address FBh.
Reset Addresses On reset, the SADDR and SADEN registers are initialized to 00h, i. e. the given and
broadc ast addr esses are XXXX XXXXb (all don ’t car e bits). Thi s ensures tha t the seria l
port will reply to any address , and so, that it is backwar ds compatible with the 80C51
microcontrollers that do not support automatic address recognition.
52 AT89C51RD2/ED2 4235C–8051–08/03
Registers Table 30. SADEN Regist er
SADEN - Slave Address Mask Register (B9h)
Reset Value = 0000 0000b
Not bit address ab le
Table 31. SADDR Register
SADDR - Slave Address Register (A9h)
Reset Value = 0000 0000b
Not bit address ab le
Baud Rate Selection for
UART for Mode 1 and 3 The Baud Rate Generator for transmit and receive clocks can be selected separately via
the T2CON and BDRCON registers.
Figure 25. Baud Rate Selection
76543210
76543210
RCLK
/16
RBCK
INT_BRG
0
1
TIMER1
0
1
0
1
TIMER2
INT_BRG
TIMER1
TIMER2
TIMER_BRG_RX
Rx Clock
/16
0
1
TIMER_BRG_TX
Tx Clock
TBCK
TCLK
53
AT89C51RD2/ED2
4235C–8051–08/03
Table 32. Baud Rate Selection Table UART
Internal Baud Rate Generator
(BRG) When the in ter na l Baud Rate G e nerator is u se d, t he Bau d Rates a re determi ned by th e
BRG overflow depending on the BRL reload value, the value of SPD bit (Speed Mode)
in BDRCON register and the value of the SMOD1 bit in PCON register.
Figure 26. Internal Bau d Rate
•The baud rate for UART is taken by the following formula:
TCLK
(T2CON) RCLK
(T2CON) TBCK
(BDRCON) RBCK
(BDRCON) Clock Source
UART Tx Clock Source
UART Rx
0000Timer 1Timer 1
1000Timer 2Timer 1
0100Timer 1Timer 2
1100Timer 2Timer 2
X010INT_BRGTimer 1
X110INT_BRGTimer 2
0 X 0 1 Timer 1 INT_BRG
1 X 0 1 Timer 2 INT_BRG
X X 1 1 INT_BRG INT_BRG
BRG
0
1
/6
BRL
/2
0
1INT_BRG
SPD
BRR
SMOD1
Auto Reload Counter
Overflow
CLK PERIPH
Baud_Rate = 2SMOD1 x FCLK PERIPH
2 x 2 x 6(1-SPD) x 16 x [256 - (BRL)]
(BRL) = 256 - 2SMOD1 x FCLK PERIPH
2 x 2 x 6(1-SPD) x 16 x Baud_Rate
54 AT89C51RD2/ED2 4235C–8051–08/03
Table 33. SCON Register
SCON - Serial Control Register (98h)
Reset Value = 0000 0000b
Bit addressable
76543210
FE/SM0 SM1 SM2 REN TB8 RB8 TI RI
Bit
Number Bit
Mnemonic Description
7FE
Framing Error bit (SMOD0 = 1)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit.
SM0 Serial port Mode bit 0
Refer to SM1 for serial port mode selection.
SMOD0 must be cleared to enable access to the SM0 bit.
6SM1
Seria l por t Mode bit 1
SM0 SM1 Mode Description Baud Rate
0 0 0 Shift Register FCPU PERIPH/6
0 1 1 8-bit UART Variable
1 0 2 9-bit UART FCPU PERIPH /32 or /16
1 1 3 9-bit UART Variable
5SM2
Serial port Mode 2 bit/Multiprocessor Communicati on Enab le bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and
eventually mode 1.This bit should be cleared in mode 0.
4REN
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
3TB8
Transmitter Bit 8:Ninth bit to transmit in modes 2 and 3
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
2RB8
Receiver Bit 8/Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not
used.
1TI
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning
of the stop bit in the other modes.
0RI
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 23
and Figure 24 in the other modes.
55
AT89C51RD2/ED2
4235C–8051–08/03
Table 34. Example of Computed Value When X2 = 1, SMOD1 = 1, SPD = 1
Table 35. Example of Computed Value When X2 = 0, SMOD1 = 0, SPD = 0
The baud rate generator can be used for mode 1 or 3 (refer to Figure 25.), but also for
mode 0 for UART, thanks to the bit SRC located in BDRCON register (Table 42.)
UART Registers Table 36. SADEN Register
SADEN - Slave Address Mask Register for UART (B9h)
Reset Value = 0000 0000b
Table 37. SADDR Register
SADDR - Slave Address Register for UART (A9h)
Reset Value = 0000 0000b
Baud Rates
FOSC = 16. 384 MHz FOSC = 24 MHz
BRL Error (%) BRL Error (%)
115200 247 1.23 243 0.16
57600 238 1.23 230 0.16
38400 229 1.23 217 0.16
28800 220 1.23 204 0.16
19200 203 0.63 178 0.16
9600 149 0.31 100 0.16
4800 43 1.23 - -
Baud Rates
FOSC = 16. 384 MHz FOSC = 24 MHz
BRL Error (%) BRL Error (%)
4800 247 1.23 243 0.16
2400 238 1.23 230 0.16
1200 220 1.23 202 3.55
600 185 0.16 152 0.16
76543210
76543210
56 AT89C51RD2/ED2 4235C–8051–08/03
Table 38. SBUF Register
SBUF - Serial Buffer Register for UART (99h)
Reset Val ue = XXXX XXX Xb
Table 39. BRL Register
BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah)
Reset Value = 0000 0000b
76543210
76543210
57
AT89C51RD2/ED2
4235C–8051–08/03
Table 40. T2CON Register
T2CON - Timer 2 Control Register (C8h)
Reset Value = 0000 0000b
Bit addressable
76543210
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#
Bit
Number Bit
Mnemonic Description
7TF2
Timer 2 overflow Flag
Must be cleared by software.
Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.
6EXF2
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if
EXEN2 = 1.
When set, causes the CPU to vector to timer 2 interrupt routine when timer 2
interrupt is enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down
counter mode (DCEN = 1)
5 RCLK Receive Clock bit for UART
Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.
4TCLK
Transmit Clock bit for UART
Cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.
3EXEN2
Timer 2 External Enable bit
Cleared to ignore events on T2EX pin for timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is
detected, if timer 2 is not used to clock the serial port.
2TR2
Timer 2 Run control bit
Cleared to turn off timer 2.
Set to tur n on time r 2.
1C/T2#
Timer/Counter 2 select bit
Cleared for timer operation (input from internal clock system: FCLK PERIPH).
Set for counter operation (input from T2 input pin, falling edge trigger). Must be
0 for clock out mode.
0 CP/RL2#
Timer 2 Capture/Reload bit
If RCLK = 1 or TCLK = 1, CP/RL2# is ignored and timer is forced to auto-reload
on timer 2 overflow.
Cleared to auto-reload on timer 2 overflows or negative transitions on T2EX pin
if EXEN2 = 1.
Set to capture on negative transitions on T2EX pin if EXEN2 = 1.
58 AT89C51RD2/ED2 4235C–8051–08/03
Table 41. PCON Register
PCON - Power Control Register (87h)
Reset Value = 00X1 0000b
Not bit address ab le
Power-off flag reset value will be 1 only after a power on (cold r eset). A warm reset
doesn’t affect the value of this bit.
76543210
SMOD1 SMOD0 - POF GF1 GF0 PD IDL
Bit
Number Bit
Mnemonic Description
7SMOD1
Serial port Mode bit 1 for UART
Set to select double baud rate in mode 1, 2 or 3.
6SMOD0
Serial port Mode bit 0 for UART
Cleared to select SM0 bit in SCON register.
Set to select FE bit in SCON register.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4POF
Power-Off Flag
Cleared to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set
by software.
3GF1
Genera l-purpose Fla g
Cleared by user for general-purpose usage.
Set by user for general-purpose usage.
2GF0
Genera l-purpose Fla g
Cleared by user for general-purpose usage.
Set by user for general-purpose usage.
1PD
Power-do wn mo de bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
0IDL
Idle mode bit
Cleared by hardware when interrupt or reset occurs.
Set to enter idle mode.
59
AT89C51RD2/ED2
4235C–8051–08/03
Table 42. BDRCON Register
BDRCON - Baud Rate Control Register (9Bh)
Reset Valu e = XXX0 000 0b
Not bit address ab le
76543210
- - - BRR TBCK RBCK SPD SRC
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4BRR
Baud Rate Run Control bit
Cleared to stop the internal Baud Rate Generator.
Set to start the internal Baud Rate Generator.
3TBCK
Transmission Baud Rate Generator Selection bit for UART
Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
2RBCK
Reception Baud Rate Generator Selection bit for UART
Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
1 SPD Baud Rate Speed Control bit for UART
Cleared to select the SLOW Baud Rate Generator .
Set to select the FAST Baud Rate Generator .
0SRC
Baud Rate Source select bit in Mode 0 for UART
Cleared to select FOSC/12 as the Baud Rate Generator (FCLK PERIPH/6 in X2
mode).
Set to select the internal Baud Rate Generator for UARTs in mode 0.
60 AT89C51RD2/ED2 4235C–8051–08/03
Keyboard Interface The AT89C51RD2/ED2 implements a keyboard interface allowing the connection of a
8 x n matrix keybo ard. It is based o n 8 input s with pr ogramm able in terrupt c apabi lity o n
both high or low level. These inputs are available as alternate function of P1 and allow to
exit from idle and power-down modes.
The k eyb oard i nter faces with the C51 cor e th rough 3 s pecial func tio n regi sters : K BLS ,
the Keyboard Level Selection register (Table 45), KBE, the Keyboard interrupt Enable
register (Table 44), and KBF, the Keyboard Flag register (Table 43).
Interrupt The keyboard inputs are considered as 8 independent interrupt sources sharing the
same interrupt vector. An interrupt enable bit (KBD in IE1) allows global enable or dis-
able of the keyboard interrupt (see Figure 27). As detailed in Figure 28 each keyboard
input has the capability to detect a programmable level according to KBLS. x bit value.
Level detection is then reported in interrupt flags KBF.x that can be masked by software
using KBE. x bits.
This structure allow keyboard arrangement from 1 by n to 8 by n matrix and allows
usage of P1 inputs for other purpose.
Figure 27. Keyboard Interface Block Diagram
Figure 28. Keyboard Input Circuitry
Power Reduction Mode P1 inputs allow exit from idle and power-down modes as detailed in Section “Power
Management”, page 83.
P1:x
KBE.x
KBF.x
KBLS.x
0
1
Vcc
Internal Pullup
P1.0
Keyboard Interface
Interrupt Request
KBD
IE1
Input Circuitry
P1.1 Input Circuitry
P1.2 Input Circuitry
P1.3 Input Circuitry
P1.4 Input Circuitry
P1.5 Input Circuitry
P1.6 Input Circuitry
P1.7 Input Circuitry
KBDIT
61
AT89C51RD2/ED2
4235C–8051–08/03
Registers Table 43. KBF Register
KBF-Keyboard Flag Register (9Eh)
Reset Value = 0000 0000b
76543210
KBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBF0
Bit
Number Bit
Mnemonic Description
7KBF7
Keyboard line 7 flag
Set by hardware when the Port line 7 detects a programmed level. It generates a
Keyboard interrupt request if the KBKBIE.7 bit in KBIE register is set.
Must be cleared by software.
6KBF6
Keyboard line 6 flag
Set by hardware when the Port line 6 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.6 bit in KBIE register is set.
Must be cleared by software.
5KBF5
Keyboard line 5 flag
Set by hardware when the Port line 5 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.5 bit in KBIE register is set.
Must be cleared by software.
4KBF4
Keyboard line 4 flag
Set by hardware when the Port line 4 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.4 bit in KBIE register is set.
Must be cleared by software.
3KBF3
Keyboard line 3 flag
Set by hardware when the Port line 3 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.3 bit in KBIE register is set.
Must be cleared by software.
2KBF2
Keyboard line 2 flag
Set by hardware when the Port line 2 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.2 bit in KBIE register is set.
Must be cleared by software.
1KBF1
Keyboard line 1 flag
Set by hardware when the Port line 1 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.1 bit in KBIE register is set.
Must be cleared by software.
0KBF0
Keyboard line 0 flag
Set by hardware when the Port line 0 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.0 bit in KBIE register is set.
Must be cleared by software.
62 AT89C51RD2/ED2 4235C–8051–08/03
Table 44. KBE Register
KBE-Keyboard Input Enable Register (9Dh)
Reset Value = 0000 0000b
76543210
KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0
Bit
Number Bit
Mnemonic Description
7KBE7
Keyboard line 7 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.7 bit in KBF register to generate an interrupt request.
6KBE6
Keyboard line 6 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.6 bit in KBF register to generate an interrupt request.
5KBE5
Keyboard line 5 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.5 bit in KBF register to generate an interrupt request.
4KBE4
Keyboard line 4 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.4 bit in KBF register to generate an interrupt request.
3KBE3
Keyboard line 3 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.3 bit in KBF register to generate an interrupt request.
2KBE2
Keyboard line 2 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.2 bit in KBF register to generate an interrupt request.
1KBE1
Keyboard line 1 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.1 bit in KBF register to generate an interrupt request.
0KBE0
Keyboard line 0 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.0 bit in KBF register to generate an interrupt request.
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Table 45. KBLS Regis ter
KBLS-Keyboard Level Selector Register (9Ch)
Reset Value = 0000 0000b
76543210
KBLS7 KBLS6 KBLS5 KBLS4 KBLS3 KBLS2 KBLS1 KBLS0
Bit
Number Bit
Mnemonic Description
7KBLS7
Keyboard line 7 Level Selection bit
Cleared to enable a low level detection on Port line 7.
Set to enable a high level detection on Port line 7.
6KBLS6
Keyboard line 6 Level Selection bit
Cleared to enable a low level detection on Port line 6.
Set to enable a high level detection on Port line 6.
5KBLS5
Keyboard line 5 Level Selection bit
Cleared to enable a low level detection on Port line 5.
Set to enable a high level detection on Port line 5.
4KBLS4
Keyboard line 4 Level Selection bit
Cleared to enable a low level detection on Port line 4.
Set to enable a high level detection on Port line 4.
3KBLS3
Keyboard line 3 Level Selection bit
Cleared to enable a low level detection on Port line 3.
Set to enable a high level detection on Port line 3.
2KBLS2
Keyboard line 2 Level Selection bit
Cleared to enable a low level detection on Port line 2.
Set to enable a high level detection on Port line 2.
1KBLS1
Keyboard line 1 Level Selection bit
Cleared to enable a low level detection on Port line 1.
Set to enable a high level detection on Port line 1.
0KBLS0
Keyboard line 0 Level Selection bit
Cleared to enable a low level detection on Port line 0.
Set to enable a high level detection on Port line 0.
64 AT89C51RD2/ED2 4235C–8051–08/03
Serial Port Interface
(SPI) The Serial Peripheral In terface module ( SPI) allows full-duplex, sy nchronous, serial
communication between the MCU and peripheral devices, including other MCUs.
Features Features of the SPI module include the following:
•Full-duplex, three-wire synchronous transfers
•Master or Slave operation
•Eight programmable Master clock rates
•Serial clock with programmable polarity and phase
•Master Mode fault error flag with MCU interrupt capability
•Write collision flag protection
Signal Description Figure 29 shows a typical SPI bus configuration using one Master controller and many
Slave peripherals. The bus is made of three wires connecting all the devices:
Figure 29. SPI Master/Slaves Interconnection
The Master device selects the individual Slave devices by using four pins of a parallel
port to control the four SS pins of the Slave devices.
Master Output Slave Input
(MOSI) This 1-bit signal is directly connected between the Master Device and a Slave Device.
The MOSI line is used to transfer data in series from the Master to the Slave. Therefore,
it is an outp ut s ig nal fr om the M as ter, a nd an input signa l to a S la ve . A b yt e ( 8-b it word)
is transmitted most significant bit (MSB) first, least significant bit (LSB) last.
Master Input Slave Output
(MISO) This 1-bit signal is directly connected between the Slave Device and a Master Device.
The MISO line is used to transfer data in series from the Slave to the Master. Therefore,
it is an output signal from the Slave, and an input signal to the Master. A byte (8-bit
word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last.
SPI Serial Clock (SCK) This signal is used to synchronize the data movement both in and out the devices
through their MOS I and M ISO lines . It is driven by the M aster for eight clock cycles
which allows to exchange one byte on the serial lines.
Slave Sel ect (SS )Each Slave peripher al is selected by one Slave Select pin (SS). This signal must stay
low for any message for a Sla ve. It is obvi ous tha t only one Ma ster (S S high level) can
Slave 1
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
SS
PORT
0
1
2
3
Slave 3
MISO
MOSI
SCK
SS
Slave 4
MISO
MOSI
SCK
SS
Slave 2
MISO
MOSI
SCK
SS
VDD
Master
65
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drive the network. The Master may select each Slave device by software through port
pins (Figu re 29). To pr event bus conflicts on the MISO line, only one slave sh ould be
selected at a time by the Master for a transmission.
In a Master config urati on, the SS line c an be us ed in conju nctio n with the M ODF flag i n
the SPI Status register (SPSTA) to prevent multiple masters from driving MO SI and
SCK (see Error conditions).
A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state.
The SS pin could be used as a general-purpose if the following conditions are met:
•The device is configured as a Master and the SSDIS control bit in SPCON is set.
This kind of configuration can be found when only one Master is driving the network
and th ere i s no way that t he SS pin could be pulled low. Therefore, the MODF flag in
the SPSTA will never be set(1).
•The Device is configured as a Slave with CPHA and SSDIS control bits set(2) This
kind of configuration can happen when the system comprises one Master and one
Slave only. Therefore, the device should always be selected and there is no reason
that the Master uses the SS pin to select the communicating Slave device.
Notes: 1. Clearing SSDIS control bit does not clear MODF.
2. Special care should be taken not to set SSDIS control bit when CPHA = ’0’ because
in this mode, the SS is used to start the transmission.
Baud Rate In Master mode, the baud rate can be selected from a baud rate generator which is con-
trolle d by three bits in th e SPCON regi ster: SPR2, SP R1 and SPR0. The Master c lock
is chos en from on e of sev en cloc k rates re sulting from the di visio n of the inte rnal cl ock
by 2, 4, 8, 16, 32, 64 or 128.
Table 46 gives the different clock rates selected by SPR2:SPR1:SPR0:
Table 46. SPI Master Baud Rate Selection
SPR2 SPR1 SPR0 Clock Rate Baud Rate Divisor (BD)
000 Don’t Use No BRG
001 F
CLK PERIPH /4 4
010 F
CLK PERIPH / 8 8
011 F
CLK PERIPH /16 16
100 F
CLK PERIPH /32 32
101 F
CLK PERIPH /64 64
110 F
CLK PERIPH /128 128
111 Don’t Use No BRG
66 AT89C51RD2/ED2 4235C–8051–08/03
Functional Description Figure 30 shows a detailed structure of the SPI module.
Figure 30. SPI Module Block Diagram
Operating Modes The Serial Peripheral Interface can be configured as one of the two modes: Master
mode or Slave mode. The configuration and initialization of the SPI module is made
through one register:
•The Serial Peripheral CONtrol register (SPCON)
Once the SPI is configured, the data exchange is made using:
•SPCON
•The Serial Peripheral STAtus register (SPSTA)
•The Serial Peripheral DATa register (SPDAT)
During an SP I trans mi ssi on, da ta i s sim ult aneously trans mi tted (shi fted out s eri all y) an d
receiv ed (shifted in serial ly). A s erial cloc k line ( SCK) synchr onizes sh ifting and sam-
pling on the two serial data lines (MOSI and MISO). A Slave Select line (SS) allows
indivi dual selecti on of a Slave SPI devic e; Slave devices that are not selec ted do not
interfere with SPI bus activities.
When the Master device transmits data to the Slave device via the MOSI line, the Slave
device responds by sendi ng data to the Master device via the MISO line. This implies
full-duplex transmission with both data out and data in synchronized with the same clock
(Figure 31).
Shift Registe r01
234567
Internal Bus
Pin
Control
Logic MISO
MOSI
SCK
M
S
Clock
Logic
Clock
Divider
Clock
Select
/4
/64
/128
SPI Interrupt Request
8-bit Bus
1-bit Signal
SS
FCLK PERIPH
/32
/8
/16 Receive Data Register
SPDAT
SPI
Control
SPSTA
CPHA SPR0
SPR1
CPOLMSTRSSDISSPEN
SPR2 SPCON
WCOL MODFSPIF ----
SSERR
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Figure 31. Full-Duplex Master-Slave Interconnection
Maste r Mode The SPI operates in Master mode when the Master bit, MSTR (1), in the SPCON register
is set. Only one Master SPI device can initiate transmissions. Software begins the trans-
mission from a Ma ster SPI module by wr iting to the Serial Periphera l Data Register
(SPDA T). If the shift regist er is empty , the byte is immedia tely transf erred to the shift
register. The byte begins shifting out on MOSI pin under the control of the serial clock,
SCK. Simultaneously, another byte shifts in from the Slave on the Master’s MISO pin.
The transmi ssion ends whe n the Serial Peripheral tr ansfer data fl ag, SPIF, in SPS TA
becomes set. At the same time that SPIF becomes set, the received byte from the Slave
is transferr ed to the receive data register in SPDAT. S oftware clears SPIF by reading
the Serial Peripheral Status register (SPSTA) with the SPIF bit set, and then reading the
SPDAT.
Slave Mode The SPI operates in Slave mode when the Master bit, MSTR (2), in the SPCON register is
cleared. Before a data transmission occurs, the Slave Select pin, SS, of the Slave
device must be set to’0’. SS must remain low until the transmission is complete.
In a Slave SPI module, data enters the shift register under the control of the SCK from
the Master SPI module. After a byte enters the shift register, it is immediately transferred
to the receive data register in SP DAT, and the SPIF bit is set. To prevent an overflow
condition, Slave software must then read the SPDAT before another byte enters the
shift register (3) . A Slave SPI must com plete the wri te to the SPDAT (s hift regist er) at
least one bus cycle before the Master SPI starts a transmission. If the write to the data
register is la te, the SPI transmi ts th e data alread y in the shi ft re giste r from the p revious
transmission.
Transmission Formats Software can select any of four combinations of serial clock (SCK) phase and polari ty
using two bits in the SPCON: the Clock POLarity (CPOL (4)) and the Clock PHAse
(CPHA(4)). CPOL defines the default SCK line level in idle state. It has no significant
effect on the tr ansmiss ion format. CPHA defines the edges on which the input da ta are
sampled and the edges on whi ch the outp ut data a re s hifted (Figure 32 and F igure 33).
The clock phase and polarity should be identical for the Master SPI device and the com-
municating Slave device.
8-bit Shift Register
SPI
Clock Generator
Master MCU
8-bit Shift Register
MISOMISO
MOSI MOSI
SCK SCK
VSS
VDD SSSS Slave MCU
1. The SPI module should be configured as a Master before it is enabled (SPEN set). Also
the Master SPI should be configured before the Slave SPI.
2. The SPI module should be configured as a Slave before it is enabled (SPEN set).
3. The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock
speed.
4. Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN = ’0’).
68 AT89C51RD2/ED2 4235C–8051–08/03
Figure 32. Data Transmission Format (CPHA = 0)
Figure 33. Data Transmission Format (CPHA = 1)
Figure 34. CPHA/SS Timing
As shown in Figure 32, the first SCK edge is the MSB capture strobe. Therefore the
Slave must begin driving its data before the first SCK edge, and a falling edge on the SS
pin is used to start the transmission. The SS pin must be toggled high and then low
between each byte transmitted (Figure 34).
Figure 33 shows an SPI transmission in which CPHA is “1”. In this case, the Master
begins driving its MOSI pin on the first SCK edge. Therefore the Slave uses the first
SCK edge as a start trans mi ssio n signal . Th e SS pin can remain low between transmis-
sions ( Figure 34). T his forma t may be pr effer ed in syst ems hav ing onl y one Ma ster an d
only one Slave driving the MISO data line.
MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB
bit6 bit5 bit4 bit3 bit2 bit1MSB LSB
13245678
Capture point
SS (to Slave)
MISO (from Slave)
MOSI (from Master)
SCK (CPOL = 1)
SCK (CPOL = 0)
SPEN (internal)
SCK Cycle Number
MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB
bit6 bit5 bit4 bit3 bit2 bit1
MSB LSB
132 45678
Capture point
SS (to Slave)
MISO (from Slave)
MOSI (from Ma s ter )
SCK (CPOL = 1)
SCK (CPOL = 0)
SPEN (internal)
SCK Cycle Number
Byte 1 Byte 2 Byte 3
MISO/MOSI
Master SS
Slave SS
(CPHA = 1)
Slave SS
(CPHA = 0)
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Error Conditions The following flags in the SPSTA signal SPI error conditions.
Mode Fault (MODF) Mode Fault (MODF) error in Master mode SPI indicates that the level on the Slave
Sele ct (SS) pin is in consistent wit h the actual mode of the dev ice. MODF is set to warn
that th ere c ould be a multi- master conf lict for syste m cont rol. In th is cas e, the S PI sys -
tem is affected in the following ways:
•An SPI receiver/error CPU interrupt request is generated
•The SPEN bit in SPCON is cleared. This disable the SPI
•The MSTR bit in SPCON is cleared.
When SS Disable (SSDIS) bi t in the SPCON regi ster is cleared, the MODF flag is set
when the SS signal becomes “0”.
Howeve r, for a sy st em with one Ma ste r, if the SS pi n of the Mas ter d evic e i s pul led lo w,
there is no way that another Master may a ttempt to drive the network. In this case, to
prevent the MODF fla g from being set, software can set the SSDIS bi t in the S PCON
register and therefore the SS pin becomes a general-purpose I/O pin.
Clearin g the MO DF bi t is acc omp li sh ed b y a re ad of SP STA r egi ste r w ith MO DF bit se t,
followed by a write to the SPCON register. SPEN Control bit may be restored to its orig-
inal set state after the MODF bit has been cleared.
Write Collision (WCOL) A Write Collision (WCOL) flag in the SPSTA is set when a write to the SPDAT register is
done during a transmit sequence.
WCOL does not cause an interruption, and the transfer continues uninterrupted.
Clear ing the WCOL bit i s done throug h a software s equence of an acce ss to SPSTA
and an access to SPDAT.
Overru n Condition An ove rrun con dition o ccurs wh en the M aster dev ice trie s to s end sev eral data bytes
and the Slav e device has no t cleared the SP IF bit issued from the previous data byte
transmition. In this case, the receiver buffer contains the byte sent after the SPIF bit was
last cleared. A read of the SPDAT returns this byte. All others bytes are lost.
This condition is not detected by the SPI peripheral.
Interrupts Two SPI status flags can generate a CPU interrupt requests.
Table 47. SPI Interrupts
Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer
has been completed. SPIF bit generates transmitter CPU interrupt requests.
Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is
inconsistent with the mode of the SPI. MODF with SSDIS reset, generates receiver/error
CPU interrupt requests. When SSDIS is set, no MODF interrupt request is generated.
Figure 35 gives a logical view of the above statements.
Flag Request
SPIF (SP data transfer) SPI Transmitter Interrupt request
MODF (Mode Fault) SPI Receiver/Error Interrupt Request (if SSDIS = ’0’)
70 AT89C51RD2/ED2 4235C–8051–08/03
Figure 35. SPI Interrupt Requests Generation
Registers There are three registers in the module that provide control, status and data storage functions. These registers
are describes in the following paragraphs.
Serial Peripheral Control
Register (SPCON) •The Serial Peripheral Control Register does the following:
•Selects one of the Master clock rates
•Configure the SPI module as Master or Slave
•Selects serial clock polarity and phase
•Enab le s the SP I modul e
•Frees the SS pin for a general-purpose usage
Table 48 describes this register and explains the use of each bit.
SSDIS
MODF
CPU Inte rr upt Requ est
SPI Receiver/Error
CPU Interrupt Request
SPI Transmitter SPI
CPU Interrupt Request
SPIF
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Table 48. SPCON Register
SPCON - Serial Peripheral Control Register (0C3H)
Reset Value = 0001 0100b
Not bit address ab le
76543210
SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0
Bit Number Bit Mnemonic Description
7 SPR2 Serial Peripheral Rate 2
Bit with SPR1 and SPR0 define the clock rate.
6SPEN
Serial Peripheral Enable
Cleared to disable the SPI interface.
Set to enable the SPI interface.
5 SSDIS
SS Disable
Cleared to enable SS in both Master and Slave modes.
Set to disable SS in both Master and Slave modes. In Slave mode,
this bit has no effect if CPHA = ’0’.
When SSDIS is set, no MODF interrupt request is generated.
5MSTR
Serial Peripheral Master
Cleared to configure the SPI as a Slave.
Set to configure the SPI as a Master.
4CPOL
Clock Polarity
Cleared to have the SCK set to ’0’ in idle state.
Set to h a ve th e SCK set to ’1’ in idle low.
3CPHA
Clock Phase
Cleared to have the data sampled when the SCK leaves the idle
state (see CPOL).
Set to have the data sampled when the SCK returns to idle state (see
CPOL).
2 SPR1 SPR2 SPR1 SPR0 Serial Peripheral Rate
0 0 0 Invalid
00 1 F
CL K PE RIPH /4
01 0 F
CL K PE RIPH /8
01 1 F
CL K PE RIPH /16
10 0 F
CL K PE RIPH /32
10 1 F
CL K PE RIPH /64
11 0 F
CL K PE RIPH /128
1 1 1 Invalid
1 SPR0
72 AT89C51RD2/ED2 4235C–8051–08/03
Serial Peripheral Status Register
(SPSTA) The Serial Peripheral Status Register contains flags to signal the following conditions:
•Data trans fer comple te
•Write collision
•Inconsistent logic level on SS pin (mode fault error)
Table 49 describes the SPSTA register and explains the use of every bit in the register.
Table 49. SPSTA Register
SPSTA - Serial Peripheral Status and Control register (0C4H)
Reset Value = 00X0 XXXXb
Not Bit addressable
76543210
SPIFWCOLSSERRMODF----
Bit
Number Bit
Mnemonic Description
7SPIF
Serial Peripheral data transfer flag
Cleared by hardware to indicate data transfer is in progress or has been
approved by a clearing sequence.
Set by hardware to indicate that the data transfer has been completed.
6WCOL
Write Collision fla g
Cleared by hardware to indicate that no collision has occurred or has been
approved by a clearing sequence.
Set by hardware to indicate that a collision has been detected.
5SSERR
Synchronous Seri al Slave Error flag
Set by hardware when SS is deasserted before the end of a received data.
Cleared by disabling the SPI (clearing SPEN bit in SPCON).
4MODF
Mo de F a ult
Cleared by hardware to indicate that the SS pin is at appropriate logic level, or
has been approved by a clearing sequence.
Set by hardware to indicate that the SS pin is at inappropriate logic level.
3-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
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Serial Peri ph eral Data Regi s ter
(SPDAT) The Serial Peripheral Data Register (Table 50) is a read/write buffer for the receive data
register. A write to SPDAT places data directly into the shift register. No transmit buffer is
available in this model.
A Read of the SPDAT returns the value located in the receive buffer and not the content
of the shift register.
Table 50. SPDAT Register
SPDAT - Serial Peripheral Data Register (0C5H)
Reset Value = Indeterm inate
R7:R0: Receive data bits
SPCON, SPSTA and S PDAT reg isters may be read and wr itten at any time wh ile th ere
is no ongoing exchange. However, special care should be taken when writing to them
while a transmission is ongoing:
•Do not change SPR2, SPR1 and SPR0
•Do not change CPHA and CPOL
•Do not change MSTR
•Clearing SPEN would immediately disable the peripheral
•Writing to the SPDAT will cause an overflow
76543210
R7 R6 R5 R4 R3 R2 R1 R0
74 AT89C51RD2/ED2 4235C–8051–08/03
Interrupt System The AT89C51RD2/ED2 has a total of 9 interrupt vectors: two external interrupts (INT0
and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI inter-
rupt, Keyboard interrupt and the PCA global interrupt. These interrupts are shown in
Figure 36.
Figure 36. Interrupt Control System
Each of the interrupt sources can be individually enabled or disabled by setting or clear-
ing a bit in the Interrupt Enable reg ister (Table 54 and T able 56). This registe r also
contains a global disable bit, which must be cleared to disable all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority lev-
els by setting or c learing a bit in the Interrupt Priority regi ster (Table 57) and in t he
Interru pt P rio ri ty Hi gh re gis te r ( Table 55 an d Ta ble 56) shows th e b it va lue s and pr io rity
levels associated with each combination.
IE1
0
3
High Priority
Interrupt
Interrupt
Polling
Sequence, Decreasing from
High to Low Priority
Low Priority
Interrupt
Global Disable
Individual Enable
EXF2
TF2
TI
RI
TF0
INT0
INT1
TF1
IPH, IPL
IE0
0
3
0
3
0
3
0
3
0
3
0
3
PCA IT
KBD IT
SPI IT
0
3
0
3
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Registers The PCA interrupt vector is located at address 0033H, the SPI interrupt vector is located
at addres s 004B H and Keybo ard int erru pt vector is locate d at addr ess 0 03BH. All ot her
vectors addresses are the same as standard C52 devices.
Table 51. Priority Level Bit Values
A low-pr iori ty inte rrupt can be int errupt ed by a high priori ty inte rrupt, but not b y an other
low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt
source.
If two interrupt requests of different priority levels are received simultaneously, the
reques t of high er prio rity lev el is s ervic ed. If in terr upt reques ts of th e same priori ty le vel
are received simultaneously, an internal polling sequence determines which request is
serviced. Thus within each priority level there is a second priority structure determined
by the polling sequence.
IPH.x IPL.x Interrupt Level Priority
0 0 0 (Lowest)
011
102
1 1 3 (Highest)
76 AT89C51RD2/ED2 4235C–8051–08/03
Interrupt Sources and
Vector Addresses Table 52. Interr up t Source s and Vec tor Addre sses
Number Polling Priority Interrupt Source Interrupt
Request Vect or
Address
0 0 Reset 0000h
1 1 INT0 IE0 0003h
2 2 Timer 0 TF0 000Bh
3 3 INT1 IE1 0013h
4 4 Timer 1 IF1 001Bh
5 6 UART RI+TI 0023h
6 7 Timer 2 TF2+EXF2 002Bh
7 5 PCA CF + CCFn (n = 0 - 4) 0033h
8 8 Keyboard KBDIT 003Bh
9 9 - - 0043h
10 10 SPI SPIIT 004Bh
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Table 53. IENO Register
IEN0 - Interrupt Enable Register (A8h)
Reset Value = 0000 0000b
Bit addressable
76543210
EA EC ET2 ES ET1 EX1 ET0 EX0
Bit
Number Bit
Mnemonic Description
7EA
Enable All interrupt bit
Cleared to disable all interrupts.
Set to enable all interrupts.
6EC
PCA interrupt ena ble bit
Cleared to disable.
Set to enable.
5ET2
Timer 2 overflow interrupt Enable bit
Cleared to disable timer 2 overflow interrupt.
Set to enable timer 2 overflow interrupt.
4ES
Seria l port Enable bit
Cleared to disable serial port interrupt.
Set to enable serial port interrupt.
3ET1
Timer 1 overflow interrupt Enable bit
Cleared to disable timer 1 overflow interrupt.
Set to enable timer 1 overflow interrupt.
2 EX1 External interrupt 1 Enable bit
Cleared to disable external interrupt 1.
Set to enable external interrupt 1.
1ET0
Timer 0 overflow interrupt Enable bit
Cleared to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.
0 EX0 External interrupt 0 Enable bit
Cleared to disable external interrupt 0.
Set to enable external interrupt 0.
78 AT89C51RD2/ED2 4235C–8051–08/03
Table 54. IPL0 Register
IPL0 - Interrupt Priority Register (B8h)
Reset Value = X000 0000b
Bit addressable
76543210
- PPCL PT2L PSL PT1L PX1L PT0L PX0L
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6PPCL
PCA interrupt Prio rity bit
Refer to PPCH for priority level.
5PT2L
Timer 2 overflow interrupt Priority bit
Refer to PT2H for priority level.
4 PSL Serial por t Priority bit
Refer to PSH for pri o rity level.
3PT1L
Timer 1 overflow interrupt Priority bit
Refer to PT1H for priority level.
2PX1L
External interrupt 1 Priority bit
Refer to PX1H for priority level.
1PT0L
Timer 0 overflow interrupt Priority bit
Refer to PT0H for priority level.
0PX0L
External interrupt 0 Priority bit
Refer to PX0H for priority level.
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Table 55. IPH0 Register
IPH0 - Interrupt Priority High Register (B7h)
Reset Value = X000 0000b
Not bit address ab le
76543210
- PPCH PT2H PSH PT1H PX1H PT0H PX0H
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6PPCH
PCA interrupt Priority high bit.
PPCH PPCL Priority Level
0 0 Lowest
01
10
1 1 Highest
5PT2H
Timer 2 overflow interrupt Priority High bit
PT2H PT2L Priority Level
0 0 Lowest
01
10
1 1 Highest
4PSH
Serial port Priority High bit
PSH PSL Priority Level
0 0 Lowest
0 1
1 0
1 1 Highest
3PT1H
Timer 1 overflow interrupt Priority High bit
PT1H PT1L Priorit y Level
0 0 Lowest
01
10
1 1 Highest
2PX1H
External interrupt 1 Priority High bit
PX1H PX1L Priority Level
0 0 Lowest
01
10
1 1 Highest
1PT0H
Timer 0 overflow interrupt Priority High bit
PT0H PT0L Priority Level
0 0 Lowest
0 1
10
1 1 Highest
0PX0H
External interrupt 0 Priority High bit
PX0H PX0L Priority Level
0 0 Lowest
01
10
1 1 Highest
80 AT89C51RD2/ED2 4235C–8051–08/03
Table 56. IEN1 Register
IEN1 - Interrupt Enable Register (B1h)
Reset Val ue = XXXX X000b
Bit addressable
76543210
-----SPITWIKBD
Bit
Number Bit
Mnemonic Description
7-Reserved
6-Reserved
5-Reserved
4-Reserved
3-Reserved
2SPI
SPI int e r r upt Enable bit
Cleared to disable SPI interrupt.
Set to enable SPI interrupt.
1Reserved
0KBD
Keyboard interrupt Enable bit
Cleared to disable keyboard interrupt.
Set to enable keyboard interrupt.
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Table 57. IPL1 Register
IPL1 - Interrupt Priority Register (B2h)
Reset Val ue = XXXX X000b
Bit addressable
76543210
-----SPIL
TWIL KBDL
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2SPIL
SPI interrupt Priority bit
Refer to SPIH for priority level.
1-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0KBDL
Keyboard interrupt Priority bit
Refer to KBDH for priority level.
82 AT89C51RD2/ED2 4235C–8051–08/03
Table 58. IPH1 Register
IPH1 - Interrupt Priority High Register (B3h)
Reset Val ue = XXXX X000b
Not bit address ab le
76543210
-----SPIH
-KBDH
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2SPIH
SPI int e r r upt Priority High bit
SPIH SPIL Priority Level
0 0 Lowest
0 1
1 0
1 1 Highest
1-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0KBDH
Keyboard interrupt Priority High bit
KB DH KBDL Priorit y Level
0 0 Lowest
0 1
10
1 1 Highest
83
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Power Management
Introduction Two power redu cti on mo des are implem ente d in the AT 8 9C51 RD2/ED2. The Idle mode
and the Power-Down mode. These modes are detailed in the following sections. In addi-
tion to these power reduction modes, the cl ocks of the core and p eripherals can be
dynamically divided by 2 using the X2 mode detailed in Section “Enhanced Features”,
page 18.
Idle Mode Idle mode is a power reduction mode that reduces the power consumption. In this mode,
progra m execution halts . Idle mode freezes the clock to the CPU at kn own states while
the peripherals continue to be clocked. The CPU status before entering Idle mode is
preserved, i.e., the program counter and program status word register retain their data
for the du ratio n of Idle mode. Th e conte nts of t he SFRs and RAM are als o ret ained. Th e
status of the Port pins during Idle mode is detailed in Table 59.
Entering Idle Mode To enter Idle mode, set the IDL bit in PCON register (see Table 60). The
AT89C51RD2/ED2 enters Idle mode upon execution of the instruction that sets IDL bit.
The instruction that sets IDL bit is the last instruction executed.
Note: If IDL bit and PD bit are set simultaneously, the AT89C51RD2/ED2 enters Power-Down
mode. Then it does not go in Idle mode when exiting Power-Down mode.
Exiting Idle Mode There are two ways to exit Idle mode:
1. Generate an enabled interrupt.
–Hardware clears IDL bit in PCON register which restores the clock to the
CPU. Execution resumes with the interrupt service routine. Upon completion
of the interrupt service routine, program execution resumes with the
instruction immediately following the instruction that activated Idle mode.
The general purpose flags (GF1 and GF0 in PCON register) may be used to
indicate whether an interrupt occurred during normal operation or during Idle
mode. When Idle mode is exited by an interrupt, the interrupt service routine
may examine GF1 and GF0.
2. Generate a reset.
–A logic high on the RST pin clears IDL bit in PCON register directly and
asynchronously. This restores the clock to the CPU. Program execution
momentarily resumes with the instruction immediately following the
instruction that activated the Idle mode and may continue for a number of
clock cycles before the internal reset algorithm takes control. Reset
initializes the AT89C51RD2/ED2 and vectors the CPU to address C:0000h.
Note: During the tim e tha t ex ecu tio n res um es , the in tern al R AM cann ot be acc es sed; how e ve r,
it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port
pins, the instruction immediately following the instruction that activated Idle mode should
not write to a Port pin or to the external RAM.
Power-Down Mode The Power-Down mode places the AT89C51RD2/ED2 in a very low power state.
Power- Down mod e s top s th e o sc illa tor , freezes a ll cl ock at know n s tate s. Th e CPU s ta-
tus prior to entering Power-Down mode is preserved, i.e., the program counter, program
status word r egiste r reta in th eir data for the dur ation of P ower- Down m ode. In add it ion,
84 AT89C51RD2/ED2 4235C–8051–08/03
the SFR and RAM contents are preserved. The status of the Port pins during Power-
Down mode is detailed in Table 59.
Note: VCC may be reduced to as low as VRET during Power-Down mode to further reduce
power dissipation. Take care, however, that VDD is not reduced until Power-Down mode
is invoked.
Entering Power-Down Mode To enter Power-Down mode, set PD bit in PCON register. The AT89C51RD2/ED2
enters th e Power-D own mode upon execution of the instru ction that sets PD bit. The
instruction that sets PD bit is the last instruction executed.
Exiting Power-Down Mode Note: If VCC was reduced during the Power-Down mode, do not exit Power-Down mode until
VCC is restored to the normal operating level.
There are two ways to exit the Power-Down mode:
1. Generate an enabled external interrupt.
–The AT89C51RD2/ED2 provides capability to exit from Power-Down using
INT0#, INT1#.
Hardware clears PD bit in PCON register which starts the oscillator and
restores the clocks to the CPU and peripherals. Using INTx# input,
execution resumes when the input is released (see Figure 37). Execution
resumes with the interrupt service routine. Upon completion of the interrupt
service routine, program execution resumes with the instruction immediately
following the instruction that activated Power-Down mode.
Note: The external interrupt used to exit Power-Down mode must be configured as level sensi-
tive (INT0# and INT1#) and must be assigned the highest priority. In addition, the
duration of the interrupt must be long enough to allow the oscillator to stabilize. The exe-
cution will only resume when the interrupt is deasserted.
Note: Exit fr om pow e r-down by extern al i nte rrupt does not a f f ect the SFRs nor th e in tern al RAM
content.
Figure 37. Power-Down Exit Waveform Using INT1:0#
2. Generate a reset.
–A logic high on the RST pin clears PD bit in PCON register directly and
asynchronously. This starts the oscillator and restores the clock to the CPU
and peripherals. Program execution momentarily resumes with the
instruction immediately following the instruction that activated Power-Down
mode and may continue for a number of clock cycles before the internal
reset algorithm takes control. Reset initializes the AT89C51RD2/ED2 and
vectors the CPU to address 0000h.
Note: During the tim e tha t ex ecu tio n res um es , the in tern al R AM cann ot be acc es sed; how e ve r,
it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port
INT1:0#
OSC
Power-down phase Oscillator restart phase Active phaseActive phase
85
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pins, the instruction immediately following the instruction that activated the Power-Down
mode should not write to a Port pin or to the external RAM.
Note: Exit from power-down by reset redefines all the SFRs, but does not affect the internal
RAM content.
Table 59. Pin Conditions in Special Operating Modes
Mode Port 0 Port 1 Port 2 Port 3 Port 4 ALE PSEN#
Reset Floating High High High High High High
Idle
(internal
code) Data Data Data Data Data High High
Idle
(external
code) Floating Data Data Data Data High High
Power-
Down(inter
nal code) Data Data Data Data Data Low Low
Power-
Down
(external
code)
Floating Data Data Data Data Low Low
86 AT89C51RD2/ED2 4235C–8051–08/03
Registers Table 60. PCON Register
PCON (S87:h) Power configuration Register
Rese t Value= XXXX 0000b
76543210
----GF1GF0PD IDL
Bit
Number Bit
Mnemonic Description
7-4 - Reserved
The value read from these bits is indeterminate. Do not set these bits.
3GF1
General Purpose flag 1
One use is to indicate whether an interrupt occurr ed during normal operation or
during Idle mode.
2GF0
General Purpose flag 0
One use is to indicate whether an interrupt occurr ed during normal operation or
during Idle mode.
1PD
Power-Down Mode bit
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Power-Down mode.
If IDL and PD are both set, PD takes precedenc e.
0IDL
Idle Mode bit
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Idle mode.
If IDL and PD are both set, PD takes precedenc e.
87
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Hardware Wa tchdo g
Timer The WDT is intended as a r ecovery method in situations where the CPU may be sub-
jected to software upset. The WDT consists of a 14-bit counter and the Watchdog Timer
ReSeT (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable
the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location
0A6H . When WDT is enable d, it will incremen t every mac hine cy cle whil e the oscil lator
is running and there is no way to disable the WDT except through reset (either hardware
reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH
pulse at the RST-pin.
Using the WDT To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR
location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH
and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it
reaches 16383 (3FFFH) and this will reset the device. When W DT is enabled, it will
increment every machine cycle while the oscillator is running. This means the user must
reset the WDT at least every 16383 machine cycle. To reset the WDT the user must
write 01 EH and 0 E1H to WDTRST . WDTRS T i s a wri te onl y r egi st er. T he W DT coun ter
cannot be read or written. When WDT overflows, it will generate an output RESET pulse
at the RST-pin. The RESET pulse duration is 96 x TCLK PERIPH, where TCLK PERIPH= 1/FCLK
PERIPH. To make the best use of the WDT, it should be serviced in those sections of code
that will periodically be executed within the time required to prevent a WDT reset.
To have a more powerful WDT, a 27 counter has been added to ext end the Time-ou t
capability, ranking from 16 ms to 2s @ FOSCA = 12 MHz. To manage this feature, refer to
WDTPRG register description, Table 61. The WDTPRG register should be configured
before the WDT activation sequence, and can not be modified until next reset.
Table 61. WDTRST Register
WDTRST - Watchdog Reset Register (0A6h)
Reset Val ue = XXXX XXX Xb
Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in
sequence.
76543210
--------
88 AT89C51RD2/ED2 4235C–8051–08/03
Table 62. WDTPRG Register
WDTPRG - Watchdog Timer Out Register (0A7h)
Reset Val ue = XXXX X000
WDT during Power-down
and Idle In Power-down m ode the osc illator stops, whi ch means th e WDT also s tops. While i n
Power-down mode the us er doe s n ot ne ed to se rvi ce t he W DT . The re ar e 2 m etho ds of
exiting Power-down mode: by a hardware reset or via a level activated external inter-
rupt which is enabled prior to entering Power-down mode. When Power-down is exited
with hardware reset, servicing the WDT should occur as it normally should whenever the
AT89C51RD2/ED2 is reset. Exiting Power-down with an interrupt is significantly differ-
ent. The interrupt is held low long enough for the oscilla tor to stabilize. When the
interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the
device while the interrupt pin is held low, the WDT is not started until the interrupt is
pulled high. It is suggested that the WDT be reset during the interrupt service routine.
To ensure that the WDT does not overflow within a few states of exiting of powerdown, it
is better to reset the WDT just before entering powerdown.
In the Idle mo de, the oscill ator con tin ues to r un. To pr even t the W DT from rese tting th e
AT89C51RD2 /ED2 while in Idle mode, the user should alway s set up a timer that will
periodically exit Idle, service the WDT, and re-enter Idle mode.
76543210
-----S2S1S0
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is undetermined. Do not try to set this bit.
6-
5-
4-
3-
2S2WDT Time-out select bit 2
1S1WDT Time-out select bit 1
0S0WDT Time-out select bit 0
S2 S1 S0 Selected Time-out
000 (2
14 - 1) machine cycles, 16. 3 ms @ FOSCA =12 MHz
001 (2
15 - 1) machine cycles, 32.7 ms @ FOSCA=12 MHz
010 (2
16 - 1) machine cycles, 65. 5 ms @ FOSCA=12 MHz
011 (2
17 - 1) machine cycles, 131 ms @ FOSCA=12 MHz
100 (2
18 - 1) machine cycles, 262 ms @ FOSCA=12 MHz
101 (2
19 - 1) machine cycles, 542 ms @ FOSCA=12 MHz
110 (2
20 - 1) machi ne cyc le s, 1.05 ms @ FOSCA=12 MHz
111 (2
21 - 1) machi ne cyc le s, 2.09 ms @ FOSCA=12 MHz
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AT89C51RD2/ED2
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ONCE® Mode (ON-
Chip Emulation) The ONCE mode fac ilita tes test ing and deb uggi ng of system s us in g AT89 C51RD2/ED2
without r emovi ng the cir cuit fr om the bo ard. Th e ONCE mode is i nvoked b y drivi ng ce r-
tain pins of the AT89C51RD2/ED2; the following sequence must be exercised:
•Pull ALE low while the device is in reset (RST high) and PSEN is high.
•Hold ALE low as RST is deactivated.
While the AT89C51RD2/ED2 is in ONCE mode, an emulator or test CPU can be used to
drive the circuit. Table 63 shows the status of the port pins during ONCE mode.
Normal operation is restored when normal reset is applied.
Table 63. External Pin Status During ONCE Mode
ALE PS EN Port 0 Port 1 Port 2 Port 3 Port I2 XTALA1/2 XTALB1/2
Weak
pull-up Weak
pull-up Float Weak
pull-up Weak
pull-up Weak
pull-up Float Active Active
90 AT89C51RD2/ED2 4235C–8051–08/03
Power-off Flag The power -off flag al lows the us er to distingu ish betwee n a “cold start” reset an d a
“warm start” reset.
A cold s tart re set is th e one indu ced by V CC switch-on. A warm start reset occurs while
VCC is still applied to the device and could be generated for example by an exit from
power-down.
The power-off flag (POF) is located in PCON reg ister (Table 64). POF is set by hard -
ware when VCC rises from 0 to its nominal voltage. T he POF can be set or cleared by
software allowing the user to determine the type of reset.
Table 64. PCON Register
PCON - Power Control Register (87h)
Reset Value = 00X1 0000b
Not bit address ab le
76543210
SMOD1 SMOD0 - POF GF1 GF0 PD IDL
Bit
Number Bit
Mnemonic Description
7SMOD1
Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
6SMOD0
Serial port Mode bit 0
Cleared to select SM0 bit in SCON register .
Set to select FE bit in SCON register .
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4POF
Power-Off Flag
Cleared by software to recognize the next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by
software.
3GF1
General- purpose Fl ag
Cleared by user for general-purpose usage.
Set by user for general-purpose usage.
2GF0
General- purpose Fl ag
Cleared by user for general-purpose usage.
Set by user for general-purpose usage.
1PD
Power-down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
0IDL
Idle mode bit
Cleared by hardware when interrupt or reset occurs.
Set to enter idle mode.
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Reduced EMI Mode The ALE signal is used to demultiplex address and data buses on port 0 when used with
external progr am or data memory. Neverthel ess, during internal code execu tion, ALE
signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting
AO bit.
The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no
longer output but remains active during MOVX and MOV C instructions and external
fetches. During ALE disabling, ALE pin is weakly pulled high.
Table 65. AUXR Register
AUXR - Auxiliary Register (8Eh)
Reset Val ue = XX00 10’HSB. XRAM’0b
Not bit address ab le
76543210
DPU - M0 XRS2 XRS1 XRS0 EXTRAM AO
Bit
Number Bit
Mnemonic Description
7DPU
Disable Weak Pull-up
Cleared by software to activate the permanent weak pull-up (default)
Set by software to disable the weak pull-up (reduce power consumpt ion)
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5M0
Pulse length
Cleared to stretch MOVX control: the RD and the WR pulse length is 6 clock
periods (default).
Set to stret c h MO VX con tr ol : the RD and the WR pulse length is 30 clock
periods.
4XRS2X RAM Size
XRS2 XRS1 XRS0 XRAM size
0 0 0 256 bytes
0 0 1 512 bytes
0 1 0 768 bytes(default)
0 1 1 1024 bytes
1 0 0 1792 bytes
3XRS1
2XRS0
1EXTRAM
EXTRAM bit
Cleared to access internal XRAM using MOVX @ Ri/ @ DPTR.
Set to access external memory.
Programmed by hardware after Powe r-up regarding Hardware Sec urity Byte
(HSB), default setting, XRAM selected.
0AO
ALE Output bi t
Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if
X2 mode is used) (default). Set, ALE is active only during a MOVX or MOVC
instruction is used.
92 AT89C51RD2/ED2 4235C–8051–08/03
EEPROM Data
Memory This feature is available only for the AT89C51ED2 device.
The 2K bytes on- chip E EPRO M memo ry block is loc ated at address es 00 00h to 0 7FFh
of the XRAM/ERAM memory space and is selected by setting control bits in the EECON
register.
A read or write access to the EEPROM memory is done with a MOVX instruction.
Write Data Data is written by byte to the EEPROM memory block as for an external RAM memory.
The following procedure is used to write to the EEPROM memory:
•Check EEBUSY flag
•If the user application interrupts routines use XRAM memory space: Save and
disable interrupts.
•Load DPTR with the address to write
•Store A register with the data to be written
•Set bit EEE of EECON register
•Execute a MOVX @DPTR, A
•Clear bit EEE of EECON re gist er
•Restore interrupts.
•EEBUSY flag in EECON is then set by hardware to indicate that programming is in
progress and that the EEPROM segment is not available for reading or writing.
•The end of programming is indicated by a hardware clear of the EEBUSY flag.
Figure 38 represents the optimal write sequence to the on-chip EEPROM data memory.
93
AT89C51RD2/ED2
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Figure 38. Recommended EEPROM Data Write Sequence
EEPROM Data Write
Sequence
Data Write
DPTR= Address
ACC= Data
Exec: MOVX @DPTR, A
Last Byte
to Load?
EEPROM Mappi ng
EECON = 00h (EEE=0)
Save & Disable IT
EA= 0
Restore IT
EEPROM Data Mappi ng
EECON = 02h (EEE=1)
EEBusy
Cleared?
94 AT89C51RD2/ED2 4235C–8051–08/03
Read Data The following procedure is used to read the data stored in the EEPROM memory:
•Check EEBUSY flag
•If the user application interrupts routines use XRAM memory space: Save and
disable interrupts.
•Load DPTR with the address to read
•Set bit EEE of EECON register
•Execute a MOVX A, @DPTR
•Clear bit EEE of EECON re gist er
•Restore interrupts.
Figure 39. Recommended EEPROM Data Read Sequence
EEPROM Data R ead
Sequence
Data Read
DPTR= Address
ACC= Data
Exec: MOVX A, @DPTR
Last Byte
to Read?
EEPROM Data Mapping
EECON = 02h (EEE=1)
EEPROM Data Mapping
EECON = 00h (EEE = 0
Save & Disable IT
EA= 0
Restore IT
EEBusy
Cleared?
95
AT89C51RD2/ED2
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Registers Table 66. EECON Register
EECON (S:0D2h)
EEPROM Control Register
Reset Val ue = XXXX XX00 b
Not bit address ab le
76543210
------EEEEEBUSY
Bit Number Bit
Mnemonic Description
7 - 2 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
1EEE
Enable EEPROM Space bit
Set to map the EEPROM space during MOVX instructions (Write or Read to
the EEPROM .
Clear to map the XRAM space during MOVX.
0EEBUSY
Progr amm ing Busy flag
Set by hardware when programming is in progress.
Cleared by hardware when programming is done.
Can not be set or cleared by software.
96 AT89C51RD2/ED2 4235C–8051–08/03
Flash/EEPROM
Memory The Flash memory increases EEPROM and ROM functionality with in-circuit electrical
erasure an d pr og rammi ng . It co ntai ns 64K bytes of pr og ram me mor y organ iz ed r espe c-
tively i n 512 pages of 128 bytes. This me mory is both pa rallel and ser ial In-System
Programmable (ISP). ISP allows devices to alter their own program memory in the
actual end product under software control. A default serial loader (bootloader) program
allows ISP of the Flash.
The pro gramming does not require externa l d edi ca ted p ro gr amm in g v olt age. Th e ne c-
essary high programming voltage is generated on-chip using the standard VCC pins of
the microcontroller.
Features •Flash EEPROM Internal Program Memory
•Boot vector allows user provided Flash loader code to reside anywhere in the Flash
memor y space. This configuration provides flexibility to the user.
•Default loader in Boot ROM allows programming via the serial port without the need
of a user provided loader.
•Up to 64K bytes external program memory if the internal program memory is
disabled (EA = 0).
•Programming and erasing voltage with standard power supply
•Read/Programming/Erase:
–Byte-wise read without wait state
–Byte or page erase and programming (10 ms)
•Typical programming time (64K bytes) is 22s with on chip serial bootloader
•Parallel programming with 87C51 compatible hardware interface to programmer
•Programmable security for the code in the Flash
•100K write cycles
•10 years data retention
Flash Programming and
Erasure The 64 -K b yte Fl ash is prog rammed by by tes or b y pages of 12 8 by tes. It is not ne ces-
sary to erase a byte or a page before programming. The programming of a byte or a
page includes a self erase before programming.
There are three methods of programming the Flash memory:
1. The on-chip ISP bootloader may be invoked which will use low level routines to
program the pages. The interface used for serial downloading of Flash is the
UART.
2. The Flash may be programmed or erased in the end-user application by calling
low-lev el routi nes through a comm on entr y point in the Boo t ROM.
3. The Flash may be programmed using the parallel method by using a conven-
tional EPROM programmer. The parallel programming method used by these
devices is similar to that used by EPROM 87C51 but it is not identical and the
commercially available programmers need to have support for the
AT89C51RD2/ED2. The bootloader and the Application Programming Interface
(API) routines are located in the BOOT ROM.
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AT89C51RD2/ED2
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Flash Registers and
Memory Map The AT89C51RD2/ED2 Flash memory uses several registers for its management:
•Hardware registers can only be accessed through the parallel programming modes
which ar e handl ed by the paralle l pro gramm er.
•Software registers are in a special page of the Flash memory which can be
accessed through the API or with the parallel programming modes. This page,
called "Extra Flash Memory", is not in the internal Flash program memory
addressing space.
Hardware Register The only hardw are r egist er of the AT8 9C5 1RD2/E D2 is calle d Ha rdwar e Sec urity Byte
(HSB).
Table 67. Hardware Security Byte (HSB)
Boot Loader Jump Bit (BLJB)
One bit of the HSB, the BLJB bit, is used to force the boot address:
•When this bit is set the boot address is 0000h.
•When this bit is reset the boot address is F800h. By default, this bit is cleared and
the ISP is enabled.
Flash Memory Lock Bits The three lock bits provi de different levels of p rotection for the on-chip code and data
when programmed as shown in Table 68.
76543210
X2 BLJB OSC - XRAM LB2 LB1 LB0
Bit
Number Bit
Mnemonic Description
7X2
X2 Mode
Programmed to force X2 mode (6 clocks per instruction)
Unprogrammed to force X1 mode, Standard Mode (Default).
6BLJB
Boot Loader Jump Bit
Unprogrammed, this bit to start the user’s application on next reset at address
0000h.
Programmed this bit to start the boot loader at address F800h (Default).
5OSC
Oscillator Bit
Programmed to allow oscillator B at startup
Unprogrammed this bit to allow oscillator A at startup ( Default).
4-Reserved
3XRAM
XRAM config bit (only programmable by programmer tools)
Programmed to inhibit XRAM.
Unprogrammed, this bit to valid XRAM (Default).
2-0 LB2-0 User Memory Lock Bits (only programmable by programmer tools)
See Table 68
98 AT89C51RD2/ED2 4235C–8051–08/03
Table 68. Program Lock Bits
Note: U: Unprogrammed or "one" level.
P: Programmed or "zero" level.
X: Do not care
WARNING: Security level 2 and 3 should only be programmed after Flash and code
verification.
These se curity bits protect the co de access through the parallel pr ogram ming interf ace.
They are se t by defau lt to lev el 4. The cod e acce ss throug h the ISP i s stil l possib le and
is cont rolle d by the "s oftware s ecurit y bits" which are store d in the ext ra Flas h memory
accessed by the ISP firmware.
To load a new application with the parallel programmer, a chip erase must first be done.
This will set the HSB in its in active s tate an d will e rase the Flash m emory . The par t ref-
erence can always be read using Flash parallel programming modes.
Default Values The default value of the HSB provides parts ready to be programmed with ISP:
•BLJB: Programmed force ISP operation.
•X2: Unprogrammed to force X1 mode (Standard Mode).
•XRAM: Unprogrammed to valid XRAM
•LB2-0: Security level four to protect the code from a parallel access with maximum
security.
Software Regist ers Sever al regist ers are use d in factor y and by para llel progr ammers. T hese value s are
used by Atmel ISP.
These registers are in the "Extra Flash Memory" part of the Flash memory. This block is
also called "XAF" or eXtra Array Flash. They are accessed in the following ways:
•Commands issued by the parallel memory programmer.
•Commands issued by the ISP software.
•Calls of API issued by the application software.
Several software registers are described in Table 69.
Program Lock Bits
Protect ion Description
Security
Level LB0 LB1 LB2
1 U U U No program lock features enabled.
2PUU
MOVC instruction executed from external program mem ory is disabled
from fetching code bytes from internal memory, EA is sampled and
latched on reset, and further parallel programming of the on chip code
memory is disabled.
ISP and software programming with API are still allowed.
3XPU
Same as 2, also verify code memory through parallel programming
interface is disabled.
4 X X P Same as 3, also external execution is disabled (Default).
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Table 69. Default Values
After pr ogrammi ng the par t by ISP, the BSB mu st be cl eared (00 h) in ord er to allow th e
application to boot at 0000h.
The content of the Software Security Byte (SSB) is described in Table 70 and Table 71.
To assu re co de protec tion from a pa ra ll el ac ce ss , t he H SB mu st al so be at t he r e qui re d
level.
Table 70. Software Security Byte
The two lock bits provide different levels of protection for the on-chip code and data,
when programmed as shown in Table 71.
Mnemonic Definition Default value Description
SBV S oftware Boot Vector FCh
BSB B oot Statu s Byte 0FFh
SSB S oftware Security Byte FFh
Copy of the Manufacturer Code 58h Atmel
Copy of the Device ID #1: Family Code D7h C51 X2, Electrically Erasable
Copy of the Device ID #2: Memories Size
and Type ECh AT89C51RD2/ED2 64KB
Copy of the Device ID #3: Name and
Revision EFh AT89C51RD2/ED2 64K B,
Revision 0
76543210
------LB1LB0
Bit
Number Bit
Mnemonic Description
7-
Reserved
Do not clear this bit.
6-
Reserved
Do not clear this bit.
5-
Reserved
Do not clear this bit.
4-
Reserved
Do not clear this bit.
3-
Reserved
Do not clear this bit.
2-
Reserved
Do not clear this bit.
1-0 LB1-0 User Memory Lock Bit s
See Table 71
100 AT89C51RD2/ED2 4235C–8051–08/03
Table 71. Program Lock Bits of the SSB
Note: U: Unprogrammed or "one" level.
P: Programmed or "zero" level.
X: Do not care
WARNING: Security level 2 and 3 should only be programmed after Flash and code
verification.
Flash Memory Status AT89C51RD2/ED2 parts are delivered in standard with the ISP ROM bootloader.
After IS P or paralle l pro gramm ing, th e poss ible conte nts of the Flas h mem ory are sum-
marized in Figure 40:
Figure 40. Flash Memory Possible Contents
Memory Organization When the EA pin is high, the processor fetches instructions from internal program Flash.
If the EA pin is tied low, all program memory fetches are from external memory.
Program Lock Bits
Protection Description
Security
Level LB0 LB1
1 U U No program lock features enabled.
2 P U ISP programming of the Flash is disabled.
3 X P Same as 2, also verify through ISP programming interface is disabled.
0000h
Virgin
Default Afte r ISP After Parallel
Programming After Parallel
Programming After Parallel
Programming
ApplicationApplication Virgin
After ISP
or
Dedicated
ISP Dedicated
ISP
Application
Virgin
or
Application
Virgin
or
Application
FFFFh
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Bootloader Architecture
Introduction The bootloader manages communication according to a specifically defined protocol to
provid e the whol e ac ce ss and se rvic e on F lash me mor y . Fur the rm or e, all ac c es se s and
routines can be called from the user application.
Figure 41. Diagram Context Description
Acronyms ISP: In-System Programming
SBV: Software Boot Vector
BSB: Boot Status Byte
SSB: Software Security Bit
HW: Hardware Byte
Bootloader Flash Mem ory
Access Via
Specific
Protocol
Access From
User
Application
102 AT89C51RD2/ED2 4235C–8051–08/03
Functional Description Figure 42. Bootloade r Func tio nal Desc ripti on
On the above diagram, the on-chip bootloader processes are:
•ISP Communication Management
The pu rpose o f this p rocess i s to man age the c ommun icatio n and its protoc ol betw een
the on-chip bootloader and a external device. The on-chip ROM implements a serial
protocol (see section “Bootloader Protocol”). This process translate serial communica-
tion frame (UART) into Flash memory acess (read, write, erase, etc).
•User Call Management
Several Application Program Interface (API) calls are available for use by an application
program to permit selective erasing and programming of Flash pages. All calls are made
through a co mmon in terface (A PI calls) , included in the ROM boo tloade r. The progr am-
ming functions are selected by setting up the microcontroller’s registers before making a
call to a common entry point (0xFFF0). Results are returned in the registers. The pur-
pose on this process is to translate the registers values into internal Flash Memory
Management.
•Flash Memory Management
This process manages low level access to Flash memory (performs read and write
access).
ISP Communication
Management
User
Application
Specific Protocol
Communication
Management
Flash
Memory
Exernal Host with
Flash Memory
User Call
Management (API )
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Bootloader Functionality The bootloader can be activated by two means: Hardware conditions or regular boot
process.
The Hardware conditions (EA = 1, PSEN = 0) during the Reset# falling edge force the
on-chip bootloader execution. This allows an application to be built that will normally
execute the end user’s code but can be manually forced into default ISP operation.
As PS EN is a an ou tput port in normal ope rating mode after reset, user applicatio n
should take care to release PSEN after falling edge of reset signal. The hardware condi-
tions are sampled at reset signal falling edge, thus they can be released at any time
when reset input is low.
The on-chip bootloader boot process is shown Figure 43.
Table 72. Bootloader Process Description
Purpose
Hardware Conditions The Hardware Conditions force the bootloader execution whatever
BLJB, BSB and SBV values.
BLJB
The Boot Loader Jump Bit forces the application execution.
BLJB = 0 => Bootloader execution
BLJB = 1 => Application execution
The BLJB is a fuse bi t in th e Hardwa re By te .
It can be modified by hardware (programmer) or by software (API).
Note: The BLJB test is performed by hardware to prevent any
program execution.
SBV
The Software Boot Vector contains the high address of customer
bootloader stored in the application.
SBV = FCh (default value) if no customer bootloader in user Flash.
Note: The customer bootloader is called by JMP [SBV]00h
instruction.
104 AT89C51RD2/ED2 4235C–8051–08/03
Boot Process
Figure 43. Bootlo ade r Proc es s
RESET
Hardware
Condition?
BLJB!= 0
?
User Application
Hardware
Software
FCON = 00h
FCON = F0h
FCON = 00h
?
Atmel BOOT LOADERUSER BOOT LOADER
Yes = Hardware Boot
F800h
BLJB = 1
BSB = 00h
?
SBV = FCh
?
PC = 0000h
PC= [SBV]00h
Conditions
BLJB = 0
If BLJB = 0 then ENBOOT Bit (AUXR1) is Set
else ENBOOT Bit (AUXR1) is Cleared
ENBOOT = 1
ENBOOT = 0
Yes (PSEN = 0, EA = 1, and ALE =1 or Not Connected)
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ISP Protocol Description
Physical Layer The UART used to transmit information has the following configuration:
•Character: 8-bit data
•Parity: none
•Stop: 2 bits
•Flow control: none
•Baudrate: autobaud is performed by the bootloader to compute the baudrate
choos en by the host.
Frame Description The Serial Protocol is based on the Intel Hex-type records.
Intel Hex records consist of ASCII characters used to represent hexadecimal values and
are summarized below.
Figure 44. Intel Hex Type Frame
•Record Mark:
Record Mark is the start of frame. This field must contain ’:’.
•Reclen:
Reclen sp ecifies the nu mber of by tes of informa tion or da ta which follows the Record
Type field of the record.
•Load Offset:
Load Offs et speci fies t he 16-b it sta rting loa d offse t of the da ta byte s, therefo re thi s field
is used only for Data Program Record (see Section “ISP Command s Sum mar y ”).
•Record Type:
Record Type specifies the command type. This field is used to interpret the remaining
information within the frame. The encoding for all the current record types is described
in Section “ISP Commands Summary”.
•Data/Info:
Data/Inf o is a v ar iable length fi eld . It consi sts of zer o o r mor e by tes encoded as pai r s of
hexadecimal digits. The meaning of data depends on the Record Type.
•Checksum:
The two’s complement of the 8-bit bytes that result from converting each pair of ASCII
hexadec im al di gits to one byte of bina ry, and inc ludi ng the Reclen field to and inc lu din g
the last byte of the Data/Info field. Therefor e, the sum of all the ASCII pai rs in a record
after conve r ting to b ina ry, fro m the Reclen field to a nd i nc lud in g the Checksum fi eld , is
zero.
Record Record
Load Data
Mark
’:’Reclen Offset Type or
Info Checksum
1-byte 1-byte 2-bytes 1-byte n-bytes 1-byte
106 AT89C51RD2/ED2 4235C–8051–08/03
Functional Description
Software Security Bits (SSB) The SSB protects any Flash access from ISP command.
The command "Program Software Security Bit" can only write a higher priority level.
There are three levels of security:
•level 0 : NO_SECURITY (FFh)
This is the default level.
From level 0, one can write level 1 or level 2.
•level 1 : WRITE_SECURITY (FEh )
For this level it is impossible to write in the Flash memory, BSB and SBV.
The Bootlo ade r re turns ’P’ on write access.
From level 1, one can write only level 2.
•level 2 : RD_WR_SECURITY (FCh
The level 2 forbids all read and write accesses to/from the Flash/EEPROM memory.
The Bootlo ade r re turns ’L’ on read or write access.
Only a full chip erase in parallel mode (using a programmer) or ISP command can reset
the software security bits.
From level 2, one cannot read and write anything.
Table 73. Software Security Byte Behavior
Level 0 Level 1 Level 2
Flash/EEPROM Any access allowed Read-only access allowed Any access not allowed
Fuse Bit Any access allowed Read-only access allowed Any access not allowed
BSB & SBV Any access allowed Read-only access allowed Any access not allowed
SSB Any access allowed Write level 2 allowed Read-only access allowed
Manufacturer
Info Read-only access allowed Read-only access allowed Read-only access allowed
Bootloader Info Read-only acces s allowed Read-onlyacc ess allowed Read-only access allowed
Erase Block Allowed Not allowed Not allowed
Full Chip Erase Allowed Allowed Allowed
Blank Check Allowed Allowed Allowed
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Full Chip Erase The ISP command "Full Chip Erase" erases all user Flash memory (fills with FFh) and
sets some bytes used by the bootloader at their default values:
•BSB = FFh
•SBV = FCh
•SSB = FFh
The Full Chip Erase does not affect the bootloader.
Checksum Error When a checksum error is detected, send ‘X’ followed with CR&L F.
Flow Description
Overview An initial ization st ep must b e perfor med after e ach Rese t. After microcontrol ler rese t,
the bootloader waits for an autobaud sequence (see section ‘Autobaud Performances’).
When the communication is initialized, the protocol depends on the record type
requested by the host.
FLIP, a software utility to implement ISP programming with a PC, is available from the
Atmel web site.
Communication Initialization The hos t ini ti ali ze s the communi ca tio n b y sendi ng a ’U’ character to help the bootloader
to compute the baudrate (autobaud).
Figure 45. Initialization
Host Bootloader
"U" Performs Autobaud
Init Communication
If (Not Received "U") "U"
Communication Opened
Else Sends Back “U” Characte
108 AT89C51RD2/ED2 4235C–8051–08/03
Autobaud Performances The IS P feature allows a wi de range of baud rates in the user appli cation. It is also
adapta ble to a wide rang e of o scilla tor freq uenci es. Thi s is accom plis hed by meas uring
the bit-time of a single bit in a received character. This information is then used to pro-
gram the ba ud rate in term s of timer coun ts based on the oscillat or frequenc y. The ISP
feature requires that an initial character (an uppercase U) be sent to the
AT89C51RD2/ED2 to establish the baud rate. Table show the autobaud capability.
Command Data Stream
Protocol All comma nds are sen t using the same flow. Eac h frame se nt by the host is echoed by
the bootloader.
Table 74. Autobaud Performances
Frequency (MHz )
Baudrate (kHz) 1.8432 2 2.4576 3 3.6864 4 5 6 7.3728
2400 OK OK OK OK OK OK OK OK OK
4800 OK - OKOKOKOKOKOKOK
9600 OK - OKOKOKOKOKOKOK
19200 OK - OK OK OK - - OK OK
38400 - - OK OK - OK OK OK
57600 ----OK---OK
115200 --------OK
Frequency (MHz )
Baudrate (kHz) 8 10 11.0592 12 14.746 16 20 24 26.6
2400 OK OK OK OK OK OK OK OK OK
4800 OK OK OK OK OK OK OK OK OK
9600 OK OK OK OK OK OK OK OK OK
19200 OKOKOKOKOKOKOKOKOK
38400 - - OKOKOKOKOKOKOK
57600 - - OK - OK OK OK OK OK
115200 --OK-OK----
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Figure 46. Command Flow
Bootloader
":"
Sends First Character of the
Frame If (not received ":")
Sends Frame (made of 2 ASCII Gets Frame, and Sends Back Ech o
for Each Received Byte
Host
Else
":" Sends Echo and Start
Reception
Characters Per Byte)
Echo Analysis
110 AT89C51RD2/ED2 4235C–8051–08/03
Write/Program Commands
Description This flow is common to the following frames:
•Flash/EEPROM Programming Data Frame
•EOF or Atmel Frame (only Programming Atmel Frame)
•Config Byte Programming Data Frame
•Baud Rate Frame
Figure 47. Write/P ro gr am Flow
Example
Host Bootloader
Write Command
’X’ & CR & LF
NO_SECURITY
Wait Write Co m mand
Checksum Error
Wait Programming
Send Security Error
Send COMMAND_OK
Send Write Command
Wait Checksum Error
Wait COMMAND_OK
Wait Security Error
OR
COMMAND ABORTED
COMMAND FINISHED
Send Checksum Error
COMMAND ABORTED
’P’ & CR & LF
OR
’.’ & CR & LF
HOST : 01 0010 00 55 9A
BOOTLOADER : 01 0010 00 55 9A . CR LF
Programming Data (write 55h at address 0010h in the Flash)
HOST : 02 0000 03 05 01 F5
BOOTLOADER : 02 0000 03 05 01 F5. CR LF
Programming Atmel function (write SSB to level 2)
HOST : 03 0000 03 06 00 55 9F
BOOTLOADER : 03 0000 03 06 00 55 9F . CR LF
Writing Frame (write BSB to 55h)
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Blank Check Command
Description
Figure 48. Blank Check Flow
Example
Host Bootloader
Blank Check Command
’X’ & CR & LF
Flash Blank
Wait Blank Check Command
Send First Address
Send COMMAND_OK
Send Blank Check Command
Wait Checksum Error
Wait Address not
Erased
Wait COMMAND_OK
OR
COMMAND ABORTED
COMMAND FINISHED
Send Checksum Error
COMMAND FINISHED
’.’ & CR & LF
OR
address & CR & LF not Erased
Checksum Error
HOST : 05 0000 04 0000 7FFF 01 78
BOOTLOADER : 05 0000 04 0000 7FFF 01 78 . CR LF
Blank Check ok
BOOTLOADER : 05 0000 04 0000 7FFF 01 70 X CR LF CR LF
Blank Check with checksum error
HOST : 05 0000 04 0000 7FFF 01 70
BOOTLOADER : 05 0000 04 0000 7FFF 01 78 xxxx CR LF
Blank Check ok at address xxxx
HOST : 05 0000 04 0000 7FFF 01 78
112 AT89C51RD2/ED2 4235C–8051–08/03
Display Data Description
Figure 49. Display Flow
Note: The maximum size of block is 400h. To read more than 400h bytes, the Host must send a new command.
Example
Host Bootloader
Display Command
’X’ & CR & LF
RD_WR_SECURITY
Wait Display Command
Read Data
Send Security Error
Send Di splay Data
Send Display Command
Wait Checksum Error
Wait Display Data
Wait Security Error
OR
COMMAND ABORTED
COMMAND FINISHED
Send Checksum Error
COMMAND ABORTED
’L’ & CR & LF
OR
"Address = "
All Data Read
Complet Frame
"Reading Value"
CR & LF
All Data ReadAll Data Read
COMMAND FINISHED
Checksum error
HOST : 05 0000 04 0000 0020 00 D7
BOOTLOADER : 05 0000 04 0000 0020 00 D7
BOOTLOADER 0000=-----data------ CR LF (16 data)
BOOTLOADER 0010=-----data------ CR LF (16 data)
BOOTLOADER 0020=data CR LF ( 1 data)
Display data from address 0000h to 0020h
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Read Function Description This flow is similar for the following frames:
•Rea ding Frame
•EOF Frame/ Atmel Frame (only reading Atmel Frame)
Figure 50. Read Flow
Example
Host Bootloader
Read Command
’X’ & CR & LF
RD_WR_SECURITY
Wait Read Command
Read Value
Send Security error
Send Data Read
Send Read Command
Wait Checksum Error
Wai t Va lue of D a t a
Wait Security Error
OR
COMMAND ABORTED
COMMAND FINISHED
Send Checksum error
COMMAND ABORTED
’L’ & CR & LF
OR
’value’ & ’.’ & CR & LF
Checksum error
HOST : 02 0000 05 07 02 F0
BOOTLOADER : 02 0000 05 07 02 F0 Value . CR LF
HOST : 02 0000 01 02 00 FB
BOOTLOADER : 02 0000 01 02 00 FB Value . CR LF
Read function (read SBV)
Atmel Read function (read Bootloader version)
114 AT89C51RD2/ED2 4235C–8051–08/03
ISP Commands Summary
Table 75. ISP Commands Summary
Command Command Name Data[0] Data[1] Command Effect
00h Program Code Program Nb Code Byte.
Bootloader will accept up to 128 (80h) data bytes. The data
bytes should be 128 byte page flash boundary.
03h Write Function
01h
00h Erase block0 (0000h-1FFFh)
20h Erase block1 (2000h-3FFFh)
40h Erase block2 (4000h-7FFFh)
80h Erase block3 (8000h- BFFFh)
C0h Erase block4 (C000h- FFFFh)
03h 00h Hardware Reset
01h Ljmp Address (data[2:3]= Address)
04h 00h Erase SBV & BSB
05h 00h Pro gram SS B le vel 1
01h Pro gram SS B le vel 2
06h 00h Program BSB (value to write in data[2])
01h Program SBV (value to write in data[2])
07h - Full Chip Erase
0Ah 04h Program BLJB fuse (value to write in data[2])
08h Program X2 fuse (value to write in data[2])
04h Display Function
Data[0:1] = start address
Data [2:3] = end address
Data[4] = 00h :Display Code
Data[4] = 01h : Blank check
Data[4] = 01h : Display EEPROM
Display Code
Blank Check
Display EEPROM data
05h Read Function
00h
00h Manufacturer Id
01h Device Id #1
02h Device Id #2
03h Device Id #3
07h
00h Read SSB
01h Read BSB
02h Read SBV
06h Read Extra Byte
0Bh 00h Read Hardware Byte
0Eh 00h Read Device Boot ID1
01h Read Device Boot ID2
0Fh 00h Read Bootloader Version
06h Program EEPROM data Program Nb Code Byte.
Bootloader will accept up to 128 (80h) data bytes.
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API Call Description The IAP allows to re program a mic rocontro ller on-chi p Flash memor y without rem oving
it from the system and while the embedded application is running.
The use r application can cal l some Applica tion Progr amming Inter face (API) routi nes
allowing IAP. These API are executed by the bootloader.
To call t he corr espon ding API , the us er m ust use a set o f Flash _api r outine s which can
be linked with the appl ication.
Example of Flash_api routines are available on the Atmel web site on the software appli-
cation note:
C Flash Drivers for the AT89C51RD2/ED2
The API calls descri ption and ar gum ents are shown in Tabl e 76.
Process The application selects an API by setting R1, ACC, DPTR0 and DPTR1 registers.
All calls are made through a common interface “USER_CALL” at the address FFF0h.
The jump at the USER_CALL must be done by LCALL instruction to be able to come-
back in the application.
Before jump at the USER_CALL, the bit ENBOOT in AUXR1 register must be set.
Constraints The interrupts are not disabled by the bootloader.
Interrupts must be disabled by user prior to jump to the USER_CALL, then re-enabled
when returning.
Interrupts must also be disabled before accessing EEPROM Data then re-enabled after.
The user must take care of hardware watchdog before launching a Flash operation.
Table 76. API Call Summary
Command R1 A DPTR0 DPTR1 Returned Value Command Effect
READ MANUF ID 00h XXh 0000h X Xh ACC = Manufacturer
Id Read Manufacturer identifier
READ DEVICE ID1 00h XXh 0001 h XXh ACC = Device Id 1 Read Device identifier 1
READ DEVICE ID2 00h XXh 0002h XXh ACC = Device Id 2 Read Device identifier 2
READ DEVICE ID3 00h XXh 0003h XXh ACC = Device Id 3 Read Device identifier 3
ERAS E BLOCK 01h XXh
DPH = 00h
00h ACC = DPH
Erase block 0
DPH = 20h Erase block 1
DPH = 40h Erase block 2
Address of
byte to
program Program one Data Byte in user Flash
XXh Erase Software boot vector and boot status
byte. (SBV = FCh and BSB = FFh)
116 AT89C51RD2/ED2 4235C–8051–08/03
PROGR A M SSB 05h XXh
DPH = 00h
DPL = 00h
00h ACC = SSB value
Set SSB level 1
DPH = 00h
DPL = 01h Set SSB level 2
DPH = 00h
DPL = 10h Set SSB level 0
DPH = 00h
DPL = 11h Set SSB level 1
PROGR A M BSB 06h New BSB
value 0000h XXh none Program boot status byte
PROGR A M SBV 06h New SBV
value 0001h XXh none P rogram software boot vector
READ SSB 07h XXh 0000h X Xh ACC = SSB Read Software Security Byte
READ BSB 07h XXh 0001h XXh ACC = BSB Read Boot Status Byte
READ SBV 07h XXh 0002h XXh ACC = SBV Read Software Boot Vector
PROGRAM DATA
PAGE 09h Number of
byte to
program
Address of
the first b y te
to program in
the Flash
memory
Address in
XRAM of the
first data to
program
ACC = 0: DONE
Program up to 128 bytes in user Flash.
Remark : number of bytes to program is
limited such as the Flash write remains in a
single 128 bytes page. Hence, when ACC
is 128, valid values of DPL are 00h, or , 80h.
PROGRAM X2 FUSE 0Ah Fuse value
00h or 01h 0008h XXh none Program X2 fuse bit with ACC
PROG RAM BLJB
FUSE 0Ah Fuse value
00h or 01h 0004h XXh none Program BLJB fuse bit with ACC
READ HSB 07h XXh 0004h XXh ACC = HSB Read Hardware Byte
READ BOOT ID1 0Eh XXh DPL = 00h XXh ACC = ID1 Read boot ID1
READ BOOT ID2 0Eh XXh DPL = 01h XXh ACC = ID2 Read boot ID2
READ BOOT VERSION 0Fh XXh XXXXh XXh ACC = Boot_Version Read bootloader version
Table 76. API Call Summary (Continued)
Command R1 A DPTR0 DPTR1 Returned Value Command Effect
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Electrical Characteristics
Absolute Maximum Ratings
DC Parameters for Standard Voltage
I = industrial..................... ...... ..... ...... ................. .-40°C to 85°C
Storage Temperature.................. ...... ..... ....... -65°C to + 150°C
Voltage on VCC to VSS (standard voltage).........-0.5V to + 6.5V
Voltage on VCC to VSS (low voltage) ..................-0.5V to + 4.5V
Voltage on Any Pin to VSS...................... ....-0.5V to VCC + 0.5V
Power Dissipation........................................................... 1 W(2)
Note: Stresses at or above those listed under “Absolute
Maximu m Rati ngs ” may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions above those indicated in the operational
sections of this specification is not implied. Exposure
to absolute maximum rating conditions may affect
device reliability.
Power dissipation is based on the maximum allow-
able die temperature and the thermal resistance of
the package.
TA = -4 0°C to +85°C; VSS = 0V; VCC =2.7V to 5.5V; F = 0 to 60 MHz
Symbol Parameter Min Typ Max Unit Test Co nditions
VIL Input Low Voltage -0.5 0.2 VCC - 0.1 V
VIH Input High Voltage except RST, XTAL1 0.2 VCC + 0.9 VCC + 0.5 V
VIH1 Input High V oltage RST, XTAL1 0.7 VCC VCC + 0.5 V
VOL Output Low Voltage, ports 1, 2, 3, 4 (6)
0.3
0.45
1.0
V
V
V
VCC = 4.5V to 5.5V
IOL = 100 µA(4)
IOL = 1.6 mA(4)
IOL = 3.5 mA(4)
0.45 V VCC = 2.7V to 5.5V
IOL = 0.8 mA(4)
VOL1 Output Low V olt age, port 0, ALE, PSEN (6)
0.3
0.45
1.0
V
V
V
VCC = 4.5V to 5.5V
IOL = 200 µA(4)
IOL = 3.2 mA(4)
IOL = 7.0 mA(4)
0.45 V VCC = 2.7V to 5.5V
IOL = 1.6 mA(4)
VOH Output High Voltage, ports 1, 2, 3, 4
VCC - 0.3
VCC - 0.7
VCC - 1.5
V
V
V
VCC = 5V ± 10%
IOH = -10 µA
IOH = -30 µA
IOH = -60 µA
0.9 VCC VVCC = 2.7V to 5.5V
IOH = -10 µA
118 AT89C51RD2/ED2 4235C–8051–08/03
Note s: 1. Ope rating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 54), VIL =
VSS + 0.5V, VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used
(see Figure 51).
2. I d le I CC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5V, VIH = VCC -
0.5V; XTAL2 N.C; Port 0 = VCC; EA = RST = VSS (see Figure 52).
3. P o we r -do w n I CC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Fig-
ure 53).
4. Capa ci t ance loa di ng o n Ports 0 an d 2 may cau se sp urio us noi se pulses t o be su pe rim pos ed on the VOLS of ALE an d Po rt s 1
and 3. The no is e is due to ex te rnal bus capacitance dischargin g in to th e Port 0 and Port 2 pin s whe n the se pin s m ak e 1 to 0
transitio ns during b us o pera tio n. In the wors t cases (ca p ac iti ve l oad ing 100 pF ), th e noi se pulse on th e AL E l in e m ay e xc ee d
0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary.
5. Typical value s are ba sed on a li mited numbe r of sampl es and a re n ot guara nteed. T he val ues li sted ar e at room tempe rature
and 5V.
6. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
Maximum total IOL for all output pin s: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
VOH1 Output High Voltage, port 0, ALE, PSEN
VCC - 0.3
VCC - 0.7
VCC - 1.5
V
V
V
VCC = 5V ± 10%
IOH = -200 µA
IOH = -3.2 mA
IOH = -7.0 mA
0.9 VCC VVCC = 2.7V to 5.5V
IOH = -10 µA
RRST RST Pull-down Resistor 50 200(5) 250 kΩ
IIL Logical 0 Input Current ports 1, 2, 3, 4 and 5 -50 µAV
IN = 0.45V
ILI Input Leakage Current ±10 µA 0.45V < VIN < VCC
ITL Logical 1 to 0 Tr ansition Current, ports 1, 2, 3, 4 -650 µAV
IN = 2.0V
CIO Capacitance of I/O Buffer 10 pF FC = 3 MHz
TA = 25°C
IPD Power-down Current 75 150 µA2.7 < V
CC < 5. 5V(3)
ICCOP Power Supply Current on normal mode 0.4 x Frequency (MHz) + 5 mA VCC = 5.5V(1)
ICCIDLE Power Supply Current on idle mode 0.3 x Frequency (MHz) + 5 mA VCC = 5.5V(2)
ICCWRITE Power Supply Current on flash or EEdata write 0.8 x Frequency (MHz) + 15 mA VCC = 5.5V
tWRITE Flash or EEdata programming time 7 17 ms 2.7 < VCC < 5.5V
TA = -4 0°C to +85°C; VSS = 0V; VCC =2.7V to 5.5V ; F = 0 to 60 MHz (Continued)
Symbol Parameter Min Typ Max Unit Test Co nditions
119
AT89C51RD2/ED2
4235C–8051–08/03
Figure 51. ICC Test Condition, Active Mode
Figure 52. ICC Test Condition, Idle Mode
Figure 53. ICC Test Condition, Power-down Mode
Figure 54. Clock Signal Waveform for ICC Tests in Active and Idle Modes
EA
VCC
VCC
ICC
(NC)
CLOCK
SIGNAL
VCC
All other pins are disconnected.
RST
XTAL2
XTAL1
VSS
VCC
P0
RST EA
XTAL2
XTAL1
VSS
VCC
VCC
ICC
(NC)
P0
VCC
All other pins are disconnected.
CLOCK
SIGNAL
RST EA
XTAL2
XTAL1
VSS
VCC
VCC
ICC
(NC)
P0
VCC
All other pins are disconnected.
VCC-0.5V
0.45V 0.7VCC
0.2VCC-0.1
TCLCH
TCHCL
TCLCH = TCHCL = 5ns.
120 AT89C51RD2/ED2 4235C–8051–08/03
AC Parameters
Explanation of the AC
Symbols Each timing symbol has 5 char acters. The first character is al ways a “T” (stands for
time). The other characters, depending on their positions, stand for the name of a signal
or the logical status of that signal. The following is a list of all the characters and what
they stand for.
Example:TAVLL = Time for Addr es s Val id to ALE Low.
TLLPL = Time for ALE Low to PSEN Low.
(Load Cap acitance for port 0, ALE and PSEN = 100 pF ; Load Capa citance for all other
outputs = 80 pF.)
Table 77 Table 80, and Table 83 give the description of each AC symbols.
Table 78, Table 79, Table 81 and Table 84 gives the range for each AC parameter.
Table 78, Table 79 and Table 85 give the frequency derating formula of the AC parame-
ter for each s peed ran ge de scr ipt ion . To calc ula te eac h A C symbo ls . take the x val ue in
the correponding column (-M or -L) and use this value in the formula.
Example: TLLIU for -M and 20 MHz, Standard clock.
x = 35 ns
T 50 ns
TCCIV = 4T - x = 165 ns
Exte rn al Pr og r am Mem o ry
Characteristics Table 77. Symbol Description
Symbol Parameter
T O scillator clock period
TLHLL ALE pulse width
TAVLL Address Valid to ALE
TLLAX Address Hold After ALE
TLLIV ALE to Valid Instruction In
TLLPL ALE to PSEN
TPLPH PSEN Pulse Width
TPLIV PSEN to Valid Instruction In
TPXIX Input Instruction Hold After PSEN
TPXIZ Input Instruction Float After PSEN
TAVIV Addres s to Valid Instruction In
TPLAZ PSEN Low to Address Float
121
AT89C51RD2/ED2
4235C–8051–08/03
Table 78. AC Parameters for a Fix Clock
Table 79. AC Parameters for a Variable Clock
Symbol -M -L Units
Min Max Min Max
T25 25 ns
TLHLL 35 35 ns
TAVLL 55ns
TLLAX 55ns
TLLIV n 65 65 ns
TLLPL 55ns
TPLPH 50 50 ns
TPLIV 30 30 ns
TPXIX 00ns
TPXIZ 10 10 ns
TAVIV 80 80 ns
TPLAZ 10 10 ns
Symbol Type Standard
Clock X2 Clock X parameter for
-M range X parameter for
-L ra nge Uni t s
TLHLL Min 2 T - x T - x 15 15 ns
TAVLL Min T - x 0.5 T - x 20 20 ns
TLLAX Min T - x 0.5 T - x 20 20 ns
TLLIV Max 4 T - x 2 T - x 35 3 5 ns
TLLPL Min T - x 0.5 T - x 15 15 ns
TPLPH Min 3 T - x 1.5 T - x 25 25 ns
TPLIV Max 3 T - x 1. 5 T - x 45 45 ns
TPXIX Min x x 0 0 ns
TPXIZ Max T - x 0.5 T - x 15 15 ns
TAVIV Ma x 5 T - x 2 . 5 T - x 45 45 ns
TPLAZ Max x x 10 10 ns
122 AT89C51RD2/ED2 4235C–8051–08/03
Exte rn al Pr og r am Mem o ry
Read Cycle
Exte rnal Dat a Mem ory
Characteristics Table 80. Symbol Description
TPLIV
TPLAZ
ALE
PSEN
PORT 0
PORT 2
A0-A7A0-A7 INSTR ININSTR IN INSTR IN
ADDRESS
OR SFR-P2 ADDRESS A8-A15ADDRESS A8-A15
12 TCLCL
TAVIV
TLHLL
TAVLL
TLLIV
TLLPL
TPLPH
TPXAV
TPXIX
TPXIZ
TLLAX
Symbol Parameter
TRLRH RD Pulse Width
TWLWH WR Pulse Width
TRLDV RD to Valid Data In
TRHDX Data Hold After RD
TRHDZ Data Float Af te r R D
TLLDV ALE to Valid Data In
TAVDV Add r ess to Valid D a ta In
TLLWL ALE to WR or RD
TAVWL Address to W R or RD
TQVWX Data Valid to WR Transition
TQVWH Da ta Set-up to WR High
TWHQX Data Hold After WR
TRLAZ RD Low to Address Float
TWHLH RD or WR High to ALE high
123
AT89C51RD2/ED2
4235C–8051–08/03
Table 81. AC Parameters for a Fix Clock
Symbol
-M -L
UnitsMin Max Min Max
TRLRH 125 125 ns
TWLWH 125 125 ns
TRLDV 95 95 ns
TRHDX 00ns
TRHDZ 25 25 ns
TLLDV 155 155 ns
TAVDV 160 160 ns
TLLWL 45 105 45 105 ns
TAVWL 70 70 ns
TQVWX 55ns
TQVWH 155 155 ns
TWHQX 10 10 ns
TRLAZ 00ns
TWHLH 5 45 5 45 ns
Table 82. AC Parameters for a Variable Clock
Symbol Type Standard
Clock X2 Clock X parameter for
-M range X parameter for
-L rang e Units
TRLRH Min 6 T - x 3 T - x 25 25 ns
TWLWH Min 6 T - x 3 T - x 25 25 ns
TRLDV Ma x 5 T - x 2.5 T - x 30 30 ns
TRHDX Min x x 0 0 ns
TRHDZ Max 2 T - x T - x 25 25 ns
TLLDV Max 8 T - x 4T -x 45 45 ns
TAVDV Max 9 T - x 4.5 T - x 65 65 ns
TLLWL Min 3 T - x 1.5 T - x 30 30 ns
TLLWL Ma x 3 T + x 1.5 T + x 30 3 0 ns
TAVWL Min 4 T - x 2 T - x 30 30 ns
TQVWX Min T - x 0.5 T - x 20 20 ns
TQVWH Min 7 T - x 3.5 T - x 20 20 ns
TWHQX Min T - x 0.5 T - x 15 15 ns
TRLAZ Max x x 0 0 ns
TWHLH Min T - x 0.5 T - x 20 20 ns
TWHLH Max T + x 0.5 T + x 20 2 0 ns
124 AT89C51RD2/ED2 4235C–8051–08/03
External Data Memory Write
Cycle
External Data Memory Read Cycle
Serial Port Timing - Shift
Regist er Mode Table 83. Symbol Description
TQVWH
TLLAX
ALE
PSEN
WR
PORT 0
PORT 2
A0-A7 DATA OUT
ADDRESS
OR SFR-P2
TAVWL
TLLWL
TQVWX
ADDRESS A8-A15 OR SFR P2
TWHQX
TWHLH
TWLWH
ALE
PSEN
RD
PORT 0
PORT 2
A0-A7 DATA IN
ADDRESS
OR SFR-P2
TAVWL
TLLWL
TRLAZ
ADDRESS A8-A15 OR SFR P2
TRHDZ
TWHLH
TRLRH
TLLDV
TRHDX
TLLAX
TAVDV
Symbol Parameter
TXLXL Serial port clock cycle time
TQVHX Output data set-up to clock rising edge
TXHQX Output data hold after clock rising edge
TXHDX Input data hold after clock rising edge
TXHDV Clock rising edge to input data valid
125
AT89C51RD2/ED2
4235C–8051–08/03
Table 84. AC Parameters for a Fix Clock
Table 85. AC Parameters for a Variable Clock
Shift Register Timing
Waveforms
External Clo ck Driv e
Waveforms
Symbol
-M -L
UnitsMin Max Min Max
TXLXL 300 300 ns
TQVHX 200 200 ns
TXHQX 30 30 ns
TXHDX 00ns
TXHDV 117 117 ns
Symbol Type Standard
Clock X2 Clock X Parameter For
-M Range X Parameter For
-L Range Units
TXLXL Min 12 T 6 T ns
TQVHX Min 10 T - x 5 T - x 50 50 ns
TXHQX Min 2 T - x T - x 20 20 ns
TXHDX Min x x 0 0 ns
TXHDV Max 10 T - x 5 T- x 133 133 ns
INPUT DATA VALIDVALID VALID VALID
0123456 87
ALE
CLOCK
OUTPUT DATA
WRITE to SB UF
CLEAR RI
TXLXL
TQVXH TXHQX
TXHDV TXHDX SET TI
SET RI
INSTRUCTION
01234567
VALID VALID VALID VALID
VCC-0.5V
0.45V
0.7VCC
0.2VCC-0.1
TCHCL TCLCX TCLCL
TCLCH
TCHCX
126 AT89C51RD2/ED2 4235C–8051–08/03
AC Testing Input/Output
Waveforms
AC in pu ts dur ing tes ting are dri ven a t VCC - 0.5 for a logic “1” and 0.45V for a l ogic “0”.
Timing measurement are ma de at VIH min for a logic “1” and VIL max for a logic “0”.
Float Waveforms
For timing purposes as port pin is no longer floating when a 100 mV change from load
voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level
occurs. IOL/IOH ≥ ± 20 mA.
Clock Waveforms Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2.
INPUT/OUTPUT 0.2 VCC + 0.9
0.2 VCC - 0.1
VCC -0.5V
0.45V
FLOAT
VOH - 0.1V
VOL + 0.1V
VLOAD VLOAD + 0.1V
VLOAD - 0.1V
127
AT89C51RD2/ED2
4235C–8051–08/03
Figure 55. Internal Cloc k Sign als
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however,
ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propaga-
tion also varies from output to output and component. Typically though (TA = 25°C fully loaded) RD and WR propagation
delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC
specifications.
DATA PCL OUT DATA PCL OUT DATA PCL OUT
SAMPLED SAMPLED SAMPLED
STATE4 STATE5 STATE6 STATE1 STATE2 STATE3 STATE4 STATE5
P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2
FLOAT FLOAT FLOAT
THESE SIGNALS ARE NOT ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION
INDIC ATES ADDRESS TRA N SI T IO N S
EXTERNAL PROGRAM MEMORY FETCH
FLOAT
DATA
SAMPLED
DPL OR Rt OUT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
PCL OUT (EVEN IF PROGRAM
MEMORY IS INTERNAL)
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
OLD DATANEW DATA P0 PINS SAMPLED
P1, P2, P3 PINS SAMPLED P1, P2, P3 PINS SAMPLED
P0 PINS SAMPLED
RXD SAMPLED
INTERNAL
CLOCK
XTAL2
ALE
PSEN
P0
P2 (EXT)
READ CYCLE
WRITE CYCLE
RD
P0
P2
WR
PORT OPERATION
MOV PORT SRC
MOV DEST P0
MOV DES T PORT (P1. P2. P3)
(INC L U D ES INTO . IN T1. TO T 1 )
SERIAL PORT SHIFT CLOCK
TXD (MODE 0)
DATA OUT
DPL OR Rt OUT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
P0
P2
RXD SAMPLED
128 AT89C51RD2/ED2 4235C–8051–08/03
Ordering Information
Note: 1. For PLCC68 and VQFP64 packages, please contact Atmel sales office for availability.
Table 86. Possible Order Entries
Part Number Data EEPROM Supply Voltage Temperature
Range Package Packing
AT89C51RD2-SLSIM
No
2.7V - 5.5V Industrial
PLCC44 Stick
AT89C51RD2-RLTIM VQFP44 Tray
AT89C51RD2-SMSIM(1) PLCC68 Stick
AT89C51RD2-RDTIM(1) VQFP64 Tray
AT89C51ED2-SLSIM
Yes
PLCC44 Stick
AT89C51ED2-RLTIM VQFP44 Tray
AT89C51ED2-SMSIM(1) PLCC68 Stick
AT89C51ED2-RDTIM(1) VQFP64 Tray
AT89C51ED2-3CSIM PDIL40 Stick
129
AT89C51RD2/ED2
4235C–8051–08/03
Packaging Information
PLCC44
130 AT89C51RD2/ED2 4235C–8051–08/03
VQFP44
131
AT89C51RD2/ED2
4235C–8051–08/03
DIL40
132 AT89C51RD2/ED2 4235C–8051–08/03
PLCC68
133
AT89C51RD2/ED2
4235C–8051–08/03
VQFP64
134 AT89C51RD2/ED2 4235C–8051–08/03
PDIL40
135
AT89C51RD2/ED2
4235C–8051–08/03
Dat ash ee t C h a n g e
Log for
AT89C51RD2/ED2
Changes from 4235A -
04/03 to 4135B - 06/03 1. VIH min changed from 0.2 VCC + 1.1 to 0.2 VCC + 0.9.
2. Added POR/PFD and reset specific sections.
3. Added DIL40 package.
4. Added Flash write programming time specification.
Changes from 4235B -
06/03 to 4235C - 08/03 1. Changed maximum frequency to 60 MHz in X1 mode and 30 MHz in X2 mode
for Vcc = 4.5V to 5.5V and internal code execution.
2. Added PDIL40 Packaging for AT89C51ED2.
i
AT89C51RD2/ED2
A–8051–08/03
Table of Contents
Features.................. ..... .............. ..... .... .............. ..... ..... .............. .... ..... .... 1
Description............. ..... ..... .... .............. ..... ..... .... .............. ..... ..... ............. 1
Block Diagram....................................................................................... 4
SFR Mapping......................................................................................... 5
Pin Configurations.............................................................................. 10
Port Types........................................................................................... 15
Oscillator............................................................................................. 16
Registers............................................................................................................. 16
Functional Block Diagram................................................................................... 17
Enhanced Features.............. ..... .............. ..... .... ..... .............. ..... .... ..... .. 18
X2 Feature.......................................................................................................... 18
Dual Data Pointer Register (DPTR) ................................................... 22
Expanded RAM (XRAM) ..................................................................... 25
Registers............................................................................................................. 27
Reset.................................................................................................... 28
Introduction......................................................................................................... 28
Reset Input ..... ....... ...... ....... ...... ...... ....... ...... .................... ...... .................... ...... ... 28
Reset Output ... .................... ...... ................... ....... ...... .................... ...... ................ 29
Power Monitor..................................................................................... 30
Description.......................................................................................................... 30
Timer 2................................................................................................. 32
Auto-relo ad Mod e............... ...... ...... ....... ...... ....... ................... .................... ...... ... 32
Programmable
Clock-output ................................................................................................................. 33
Registers............................................................................................................. 35
Programmable Counter Array (PCA) ................................................ 37
PCA Capture Mode............................................................................................. 45
16-bit Software Timer/ Compare Mode............................................................... 45
High Speed Output Mode................................................................................... 46
Pulse Width Modulator Mode.............................................................................. 47
PCA Watchdog Timer......................................................................................... 48
ii AT89C51RD2/ED2 A–8051–08/03
Serial I/O Port...................................................................................... 49
Framing Error Detection ..................................................................................... 49
Automatic Address Recognition.......................................................................... 50
Registers............................................................................................................. 52
Baud Rate Selection for UART for Mode 1 and 3............................................... 52
UART Registers.................................................................................................. 55
Keyboard Interface............................................................................. 60
Registers............................................................................................................. 61
Serial Port Interface (SPI)................................................................... 64
Features.............................................................................................................. 64
Signal Des criptio n............... ...... ...... ....... ...... ....... ...... ....... ...... .................... ......... 64
Functional Description........................................................................................ 66
Interrupt System................................................................................. 74
Registers............................................................................................................. 75
Interrupt Sources and Vector Addresses............................................................ 76
Power Management............................................................................ 83
Introduction......................................................................................................... 83
Idle Mode............................................................................................................ 83
Power-Down Mode ............................................................................................. 83
Registers............................................................................................................. 86
Hardware Watchdog Timer ................................................................ 87
Using the WDT ................................................................................................... 87
WDT during Power-down and Idle...................................................................... 88
ONCE® Mode (ON- Chip Emulation).................................................. 89
Power-off Flag..................................................................................... 90
Reduced EMI Mode............................................................................. 91
EEPROM Data Memory....................................................................... 92
Write Data........................................................................................................... 92
Read Data........................................................................................................... 94
Registers............................................................................................................. 95
Flash/EEPROM Memory..................................................................... 96
Features.............................................................................................................. 96
Flash Programming and Erasure........................................................................ 96
Flash Registers and Memory Map...................................................................... 97
Flash Memory Status........................................................................................ 100
Memory Organization ....................................................................................... 100
iii
AT89C51RD2/ED2
A–8051–08/03
Bootloader Architecture.................................................................................... 101
ISP Protocol Description................................................................................... 105
Functional Description...................................................................................... 106
Flow Description............................................................................................... 107
API Call Description.......................................................................................... 115
Electrical Characteristics................................................................. 117
Absolute Maximum Ratings.............................................................................. 117
DC Parameters for Standard Voltage............................................................... 117
AC Parameters................................................................................................. 120
Ordering Information........................................................................ 128
Packaging Information..................................................................... 129
PLCC44............................................................................................................ 129
VQFP44............................................................................................................ 130
DIL40................................................................................................................ 131
PLCC68............................................................................................................ 132
VQFP64............................................................................................................ 133
Datasheet Change Log for AT89C51RD2/ED2 ............................... 134
Changes from 4235A -04/03 to 4135B - 06/03................................................. 134
Changes from 4235B -06/03 to 4135C - 07/03................................................. 134
Table of Contents .................................................................................. i
Printed on recycled paper.
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warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no respon sibility for any
errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and
does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are
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