VOUT
AVIN
SW
CI
SW
LED1
CO
10 mF
PGND
PGND
AGND
L
2.2 Hm
SDA
SCL
TPS61300
LED2
LED3
D2
2.5V..5.5V
ENDCL
FLASH_SYNC
Tx- MASK
GPIO/PGENVM
INDLED
Privacy
Indicator
CAMERA ENGINE
I2CI/F
HC_SEL BAL
FLASHREADY
PHONEPOWERON
1.8 V
SUPER-CAP
D1
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
1.5A/4.1A Multiple LED Camera Flash Driver With I
2
C
TM
Compatible Interface
Check for Samples: TPS61300,TPS61301,TPS61305
1FEATURES DESCRIPTION
The TPS6130x device is based on a high-frequency
23• Four Operational Modes synchronous boost topology with constant current
– DC Light and Flashlight sinks to drive up to three white LEDs in parallel
– Voltage Regulated Converter: 3.8V...5.7V (400mA/800mA/400mA maximum flash current). The
extended high-current mode (HC_SEL) allows up
– Standby: 2μA (typ.) to 1025mA/2050mA/1025mA flash current out of
• Storage Capacitor Friendly Solution the storage capacitor.
• Automatic VFand ESR Calibration The high-capacity storage capacitor on the output of
• Power-Save Mode for Improved Efficiency at the boost regulator provides the high-peak flash LED
Low Output Power, Up to 95% Efficiency current, thereby reducing the peak current demand
• Output Voltage Remains Regulated When from the battery to a minimum.
Input Voltage Exceeds Nominal Output Voltage The 2-MHz switching frequency allows the use of
• I2C Compatible Interface up to 3.4Mbits/s small and low profile 2.2μH inductors. To optimize
overall efficiency, the device operates with a 400mV
• Zero Latency Tx-Masking Input LED feedback voltage.
• Hardware Voltage Mode Selection Input
(TPS61300, TPS61301) The TPS6130x device not only operates as a
regulated current source, but also as a standard
• DC Light Mode Selection Input voltage boost regulator. The device keeps the output
(TPS61300, TPS61306) voltage regulated even when the input voltage
• Hardware Reset Input (TPS61301, TPS61305) exceeds the nominal output voltage. The device
• LED Temperature Monitoring (TPS61305) enters power-save mode operation at light load
currents to maintain high efficiency over the entire
• Privacy Indicator LED Output load current range.
• Integrated LED Safety Timer To simplify flashlight synchronization with the camera
• Total Solution Size of Less Than 25 mm2module, the device offers a trigger pin
(<1mm height) (FLASH_SYNC) for zero latency LED turn-on time.
• Available in a 20-Pin NanoFree™ (CSP)
APPLICATIONS
• Single/Dual/Triple White LED Flashlight Supply
for Cell Phones and Smart-Phones
• LED Based Xenon "Killer" Flashlight
• Audio Amplifier Power Supply
Figure 1. Typical Application
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2NanoFree is a trademark of Texas Instruments.
3I2C is a trademark of NXP Semiconductors.
PRODUCTION DATA information is current as of publication date. Copyright © 2009–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
AVAILABLE OPTIONS
PART NUMBER(1) PACKAGE MARKING PACKAGE DEVICE SPECIFIC FEATURES(2)
TPS61300YFF TPS61300 CSP-20 Hardware Enable DC Light Input (ENDCL)
TPS61301YFF TPS61301 CSP-20 Hardware Enable / Disable Input (NRESET)
Hardware Enable / Disable Input (NRESET)
TPS61305YFF TPS61305 CSP-20 LED Temperature Monitoring Input (TS)
Hardware Enable DC Light Input (ENDCL)
TPS61306YFF(3) TPS61306 CSP-20 LED Temperature Monitoring Input (TS)
(1) The YFF package is available in tape and reel. Add R suffix (TPS6130xYFFR) to order quantities of 3000 parts per reel, T suffix for 250
parts per reel.
(2) For more details, refer to the section Application Diagrams.
(3) Device status is Product Preview. Please contact TI for more details.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VALUE UNIT
Voltage range on AVIN, VOUT, SW, LED1, LED2, LED3(2) –0.3 to 7 V
VIVoltage range on SCL, SDA, FLASH_SYNC, ENDCL, NRESET, ENVM, GPIO/PG(2) –0.3 to 7 V
Voltage range on HC_SEL, Tx-MASK, TS, BAL (2) –0.3 to 7 V
Current on GPIO/PG ±25 mA
Power dissipation Internally limited
TA(3) Operating ambient temperature range –40 to 85 °C
TJ (MAX) Maximum operating junction temperature 150 °C
Tstg Storage temperature range –65 to 150 °C
Human body model 2 kV
ESD rating (4) Charge device model 500 V
Machine model 100 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature [TA(max)] is dependent on the maximum operating junction temperature [TJ(max)], the
maximum power dissipation of the device in the application [PD(max)], and the junction-to-ambient thermal resistance of the part/package
in the application (θJA), as given by the following equation: TA(max) = TJ(max) – (θJA × PD(max))
(4) The human body model is a 100-pF capacitor discharged through a 1.5-kΩresistor into each pin. The machine model is a 200-pF
capacitor discharged directly into each pin.
DISSIPATION RATINGS
PACKAGE THERMAL RESISTANCE(1) THERMAL RESISTANCE(1) POWER RATING DERATING FACTOR
θJA θJB TA= 25°C ABOVE(2) TA= 25°C
YFF 71°C/W 21°C/W 1.4 W 14mW/°C
(1) Simulated with high-K board
(2) Maximum power dissipation is a function of TJ(max), θJA and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD= (TJ(max) – TA)/ θJA.
2Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
ELECTRICAL CHARACTERISTICS
Unless otherwise noted the specification applies for VIN = 3.6V over an operating junction temp. –40°C ≤TJ≤125°C; Circuit
of Parameter Measurement Information section (unless otherwise noted). Typical values are for TJ= 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
VIN Input voltage range 2.5 5.5 V
IOUT = 0 mA, device not switching μA
590 700
–40°C ≤TJ≤+85°C
IQOperating quiescent current into AVIN IOUT(DC) = 0mA, PWM operation mA
11.3
VOUT = 4.95V, voltage regulation mode
ISD Shutdown current HC_SEL = 0, –40°C ≤TJ≤+85°C 1 5 μA
HC_SEL = 1, storage capacitor balanced μA
ISTBY Standby current 2 12
–40°C ≤TJ≤+85°C
Pre-charge current VOUT = 2.3V, 2.5V ≤VIN ≤5.5V 150 mA
Pre-charge hysteresis (referred to VOUT) 40 75 mV
VUVLO Undervoltage lockout threshold V
VIN falling 2.3 2.4
(analog circuitry)
OUTPUT
Current regulation mode VIN 5.5 V
Output voltage range Voltage regulation mode 3.825 5.7 V
VOUT 2.5V ≤VIN ≤4.8V, –20°C ≤TJ≤+125°C
Internal feedback voltage accuracy –2% 2%
Boost mode, PWM voltage regulation
Power-save mode ripple voltage IOUT = 10 mA 0.015 VOUT VP-P
VOUT rising, 0000 ≤OV[3:0] ≤0100 4.5 4.65 4.8 V
Output overvoltage protection
OVP VOUT rising, 0101 ≤OV[3:0] ≤1111 5.8 6.0 6.2 V
Output overvoltage protection hysteresis VOUT falling, 0101 ≤OV[3:0] ≤1111 0.15 V
POWER SWITCH
rDS(on) Switch MOSFET on-resistance VOUT = VGS = 3.6 V 90 mΩ
Rectifier MOSFET on-resistance VOUT = VGS = 3.6 V 135 mΩ
Ilkg(SW) Leakage into SW VOUT = 0V, SW = 3.6V, –40°C ≤TJ≤+85°C 0.3 4 μA
VOUT = 4.95V, HC_SEL = 0
Ilim Rectifier valley current limit (open-loop) –20°C ≤TJ≤+85°C –15 +15 %
PWM operation, relative to selected ILIM
OSCILLATOR
fOSC Oscillator frequency 1.92 MHz
fACC Oscillator frequency –10 +7 %
THERMAL SHUTDOWN, HOT DIE DETECTOR
Thermal shutdown(1) 140 160 °C
Thermal shutdown hysteresis(1) 20 °C
Hot die detector accuracy(1) –8 8 °C
(1) Verified by characterization. Not tested in production.
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TPS61300 TPS61301 TPS61305
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
ELECTRICAL CHARACTERISTICS (Continued)
Unless otherwise noted the specification applies for VIN = 3.6V over an operating junction temp. –40°C ≤TJ≤125°C; Circuit
of Parameter Measurement Information section (unless otherwise noted). Typical values are for TJ= 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LED CURRENT REGULATOR
0.4V ≤VLED1/3 ≤2.0V –10 +10 %
00 ≤DCLC13[1:0] ≤11, TJ= +85°C
LED1/3 current accuracy(1) 0.4V ≤VLED1/3 ≤2.0V –7.5 +7.5 %
00 ≤FC13[1:0] ≤11, TJ= +85°C
HC_SEL = 0 0.4V ≤VLED2 ≤2.0V –10 +10 %
000 ≤DCLC2[2:0] ≤111, TJ= +85°C
LED2 current accuracy(1) 0.4V ≤VLED2 ≤2.0V –7.5 +7.5 %
000 ≤FC2[2:0] ≤111, TJ= +85°C
0.4V ≤VLED1/3 ≤2.0V –10 +10 %
00 ≤DCLC13[1:0] ≤11, TJ= +85°C
LED1/3 current accuracy(1) 0.4V ≤VLED1/3 ≤2.0V –10 +10 %
00 ≤FC13[1:0] ≤11, TJ= +85°C
HC_SEL = 1 0.4V ≤VLED2 ≤2.0V –10 +10 %
000 ≤DCLC2[2:0] ≤111, TJ= +85°C
LED2 current accuracy(1) 0.4V ≤VLED1/3 ≤2.0V –10 +10 %
000 ≤FC2[2:0] ≤111, TJ= +85°C
LED1/3 current matching(1) –10 +10 %
LED1/2/3 current temperature coefficient 0.05 %/°C
1.5V ≤(VIN-VINDLED) ≤2.5V
INDLED current accuracy 2.6mA ≤IINDLED ≤7.9mA –20 +20 %
TJ= +25°C
INDLED current temperature coefficient 0.04 %/°C
LED1/2/3 sense voltage ILED1-3 = full-scale current, HC_SEL = 0 400 mV
VDO LED1/2/3 sense voltage ILED1-3 = full-scale current, HC_SEL = 1 400 450 mV
VOUT dropout voltage IOUT = -7.5mA, device not switching 220 mV
LED1/2/3 input leakage current VLED1/2/3 = VOUT = 5V, –40°C ≤TJ≤+85°C 0.1 4 μA
INDLED input leakage current VINDLED = 0V, –40°C ≤TJ≤+85°C 0.1 1 μA
(1) Verified by characterization. Not tested in production.
4Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
ELECTRICAL CHARACTERISTICS
Unless otherwise noted the specification applies for VIN = 3.6V over an operating junction temp. –40°C ≤TJ≤125°C; Circuit
of Parameter Measurement Information section (unless otherwise noted). Typical values are for TJ= 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STORAGE CAPACITOR ACTIVE CELL BALANCING
Active cell balancing circuitry HC_SEL = 1, storage capacitor balanced 1.7 6.0 μA
quiescent current into VOUT –40°C ≤TJ≤+85°C
(VOUT – BAL) vs. BAL voltage difference
Active cell balancing accuracy Storage capacitor balanced HC_SEL = 1 –100 100 mV
VOUT = 5.7V
BAL output drive capability VOUT = 4.95V, Sink and source current ±10 ±15 mA
HC_SEL = 0, device in shutdown mode
Active discharge resistor 0.85 1.5 kΩ
VOUT to BAL and BAL to GND
LED TEMPERATURE MONITORING (TPS61305)
IO(TS) Temperature Sense Current Source Thermistor bias current 23.8 μA
TS Resistance (Warning Temperature) LEDWARN bit = 1, TJ≥25°C 39 44.5 50 kΩ
TS Resistance (Hot Temperature) LEDHOT bit = 1, TJ≥25°C 12.5 14.5 16.5 kΩ
SDA, SCL, GPIO/PG, ENVM, Tx-MASK, ENDCL, NRESET, FLASH_SYNC, HC_SEL
V(IH) High-level input voltage 1.2 V
V(IL) Low-level input voltage 0.4 V
Low-level output voltage (SDA) IOL = 8mA 0.3 V
V(OL) Low-level output voltage (GPIO) DIR = 1, IOL = 5mA 0.3 V
V(OH) High-level output voltage (GPIO) DIR = 1, GPIOTYPE = 0, IOH = 8mA VIN–0.4 V
Input connected to VIN or GND
I(LKG) Logic input leakage current 0.01 0.1 μA
–40°C ≤TJ≤+85°C
ENVM pull-down resistance ENVM ≤0.4 V 350 kΩ
ENDCL, NRESET pull-down ENDCL, NRESET ≤0.4 V 350 kΩ
resistance
RPD FLASH_SYNC pull-down resistance FLASH_SYNC ≤0.4 V 350 kΩ
Tx-MASK pull-down resistance Tx-MASK ≤0.4 V 350 kΩ
HC_SEL pull-down resistance HC_SEL ≤0.4 V 350 kΩ
SDA Input Capacitance SDA = VIN or GND 9 pF
SCL Input Capacitance SCL = VIN or GND 4 pF
GPIO/PG Input Capacitance DIR = 0, GPIO/PG = VIN or GND 9 pF
ENVM Input Capacitance ENVM = VIN or GND 4 pF
C(IN) ENDCL Input Capacitance ENDCL = VIN or GND 3 pF
HC_SEL Input Capacitance HC_SEL = VIN or GND 3.5 pF
Tx-MASK Input Capacitance Tx-MASK = VIN or GND 4 pF
FLASH_SYNC Input Capacitance FLASH_SYNC = VIN or GND 3 pF
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TPS61300 TPS61301 TPS61305
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise noted the specification applies for VIN = 3.6V over an operating junction temp. –40°C ≤TJ≤125°C; Circuit
of Parameter Measurement Information section (unless otherwise noted). Typical values are for TJ= 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TIMING
tNRESET Reset pulse width 10 μs
From shutdown into DC light mode 1.4 ms
HC_SEL = 0, ILED = 100mA
Start-up time From shutdown into voltage mode via ENVM 550 μs
HC_SEL = 0, IOUT = 0mA
MODE_CTRL[1:0] = 10, HC_SEL = 0 400 μs
ILED2 = from 0mA to 800mA
LED current settling time(1) triggered
by a rising edge on FLASH_SYNC MODE_CTRL[1:0] = 10, HC_SEL = 1 16 μs
ILED2 = from 0mA to 1800mA
LED current settling time(1) triggered MODE_CTRL[1:0] = 10, HC_SEL = 0 15 μs
by Tx-MASK ILED2 = from 800mA to 350mA
(1) Settling time to ±15% of the target value.
I2C INTERFACE TIMING CHARACTERISTICS(1)
PARAMETER TEST CONDITIONS MIN MAX UNIT
Standard mode 100 kHz
Fast mode 400 kHz
High-speed mode (write operation), CB– 100 pF max 3.4 MHz
f(SCL) SCL Clock Frequency High-speed mode (read operation), CB– 100 pF max 3.4 MHz
High-speed mode (write operation), CB– 400 pF max 1.7 MHz
High-speed mode (read operation), CB– 400 pF max 1.7 MHz
Standard mode 4.7 μs
Bus Free Time Between a STOP and
tBUF START Condition Fast mode 1.3 μs
Standard mode 4 μs
Hold Time (Repeated) START
tHD, tSTA Fast mode 600 ns
Condition High-speed mode 160 ns
Standard mode 4.7 μs
Fast mode 1.3 μs
tLOW LOW Period of the SCL Clock High-speed mode, CB– 100 pF max 160 ns
High-speed mode, CB– 400 pF max 320 ns
Standard mode 4 μs
Fast mode 600 ns
tHIGH HIGH Period of the SCL Clock High-speed mode, CB– 100 pF max 60 ns
High-speed mode, CB– 400 pF max 120 ns
Standard mode 4.7 μs
Setup Time for a Repeated START
tSU, tSTA Fast mode 600 ns
Condition High-speed mode 160 ns
Standard mode 250 ns
tSU, tDAT Data Setup Time Fast mode 100 ns
High-speed mode 10 ns
Standard mode 0 3.45 μs
Fast mode 0 0.9 μs
tHD, tDAT Data Hold Time High-speed mode, CB– 100 pF max 0 70 ns
High-speed mode, CB– 400 pF max 0 150 ns
(1) Specified by design. Not tested in production.
6Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
I2C INTERFACE TIMING CHARACTERISTICS(1) (continued)
PARAMETER TEST CONDITIONS MIN MAX UNIT
Standard mode 20 + 0.1 CB1000 ns
Fast mode 20 + 0.1 CB300 ns
tRCL Rise Time of SCL Signal High-speed mode, CB– 100 pF max 10 40 ns
High-speed mode, CB– 400 pF max 20 80 ns
Standard mode 20 + 0.1 CB1000 ns
Rise Time of SCL Signal After a Fast mode 20 + 0.1 CB300 ns
tRCL1 Repeated START Condition and After High-speed mode, CB– 100 pF max 10 80 ns
an Acknowledge BIT High-speed mode, CB– 400 pF max 20 160 ns
Standard mode 20 + 0.1 CB300 ns
Fast mode 20 + 0.1 CB300 ns
tFCL Fall Time of SCL Signal High-speed mode, CB– 100 pF max 10 40 ns
High-speed mode, CB– 400 pF max 20 80 ns
Standard mode 20 + 0.1 CB1000 ns
Fast mode 20 + 0.1 CB300 ns
tRDA Rise Time of SDA Signal High-speed mode, CB– 100 pF max 10 80 ns
High-speed mode, CB– 400 pF max 20 160 ns
Standard mode 20 + 0.1 CB300 ns
Fast mode 20 + 0.1 CB300 ns
tFDA Fall Time of SDA Signal High-speed mode, CB– 100 pF max 10 80 ns
High-speed mode, CB– 400 pF max 20 160 ns
Standard mode 4 μs
tSU, tSTO Setup Time for STOP Condition Fast mode 600 ns
High-speed mode 160 ns
CBCapacitive Load for SDA and SCL 400 pF
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): TPS61300 TPS61301 TPS61305
Sr PSr
tfDA trDA
thd;DAT
tsu;STA thd;STA tsu;DAT
tsu;STO
trCL1
tfCL
tHIGH tLOW tLOW tHIGH
trCL trCL1
=MCSCurrentSourcePull-Up
=R(P) ResistorPull-Up
SDAH
SCLH
NoteA:FirstrisingedgeoftheSCLHsignalafterSrandaftereachacknowledgebit.
SeeNoteASeeNoteA
tftLOW tr
thd;STA
thd;DAT
tsu;DAT tf
HIGH
tsu;STA
S Sr P S
thd;STA tr
tBUF
tsu;STO
SDA
SCL
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
I2C TIMING DIAGRAMS
Figure 2. Serial Interface Timing for F/S-Mode
Figure 3. Serial Interface Timing for H/S-Mode
8Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
E4
E3
E2
E1
D4
D3
D2
D1
C4
C3
C2
C1
B4
B3
B2
B1
A4
A3
A2
A1
A4
A3
A2
A1
B4
B3
B2
B1
C4
C3
C2
C1
D4
D3
D2
D1
E4
E3
E2
E1
CSP-20
(TOP VIEW)
CSP-20
(BOTTOMVIEW)
VOUT
AVIN
SW
CI
SW
LED1
PGND
PGND
AGND
L
2.2 mH
SDA
SCL
High-Speed
I2
CI/F
TPS61305
LED2
LED3
D1 D2
2.5 V..5.5 V
FLASH_SYNC
TS
HC_SEL
GPIO/PG
INDLED
Privacy
Indicator
BAL
NTC
Tx -MASK
ENDCL
CO
10 mF
SUPER-CAP
VOUT
AVIN
SW
CI
SW
LED1
PGND
PGND
AGND
L
2.2 mH
SDA
SCL
High- Speed
I2
CI/F
TPS61301
LED2
LED3
D1 D2
2.5 V..5.5 V
NRESET
FLASH_SYNC
Tx-MASK
HC_SEL
GPIO/PGENVM
INDLED
Privacy
Indicator
BAL
CO
10mF
SUPER-CAP
VOUT
AVIN
SW
CI
SW
LED1
PGND
PGND
AGND
L
2.2 mH
SDA
SCL
High-Speed
I2CI/F
TPS61305
LED2
LED3
D1 D2
2.5 V..5.5 V
FLASH_SYNC
TS
HC_SEL
GPIO/PG
INDLED
Privacy
Indicator
BAL
NTC
Tx-MASK
NRESET
CO
10 mF
SUPER-CAP
VOUT
AVIN
SW
CI
SW
LED1
CO
10 mF
PGND
PGND
AGND
L
2.2 mH
SDA
SCL
TPS61300
LED2
LED3
D1 D2
2.5V.. 5.5V
ENDCL
FLASH_SYNC
Tx- MASK
GPIO/PGENVM
INDLED
Privacy
Indicator
CAMERA ENGINE
I2CI/F
HC_SEL BAL
PHONEPOWERON
SUPER-CAP
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
DEVICE INFORMATION
APPLICATION DIAGRAMS
Figure 4. TPS61300, Typical Application Figure 5. : TPS61305, Typical Application
Figure 6. TPS61301, Typical Application Figure 7. TPS61306, Typical Application
PIN ASSIGNMENTS
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): TPS61300 TPS61301 TPS61305
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
PIN FUNCTIONS (TPS61300)
PIN I/O DESCRIPTION
NAME NO.
AVIN E4 I This is the input voltage pin of the device. Connect directly to the input bypass capacitor.
VOUT A2 O This is the output voltage pin of the converter.
LED1 E2 I LED return input. This feedback pin regulates the LED current through the internal sense resistor by
regulating the voltage across it. The regulation operates with typically 400mV (HC_SEL = L) or 400mV
LED2 E1 I (HC_SEL = H) dropout voltage. Connect to the cathode of the LEDs.
LED3 E3 I
FLASH_SYNC B4 I Flashlight strobe pulse synchronization input.
FLASH_SYNC = LOW: The device is operating and regulating the LED current to the DC light current level
(DCLC).
FLASH_SYNC = HIGH: The device is operating and regulating the LED current to the flashlight current level
(FC).
HC_SEL B3 I Extended high-current mode selection input. This pin must not be left floating and must be terminated.
HC_SEL = LOW: LED direct drive mode. The power stage is active and the maximum LED currents are
defined as 400mA/800mA/400mA (ILED1/ILED2/ILED3).
HC_SEL = HIGH: Energy storage mode. In flash mode, the power stage is either active with reduced
current capability or disabled. The maximum LED current is defined as 925mA/1850mA/925mA
(ILED1/ILED2/ILED3).
SCL B2 I Serial interface clock line. This pin must not be left floating and must be terminated.
SDA B1 I/O Serial interface address/data line. This pin must not be left floating and must be terminated.
GPIO/PG D4 I/O This pin can either be configured as a general purpose input/output pin (GPIO) or either as an open-drain or
a push-pull output to signal when the converters output voltage is within the regulation limits (PG). Per
default, the pin is configured as an open-drain power-good output.
ENVM C4 I Enable pin for voltage mode converter. Pulling this pin high forces the device into voltage regulation mode
(VOUT is preset to a fixed value, 4.95V).
INDLED A1 O This pin provides a constant current source to drive low VFLEDs. Connect to LED anode.
ENDCL D3 I Hardware control pin for DC light operation. Pulling this pin high forces the device into DC light operation.
The ENDCL input is only active when the device is programmed into shutdown or voltage mode regulation.
LED1-3 inputs are controlled according to ENLED[3:1] bit settings.
Tx-MASK C3 I RF PA synchronization control input. Pulling this pin high turns the LED from flashlight to DC light operation,
thereby reducing almost instantaneously the peak current loading from the battery.
SW C1 I/O Inductor connection. Drain of the internal power MOSFET. Connect to the switched side of the inductor. SW
C2 is high impedance during shutdown.
BAL A3 O Balancing output for dual cells super-capacitor. In steady-state operation, this output compensates for
leakage current mismatch between the cells.
PGND D1 Power ground. Connect to AGND underneath IC.
D2
AGND A4 Analog ground.
10 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
PIN FUNCTIONS (TPS61301)
PIN I/O DESCRIPTION
NAME NO.
AVIN E4 I This is the input voltage pin of the device. Connect directly to the input bypass capacitor.
VOUT A2 O This is the output voltage pin of the converter.
LED1 E2 I LED return input. This feedback pin regulates the LED current through the internal sense resistor by
regulating the voltage across it. The regulation operates with typically 400mV (HC_SEL = L) or 400mV
LED2 E1 I (HC_SEL = H) dropout voltage. Connect to the cathode of the LEDs.
LED3 E3 I
FLASH_SYNC B4 I Flashlight strobe pulse synchronization input.
FLASH_SYNC = LOW: The device is operating and regulating the LED current to the DC light current
level (DCLC).
FLASH_SYNC = HIGH: The device is operating and regulating the LED current to the flashlight current
level (FC).
HC_SEL B3 I Extended high-current mode selection input. This pin must not be left floating and must be terminated.
HC_SEL = LOW: LED direct drive mode. The power stage is active and the maximum LED currents are
defined as 400mA/800mA/400mA (ILED1/ILED2/ILED3).
HC_SEL = HIGH: Energy storage mode. In flash mode, the power stage is either active with reduced
current capability or disabled. The maximum LED current is defined as 925mA/1850mA/925mA
(ILED1/ILED2/ILED3).
SCL B2 I Serial interface clock line. This pin must not be left floating and must be terminated.
SDA B1 I/O Serial interface address/data line. This pin must not be left floating and must be terminated.
GPIO/PG D4 I/O This pin can either be configured as a general purpose input/output pin (GPIO) or either as an open-drain
or a push-pull output to signal when the converters output voltage is within the regulation limits (PG). Per
default, the pin is configured as an open-drain power-good output.
ENVM C4 I Enable pin for voltage mode converter. Pulling this pin high forces the device into voltage regulation mode
(VOUT is preset to a fixed value, 4.95V).
INDLED A1 O This pin provides a constant current source to drive low VFLEDs. Connect to LED anode.
NRESET D3 I Master hardware reset input. NRESET = LOW: The device is forced in shutdown mode and the I2C
control I/F is reset. NRESET = HIGH: The device is operating normally under the control of the I2C
interface.
Tx-MASK C3 I RF PA synchronization control input. Pulling this pin high turns the LED from flashlight to DC light
operation, thereby reducing almost instantaneously the peak current loading from the battery.
SW C1 I/O Inductor connection. Drain of the internal power MOSFET. Connect to the switched side of the inductor.
C2 SW is high impedance during shutdown.
BAL A3 O Balancing output for dual cells super-capacitor. In steady-state operation, this output compensates for
leakage current mismatch between the cells.
PGND D1 Power ground. Connect to AGND underneath IC.
D2
AGND A4 Analog ground.
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): TPS61300 TPS61301 TPS61305
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
PIN FUNCTIONS (TPS61305)
PIN I/O DESCRIPTION
NAME NO.
AVIN E4 I This is the input voltage pin of the device. Connect directly to the input bypass capacitor.
VOUT A2 O This is the output voltage pin of the converter.
LED1 E2 I LED return input. This feedback pin regulates the LED current through the internal sense resistor by
regulating the voltage across it. The regulation operates with typically 400mV (HC_SEL = L) or 400mV
LED2 E1 I (HC_SEL = H) dropout voltage. Connect to the cathode of the LEDs.
LED3 E3 I
FLASH_SYNC B4 I Flashlight strobe pulse synchronization input.
FLASH_SYNC = LOW: The device is operating and regulating the LED current to the DC light current level
(DCLC).
FLASH_SYNC = HIGH: The device is operating and regulating the LED current to the flashlight current
level (FC).
HC_SEL B3 I Extended high-current mode selection input. This pin must not be left floating and must be terminated.
HC_SEL = LOW: LED direct drive mode. The power stage is active and the maximum LED currents are
defined as 445mA/890mA/445mA (ILED1/ILED2/ILED3).
HC_SEL = HIGH: Energy storage mode. In flash mode, the power stage is either active with reduced
current capability or disabled. The maximum LED current is defined as 1025mA/2050mA/1025mA
(ILED1/ILED2/ILED3).
SCL B2 I Serial interface clock line. This pin must not be left floating and must be terminated.
SDA B1 I/O Serial interface address/data line. This pin must not be left floating and must be terminated.
GPIO/PG D4 I/O This pin can either be configured as a general purpose input/output pin (GPIO) or either as an open-drain
or a push-pull output to signal when the converters output voltage is within the regulation limits (PG). Per
default, the pin is configured as an open-drain power-good output.
TS C4 I/O NTC resistor connection. This pin can be used to monitor the LED temperature. Connect a 220kΩNTC
resistor from the TS input to ground. In case this functionality is not desired, the TS input should be tied to
AVIN or left floating.
INDLED A1 O This pin provides a constant current source to drive low VFLEDs. Connect to LED anode.
NRESET D3 I Master hardware reset input.
NRESET = LOW: The device is forced in shutdown mode and the I2C control I/F is reset.
NRESET = HIGH: The device is operating normally under the control of the I2C interface.
Tx-MASK C3 I RF PA synchronization control input. Pulling this pin high turns the LED from flashlight to DC light
operation, thereby reducing almost instantaneously the peak current loading from the battery.
SW C1 I/O Inductor connection. Drain of the internal power MOSFET. Connect to the switched side of the inductor.
C2 SW is high impedance during shutdown.
BAL A3 O Balancing output for dual cells super-capacitor. In steady-state operation, this output compensates for
leakage current mismatch between the cells.
PGND D1 Power ground. Connect to AGND underneath IC.
D2
AGND A4 Analog ground.
12 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
PIN FUNCTIONS (TPS61306)
PIN I/O DESCRIPTION
NAME NO.
AVIN E4 I This is the input voltage pin of the device. Connect directly to the input bypass capacitor.
VOUT A2 O This is the output voltage pin of the converter.
LED1 E2 I LED return input. This feedback pin regulates the LED current through the internal sense resistor by
regulating the voltage across it. The regulation operates with typically 400mV (HC_SEL = L) or 400mV
LED2 E1 I (HC_SEL = H) dropout voltage. Connect to the cathode of the LEDs.
LED3 E3 I
FLASH_SYNC B4 I Flashlight strobe pulse synchronization input.
FLASH_SYNC = LOW: The device is operating and regulating the LED current to the DC light current level
(DCLC).
FLASH_SYNC = HIGH: The device is operating and regulating the LED current to the flashlight current
level (FC).
HC_SEL B3 I Extended high-current mode selection input. This pin must not be left floating and must be terminated.
HC_SEL = LOW: LED direct drive mode. The power stage is active and the maximum LED currents are
defined as 445mA/890mA/445mA (ILED1/ILED2/ILED3).
HC_SEL = HIGH: Energy storage mode. In flash mode, the power stage is either active with reduced
current capability or disabled. The maximum LED current is defined as 1025mA/2050mA/1025mA
(ILED1/ILED2/ILED3).
SCL B2 I Serial interface clock line. This pin must not be left floating and must be terminated.
SDA B1 I/O Serial interface address/data line. This pin must not be left floating and must be terminated.
GPIO/PG D4 I/O This pin can either be configured as a general purpose input/output pin (GPIO) or either as an open-drain
or a push-pull output to signal when the converters output voltage is within the regulation limits (PG). Per
default, the pin is configured as an open-drain power-good output.
TS C4 I/O NTC resistor connection. This pin can be used to monitor the LED temperature. Connect a 220kΩNTC
resistor from the TS input to ground. In case this functionality is not desired, the TS input should be tied to
AVIN or left floating.
INDLED A1 O This pin provides a constant current source to drive low VFLEDs. Connect to LED anode.
ENDCL D3 I Hardware control pin for DC light operation. Pulling this pin high forces the device into DC light operation.
The ENDCL input is only active when the device is programmed into shutdown or voltage mode regulation.
LED1-3 inputs are controlled according to ENLED[3:1] bit settings.
Tx-MASK C3 I RF PA synchronization control input. Pulling this pin high turns the LED from flashlight to DC light
operation, thereby reducing almost instantaneously the peak current loading from the battery.
SW C1 I/O Inductor connection. Drain of the internal power MOSFET. Connect to the switched side of the inductor.
C2 SW is high impedance during shutdown.
BAL A3 O Balancing output for dual cells super-capacitor. In steady-state operation, this output compensates for
leakage current mismatch between the cells.
PGND D1 Power ground. Connect to AGND underneath IC.
D2
AGND A4 Analog ground.
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TPS61300 TPS61301 TPS61305
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
FUNCTIONAL BLOCK DIAGRAM (TPS61300)
14 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
Undervoltage
Lockout
BiasSupply
AVIN
VOUT
SW
LED2
REF
Bandgap
SCL
SDA
I2CI/F
AGND PGND
FLASH_SYNC
CURRENT
CONTROL
P
P
SENSEFB
COMPARATOR
ERROR
AMPLIFIER
OVP
COMPARATOR
VOLTAGE
REGULATION
CURRENT
REGULATION
VREF
ON/OFF
Control
Logic
MaxtON Timer
DAC
TON
Control
Backgate
Control
LED1
CURRENT
CONTROL
Low-SideLEDCurrentRegulator
P
SENSEFB
ON/OFF
P
LED3
VLEDSense
DAC
SENSEFB
Tx- MASK
NRESET
ENVM
INDLED
AVIN
INDC[1:0]
High-SideLEDCurrentRegulator
Slew-Rate
Controller
HotDie
Indicator
HC_SEL
VOUT
BAL
EN
HC_SEL
VOUT
2Z
Z
Oscillator
R
S
Q
Q
CONTROL LOGIC
VREF =1.238V
350 kΩ
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
FUNCTIONAL BLOCK DIAGRAM (TPS61301)
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TPS61300 TPS61301 TPS61305
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
FUNCTIONAL BLOCK DIAGRAM (TPS61305)
16 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
FUNCTIONAL BLOCK DIAGRAM (TPS61306)
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): TPS61300 TPS61301 TPS61305
16-bitPrescaler Safety Timer
Time-Out (TO)
Dimming
(DIM)
Timer
Value
(STIM)
FLASH_SYNC
tPULSE
CLOCK
EdgeDetect
Start
MODE 0
MODE 1
CURRENT REGULATORMODE – DCLIGHT / FLASH ACTIVE
MODE 0 = LOW
MODE 1 = HIGH
Duty-CycleGenerator (0.8% … 8.6%) LED1-3 ON/OFFCONTROL
0: LED1-3 OFF
1: DCLIGHT CURRENT LEVEL
Start
Flash/Timer
(SFT)
Tx-MASK
0: DCLIGHT CURRENT LEVEL
1: FLASHCURRENT LEVEL
LED1-3 CURRENT CONTROL
350 kW
Safety Timer Trigger
(STT)
1
0
1
GPIO/PG
(GPIOBit)
PortDirection
(DIR)
(GPIOBit)
PWROK
Port Type
(PG)
DCLight
Safety Timer
(11.2s)
MODE 1
MODE 0
0: NORMAL OPERATION
1: DISABLECURRENT SINK
350 kW
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
TIMER BLOCK DIAGRAM
18 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
VOUT
AVIN
SW
CI
SW
LED1
PGND
PGND
AGND
L
2.2 mH
SDA
SCL
I2CI/F
TPS61305
LED2
LED3
D1 D2
2.5 V..5.5 V
FLASH_SYNC
TS
HC_SEL
GPIO/PG
INDLED
Privacy
Indicator
BAL
NTC
Tx-MASK
NRESET
CO
10 mF
SUPER-CAP
VOUT
AVIN
SW
CI
SW
LED1
CO
10 mF
PGND
PGND
AGND
L
2.2 mH
SDA
SCL
I2CI/F
TPS61300
LED2
LED3
D1 D2
2.5 V..5.5 V
ENDCL
FLASH_SYNC
Tx-MASK
HC_SEL
GPIO/PGENVM
INDLED
Privacy
Indicator
BAL
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
PARAMETER MEASUREMENT INFORMATION
List of Components:
L = 2.2μH, Wuerth Elektronik WE-TPC Series
CI, CO= 10μF 6.3V X5R 0603 – TDK C1605X5R0J106MT
Storage Capacitor = TDK EDLC262020-500mF
NTC = 220kΩ, muRata NCP18WM224J03RB
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): TPS61300 TPS61301 TPS61305
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS FIGURE
LED Power Efficiency vs. Input Voltage Figure 8, Figure 9
DC Input Current vs. Input Voltage Figure 10
Figure 11, Figure 12,
LED Current vs. LED Pin Headroom Voltage Figure 13
Figure 14, Figure 15,
LED Current vs. LED Current Digital Code Figure 16, Figure 17
INDLED Current vs. LED Pin Headroom Voltage Figure 18
Voltage Mode Efficiency vs. Output Current Figure 19, Figure 20
DC Output Voltage vs. Output Current Figure 21, Figure 22
Maximum Output Current vs. Input Voltage Figure 23
DC Pre-Charge Current vs. Differential Input-Output Voltage Figure 24, Figure 25
Valley Current Limit Figure 26, Figure 27
Balancing Current vs. Balance Pin Voltage Figure 28
Supply Current vs. Input Voltage Figure 29
Standby Current vs. Ambient Temperature Figure 30
Temperature Detection Threshold Figure 31, Figure 32
Junction Temperature vs. Port Voltage Figure 33
Flash Sequence (Direct Drive Mode) Figure 34
Figure 35, Figure 36,
Tx-Masking Operation Figure 37
Low-Light Dimming Mode Operation Figure 38
PWM Operation Figure 39
PFM Operation Figure 40
Down-Mode Operation (Voltage Mode) Figure 41
Voltage Mode Load Transient Response Figure 42
Start-up Into DC Light Operation Figure 43
Start-up Into Voltage Mode Operation Figure 44
Storage Capacitor Pre-Charge Figure 45
Figure 46, Figure 47,
Storage Capacitor Charge-Up Figure 48
DC Light Operation (Energy Storage Mode) Figure 49
Figure 50, Figure 51,
Flash Sequence (Energy Storage Mode) Figure 52, Figure 53,
Figure 54
Junction Temperature Monitoring Figure 55
Shutdown (Energy Storage Mode) Figure 56
20 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
0
100
200
300
400
500
600
700
800
900
400 500 600 700 800 900 1000 1100 1200 1300 1400
LED2PinHeadroomVoltage-mV
ILED2=800mA
ILED2=700mA
ILED2=550mA
ILED2=300mA
ILED2=450mA
ILED2=350mA
TPS61300
I =1750mA,
HC_SEL =Low
LIM
LED2Current-mA
0
250
500
750
1000
1250
1500
1750
2000
2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3
V -InputVoltage-V
I
I =1750mA,
HC_SEL =Tx-MASK=Low
LIM
ILED1= 50mA
ILED2=550mA
ILED3=2
ILED1= 50mA
ILED2=600mA
ILED3=3
ILED1= 50mA
ILED2=450mA
ILED3=2
TPS61300
ILED1= 50mA
ILED2=275mA
ILED3=2
DCInputCurrent-mA
0
10
20
30
40
50
60
70
80
90
100
LEDPowerEfficiency(PLED/PIN)-%
2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3
V -InputVoltage-V
I
TPS61300
ILED1= 50mA
ILED2=100mA
ILED3=
I =1750mA,
HC_SEL =Tx-MASK=Low
LIM
ILED1= 0mA
ILED2=200mA
ILED3=10
ILED1= 5mA
ILED2=150mA
ILED3=7
ILED1= 50mA
ILED2=550mA
ILED3=2
ILED1= 50mA
ILED2=600mA
ILED3=3
ILED1= 50mA
ILED2=450mA
ILED3=2
2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3
V -InputVoltage-V
I
0
10
20
30
40
50
60
70
80
90
100
LEDPowerEfficiency(PLED/PIN)-%
ILED2=75mA
ILED2=100mA
ILED2=150mA
ILED2=200mA
ILED2=250mA
TPS61300
I =1750mA,
HC_SEL =Tx-MASK=Low
LED2ChannelOnly
LIM
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
TYPICAL CHARACTERISTICS (continued)
Figure 8. LED Power Efficiency Figure 9. LED Power Efficiency
vs. vs.
Input Voltage Input Voltage
Figure 10. DC Input Current Figure 11. LED2 Current
vs. vs.
Input Voltage LED2 Pin Headroom Voltage (HC_SEL=0)
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): TPS61300 TPS61301 TPS61305
25
50
75
100
125
25 50 75 100 125
LED1,LED3CurrentDigitalCode-mA
V =4.5V
IN
V =3.6V
IN
V =2.5V
IN
LED1,LED3Current-mA
TPS61300
I =1750mA,
HC_SEL =Low
LIM
0
25
50
75
100
125
150
175
200
225
250
275
300
0 25 50 75 100 125 150 175 200 225 250 275 300
LED2CurrentDigitalCode-mA
V =2.5V
IN
V =4.5V
IN
V =3.6V
IN
LED2Current-mA
TPS61300
I =1750mA,
HC_SEL =Low
LIM
0
100
200
300
400
500
600
700
800
900
400 500 600 700 800 900 1000 1100 1200 1300 1400
LED1,LED3PinHeadroomVoltage-mV
LED1+LED3Current-mA
ILED1= ILED3=400mA
I =1750mA,
HC_SEL =Low
LIM
TPS61300
ILED1= ILED3=350mA
ILED1= ILED3=300mA
ILED1= ILED3=250mA
1400
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
300 400 500 600 700 800 900 1000 1100 1200 1300 1400
LED2PinHeadroomVoltage-mV
LED2Current-mA
TPS61305
ILED2=2050mA,T =85°C
A
ILED2=2050mA,T =25°C
A
ILED2=2050mA,T =-40°C
A
ILED2=1775mA,
T =25°C
A
ILED2=1775mA,
T =85°C
AILED2=1775mA,
T =-40°C
A
V =3.6V,V =4.95V
HC_SEL =High
IN OUT
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Figure 12. LED1+LED3 Current Figure 13. LED2 Current
vs. vs.
LED1+LED3 Pin Headroom Voltage (HC_SEL=0) LED2 Pin Headroom Voltage (HC_SEL=1)
Figure 14. LED2 Current Figure 15. LED1, LED3 Current
vs. vs.
LED2 Current Digital Code (HC_SEL=0) LED1, LED3 Current Digital Code (HC_SEL=0)
22 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1000 10000
I -OutputCurrent-mA
O
Efficiency-%
V =4.2V
IN
V =3.6V
IN
V =2.5V
IN
TPS61300
V =4.95V
VoltageModeRegulation
OUT
I =1750mA
LIM
V =3V
IN
PFM/PWMOperation
ForcedPWMOperation
0
1
2
3
4
5
6
7
8
9
0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9
INDLEDPinHeadroomVoltage-V
INDLEDCurrent-mA
INDLED=0011
INDLED=0010
INDLED=0001
T =85°C
A
T =25°C
A
T =-40°C
A
T =85°C
A
T =25°C
A
T =-40°C
A
T =85°C
A
T =25°C
A
TPS61300
V =3.6V
IN
T =-40°C
A
200
225
250
275
300
325
350
375
400
425
450
200 225 250 275 300 325 350 375 400 425 450
LED1,LED3CurrentDigitalCode-mA
V =4.5V
IN
V =3.6V
IN
V =2.5V
IN
TPS61300
I =1750mA,
HC_SEL =Low
LIM
LED1,LED3Current-mA
200
250
300
350
400
450
500
550
600
650
700
750
800
850
900
LED2CurrentDigitalCode-mA
V =4.5V
IN
V =3.6V
IN
TPS61300
I =1750mA,
HC_SEL =Low
LIM
200 300 400 500 600 700 800 900
V =2.5V
IN
LED2Current-mA
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
TYPICAL CHARACTERISTICS (continued)
Figure 16. LED2 Current Figure 17. LED1, LED3 Current
vs. vs.
LED2 Current Digital Code (HC_SEL=0) LED1, LED3 Current Digital Code (HC_SEL=0)
Figure 18. INDLED Current Figure 19. Efficiency
vs. vs.
INDLED Pin Headroom Voltage Output Current
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): TPS61300 TPS61301 TPS61305
3.71
3.749
3.787
3.825
3.863
3.902
3.94
3.978
4.016
2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3
I -OutputCurrent-mA
O
V -OutputVoltage(DC)-V
O
I =0mA
OUT
I =100mA
OUT
I =1000mA
OUT
TPS61300
VoltageModeRegulation
V =3.825V
OUT
I =1750mA
LIM
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3
V -InputVoltage-V
I
I -OutputCurrent(max)-mA
O
V =4.95V,
I =1250mA
OUT
LIM
TPS61300
VoltageModeRegulation
V =5.7V,
I =1250mA
OUT
LIM
V =5.7V,
I =500mA
OUT
LIM
V =4.95V,
I =250mA
OUT
LIM T =25°C
A
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1000 10000
I -OutputCurrent-mA
O
Efficiency-%
ForcedPWMOperation
PFM/PWMOperation
V =4.2V
IN
V =3.6V
IN
V =2.5V
IN V =3V
IN
TPS61300
V =3.825V
VoltageModeRegulation
OUT
I =1750mA
LIM
4.8
4.85
4.9
4.95
5
5.05
5.1
5.15
5.2
1 10 100 1000 10000
I -OutputCurrent-mA
O
V -OutputVoltage(DC)-V
O
TPS61300
VoltageModeRegulation
ForcedPWMOperation
PFM/PWMOperation
V =3.6V
IN
V =2.5V
IN
V =4.95V,
I =1750mA
OUT
LIM
V =4.2V
IN
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Figure 20. Efficiency Figure 21. DC Output Voltage
vs. vs.
Output Current Load Current
Figure 22. DC Output Voltage Figure 23. Maximum Output Current
vs. vs.
Load Current Input Voltage
24 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
0
3
6
9
12
15
18
21
24
27
30
33
36
39
42
45
48
300
330
360
390
420
450
480
510
540
570
600
630
660
690
720
750
T =25°C
A
T =85°C
A
T =-40°C
A
V =3.6V
IN
HC_SEL =1,
Tx-MASK=1,
I bit=1
LIM
SampleSize=70
I -ValleyCurrentLimit-mA
LIM
SamplePercentage-%
TPS61305
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
150
165
180
195
210
225
240
255
270
285
300
315
330
345
360
375
I -ValleyCurrentLimit-mA
LIM
SamplePercentage-%
HC_SEL =1,
Tx-MASK=1,
I bit=0
LIM
TPS61305
T =25°C
A
T =85°C
A
T =-40°C
A
V =3.6V
IN
SampleSize=70
0
50
100
150
200
250
300
350
400
0 0.6 1.2 1.8 2.4 3 3.6 4.2
DifferentialInput-OutputVoltage-V
TPS61305
V =3.6V,T =25°C
IN A
HC_SEL =1
V =2.5V,T =25°C
IN A
V =4.2V,T =25°C
IN A
DCPre-ChargeCurrent-mA
0
50
100
150
200
250
300
350
400
0 0.6 1.2 1.8 2.4 3 3.6 4.2
DifferentialInput-OutputVoltage-V
V =3.6V,T =-40°C
IN A
V =3.6V,T =25°C
IN A
V =3.6V,T =85°C
IN A
TPS61305
HC_SEL =1
DCPre-ChargeCurrent-mA
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
TYPICAL CHARACTERISTICS (continued)
Figure 24. DC Pre-Charge Current Figure 25. DC Pre-Charge Current
vs. vs.
Differential Input-Output Voltage (HC_SEL=1) Differential Input-Output Voltage (HC_SEL=1)
Figure 26. Valley Current Limit (HC_SEL=1) Figure 27. Valley Current Limit (HC_SEL=1)
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): TPS61300 TPS61301 TPS61305
0
0.5
1
1.5
2
2.5
3
-35 -25 -15 -5 5 15 25 35 45 55 65 75 85
T - AmbientTemperature-°C
A
I -StandbyCurrent- A
STBY m
V =4.8V
IN
V =3.6V
IN
V =2.5V
IN
HC_SEL =1
Storagecapacitorbalanced(I =0 A)
OUT m
TPS61305
0
2
4
6
8
10
12
14
16
18
20
22
24
26
50 51 52 53 54 55 56 57 58 59 60
TemperatureDetection(55°CThreshold)
SamplePercentage-%
V =3.6V
IN TPS61305
SampleSize=76
-20
-15
-10
-5
0
5
10
15
20
25
2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
V -BalancePinVoltage-V
BAL
TPS61305 V =4.95V,
HC_SEL =1
OUT
T =25°C
A
T =85°C
A
T =-40°C
A
I -BalancePinCurrent-mA
BAL
1000
500
600
700
800
900
1100
1200
1300
1400
1500
2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3
V -InputVoltage-V
I
I -SupplyCurrent- A
CC m
TPS61305
V =5.7V,T =25°C
OUT A
V =3.825V,
T =25°C
OUT
A
V =4.95V,
T =25°C
OUT
A
V =4.95V,T =85°C
OUT A
V =4.95V,
T =-40°C
OUT
A
I =0mA
ENPSMbit=ENVMbit=1
OUT
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Figure 28. Balancing Current Figure 29. Supply Current
vs. vs.
Balance Pin Voltage Input Voltage
Figure 30. Standby Current Figure 31. Temperature Detection Threshold
vs.
Ambient Temperature (HC_SEL=1)
26 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
t - Time = 500 µs/div
Tx-MASK
(2V/div)
I
(200mA/div)
LED2
TPS61300, HC_SEL = 0
V = 3.6V, V = 4.95V, I = 1750mA
IN OUT LIM
DCLC2[2:0] = 000
FC2[2:0] = 100
FLASH_SYNC
(2V/div)
I +
(200mA/div)
LED1 ILED3
DCLC13[1:0] = 00
FC13[1:0] = 01
t - Time = 1 ms/div
I
(500mA/div)
LED2
TPS61300, HC_SEL = 0
V = 3.6V, V = 4.95V, I = 1750mA
IN OUT LIM
LED2 Channel Only
DCLC2[2:0] = 000
FC2[2:0] = 111
FLASH_SYNC
(2V/div)
LED2 Pin Headroom Voltage
(1V/div)
V
(1V/div - 3.6V Offset)
OUT
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
64 65 66 67 68 69 70 71 72 73 74 75
TemperatureDetection(70°CThreshold)
SamplePercentage-%
V =3.6V
IN
SampleSize=76
TPS61305
-50
-25
0
25
50
75
100
125
150
175
200
-0.6 -0.55 -0.5 -0.45 -0.4 -0.35 -0.3 -0.25 -0.2 -0.15 -0.1
PortVoltage-V
T -JunctionTemperature-°C
J
VPORT
Port
InputBuffer
100 Am
TPS61300
I =-100 A
PORT m
ENDCL Input
Tx-MASKInput
ENVMInput
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
TYPICAL CHARACTERISTICS (continued)
Figure 32. Temperature Detection Threshold Figure 33. Junction Temperature
vs.
Port Voltage
Figure 34. FLASH SEQUENCE (HC_SEL=0) Figure 35. Tx-MASKING OPERATION (HC_SEL=0)
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): TPS61300 TPS61301 TPS61305
TPS61300,HC_SEL =0
V
(500mV/div-3.6VOffset)
OUT
I
(20mA/div)
LED2 Frequency=121Hz
DutyCycle=6.3%
V =3.6V,I =75mA
IN DCLIGHT2
t-Time=2ms/div
LED2ChannelOnly
INDC[3:0]=1110
t-Time=125ns/div
SW
(2V/div)
I
(200mA/div)
L
V
(20mV/div-4.95VOffset)
OUT
V =3.6V,
IN V =4.95V
I =300mA,I =1750mA
OUT
OUT LIM
ForcedPWMOperation
ENPSMbit=0
TPS61300,HC_SEL =0
t - Time = 5 µs/div
Tx-MASK
(2V/div)
I
(200mA/div)
LED2
I
(200mA/div)
L
TPS61300, HC_SEL = 0
V = 3.6V, V = 4.95V
I = 1750mA
IN OUT
LIM
LED2 Channel Only
DCLC2[2:0] = 110
FC2[2:0] = 111
t - Time = 100 µs/div
Tx-MASK
(2V/div)
I
(200mA/div)
LED2
I
(500mA/div)
L
TPS61300, HC_SEL = 0
V = 3.6V, V = 4.95V
I = 1750mA
IN OUT
LIM
LED2 Channel Only
DCLC2[2:0] = 001
FC2[2:0] = 111
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Figure 36. Tx-MASKING OPERATION (HC_SEL=0) Figure 37. Tx-MASKING OPERATION (HC_SEL=0)
Figure 38. LOW-LIGHT DIMMING MODE OPERATION Figure 39. PWM OPERATION
28 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
t-Time=50 s/divm
I
(500mA/div)
L
V
(500mV/div-4.95VOffset)
OUT
V =3.6V,
IN V =4.95V
I =1750mA
OUT
LIM
PFM/PWMOperation
ENPSMbit=1
TPS61300,HC_SEL =0
I
(500mA/div)
OUT
50mA to500mA LoadStep
t - Time = 200 µs/div
ENDCL
(2V/div)
I
(50mA/div)
LED2
I
(200mA/div)
L
TPS61300, HC_SEL = 0
V = 3.6V, V = 4.95V
I = 1750mA
IN OUT
LIM
LED2 Channel Only
DCLC2[2:0] = 011
V
(2V/div)
OUT
t-Time=2 s/divm
SW
(5V/div)
I
(200mA/div)
L
V
(100mV/div-4.95VOffset)
OUT
V =3.6V,
IN V =4.95V
I =50mA,I =1750mA
OUT
OUT LIM
PFM/PWMOperation
ENPSMbit=1
TPS61300
HC_SEL =0
t-Time=2 s/divm
SW
(5V/div)
I
(200mA/div)
L
V
(100mV/div-3.825VOffset)
OUT
V =4.2V,
IN V =3.825V
I =50mA,I =1750mA
OUT
OUT LIM
PFM/PWMOperation
ENPSMbit=1
TPS61300,HC_SEL =0
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
TYPICAL CHARACTERISTICS (continued)
Figure 40. PFM OPERATION Figure 41. DOWN-MODE OPERATION (VOLTAGE MODE)
Figure 42. VOLTAGE MODE LOAD TRANSIENT RESPONSE Figure 43. START-UP INTO DC LIGHT OPERATION
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Link(s): TPS61300 TPS61301 TPS61305
t - Time = 2 s/div
I
(200mA/div)
L
V
(2V/div)
OUT
V = 3.6V,
IN V = 4.95V
I = 0mA
OUT
OUT
ENPSM bit = 1, ILIM bit = 0
Tx-MASK = 1
TPS61305
(NRESET = 1)
PG (2V/div)
HC_SEL, ENVM (2V/div)
t - Time = 1 s/div
I
(500mA/div)
L
V
(1V/div)
OUT
V = 3.6V,
IN V = 4.95V
I = 0mA
OUT
OUT
ENPSM bit = 1, ILIM bit = 0
Tx-MASK = 0
TPS61305
(NRESET = 1)
PG (2V/div)
HC_SEL, ENVM (2V/div)
t - Time = 100 µs/div
ENVM
(2V/div)
I
(200mA/div)
L
TPS61300, HC_SEL = 0
V = 3.6V, V = 4.95V
I = 1750mA
IN OUT
LIM
I = 0mA,
OUT
V
(2V/div)
OUT
t - Time = 1 s/div
I
(100mA/div)
L
V
(1V/div)
OUT
V = 3.6V,
IN V = 4.95V
I = 0mA
OUT
OUT ENPSM bit = 1
TPS61305 (NRESET = 1)
PG (2V/div)
HC_SEL (2V/div)
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Figure 44. START-UP INTO VOLTAGE MODE OPERATION Figure 45. STORAGE CAPACITOR PRE-CHARGE
(HC_SEL=1)
Figure 46. STORAGE CAPACITOR CHARGE-UP (HC_SEL=1) Figure 47. STORAGE CAPACITOR CHARGE-UP (HC_SEL=1)
30 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
t - Time = 50 ms/div
V
(200mV/div - 4.95V Offset)
OUT
V = 3.6V,
IN V = 4.95V, LED2 Channel Only
OUT
ENPSM bit = 1,
ILIM bit = 0,
Tx-MASK = 1
TPS61305
(NRESET = 1)
PG (2V/div)
I
(1A/div)
LED2
DCLC2[2:0] = 000
FC2[2:0] = 111
FLASH_SYNC
(2V/div)
t - Time = 100 ms/div
V
(500mV/div - 4.95V Offset)
OUT
V = 3.6V,
IN V = 4.95V, LED2 Channel Only
OUT
ENPSM bit = 1,
ILIM bit = 0,
Tx-MASK = 1
TPS61305
(NRESET = 1)
I
(1A/div)
LED2
DCLC2[2:0] = 000
FC2[2:0] = 111
FLASH_SYNC
(2V/div)
I
(200mA/div)
L
PG (2V/div)
TPS61305
(NRESET=1)
V
(1V/div)
OUT
I
(200mA/div)
L
ENVMbit=1
V =3.6V,V =4.95V,
I =0mA
IN OUT
OUT
ENPSMbit=1,ILIMbit=0,
Tx-MASK=1,HC_SEL =1
t-Time=1s/div
t - Time = 500 ms/div
I + I
(50mA/div)
LED1 LED3
V
(1V/div)
OUT
V = 3.6V,
IN V = 4.95V
All LED Channels Active
OUT ENPSM bit = 1, ILIM bit = 0
Tx-MASK = 1
TPS61305
(NRESET = 1)
PG (2V/div)
I
(50mA/div)
LED2
DC Light
Turn-On Command
DC Light
Turn-Off Command
DCLC13[1:0] = 01
DCLC2[2:0] = 010
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
TYPICAL CHARACTERISTICS (continued)
Figure 48. STORAGE CAPACITOR CHARGE-UP (HC_SEL=1) Figure 49. DC LIGHT OPERATION (HC_SEL=1)
Figure 50. FLASH SEQUENCE (HC_SEL=1) Figure 51. FLASH SEQUENCE (HC_SEL=1)
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 31
Product Folder Link(s): TPS61300 TPS61301 TPS61305
T =55°C
J
TPS61305
(NRESET=1)
LEDV CalibratedCircuit,
ca.500mVLEDPinHeadroomPin(e/oStrobe)
F
DCLight=2sFlashStrobe=35ms
I +I
(1 A/div)
LED1 LED3
ENPSMbit=1,
Tx-MASKbit=0,
ILIMbit=1
I
(1 A/div)
LED2
DCLC2[2:0]=011
FC2[2:0]=111
V =3.6V,V =4.7V, AllLEDChannels Active
IN OUT
Tx-MASK
(10mV/div--0.55VOffset)
T =25°C
J
DCLC13[1:0]=01
FC13[1:0]=11
t-Time=500ms/div
PG
(2V/div)
TPS61305
(NRESET=1)
LEDV CalibratedCircuit,
ca.500mVLEDPinHeadroomPin(e/oStrobe)
F
V
(500mV/div-4.95VOffset)
OUT
I +I
(1 A/div)
LED1 LED3
Tx-MASKInput=1
ENPSMbit=1,
Tx-MASKbit=0,
ILIMbit=1
I
(1 A/div)
LED2 DCLC13[1:0]=00DCLC2[2:0]=000
FC13[1:0]=11FC2[2:0]=111
V =3.6V,V =4.95V, AllLEDChannels Active
IN OUT
t-Time=50ms/div
PG
(2V/div)
TPS61305
(NRESET=1)
LEDV CalibratedCircuit,
ca.500mVLEDPinHeadroomPin(e/oStrobe)
F
V
(200mV/div
-4.7VOffset)
OUT
I +I
(1 A/div)
LED1 LED3 Tx-MASKInput=1
Tx-MASKbit=0,
ILIMbit=1
ENPSMbit=1,
I
(1 A/div)
LED2 DCLC13[1:0]=00
FC13[1:0]=11
DCLC2[2:0]=000
FC2[2:0]=111
V =3.6V,V =4.7V, AllLEDChannels Active
IN OUT
t-Time=10ms/div
TPS61305
(NRESET=1)
V
(500mV/div-4.95VOffset)
OUT
ENPSMbit=1,
Tx-MASKbit=0,
ILIMbit=0
I
(1 A/div)
LED2
DCLC2[2:0]=000
FC2[2:0]=111
V =3.6V,V =4.95V,LED2ChannelOnly
IN OUT
FLASHSYNC
(2V/div)
I
(500mA/div)
L
Tx-MASKInput=1
t-Time=20ms/div
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Figure 52. FLASH SEQUENCE (HC_SEL=1) Figure 53. FLASH SEQUENCE (HC_SEL=1)
Figure 54. FLASH SEQUENCE (HC_SEL=1) Figure 55. JUNCTION TEMPERATURE MONITORING
(HC_SEL=1)
32 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
t - Time = 100 s/div
V
(500mV/div)
OUT
V = 3.6V,
IN I = 0mA
OUT
TPS61305 (NRESET = 1)
PG (2V/div)
HC_SEL (2V/div)
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
TYPICAL CHARACTERISTICS (continued)
Figure 56. SHUTDOWN (HC_SEL=1)
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 33
Product Folder Link(s): TPS61300 TPS61301 TPS61305
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
DETAILED DESCRIPTION
OPERATION
The TPS6130x family employs a 2MHz fixed on-time, PWM current-mode converter to generate the output
voltage required to drive up to three high power LEDs in parallel. The device integrates a power stage based on
an NMOS switch and a synchronous PMOS rectifier. The device also implements a set of linear low-side current
regulators to control the LED current when the battery voltage is higher than the diode forward voltage.
A special circuit is applied to disconnect the load from the battery during shutdown of the converter. In
conventional synchronous rectifier circuits, the back-gate diode of the high-side PMOS is forward biased in
shutdown and allows current flowing from the battery to the output. This device however uses a special circuit
which takes the cathode of the back-gate diode of the high-side PMOS and disconnects it from the source when
the regulator is in shutdown (HC_SEL = L).
The TPS6130x device cannot only operate as a regulated current source but also as a standard voltage boost
regulator featuring power-save mode for improved efficiency at light load. The voltage mode operation can be
activated either by a software command or by means of a hardware signal (ENVM). This additional operating
mode can be useful to properly synchronize the converter when supplying other high power consuming devices
in the system (e.g. hands-free audio power amplifier…) or any other component requiring a supply voltage higher
than the battery voltage.
The TPS6130x device also supports storage capacitor on its output (so called energy storage mode). In this
operating mode (HC_SEL = H), the inductive power stage is used to charge-up the super-capacitor to a user
selectable value. Once the charge-up is complete, the LEDs can be fired up to 1025mA (LED1 and LED3) and
2050mA (LED2) without causing a battery overload.
In general, a boost converter only regulates output voltages which are higher than the input voltage. This device
operates differently. For example, in the voltage mode operation the device is capable to regulate 4.2V at the
output from a battery voltage pulsing as high 5.5V. To control these applications properly, a down conversion
mode is implemented.
If the input voltage reaches or exceeds the output voltage, the converter changes to a down conversion mode. In
this mode, the control circuit changes the behavior of the rectifying PMOS. It sets the voltage drop across the
PMOS as high as needed to regulate the output voltage. This means the power losses in the converter increase.
This has to be taken into account for thermal consideration.
In direct drive mode (HC_SEL = L), the power stage is capable of supplying a maximum total current of roughly
1300 to 1500mA. The TPS61300 provides three constant current inputs, capable of sinking up to 400mA (LED1
and LED3) and 800mA (LED2) in flashlight mode.
The TPS6130x integrates an I2C compatible interface allowing transfers up to 3.4Mbits/s. This communication
interface can be used to set the operating mode (shutdown, constant output current mode vs. constant output
voltage mode), to control the brightness of the external LED (DC light and flashlight modes), to adjust the output
voltage (between 3.825V and 5.7V in 125mV steps) or to program the safety timer for instance. For more details,
refer to the I2C register description section.
In the TPS6130x device, the DC light and flash can be controlled either by the I2C interface or by the means of
hardware control signals (ENDCL and FLASH_SYNC). To simplify flashlight synchronization with the camera
module, the device offers a FLASH_SYNC strobe input pin to turn, with zero latency, the LED current from DC
light to flashlight.
The maximum duration of the flashlight pulse can be limited by means of an internal user programmable safety
timer (STIM). To avoid the LEDs to be kept accidentally on in DC light mode by software control, the device
implements a 11.2s watchdog timer.
34 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
DOWN MODE IN VOLTAGE REGULATION MODE
In general, a boost converter only regulates output voltages which are higher than the input voltage. The featured
devices come with the ability to regulate 4.2 V at the output with an input voltage being has high as 5.5V. To
control these applications properly, a down conversion mode is implemented.
In voltage regulation mode, if the input voltage reaches or exceeds the output voltage, the converter changes to
the down-conversion mode. In this mode, the control circuit changes the behavior of the rectifying PMOS. It sets
the voltage drop across the PMOS as high as needed to regulate the output voltage. This means the power
losses in the converter increase. This has to be taken into account for thermal consideration. The down
conversion mode is automatically turned-off as soon as the input voltage falls about 200mV below the output
voltage.
For proper operation in down conversion mode the output voltage should not be programmed higher than ca.
5.3V. Care should be taken not to violate the absolute maximum ratings at the SW pins.
The TPS6130x device uses a control architecture that allows to “recycle” excessive energy that might be stored
in the output capacitor. By reversing the operation of the boost power stage, the converter is capable of
transferring energy from its output back into the input source.
In high-current mode (HC_SEL = 1), this feature becomes useful to dynamically adjust the output voltage (VOUT)
depending on the operating conditions (e.g. +4.95V constant output voltage to support audio applications or
variable storage capacitor pre-charge voltage, refer to “storage capacitor pre-charge voltage calibration” section).
Notice that this reverse operating mode can only perform within an output voltage range higher than the input
supply. For example, if the storage capacitor is initially pre-charged to 4.95V, the input voltage is around 4.1V
and the target output voltage is set to 3.825V, the converter will only be able to lower the output node down to
the input level.
LED HIGH-CURRENT REGULATORS, UNUSED INPUTS
The TPS6130x device utilizes LED forward voltage sensing circuitry on LED1-3 pins to optimize the power stage
boost ratio for maximum efficiency. Due to the nature of the sensing circuitry, it is not recommended to leave any
of the LED1-3 pins unused if the operation has been selected via ENLED[3:1] bits. Leaving LED1-3 pins
unconnected, whilst the respective ENLEDx bits have been set, will force the control loop into high gain and
eventually trip the output over-voltage protection.
The LED1-3 inputs may be connected together to drive one or two LEDs at higher currents. Connecting the
current sink inputs in parallel does not affect the internal operation of the TPS6130x. For best operation, it is
recommended to disabled the LED inputs that are not used (refer to ENLED[3:1] bits description).
To achieve smooth LED current waveforms, the TPS61300 device actively controls the LED current ramp-
up/down sequence.
Table 1. LED Current Ramp-Up/Down Control vs Operating Mode
DIRECT DRIVE MODE (HC_SEL = 0) HIGH-CURRENT MODE (HC_SEL = 1)
ISTEP = 25 mA ISTEP = 56.25 mA
LED CURRENT RAMP-UP tRISE = 12 μs tRISE = 0.5 μs
Slew-rate ≉2.08 mA/μs Slew-rate ≉112.5 mA/μs
ISTEP = 25 mA ISTEP = 56.25 mA
LED CURRENT RAMP-DOWN tFALL = 0.5 μs tFALL = 0.5 μs
Slew-rate ≉50 mA/μs Slew-rate ≉112.5 mA/μs
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 35
Product Folder Link(s): TPS61300 TPS61301 TPS61305
VOUT NOM.
PFMmodeatlightload
PWMmodeatheavyload
PFMrippleabout 0.015 xVOUT
1.013 xVOUT NOM.
Output
Voltage
LED
CURRENT
Time
tRISE
ISTEP
tFALL
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
Figure 57. LED Current Slew-Rate Control
In high-current mode (HC_SEL = 1), the LED current settings are defined as a fixed ratio (x2.25) versus the
direct drive mode values (HC_SEL = L).
POWER-SAVE MODE OPERATION, EFFICIENCY
The TPS6130x device integrates a power save mode to improve efficiency at light load. In power save mode the
converter only operates when the output voltage trips below a set threshold voltage. It ramps up the output
voltage with one or several pulses and goes again into power save mode once the output voltage exceeds the
set threshold voltage.
Figure 58. Operation in PFM Mode and Transfer to PWM Mode
The power save mode can be enabled and disabled via the ENPSM bit. In down conversion mode, power save
mode is always active and the device cannot be forced into fixed frequency operation at light loads.
The LED sense voltage has a direct effect on the converter’s efficiency. Because the voltage across the low-side
current regulator does not contribute to the output power (LED brightness), the lower the sense voltage the
higher the efficiency will be.
In direct drive mode (HC_SEL = L), the energy is being directly transferred from the battery to the LEDs. The
integrated current control loop automatically selects the minimum boosting ratio to maintain regulation based on
the LED forward voltage and current requirements. The low-side current regulators will be dropping the voltage
difference between the input voltage and the LEDs forward voltage (VF(LED) < VIN). When running in boost mode
(VF(LED) > VIN), the voltage present at the LED1-3 pins of the low-side current regulators will be typically 400mV
leading to high power conversion efficiency. Depending on the input voltage and the LEDs forward voltage
characteristic the converter will show efficiency in the range of about 75% to 90%.
In high-current mode (HC_SEL = H), the device is only supplying a limited amount of energy directly from the
battery (i.e. DC light, contribution to flash current or voltage regulation mode). During a flash strobe, the bulk of
the energy supplied to the LEDs is provided by the reservoir capacitor. The low-side current regulators will be
typically operating with 400mV headroom voltage. This means the power losses in the device increase and
special care should be taken for thermal considerations.
36 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
FLASH _SYNCor (SFT )
LEDCONTROL
TIMER STIM
TIME-OUT RESET (SF)
FLASH
DCLIGHT
FLASH_SYNCor (SFT)
TIMER STIM
LEDCONTROL
TIME-OUT RESET (SF)FLASH
DCLIGHT
FLASH
FLASH_SYNC
FREE FREEI2CBus
LEDCurrent
DC/DC Turn-OnCommand
MODE_CTRL[1:0]= “10"
DC/DC Turn-OffCommand
MODE_CTRL [1:0]= “00"
DCLIGHT
FREEFREE FREEI2CBus
LEDCurrent
LED Turn-OnCommand
MODE_CTRL [1:0]= “01"
LED Turn-OffCommand
MODE_CTRL[1:0]= “00"
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
MODE OF OPERATION: DC LIGHT AND FLASHLIGHT
Operation is understood best by referring to the timer block diagram. Depending on the settings of
MODE_CTRL[1:0] bits the device can enter 4 different operating modes. The below section details the
converter’s operation for ENVM = 0.
• MODE_CTRL[1:0] = 00: The device is in shutdown mode.
• MODE_CTRL[1:0] = 01: The device is regulating the LED current to the DC light current level (DCLC bits)
regardless of the FLASH_SYNC input and START_FLASH/TIMER (SFT) bit. To avoid device shutdown by
DC light safety timeout, MODE_CTRL[1:0] needs to be refreshed within less than 11.2s.
• MODE_CTRL[1:0] = 11: The device is regulating a constant output voltage according to OV[3:0] bits settings.
The low-side LED1-3 current sinks are disabled and the LEDs are disconnected from the output. In this
operating mode, the safety timer is disabled.
• MODE_CTRL[1:0] = 10: The flashlight pulse can be either trigger by a hardware signal (FLASH_SYNC) or by
a software bit (SFT). LED strobe pulse follows FLASH_SYNC.
FLASH STROBE IS LEVEL SENSITIVE (STT = 0): LED STROBE FOLLOWS FLASH_SYNC INPUT
FLASH_SYNC and (SFT) = 0: LED operation is set to the DC light current level. To avoid device shutdown by
DC light safety timeout, MODE_CTRL[1:0] needs to be refreshed within less than 11.2s.
FLASH_SYNC or (SFT) = 1: The LED is driven at the flashlight current level and the safety timer is running. The
maximum duration of the flashlight pulse is defined in the STIM[2:0] register.
Figure 59. DC Light Operation Figure 60. Synchronized Flashlight Strobe
Figure 61. Level Sensitive Safety Timer Figure 62. Level Sensitive Safety Timer
(Timeout) (Normal Operation + Timeout)
The safety timer is started by:
• a rising edge of FLASH_SYNC signal.
• a rising edge of START_FLASH/TIMER (SFT) bit.
The safety timer is stopped by:
• a low level of FLASH_SYNC signal or START_FLASH/TIMER (SFT) bit.
• a timeout signal (TO).
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 37
Product Folder Link(s): TPS61300 TPS61301 TPS61305
FLASH _SYNCor (SFT )
LEDCONTROL
TIMER STIM
RESET (SFT)
FLASH
DCLIGHT
FLASH_ SYNCor (SFT )
LEDCONTROL
TIMER STIM
RESET (SFT)
FLASH
DCLIGHT
FLASH _SYNCor (SFT )
LEDCONTROL
TIMER STIM
RESET (SFT)
FLASH
DCLIGHT
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
START-FLASH/TIMER (SFT) bit is being reset by the timeout (TO) signal.
FLASH STROBE IS LEADING EDGE SENSITIVE (STT = 1): ONE-SHOT LED STROBE
When FLASH_SYNC and START_FLASH/TIMER (SFT) are both low the LED operation is set to the DC Light
current level. To avoid device shutdown by DC light safety timeout, MODE_CTRL[1:0] needs to be refreshed
within less than 11.2s.
The duration of the flashlight pulse is defined in the STIM register. The flashlight strobe is started by:
• a rising edge of START_FLASH/TIMER (SFT) bit.
• a rising edge of FLASH_SYNC signal.
Once running, the timer ignores all kind of triggering signal and only stops after a timeout (TO). START-
FLASH/TIMER (SFT) bit is being reset by the timeout (TO) signal.
Figure 63. Edge Sensitive Timer Figure 64. Edge Sensitive Timer
(Single Trigger Event) (Single Trigger Event)
Figure 65. Edge Sensitive Timer
(Multiple Trigger Events)
SAFETY TIMER ACCURACY
The LED strobe timer uses the internal oscillator as reference clock. As a matter of fact, the timer execution
speed (refer to STIM[2:0]) scales according to the reference clock accuracy.
OSCILLATOR FREQUENCY SAFETY TIMER DURATION
Minimum Maximum = Typical × (1 + fACC)(1)
Typical Typical (2)
Maximum Minimum = Typical x (1 - fACC)(1)
(1) Refer to REGISTER3, STIM[2:0] definition.
(2) Refer to the Electrical Characteristics table.
38 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
IIN (DC)
Inductor
Current
Rectifier
Current
DIL
f
D
L
V
ΔI IN
L×=
DIL
CurrentLimit
Threshold IVALLEY = ILIM
IIN (DC)
Increased
LoadCurrent
IOUT (CL)
DIL
f
IPEAK
I (=I )
OUT(DC) LED
OUT ININ
OUT(CL) VALLEY L L
OUT
V VV
1 D
I = (1 D) (I + I ) with I = and D
2 L f V
-
- ´ D D ´ »
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
CURRENT LIMIT OPERATION
The current limit circuit employs a valley current sensing scheme. Current limit detection occurs during the off
time through sensing of the voltage drop across the synchronous rectifier. The detection threshold is user
selectable via the ILIM bit. The ILIM bit can only be set before the device enters operation (i.e., initial shutdown
state).
Figure 66 illustrates the inductor and rectifier current waveforms during current limit operation. The output
current, IOUT, is the average of the rectifier ripple current waveform. When the load current is increased such
that the lower peak is above the current limit threshold, the off time is lengthened to allow the current to decrease
to this threshold before the next on-time begins (so called frequency fold-back mechanism).
Both the output voltage and the switching frequency are reduced as the power stage of the device operates in a
constant current mode. The maximum continuous output current (IOUT(CL)), before entering current limit operation,
can be defined as:
(1)
The TPS6130x device also provides a negative current limit (c.a. 300mA) to prevent an excessive reverse
inductor current when the power stage sinks current from the output (i.e., storage capacitor) in the forced
continuous conduction mode.
Figure 66. Inductor/Rectifier Currents in Current Limit Operation
To minimize the requirements on the energy storage capacitor present at the output of the driver (HC_SEL = 1),
the TPS6130x device can contribute to a larger extent in supporting directly the high-current LED flash strobe. In
fact, the device can dynamically adjust it’s current limit setting according to the Tx-MASK input.
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 39
Product Folder Link(s): TPS61300 TPS61301 TPS61305
1.02 VOUT (NOM)
0.98 VOUT (NOM)
VOUT (NOM) = 4.2 V
OVP Threshold
DynamicLoad Transient LEDDisconnect
4.65 V ±150 mV
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
Table 2. Inductor Current Limit Operation vs HC_SEL/Tx-MASK Inputs
CURRENT LIMIT SETTING ILIM BIT HC_SEL INPUT Tx-MASK INPUT
1250 mA Low Low Low
1750 mA High Low Low
1250 mA Low High Low
1750 mA High High Low
1250 mA Low Low High
1750 mA High Low High
250 mA Low High High
500 mA High High High
LED FAILURE MODES AND OVER-VOLTAGE PROTECTION
If a high-power LED fails as a short circuit, the low-side current regulator will limit the maximum output current
and the HIGH-POWER LED FAILURE (HPLF) flag will be set.
If a high-power LED fails as an open circuit, the control loop will initially attempt to regulate off of its low-side
current regulator feedback signal. This will drive VOUT higher. As the open circuited LED will never accept its
programmed current, VOUT must be voltage-limited by means of a secondary control loop.
The TPS6130x device limits VOUT according to the over-voltage protection settings (refer to OVP specification). In
this failure mode, VOUT is either limited to 4.65V (typ.) or 6.0V (typ.) and the HIGH-POWER LED FAILURE
(HPLF) flag is set.
OVP THRESHOLD OPERATING CONDITIONS
4.65 V typ HC_SEL = L and 0000 ≤OV[3:0] ≤0100
6.0 V typ HC_SEL = H or 0101 ≤OV[3:0] ≤1111
Refer to the section “LED High-Current Regulators, Unused inputs” for additional information.
Figure 67. Over-Voltage Protection Operation (4.65V typ)
HARDWARE VOLTAGE MODE SELECTION
The TPS6130x device integrates a logic input (ENVM) and/or a software control bit (ENVM bit) that can be used
to force the converter to run in voltage mode regulation. Pulling the ENVM pin high forces the device into voltage
regulation mode (VOUT is preset to a fixed value, 4.95V). This additional operating mode can be useful to supply
other high power consuming devices in the system (e.g., hands-free audio power amplifier…) or any other
component requiring a regulated supply voltage higher or lower than the battery voltage.
Table 3 gives an overview of the different mode of operation.
40 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
Table 3. Operating Mode Description
INTERNAL REGISTER
SETTINGS ENVM BIT OPERATING MODES
MODE_CTRL[1:0]
00 0 The converter is in shutdown mode and the load is disconnected from the battery.
01 0 LEDs are turned-on for DC light operation (i.e. movie-light). The converter is operating in
the current regulation mode (CM). The output voltage is controlled by the forward voltage
characteristic of the LED. The energy is being directly transferred from the battery to the output.
The integrated current control loop automatically selects the minimum boosting ratio to maintain
regulation based on the LED forward voltage and current requirements. When running in linear
mode (VF(LED) < VIN), the dc/dc power stage featuring valley-current limit is not active permitting
relatively large currents to circulate from the input to the output of the device.
10 0 The converter is operating in the current regulation mode (CM). The output voltage is controlled
by the forward voltage characteristic of the LED. LEDs are ready for flashlight operation and
DC light operation is supported directly from the battery.
The integrated current control loop automatically selects the minimum boosting ratio to maintain
regulation based on the LED forward voltage and current requirements. When running in linear
mode (VF(LED) < VIN), the dc/dc power stage featuring valley-current limit is not active permitting
relatively large currents to circulate from the input to the output of the device.
In high-current mode (HC_SEL = H), the energy is supplied by the output reservoir
capacitor and the inductive power stage is turned-off for the flash strobe period of time.
11 0 LEDs are turned-off and the converter is operating in the voltage regulation mode (VM). The
output voltage is set via the register OV[3:0].
00 1 LEDs are turned-off and the converter is operating in the voltage regulation mode (VM). The
output voltage is set via the register OV[3:0].
01 1 The converter is operating in the voltage regulation mode (VM) and it’s output voltage is
set via the register OV[3:0]. The LEDs are turned-on for DC light operation and the
energy is being directly transferred from the battery to the output. The LED currents are
regulated by the means of the low-side current sinks.
10 1 The converter is operating in the voltage regulation mode (VM) and it’s output voltage is set via
the register OV[3:0]. The LED currents are regulated by the means of the low-side current
sinks. The LEDs are ready for flashlight operation.
In direct drive mode (HC_SEL = L), the energy is being directly transferred from the battery to
the output.
In high-current mode (HC_SEL = H), the energy is largely supplied by the output
reservoir capacitor. The inductive power stage is turned-on to support DC light
operation and to contribute the flash strobe itself.
11 1 LEDs are turned-off and the converter is operating in the voltage regulation mode (VM). The
output voltage is set via the register OV[3:0].
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 41
Product Folder Link(s): TPS61300 TPS61301 TPS61305
0
50
100
150
200
250
300
350
400
0 0.6 1.2 1.8 2.4 3 3.6 4.2
DifferentialInput-OutputVoltage-V
V =3.6V,T =25°C
IN A
V =3.6V,T =85°C
IN A
V =3.6V,T =-40°C
IN A
TPS61305
HC_SEL =1
DCPre-ChargeCurrent-mA
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
START-UP SEQUENCE
To avoid high inrush current during start-up, special care is taken to control the inrush current. When the device
enables, the internal startup cycle starts with the first step, the pre-charge phase.
During pre-charge, the rectifying switch is turned on until the output capacitor is either charged to a value close
to the input voltage or ca. 3.3V, whichever occurs first. The rectifying switch is current limited during that phase.
The current limit increases with decreasing input to output voltage difference. This circuit also limits the output
current under short-circuit conditions at the output. Figure 68 shows the typical pre-charge current vs. input
minus the output voltage for a specific input voltage.
Figure 68. Typical DC Pre-charge and Short-Circuit Current
In direct drive mode (HC_SEL = L, TPS6130x), after having pre-charged the output capacitor, the device starts-
up switching and increases its current limit in three steps of typically 250mA, 500mA and full current limit (ILIM
setting). The current limit transitions from the first to the second step occurs after a milli-second operation. Full
current limit operation is set once the output voltage has reached its regulation limits. In this mode, the active
balancing circuit is disabled.
In high-current mode (HC_SEL = H), the pre-charge voltage of the storage capacitor is depending on the input
voltage and operating mode (i.e., voltage regulation vs. current regulation mode). In case the device is set for
exclusive current regulation operation (i.e., MODE_CTRL[1:0] = 01 or 10 and ENVM = 0), the output capacitor
pre-charge voltage will be close to the input voltage. Under all other operating conditions, the pre-charge voltage
will either be close to the input voltage or to approximately 3.3V, whichever is lower.
After having pre-charged the storage capacitor, the device starts-up switching. During down-mode operation, the
inductor valley current is actively limited either to 250mA or 500mA (refer to ILIM setting). As the device enters
boost mode operation, the current limit transitions to its full capability (refer to ILIM setting and Tx-MASK input
logic state). As a consequence, the output voltage ramps-up linearly and the start-up time needed to reach the
programmed output voltage (refer to OV[3:0] bits) will mainly depend on the super-capacitor value and load
current. In this mode, the active balancing circuit is enabled.
42 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
VoltageModeRequest
OutputVoltage, VOUT
Nom. Voltage
Start-upphase
PowerGoodBit, (PG)
PowerGoodOutput,
GPIO/PG Hi-Z Hi-Z
1.025 VOUT (NOM )
0.985 VOUT (NOM )
VOUT (NOM )
OutputVoltage
DownRegulation
OutputVoltage
UpRegulation
ForcedPWMmodeoperation
ForcedPWMmodeoperation
(PG) Bit
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
POWER GOOD (FLASH READY)
The TPS6130x integrates a power good circuitry that is activated when the device is operating in voltage
regulation mode (MODE_CTRL[1:0] = 11 or ENVM = 1). In shutdown mode (MODE_CTRL[1:0] = 00, ENDCL = 0
and ENVM = 0), the GPIO/PG pin state is defined as following:
GPIOTYPE GPIO/PG SHUTDOWN STATE
0 Reset/pulled to ground
1 Open-drain
Depending on the GPIO/PG output stage type selection (i.e., push-pull or open-drain), the polarity of the power-
good output signal (PG) can be inverted or not. The power-good software bit and hardware signal polarity is
defined as following:
GPIOTYPE PG BIT GPIO/PG OUTPUT PORT COMMENTS
0 0
0: push-pull output Output is active high signal polarity
1 1
0 Open-drain
1: open-drain output Output is active low signal polarity
1 Low
The power good signal is valid when the output voltage is within –1.5% and +2.5% of its nominal value.
Conversely, it is asserted low when the voltage mode operation gets suspended (MODE_CTRL[1:0] ≠11 and
ENVM = 0).
Figure 69. Power Good Operation (DIR = 1, GPIOTYPE = 1)
The TPS6130x device uses a control architecture that allows to “recycle” excessive energy that might be stored
in the output capacitor. By reversing the operation of the boost power stage, the converter is capable of
transferring energy from its output back into the input source. In this case, the power good signal is de-asserted
whilst the output voltage is decreasing towards its target value (i.e., the closest fit voltage the converter can
support, refer to the section “Down-Mode in Voltage Regulation Mode” for additional information).
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 43
Product Folder Link(s): TPS61300 TPS61301 TPS61305
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
LED TEMPERATURE MONITORING (TPS61305, TPS61306)
The TPS61305 and TPS61306 devices monitor the LED temperature by measuring the voltage between the TS
and AGND pins. An internal current source provides the bias (c.a. 24 μA) for a negative-temperature coefficient
resistor (NTC), and the TS pin voltage is compared to internal thresholds (1.05V and 0.345V) to protect the LEDs
against overheating.
The temperature monitoring related blocks are always active in DC light or flashlight modes. In voltage mode
operation (MODE_CTRL[1:0] = 11), the device only activates the TS input when the ENTS bit is set to high. In
shutdown mode, the LED temperature supervision is disabled and the quiescent current of the device is
dramatically reduced.
The LEDWARN and LEDHOT bits reflect the LED temperature. The LEDWARN bit is set when the voltage seen
at the TS pin is lower than 1.05V. This threshold corresponds to an LED warning temperature value, the device
operation is still permitted.
While regulating LED current (i.e.. DC light or flashlight modes), the LEDHOT bit is latched when the voltage
seen at the TS pin is lower than 0.345V. This threshold corresponds to an excessive LED temperature value, the
device operation is immediately suspended (MODE_CTRL[1:0] bits are reset and HOTDIE[1:0] bits are set).
HOT DIE DETECTOR
The hot die detector monitors the junction temperature but does not shutdown the device. It provides an early
warning to the camera engine to avoid excessive power dissipation thus preventing from thermal shutdown
during the next high-power flash strobe.
The hot die detector (HOTDIE[1:0] bits) reflects the instantaneous junction temperature and is always enabled
excepted when the device is in shutdown mode (MODE_CTRL[1:0] = 00, ENVM = 0 and ENDCL = 0).
NRESET INPUT: HARDWARE ENABLE / DISABLE
Some devices out of the TPS6130x family feature a hardware reset pin (NRESET). This reset pin allows the
device to be disabled by an external controller without requiring an I2C write command. Under normal operation,
the NRESET pin should be held high to prevent an unwanted reset. When the NRESET is driven low, the I2C
control interface and all internal control registers are reset to the default states and the part enters shutdown
mode.
ENDCL INPUT: DC LIGHT HARDWARE CONTROL
Some devices out of the TPS6130x family feature a dedicated DC light control input (ENDCL). This logic input
can be used to turn-on the LEDs for DC light operation. This hardware control pin can be useful to control the
torch light functionality from a separate engine (e.g., base-band). In this mode of operation, the DC light safety
timer is not activated.
The ENDCL input is only active when the device is programmed into shutdown (MODE_CTRL[1:0] = 00) or into
voltage regulation mode (MODE_CTRL[1:0] = 11 or ENVM = 1) and the indicator control is turned-off (INDC[3:0]
= 0000). LED1-3 inputs are controlled according to ENLED[3:1] bit settings.
44 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
FLASH
DCLIGHT
LEDCurrent
FLASH_SYNC
Tx- MASK
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
FLASHLIGHT BLANKING (Tx-MASK)
In direct drive mode (HC_SEL = 0), the Tx-MASK input signal can be used to disable the flashlight operation,
e.g., during a RF PA transmission pulse. This blanking function turns the LED from flashlight to DC light thereby
reducing almost instantaneously the peak current loading from the battery. The Tx-MASK function has no
influence on the safety timer duration.
Figure 70. Synchronized Flashlight With Blanking Periods
In high-current mode (HC_SEL = 1), the Tx-MASK input pin is also used to dynamically adjusts the device’s
current limit setting (i.e. controls the maximum current drawn from the input source). Refer to the section “Current
Limit Operation” for additional information.
UNDERVOLTAGE LOCKOUT
The under-voltage lockout circuit prevents the device from mis-operation at low input voltages. It prevents the
converter from turning on the switch–MOSFET, or rectifier–MOSFET for battery voltages below 2.3V. The I2C
compatible interface is fully functional down to 2.1V input voltage.
SHUTDOWN
MODE_CTRL[1:0] bits low force the device into shutdown. The shutdown state can only be entered when the
voltage regulation and DC light modes are both turned-off (ENVM = 0 and ENDCL = 0).
In direct drive mode (HC_SEL = L), the regulator stops switching, the high-side PMOS disconnects the load from
the input and the LEDx pins are high impedance thus eliminating any DC conduction path. The TPS6130x device
actively discharges the output capacitor when it turns off.
The integrated discharge resistor has a typical resistance of 2kΩequally split-off between VOUT to BAL and BAL
to GND outputs. The required time to discharge the output capacitor at VOUT depends on load current and the
effective output capacitance. The active balancing circuit is disabled and the device consumes only a shutdown
current of 1μA (typ).
In high-current mode (HC_SEL = H), the device maintains its output biased at the input voltage level. In this
mode, the synchronous rectifier is current limited (i.e. pre-charge current) allowing external load (e.g. audio
amplifier) to be powered with a restricted supply. The active balancing circuit is enabled and the device
consumes only a standby current of 5μA (typ).
THERMAL SHUTDOWN
As soon as the junction temperature, TJ, exceeds 160°C typical, the device goes into thermal shutdown. In this
mode, the power stage and the low-side current regulators are turned-off, the HOTDIE[1:0] bits are set and can
only be reset by a readout.
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 45
Product Folder Link(s): TPS61300 TPS61301 TPS61305
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
In the voltage mode operation (MODE_CTRL[1:0] = 11 or ENVM = 1), the device continues its operation when
the junction temperature falls below 140°C typ. again. In the current regulation mode (i.e., DC light or flashlight
modes) the device operation is suspended.
STORAGE CAPACITOR ACTIVE CELL BALANCING
A fully charged super-capacitor will typically have leakage current of under 1μA. The TPS6130x device integrates
an active balancing feature to cut the total leakage current from the super-capacitor and balance circuit to less
than 1.7μA typ.
The device integrates a window comparator monitoring the tap point of the multi-cell super-capacitor. The
balancing output (BAL) is substantially half the actual output voltage (VOUT). If the internal leakage current in one
of the capacitors is larger than that in the other, then the voltage at their junction will tend to change in such a
way that the voltage on the capacitor with the larger (or largest) leakage current will reduce.
When this happens, a current will begin to flow from the BAL output in such a direction as to reduce the amount
by which the voltage changes. The current that will flow after a long period of steady-state conditions will be
approximately equal to the difference between the leakage currents of the pair of capacitors which is being
balanced by the circuit. The output resistance of the balancing circuit (c.a. 250Ω) determines how quickly an
imbalance will be corrected.
46 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
VBAT
P
P
L
PP
VOUT
D1
D2
Backgate
Control
LED2
INDLED
AVIN
INDC[3:0]
High-SideLEDCurrentRegulator
SW
AVIN
P
ON/OFF
LED1
P
ON/OFF
LED3
P
Hi-Z
Hi-Z
SHUTDOWN ACTIF
INDC[3:2]= 01 && INDC[1:0] 00
VOUT < TBDV
CO
CIN
CIN
VBAT
CO
P
P
L
PP
VOUT
D1 D2
Backgate
Control
LED2
INDLED
AVIN
INDC[3:0]
High-SideLEDCurrentRegulator
SW
AVIN
P
ON/OFF
LED1
P
ON/OFF
LED3
P
SHUTDOWN ACTIF
INDC [3:2]= 01 && INDC[1:0] 00
Hi-Z
Hi-Z
VOUT < TBDV
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
RED LIGHT PRIVACY INDICATOR
The TPS6130x device provides a high-side linear constant current source to drive low VF LEDs. The LED current
is directly regulated off the battery and can be controlled via the INDC[3:0] bits. Operation is understood best by
referring to the Figure 71 and Figure 72.
Figure 71. RED Light Indicator, Configuration 1
Figure 72. RED Light Indicator, Configuration 2
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 47
Product Folder Link(s): TPS61300 TPS61301 TPS61305
PWMDimmingSteps
0.8%,1.6%,2.3%,3.1%,3.9%,4.7%,6.3%,8.6%
IDCLIGHT
0
ILED (DC ) = I DCLIGHT xPWMDimmingStep
t 1
TPWM
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
The device can provide a path to allow for reverse biasing of white LEDs (refer to Figure 72). To do so, the
output of the converter (VOUT) is pulled to ground thus allowing a reverse current to flow. This mode of
operation is only possible when the converter’s power stage is in shutdown (MODE_CTRL[1:0] = 00, ENVM = 0,
ENDCL = 0 and HC_SEL = 0).
WHITE LED PRIVACY INDICATOR
The TPS6130x device features white LED drive capability at very low light intensity. To generate a reduced LED
average current, the device employs a 122Hz fixed frequency PWM modulation scheme. Operation is understood
best by referring to the timer block diagram.
The DC light current is modulated with a duty cycle defined by the INDC[3:0] bits. The low light dimming mode
can only be activated in the software controlled DC light only mode (MODE_CTRL[1:0] = 01, ENVM = X, ENDCL
= 0) and applies to the LEDs selected via ENLED[3:1] bits. In this mode, the DC light safety timeout feature is
disabled.
Figure 73. PWM Dimming Principle
STORAGE CAPACITOR, PRE-CHARGE VOLTAGE CALIBRATION
High-power LEDs tend to exhibit a wide forward voltage distribution. The TPS6130x device integrates a self-
calibration procedure that can be used to determine the optimum super-capacitor pre-charge voltage based on
the actual worst case LED forward voltage and ESR of the storage capacitor. This calibration procedure is meant
to start-off at a min. output voltage and can be initiated by setting the SELFCAL bit (preferably with
MODE_CTRL[1:0] = 00, ENVM = 0, ENDCL = 0).
The calibration procedure monitors the sense voltage across the low-side current regulators (according to
ENLED[3:1] bits setting) and registers the worst case LED (i.e. the LED featuring the largest forward voltage).
The TPS6130x device automatically sweeps through its output voltage range and performs a short duration flash
strobe for each step (refer to FC13[1:0] and FC2[2:0] bits settings).
In direct drive mode (HC_SEL = L), the energy is being directly transferred from the battery to the LEDs. In high-
current mode (HC_SEL = H), the energy is supplied exclusively by the output reservoir capacitor and the
inductive power stage is turned-off for the flash strobe period of time.
The sequence is stopped as soon as the device detects that each of the low-side current regulators have enough
headroom voltage (i.e. 400mV typ.). The device returns the according output voltage in the register OV[3:0] and
sets the SELFCAL bit. This bit is only being reset at the (re-)start of a calibration cycle. In other words, when
SELFCAL is asserted the output voltage register (OV[3:0]) returns the result of the last calibration sequence.
48 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
OutputVoltage, VOUT
PowerGood, PG
VBAT
LEDFlashCurrent, IFLASH
OV[3:0] 0000 0001 0010 0011 0100 0101
~200 ms
FeedbackSenseComparatorOutput
VLED > 400 mV
Self-Calibration,
SELFCAL bit (write)
Self-Calibration,
SELFCAL bit (read)
ESRxILED ~200 ms
FeedbackSense
ComparatorInformation
X
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
Figure 74. LED Forward Voltage Self-Calibration Principle
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 49
Product Folder Link(s): TPS61300 TPS61301 TPS61305
OutputVoltage, VOUT
PowerGood, PG
LEDFlashCurrent, IFLASH
FeedbackSenseComparatorOutput
(VLED > 400 mV)
LEDHDRbit
ESRxILED
CriticalHeadroomVoltage
FLASH_SYNC
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
STORAGE CAPACITOR, ADAPTIVE PRE-CHARGE VOLTAGE
In high-power LED camera flash applications, the storage capacitor is supposed to be charged to an optimum
voltage level in order to:
• Maintain sufficient headroom voltage across the LED current regulators for the entire strobe time.
• Minimize the power dissipation in the device.
High-power LEDs tend to exhibit large dynamic forward voltage variation relating to own self-heating effects. In
addition, the energy storage capacitor (i.e., Electrochemical Double-Layer Capacitor or Super-Capacitor) also
shows a relatively large effective capacitance and ESR spread. The main factors contributing to these variations
are:
• Flash strobe duration
• Temperature
• Ageing effects
In practice, it normally becomes very challenging to compensate for all these variations and a worst-case design
would presumably be too pessimistic. As a consequence, designers would have to give-up on the benefits
coming along with the “Storage Capacitor, Pre-Charge Voltage Calibration” approach.
The TPS6130x device offers the possibility of controlling the storage capacitor pre-charge voltage in a closed-
loop manner. The principle is to dynamically adjust the initial pre-voltage to the minimum value, as required for
the particular components characteristic and operating conditions.
The reference criteria used to evaluate proper operation is the headroom voltage across the LED current
regulators. In case of a critical headroom voltage (VLED1-3) at the end of a flash strobe (i.e., n cycle), the pre-
charge voltage should be increased prior to the next capture sequence (i.e., n+1 cycle).
Figure 75. Storage Capacitor, Simple Adaptive Pre-Charge Voltage
50 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
Dataline
stable;
datavalid
DATA
CLK
Change
ofdata
allowed
START Condition
DATA
CLK
STOP Condition
S P
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
SERIAL INTERFACE DESCRIPTION
I2C™ is a 2-wire serial interface developed by Philips Semiconductor, now NXP Semiconductors (see I2C-Bus
Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-
up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices
connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or
a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device
addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A
slave device receives and/or transmits data on the bus under control of the master device.
The TPS6130x device works as a slave and supports the following data transfer modes, as defined in the I2C-
Bus Specification: standard mode (100 kbps) and fast mode (400 kbps), and high-speed mode (3.4 Mbps). The
interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values
depending on the instantaneous application requirements. Register contents remain intact as long as supply
voltage remains above 2.1V.
The data transfer protocol for standard and fast modes is exactly the same, therefore they are referred to as F/S-
mode in this document. The protocol for high-speed mode is different from F/S-mode, and it is referred to as HS-
mode. The TPS6130x device supports 7-bit addressing; 10-bit addressing and general call address are not
supported. The device 7bit address is defined as ‘011 0011’.
F/S-MODE PROTOCOL
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 76. All I2C-compatible devices should
recognize a start condition.
Figure 76. START and STOP Conditions
The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see Figure 77). All devices recognize
the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see Figure 78) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a
slave has been established.
Figure 77. Bit Transfer on the Serial Interface
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary.
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 51
Product Folder Link(s): TPS61300 TPS61301 TPS61305
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to
high while the SCL line is high (see Figure 76). This releases the bus and stops the communication link with the
addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop
condition, all devices know that the bus is released, and they wait for a start condition followed by a matching
address.
Attempting to read data from register addresses not listed in this section will result in 00h being read out.
Figure 78. Acknowledge on the I2C Bus
Figure 79. Bus Protocol
HS-MODE PROTOCOL
The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX.
This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS
master code, but all devices must recognize it and switch their internal setting to support 3.4 Mbps operation.
The master then generates a repeated start condition (a repeated start condition has the same timing as the start
condition). After this repeated start condition, the protocol is the same as F/S-mode, except that transmission
speeds up to 3.4 Mbps are allowed. A stop condition ends the HS-mode and switches all the internal settings of
the slave devices to support the F/S-mode. Instead of using a stop condition, repeated start conditions should be
used to secure the bus in HS-mode.
Attempting to read data from register addresses not listed in this section will result in 00h being read out.
52 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
Slave Address R/W A Register Address A P
Sr
171 1 1 1
8
Data
8
A/A
1
S HS-MasterCode A
1 1
8
F/SMode HSMode F/SMode
Data Transferred
(nxBytes + Acknowledge) HSModeContinues
Slave AddressSr
FromMasterto TPS6130x
From TPS6130xtoMaster
A = Acknowledge
A = Acknowledge
S = START condition
Sr = REPEATEDSTART condition
P = STOP condition
Slave Address R/W A Register Address A Data A P
S
171 1 1 1 1
88
“0” Write
Sr
1
Slave Address R/W
71
“1” Read
A
1
FromMasterto TPS6130x
From TPS6130xtoMaster
A = Acknowledge
S = START condition
Sr = REPEATEDSTART condition
P = STOP condition
Slave Address R/W A Register Address A Data A PS
171 1 1 1 1
8 8
“0” Write
FromMasterto TPS6130x
From TPS6130xtoMaster
A = Acknowledge
S = START condition
Sr = REPEATEDSTART condition
P = STOP condition
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
TPS6130x I2C UPDATE SEQUENCE
The TPS6130x requires a start condition, a valid I2C address, a register address byte, and a data byte for a
single update. After the receipt of each byte, TPS6130x device acknowledges by pulling the SDA line low during
the high period of a single clock pulse. A valid I2C address selects the TPS6130x. TPS6130x performs an update
on the falling edge of the acknowledge signal that follows the LSB byte.
Figure 80. : “Write” Data Transfer Format in F/S-Mode
Figure 81. “Read” Data Transfer Format in F/S-Mode
Figure 82. Data Transfer Format in H/S-Mode
SLAVE ADDRESS BYTE
MSB LSB
X X X X X X A1 A0
The slave address byte is the first byte received following the START condition from the master device.
REGISTER ADDRESS BYTE
MSB LSB
0 0 0 0 00 D2 D1 D0
Following the successful acknowledgement of the slave address, the bus master will send a byte to the
TPS6130x, which will contain the address of the register to be accessed.
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 53
Product Folder Link(s): TPS61300 TPS61301 TPS61305
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
REGISTER1 DESCRIPTION (TPS61300, TPS61301)
Memory location: 0x01
Description ENVM MODE_CTRL[1:0] DCLC13[1:0] DCLC2[1:0]
Bits D7 D6 D5 D4 D3 D2 D1 D0
Memory type R/W R/W R/W R/W R/W R/W R/W R/W
Default value 00001001
Bit Description
ENVM Enable Voltage Mode bit.
0: Normal operation.
1: Forces the device into a constant voltage source.
In read mode, the ENVM bit is automatically updated to reflect the logic state of the ENVM input pin.
MODE_CTRL[1:0] Mode Control bits.
00: Device in shutdown mode.
01: Device operates in DC light mode.
10: Device operates in DC light and flash mode.
11: Device operates as constant voltage source.
To avoid device shutdown by DC light safety timeout, MODE_CTRL[1:0] bits need to be refreshed within less than
11.2s.
Writing to REGISTER1[6:5] automatically updates REGISTER2[6:5].
DCLC13[1:0] DC Light Current Control bits (LED1/3).
00: 0mA. LEDs are off, VOUT set according to OV[3:0].(1) (2)
01: 50mA
10: 75mA
11: 100mA
DCLC2[2:0] DC Light Current Control bits (LED2).
000: 0mA. LEDs are off, VOUT set according to OV[3:0]. (1) (2)
001: 50mA
010: 75mA
011: 100mA
100: 125mA
101: 150mA
110: 200mA, 350mA current level can be activated simultaneously with Tx-MASK = 1.
111: 250mA, 500mA current level can be activated simultaneously with Tx-MASK = 1.
(1) When DCLC2[2:0] and DCLC13[1:0] are both reset, the device operates in voltage regulation mode. The output voltage is set according
to OV[3:0].
(2) To ensure a proper transition into voltage mode operation, it is recommended to disable the LEDs (i.e. ENLED[2:0] bits are reset) prior
to clearing DCLC2[2:0] and DCLC13[1:0] bits.
54 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
REGISTER1 DESCRIPTION (TPS61305, TPS61306)
Memory location: 0x01
Description ENVM MODE_CTRL[1:0] DCLC13[1:0] DCLC2[1:0]
Bits D7 D6 D5 D4 D3 D2 D1 D0
Memory type R/W R/W R/W R/W R/W R/W R/W R/W
Default value 00001001
Bit Description
ENVM Enable Voltage Mode bit.
0: Normal operation.
1: Forces the device into a constant voltage source.
In read mode, the ENVM bit is automatically updated to reflect the logic state of the ENVM input pin.
MODE_CTRL[1:0] Mode Control bits.
00: Device in shutdown mode.
01: Device operates in DC light mode.
10: Device operates in DC light and flash mode.
11: Device operates as constant voltage source.
To avoid device shutdown by DC light safety timeout, MODE_CTRL[1:0] bits need to be refreshed within less than
11.2s.
Writing to REGISTER1[6:5] automatically updates REGISTER2[6:5].
DCLC13[1:0] DC Light Current Control bits (LED1/3).
00: 0mA. LEDs are off, VOUT set according to OV[3:0]. (1) (2)
01: 55mA
10: 85mA
11: 110mA
DCLC2[2:0] DC Light Current Control bits (LED2).
000: 0mA. LEDs are off, VOUT set according to OV[3:0].(1) (2)
001: 55mA
010: 85mA
011: 110mA
100: 140mA
101: 165mA
110: 220mA, 350mA current level can be activated simultaneously with Tx-MASK = 1.
111: 275mA, 500mA current level can be activated simultaneously with Tx-MASK = 1.
(1) When DCLC2[2:0] and DCLC13[1:0] are both reset, the device operates in voltage regulation mode. The output voltage is set according
to OV[3:0].
(2) To ensure a proper transition into voltage mode operation, it is recommended to disable the LEDs (i.e. ENLED[2:0] bits are reset) prior
to clearing DCLC2[2:0] and DCLC13[1:0] bits.
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 55
Product Folder Link(s): TPS61300 TPS61301 TPS61305
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
REGISTER2 DESCRIPTION (TPS61300, TPS61301)
Memory location: 0x02
Description ENVM MODE_CTRL[1:0] FC13[1:0] FC2[1:0]
Bits D7 D6 D5 D4 D3 D2 D1 D0
Memory type R/W R/W R/W R/W R/W R/W R/W R/W
Default value 00000011
Bit Description
ENVM Enable Voltage Mode bit.
0: Normal operation.
1: Forces the device into a constant voltage source.
In read mode, the ENVM bit is automatically updated to reflect the logic state of the ENVM input pin.
MODE_CTRL[1:0] Mode Control bits.
00: Device in shutdown mode.
01: Device operates in DC light mode.
10: Device operates in DC light and flash mode.
11: Device operates as constant voltage source.
To avoid device shutdown by DC light safety timeout, MODE_CTRL[1:0] bits need to be refreshed within less than
11.2s.
Writing to REGISTER2[6:5] automatically updates REGISTER1[6:5].
FC13[1:0] Flash Current Control bits (LED1/3).
HC_SEL = 0 HC_SEL = 1
00: 250mA 00: 600mA
01: 300mA 01: 700mA
10: 350mA 10: 800mA
11: 400mA 11: 925mA
FC2[2:0] Flash Current Control bits (LED2).
HC_SEL = 0 HC_SEL = 1
000: 275mA 000: 650mA
001: 300mA 001: 700mA
010: 350mA 010: 825mA
011: 450mA 011: 1050mA
100: 550mA 100: 1300mA
101: 600mA 101: 1400mA
110: 700mA 110: 1600mA
111: 800mA 111: 1850mA
56 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
REGISTER2 DESCRIPTION (TPS61305, TPS61306)
Memory location: 0x02
Description ENVM MODE_CTRL[1:0] FC13[1:0] F2[1:0]
Bits D7 D6 D5 D4 D3 D2 D1 D0
Memory type R/W R/W R/W R/W R/W R/W R/W R/W
Default value 00000011
Bit Description
ENVM Enable Voltage Mode bit.
0: Normal operation.
1: Forces the device into a constant voltage source.
In read mode, the ENVM bit is automatically updated to reflect the logic state of the ENVM input pin.
MODE_CTRL[1:0] Mode Control bits.
00: Device in shutdown mode.
01: Device operates in DC light mode.
10: Device operates in DC light and flash mode.
11: Device operates as constant voltage source.
To avoid device shutdown by DC light safety timeout, MODE_CTRL[1:0] bits need to be refreshed within less than
11.2s.
Writing to REGISTER2[6:5] automatically updates REGISTER1[6:5].
FC13[1:0] Flash Current Control bits (LED1/3).
HC_SEL = 0 HC_SEL = 1
00: 275mA 00: 665mA
01: 335mA 01: 775mA
10: 385mA 10: 890mA
11: 445mA 11: 1025mA
FC2[2:0] Flash Current Control bits (LED2).
HC_SEL = 0 HC_SEL = 1
000: 305mA 000: 720mA
001: 335mA 001: 775mA
010: 385mA 010: 915mA
011: 500mA 011: 1165mA
100: 610mA 100: 1450mA
101: 665mA 101: 1550mA
110: 775mA 110: 1775mA
111: 885mA 111: 2050mA
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 57
Product Folder Link(s): TPS61300 TPS61301 TPS61305
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
REGISTER3 DESCRIPTION
Memory location: 0x03
Description STIM[2:0] HPLF SELSTIM (W) STT SFT Tx-MASK
TO (R)
Bits D7 D6 D5 D4 D3 D2 D1 D0
Memory type R/W R/W R/W R R R/W R/W R/W
Default value 1100 0 001
Bit Description
STIM[2:0] Safety Timer bits.
STIM[2:0] RANGE 0 RANGE 1 STIM[2:0] RANGE 0 RANGE 1
000 68.2ms 5.3ms 100 204.5ms 26.6ms
001 102.2ms 10.7ms 101 340.8ms 32.0ms
010 136.3ms 16.0ms 110 579.3ms 37.3ms
011 170.4ms 21.3ms 111 852ms 207.7ms
HPFL High-Power LED Failure flag.
0: Proper LED operation.
1: LED failed (open or shorted).
High-power LED failure flag is reset after readout
SELSTIM Safety Timer Selection Range (Write Only).
0: Safety timer range 0.
1: Safety timer range 1.
TO Time-Out Flag (Read Only).
0: No time-out event occurred.
1: Time-out event occurred. Time-out flag is reset at re-start of the safety timer.
STT Safety Timer Trigger bit.
0: LED safety timer is level sensitive.
1: LED safety timer is rising edge sensitive.
This bit is only valid for MODE_CTRL[1:0] = 10.
SFT Start/Flash Timer bit.
In write mode, this bit initiates a flash strobe sequence.
0: No change in the high-power LED current.
1: High-power LED current ramps to the flash current level.
In read mode, this bit indicates the high-power LED status.
0: High-power LEDs are idle.
1: Ongoing high-power LED flash strobe.
Tx-MASK Flash Blanking Control bit.
In write mode, this bit enables/disables the flash blanking/LED current reduction function.
0: Flash blanking disabled.
1: LED current is reduced to DC light level when Tx-MASK input is high.
In read mode, this flag indicates whether or not the flashlight masking input has been activated. Tx-MASK flag is reset
after readout of the flag.
0: No flash blanking event occurred.
1: Tx-MASK input triggered.
58 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
REGISTER4 DESCRIPTION
Memory location: 0x04
Description PG HOTDIE[1:0] ILIM INC[3:0]
Bits D7 D6 D5 D4 D3 D2 D1 D0
Memory type R/W R R R/W R/W R/W R/W R/W
Default value 00000000
Bit Description
PG Power Good bit.
In write mode, this bit selects the functionality of the GPIO/PG output.
0: PG signal is routed to the GPIO port.
1: GPIO PORT VALUE bit is routed to the GPIO port.
In read mode, this bit indicates the output voltage conditions.
0: The converter is not operating within the voltage regulation limits.
1: The output voltage is within its nominal value.
HOTDIE[1:0] Instantaneous Die Temperature bits.
00: TJ< +55°C
01: +55°C < TJ< +70°C
10: TJ> +70°C
11: Thermal shutdown tripped. Indicator flag is reset after readout.
ILIM Inductor Valley Current Limit bit.
The ILIM bit can only be set before the device enters operation (i.e. initial shutdown state).
CURRENT LIMIT ILIM BIT HC_SEL Tx-MASK
SETTING SETTING INPUT LEVEL INPUT LEVEL
1250mA Low Low Low
1750mA High Low Low
1250mA Low High Low
1750mA High High Low
1250mA Low Low High
1750mA High Low High
250mA Low High High
500mA High High High
INDC[3:0] Indicator Light Control bits.
PRIVACY INDICATOR PRIVACY INDICATOR
INDC[3:0] INDC[3:0]
INDLED CHANNEL LED1-3 CHANNELS (1)
0000 Privacy indicator turned-off 1000 0.8% PWM dimming ratio
0001 INDLED current = 2.6mA 1001 1.6% PWM dimming ratio
0010 INDLED current = 5.2mA 1010 2.3% PWM dimming ratio
0011 INDLED current = 7.9mA 1011 3.1% PWM dimming ratio
0100 Privacy indicator turned-off 1100 3.9% PWM dimming ratio
0101 INDLED current = 2.6mA(2) 1101 4.7% PWM dimming ratio
0110 INDLED current = 5.2mA(2) 1110 6.3% PWM dimming ratio
0111 INDLED current = 7.9mA (2) 1111 8.6% PWM dimming ratio
(1) This mode of operation can only be activated for MODE_CTRL[1:0] = 01 & ENDCL = 0.
(2) The output node is internally pulled to ground. This mode is only possible for HC_SEL = L.
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 59
Product Folder Link(s): TPS61300 TPS61301 TPS61305
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
REGISTER5 DESCRIPTION
Memory location: 0x05
Description DIR (W)
SELFCAL ENPSM STENDCL GPIO GPIOTYPE ENLED3 ENLED2 ENLED1
(R)
Bits D7 D6 D5 D4 D3 D2 D1 D0
Memory type R/W R/W R/W R/W R/W R/W R/W R/W
Default value 01101010
Bit Description
SELFCAL High-Current LED Forward Voltage Self-Calibration Start bit.
In write mode, this bit enables/disables the output voltage vs. LED forward voltage/current self-calibration procedure.
0: Self-calibration disabled.
1: Self-calibration enabled.
In read mode, this bit returns the status of the self-calibration procedure.
0: Self-calibration ongoing
1: Self-calibration done Notice that this bit is only being reset at the (re-)start of a calibration cycle.
ENPSM Enable / Disable Power-Save Mode bit.
0: Power-save mode disabled.
1: Power-save mode enabled.
STENDCL ENDCL Input Status bit (Read Only).
This bit indicates the logic state on the ENDCL state. This bit is only active in TPS61300.
DIR GPIO Direction bit.
0: GPIO configured as input.
1: GPIO configured as output.
GPIO GPIO Port Value.
This bit contains the GPIO port value.
GPIOTYPE GPIO Port Type.
0: GPIO is configured as push-pull output.
1: GPIO is configured as open-drain output.
ENLED3 Enable / Disable High-Current LED3 bit.
0: LED3 input is disabled.
1: LED3 input is enabled.
ENLED2 Enable / Disable High-Current LED2 bit.
0: LED2 input is disabled.
1: LED2 input is enabled.
ENLED1 Enable / Disable High-Current LED1 bit.
0: LED1 input is disabled.
1: LED1 input is enabled.
60 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
REGISTER6 DESCRIPTION (TPS61300, TPS61301)
Memory location: 0x06
Description NOT USED LEDHDR OV[3:0]
Bits D7 D6 D5 D4 D3 D2 D1 D0
Memory type R/W R/W R/W R R/W R/W R/W R/W
Default value 00001001
Bit Description
LEDHDR LED High-Current Regulator Headroom Voltage Monitoring bit.
This bit returns the headroom voltage status of the LED high-current regulators. This value is being updated at the end of a
flash strobe, prior to the LED current ramp-down phase.
0: Low headroom voltage.
1: Sufficient headroom voltage.
OV[3:0] Output Voltage Selection bits. In read mode, these bits return the result of the high-current LED forward voltage self-
calibration procedure.
In write mode, these bits are used to set the target output voltage (refer to voltage regulation mode). In applications
requiring dynamic voltage control, care should be take to set the new target code after voltage mode operation has been
enabled (MODE_CTRL[1:0] = 11 and/or ENVM bit = 1).
OV[3:0] Target Output Voltage
0000 3.825V
0001 3.950V
0010 4.075V
0011 4.200V
0100 4.325V
0101 4.450V
0110 4.575V
0111 4.700V
1000 4.825V
1001 4.950V
1010 5.075V
1011 5.200V
1100 5.325V
1101 5.450V
1110 5.575V
1111 5.700V
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 61
Product Folder Link(s): TPS61300 TPS61301 TPS61305
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
REGISTER6 DESCRIPTION (TPS61305)
Memory location: 0x06
Description ENTS LEDHOT LEDWARN LEDHDR OV[3:0]
Bits D7 D6 D5 D4 D3 D2 D1 D0
Memory type R/W R/W R R R/W R/W R/W R/W
Default value 00001001
Bit Description
ENTS Enable / Disable LED Temperature Monitoring.
0: LED temperature monitoring disabled.
1: LED temperature monitoring enabled
LEDHOT LED Excessive Temperature Flag.
This bit can be reset by writing a logic level zero.
0: TS input voltage > 0.345V.
1: TS input voltage < 0.345V.
LEDWARN LED Temperature Warning Flag (Read Only).
This flag is reset after readout.
0: TS input voltage > 1.05V.
1: TS input voltage < 1.05V.
LEDHDR LED High-Current Regulator Headroom Voltage Monitoring bit.
This bit returns the headroom voltage status of the LED high-current regulators. This value is being updated at the end of a
flash strobe, prior to the LED current ramp-down phase.
0: Low headroom voltage.
1: Sufficient headroom voltage.
0V[3:0] Output Voltage Selection bits.
In read mode, these bits return the result of the high-current LED forward voltage self-calibration procedure.
In write mode, these bits are used to set the target output voltage (refer to voltage regulation mode). In applications
requiring dynamic voltage control, care should be take to set the new target code after voltage mode operation has been
enabled (MODE_CTRL[1:0] = 11 and/or ENVM bit = 1).
OV[3:0] Target Output Voltage
0000 3.825V
0001 3.950V
0010 4.075V
0011 4.200V
0100 4.325V
0101 4.450V
0110 4.575V
0111 4.700V
1000 4.825V
1001 4.950V
1010 5.075V
1011 5.200V
1100 5.325V
1101 5.450V
1110 5.575V
1111 5.700V
62 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
REGISTER7 DESCRIPTION
Memory location: 0x07
Description NOT USED REVID[2:0]
Bits D7 D6 D5 D4 D3 D2 D1 D0
Memory type R/W R/W R/W R/W R/W R R R
Default value 00000100
Bit Description
REVID[2:0] Silicon Revision ID.
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 63
Product Folder Link(s): TPS61300 TPS61301 TPS61305
OUT OUT ININ
L(PEAK)
OUT
I V VV D
I = + with D =
2 f L (1 D) V
-´
´ ´ - ´ h
OUT
L OUT
IN
V
I I η V
» ´
´
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
APPLICATION INFORMATION
INDUCTOR SELECTION
A boost converter requires two main passive components for storing energy during the conversion. A boost
inductor and a storage capacitor at the output are required. The TPS6130x device integrates a current limit
protection circuitry. The valley current of the PMOS rectifier is sensed to limit the maximum current flowing
through the synchronous rectifier and the inductor. The valley peak current limit
(250mA/500mA/1250mA/1750mA) is user selectable via the I2C interface.
In order to optimize solution size the TPS6130x device has been designed to operate with inductance values
between a minimum of 1.3 μH and maximum of 2.9 μH. In typical high current white LED applications a 2.2μH
inductance is recommended.
The highest peak current through the inductor and the power switch depends on the output load, the input and
output voltages. Estimation of the maximum average inductor current and the maximum inductor peak current
can be done using Equation 2 and Equation 3:
(2)
(3)
Withf = switching frequency (2MHz)
L = inductance value (2.2μH)
η= estimated efficiency (85%)
The losses in the inductor caused by magnetic hysteresis losses and copper losses are a major parameter for
total circuit efficiency.
Table 4. List of Inductors
MANUFACTURER SERIES DIMENSIONS ILIM SETTINGS
MIPST2520 2.5mm x 2.0mm x 0.8mm max. height
FDK MIP2520 2.5mm x 2.0mm x 1.0mm max. height 250mA (typ.)
MIPSA2520 2.5mm x 2.0mm x 1.2mm max. height 500mA (typ.)
LQM2HP-G0 2.5mm x 2.0mm x 1.0mm max. height
MURATA LQM2HP-GC 2.5mm x 2.0mm x 1.0mm max. height
TDK VLF3014AT 2.6mm x 2.8mm x 1.4mm max. height
COILCRAFT LPS3015 3.0mm x 3.0mm x 1.5mm max. height 1250mA (typ.)
MURATA LQH2HPN 2.5mm x 2.0mm x 1.2mm max. height
TOKO FDSE0312 3.0mm x 3.0mm x 1.2mm max. height 1750mA (typ.)
MURATA LQM32PN 3.2mm x 2.5mm x 1.2mm max. height
INPUT CAPACITOR
For good input voltage filtering low ESR ceramic capacitors are recommended. A 10-μF input capacitor is
recommended to improve transient behavior of the regulator and EMI behavior of the total power supply circuit.
The input capacitor should be placed as close as possible to the input pin of the converter.
64 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
OUT OUT IN
min
OUT
I × (V V )
Cf V V
-
»
´ D ´
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
OUTPUT CAPACITOR
The major parameter necessary to define the output capacitor is the maximum allowed output voltage ripple of
the converter. This ripple is determined by two parameters of the capacitor, the capacitance and the ESR. It is
possible to calculate the minimum capacitance needed for the defined ripple, supposing that the ESR is zero, by
using Equation 4:
(4)
Parameter f is the switching frequency and ΔV is the maximum allowed ripple.
With a chosen ripple voltage of 10mV, a minimum capacitance of 10μF is needed. The total ripple is larger due
to the ESR of the output capacitor. This additional component of the ripple can be calculated using Equation 5:
ΔVESR = IOUT × RESR (5) (5)
The total ripple is the sum of the ripple caused by the capacitance and the ripple caused by the ESR of the
capacitor. Additional ripple is caused by load transients. This means that the output capacitor has to completely
supply the load during the charging phase of the inductor. A reasonable value of the output capacitance depends
on the speed of the load transients and the load current during the load change.
For the standard current white LED application (HC_SEL = 0, TPS6130x), a minimum of 3μF effective output
capacitance is usually required when operating with 2.2μH (typ) inductors. For solution size reasons, this is
usually one or more X5R/X7R ceramic capacitors.
Depending on the material, size and therefore margin to the rated voltage of the used output capacitor,
degradation on the effective capacitance can be observed. This loss of capacitance is related to the DC bias
voltage applied. It is therefore always recommended to check that the selected capacitors are showing enough
effective capacitance under real operating conditions.
To support high-current camera flash application (HC_SEL = 1), the converter is designed to work with a low
voltage super-capacitor on the output to take advantage of the benefits they offer. A low-voltage super-capacitor
in the 0.1F to 1.5F range, and with ESR larger than 40mΩ, is suitable in the TPS6130x application circuit. For
this device the output capacitor should be connected between the VOUT pin and a good ground connection.
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 65
Product Folder Link(s): TPS61300 TPS61301 TPS61305
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
NTC SELECTION (TPS61305, TPS61306)
The TPS61305/306 requires a negative thermistor (NTC) for sensing the LED temperature. Once the
temperature monitoring feature is activated, a regulated bias current (c.a. 24μA) will be driven out of the TS port
and produce a voltage across the thermistor.
If the temperature of the NTC-thermistor rises due to the heat dissipated by the LED, the voltage on the TS input
pin decreases. When this voltage goes below the “warning threshold”, the LEDWARN bit in REGISTER6 is set.
This flag is cleared by reading the register.
If the voltage on the TS input decreases further and falls below “hot threshold”, the LEDHOT bit in REGISTER6
is set and the device goes automatically in shutdown mode to avoid damaging the LED. This status is latched
until the LEDHOT flag gets cleared by software.
The selection of the NTC-thermistor value strongly depends on the power dissipated by the LED and all
components surrounding the temperature sensor and on the cooling capabilities of each specific application. With
a 220kΩ(at 25°C) thermistor, the valid temperature window is set between 60°C to 90°C. The temperature
window can be enlarged by adding external resistors to the TS pin application circuit. In order to ensure proper
triggering of the LEDWARN and LEDHOT flags in noisy environments, the TS signal may require additional
filtering capacitance.
Figure 83. Temperature Monitoring Characteristic
Table 5. List of Negative Thermistor (NTC)
MANUFACTURER PART NUMBER VALUE
MURATA NCP18WM224J03RB 220kΩ
66 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
GND
LED1
LED2 LED3
VIN
GND
L1
COUT
CIN
1
INDLED
SDA
FLASH_SYNC
ENVM(TPS61300/1)
TS(TPS61305)
B2:SCL
B3:HC_SEL
C3: Tx_MASK
D3:ENDCL (TPS61300)
D4:GPIO/PG
nRESET (TPS61301/5)
BAL
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
CHECKING LOOP STABILITY
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:
• Switching node, SW
• Inductor current, IL
• Output ripple voltage, VOUT(AC)
These are the basic signals that need to be measured when evaluating a switching converter. When the
switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations the
regulation loop may be unstable. This is often a result of improper board layout and/or L-C combination.
As a next step in the evaluation of the regulation loop the load transient response needs to be tested. VOUT can
be monitored for settling time, overshoot or ringing that helps judge the converter's stability. Without any ringing,
the loop has usually more than 45° of phase margin.
Because the damping factor of the circuitry is directly related to several resistive parameters (e.g., MOSFET
rDS(on)) that are temperature dependant, the loop stability analysis has to be done over the input voltage range,
output current range, and temperature range.
LAYOUT CONSIDERATIONS
As for all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground
tracks.
The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC. Use a
common ground node for power ground and a different one for control ground to minimize the effects of ground
noise. Connect these ground nodes at any place close to one of the ground pins of the IC.
To lay out the control ground, it is recommended to use short traces as well, separated from the power ground
traces. This avoids ground shift problems, which can occur due to superimposition of power ground current and
control ground current.
Figure 84. Suggested Layout (Top)
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 67
Product Folder Link(s): TPS61300 TPS61301 TPS61305
0
1
2
3
4
5
6
7
8
9
10
0 20 40 60 80 100 120 140 160 180 200
PulseWidth-ms
P -SinglePulseConstantPowerDissipation-W
DIS
T =65°Crise
J
T =40°Crise
J
No Airflow
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
THERMAL INFORMATION
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependant issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-
dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below:
• Improving the power dissipation capability of the PCB design
• Improving the thermal coupling of the component to the PCB
• Introducing airflow in the system
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where
high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design.
The maximum junction temperature (TJ) of the TPS6130x is 150°C.
The maximum power dissipation is especially critical when the device operates in the linear down mode at high
LED current. For single pulse power thermal analysis (e.g., flashlight strobe), the allowable power dissipation for
the device is given by Figure 85. These values are derived using the reference design.
Figure 85. Single Pulse Power Capability
68 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
VOUT
AVIN
SW
CI
SW
LED1
CO
10 mF
PGND
PGND
AGND
L
2.2 mH
SDA
SCL
TPS61300
LED2
LED3
D1 D2
2.5 V..5.5 V
ENDCL
FLASH_SYNC
Tx-MASK
GPIO/PGENVM
INDLED
Privacy
Indicator
CAMERA ENGINE
RFPA TX ACTIVE
I2CI/F
HC_SEL BAL
VOUT
AVIN
SW
CI
SW
LED 1
CO
10 mF
PGND
PGND
AGND
L
2.2 mH
SDA
SCL
TPS61305
LED 2
LED 3
D1 D2
2.5 V..5.5 V
NRESET
FLASH_SYNC
TS GPIO/PG
INDLED
Privacy
Indicator
CAMERA ENGINE
I2CI/F
HC_ SEL BAL
FLASHREADY
PHONEPOWERON
1.8V
220k
NTC
Tx-MASK
SUPER-CAP
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
TYPICAL APPLICATIONS
Figure 86. 4100mA Two White High-Power LED Flashlight Featuring Storage Capacitor
Figure 87. 2x 600mA High Power White LED Solution Featuring Privacy Indicator
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 69
Product Folder Link(s): TPS61300 TPS61301 TPS61305
VOUT
AVIN
SW
CI
SW
LED1
CO
10mF
PGND
PGND
AGND
L
2.2 mH
SDA
SCL
High -SpeedI2CI/F
TPS61300
LED2
LED3
D1 D 2
2.5 V..5.5 V
ENDCL
FLASH_SYNC
Tx-MASK
GPIO/PGENVM
INDLED
Privacy
Indicator
CAMERA ENGINE
RFPA TX ACTIVE
ENABLE TORCH(BB)
+4.2 V
AudioInput
AudioInput
CLASS-D APA
FEATURINGI2CCONTROL I/F
Note:
Reduceaudiogaintoallowsimultaneous
operationtogetherthisthecameraengine.
HC_SEL BAL
VOUT
AVIN
SW
CI
SW
LED 1
CO
10mF
PGND
PGND
AGND
L
2.2 mH
SDA
SCL
I2CI/F
TPS61300
LED 2
LED 3
D1 D 2
2.5V..5.5V
ENDCL
FLASH_SYNC
Tx-MASK
GPIO/PGENVM
INDLED
Privacy
Indicator
CAMERA ENGINE
RFPA TX ACTIVE
ENABLE APA (BB)
ENABLE TORCH(BB)
AudioInput
AudioInput
+5.0 V
CLASS-D APA
EN
HC_SEL BAL
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
Figure 88. White LED Flashlight Driver and Audio Amplifier Power Supply Operating Simultaneously
Figure 89. White LED Flashlight Driver and Audio Amplifier Power Supply Operating Simultaneously
70 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
VOLTAGEMODEENABLE
BASE-BANDENGINE
Dx Dy Dz
P0
P1
P2
SDA
SCL
EN
TCA6507
GND
VCC
+1.8V
BASE-BANDENGINE
I2CI/F
VOUT
AVIN
SW
CI
SW
LED1
CO
10 mF
PGND
PGND
AGND
L
2.2mH
SDA
SCL
CAMERA ENGINE
I2CI/F
TPS 61300
LED2
LED3
D1 D2
2.5 V..5.5 V
ENDCL
FLASH_SYNC
Tx-MASK
GPIO/PGENVM
INDLED
Privacy
Indicator
CAMERA ENGINE
RFPA TX ACTIVE
ENABLE TORCH (BB)
HC_SEL BAL
VOUT
AVIN
SW
CI
SW
LED1
CO
10mF
PGND
PGND
AGND
L
2.2mH
SDA
SCL
I2CI/F
TPS61300
LED2
LED3
D1 D2
2.5 V..5.5 V
ENDCL
FLASH_SYNC
Tx-MASK
GPIO/PGENVM
INDLED
Privacy
Indicator
CAMERA ENGINE
RFPA TX ACTIVE
ENABLE TORCH(BB)
+5.0V
AudioInput
AudioInput
EN_APA GAIN _SEL
0:NominalGain
1:-6 dBGain
ENABLE APA (BB)
HC_SEL BAL
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
Figure 90. White LED Flashlight Driver and Audio Amplifier Power Supply Exclusive Operation
Figure 91. White LED Flashlight Driver and Auxiliary Lighting Zone Power Supply
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 71
Product Folder Link(s): TPS61300 TPS61301 TPS61305
A1
B1
D
E
A2
B2
A3
B3
A4
B4
C2 C1
C3
C4
E2 E1
E3
E4
D2 D1
D3
D4
TIYMLLLLS
TPS613__
A1
TPS61300, TPS61301, TPS61305
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
www.ti.com
PACKAGE SUMMARY
CHIP SCALE PACKAGE CHIP SCALE PACKAGE
(BOTTOM VIEW) (TOP VIEW)
Code:
• YM — Year Month date code
• LLLL — Lot trace code
• S — Assembly site code
CHIP SCALE PACKAGE DIMENSIONS
The TPS6130x device is available in a 20-bump chip scale package (YFF, NanoFree™). The package
dimensions are given as:
• D = 2170 ±30 μm
• E = 1928 ±30 μm
72 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61300 TPS61301 TPS61305
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957 C –JUNE 2009–REVISED AUGUST 2012
REVISION HISTORY
NOTE: Page numbers of current version may differ from previous versions.
Changes from Original (June 2009) to Revision A Page
• Deleted product preview device number TPS61306 from data sheet header. ..................................................................... 1
• Deleted "Product Preview" cross reference from TPS61301 device in Available Options table. ......................................... 2
• Added "TI" to package marking illustration example .......................................................................................................... 72
Changes from Revision A (September 2010) to Revision B Page
• Changed ISTBY MAX current from 5 µA to 12 µA .................................................................................................................. 3
Changes from Revision B (September 2011) to Revision C Page
• Changed active cell balancing circuitry maximum quiescent current into VOUT from 3.0 to 6.0µA .................................... 5
• Added additional information related to the dc/dc input current limiting scheme. .............................................................. 41
• Added additional information related to the dc/dc input current limiting scheme. .............................................................. 41
• Added note 2 to REGISTER1 DESCRIPTION (TPS61300, TPS61301) table ................................................................... 54
• Added note 2 to REGISTER1 DESCRIPTION (TPS61305, TPS61306) table ................................................................... 55
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 73
Product Folder Link(s): TPS61300 TPS61301 TPS61305
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS61300YFFR DSBGA YFF 20 3000 180.0 8.4 2.2 2.35 0.8 4.0 8.0 Q1
TPS61300YFFT DSBGA YFF 20 250 180.0 8.4 2.2 2.35 0.8 4.0 8.0 Q1
TPS61301YFFR DSBGA YFF 20 3000 180.0 8.4 2.18 2.18 0.81 4.0 8.0 Q1
TPS61301YFFT DSBGA YFF 20 250 180.0 8.4 2.18 2.18 0.81 4.0 8.0 Q1
TPS61305YFFR DSBGA YFF 20 3000 180.0 8.4 2.18 2.18 0.81 4.0 8.0 Q1
TPS61305YFFT DSBGA YFF 20 250 180.0 8.4 2.18 2.18 0.81 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 12-Jun-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS61300YFFR DSBGA YFF 20 3000 210.0 185.0 35.0
TPS61300YFFT DSBGA YFF 20 250 210.0 185.0 35.0
TPS61301YFFR DSBGA YFF 20 3000 210.0 185.0 35.0
TPS61301YFFT DSBGA YFF 20 250 210.0 185.0 35.0
TPS61305YFFR DSBGA YFF 20 3000 210.0 185.0 35.0
TPS61305YFFT DSBGA YFF 20 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 12-Jun-2012
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated