FEATURES FUNCTIONAL BLOCK DIAGRAM GND 1 12 GND RF1 2 11 RF2 NIC 3 10 NIC 9 RFC 7 GND 8 GND 5 GND 4 GND 16424-001 14 VCTL 13 GND 16 VDD 15 GND ADRF5132 Reflective, 50 design Low insertion loss: 0.6 dB typical at 2.7 GHz High power handling at TCASE = 105C Long-term (>10 years operation) Peak power: 43 dBm CW power: 38 dBm LTE power average (8 dB PAR): 35 dBm Single event (<10 sec operation) LTE power average (8 dB PAR): 41 dBm High linearity P0.1dB: 42.5 dBm typical IP3: 65 dBm typical at 2.0 GHz to 4.0 GHz ESD ratings HBM: 2 kV, Class 2 CDM: 1.25 kV Single positive supply: 5 V Positive control, CMOS/TTL compatible 16-lead, 3 mm x 3 mm LFCSP package GND 6 Data Sheet High Power, 20 W Peak, Silicon SPDT, Reflective Switch, 0.7 GHz to 5.0 GHz ADRF5132 Figure 1. APPLICATIONS Cellular/4G infrastructure Wireless infrastructure Military and high reliability applications Test equipment Pin diode replacement GENERAL DESCRIPTION The ADRF5132 is a high power, reflective, 0.7 GHz to 5.0 GHz, silicon, single-pole, double-throw (SPDT) reflective switch in a leadless, surface-mount package. The switch is ideal for high power and cellular infrastructure applications, like long-term evolution (LTE) base stations. The ADRF5132 has high power handling of 35 dBm LTE (average typical at 105C), a low insertion loss of 0.6 dB at 2.7 GHz, input third-order intercept of 65 dBm (typical), and 0.1 dB compression (P0.1dB) of 42.5 dBm. Rev. B The on-chip circuitry operates at a single, positive supply voltage of 5 V and a typical supply current of 1.1 mA typical, making the ADRF5132 an ideal alternative to pin diode-based switches. The device is in a RoHS compliant, compact, 16-lead, 3 mm x 3 mm LFCSP package. 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Technical Support www.analog.com ADRF5132 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Interface Schematics .....................................................................5 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................6 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Insertion Loss, Isolation, Return Loss, Third-Order Intercept, and Power Compression...............................................................6 Revision History ............................................................................... 2 Theory of Operation .........................................................................8 Specifications..................................................................................... 3 Applications Information .................................................................9 Absolute Maximum Ratings............................................................ 4 Evaluation Board ...........................................................................9 Thermal Resistance ...................................................................... 4 Application Circuit..................................................................... 10 ESD Caution .................................................................................. 4 Outline Dimensions ....................................................................... 12 Pin Configuration and Function Descriptions ............................. 5 Ordering Guide .......................................................................... 12 REVISION HISTORY 8/2019--Rev. A to Rev. B Changes to Figure 11 and Figure 12 ............................................... 7 Updated Outline Dimensions ....................................................... 12 4/2018--Rev. 0 to Rev. A Changes to Figure 1 .......................................................................... 1 Changes to Figure 2 and Table 2 ..................................................... 5 Changes to Figure 17 ...................................................................... 11 12/2017--Revision 0: Initial Version Rev. B | Page 2 of 12 Data Sheet ADRF5132 SPECIFICATIONS VDD = 5 V, VCTL = 0 V or VDD, TA = 25C, and 50 system, unless otherwise noted. Table 1. Parameter FREQUENCY RANGE INSERTION LOSS ISOLATION RFC to RF1/RF2 (Worst Case) RF1 to RF2 (Worst Case) RETURN LOSS RFC RFC to RF1/RF2 SWITCHING SPEED Rise and Fall Time (tRISE, tFALL) On and Off Time (tON, tOFF) INPUT POWER 0.1 dB Compression (P0.1dB) INPUT THIRD-ORDER INTERCEPT (IP3) RECOMMENDED OPERATING CONDITIONS Bias Voltage Range (VDD) Control Voltage Range (VCTL) Maximum RF Input Power TCASE = 105C 1 TCASE = 85C TCASE = 25C Case Temperature Range (TCASE) DIGITAL INPUT CONTROL VOLTAGE Low (VIL) High (VIH) SUPPLY CURRENT (IDD) 1 Test Conditions/Comments Min 0.7 0.9 GHz 2.7 GHz 3.8 GHz 5.0 GHz 0.5 0.6 0.65 0.9 Unit GHz dB dB dB dB 0.7 GHz to 2.0 GHz 2.0 GHz to 5.0 GHz 0.7 GHz to 2.0 GHz 2.0 GHz to 5.0 GHz 50 45 50 35 dB dB dB dB 0.7 GHz to 4.0 GHz 4.0 GHz to 5.0 GHz 0.7 GHz to 4.0 GHz 4.0 GHz to 5.0 GHz 25 15 25 15 dB dB dB dB 90% to 10% of radio frequency (RF) output 50% VCTL to 10% to 90% of RF output 140 550 ns ns 42.5 dB 68 65 62 dBm dBm dBm Two-tone input power = 30 dBm per tone at 10 MHz tone spacing 0.7 GHz to 2.0 GHz 2.0 GHz to 4.0 GHz 4.0 GHz to 5.0 GHz 0.7 GHz to 4.0 GHz Typ 4.5 0 Max 5.0 5.4 VDD V V 38 35 dBm dBm -40 41 40 35 41 43 35 41 +105 dBm dBm dBm dBm dBm dBm dBm C 0 1.3 0.8 5.0 V V mA Continuous wave (CW) 8 dB peak average ratio (PAR), long-term (>10 years operation), average 8 dB PAR LTE, single event (<10 sec), average CW 8 dB PAR LTE, long-term (>10 years operation), average 8 dB PAR LTE, single event (<10 sec), average CW 8 dB PAR LTE, long-term (>10 years operation), average 8 dB PAR LTE, single event (<10 sec), average VDD = 4.5 V to 5.4 V, TCASE = -40C to +105C, at <1 A typical VDD = 5 V 1.1 Peak power is 43 dBm, corresponding to PAR of 8 dB at LTE long-term. Rev. B | Page 3 of 12 ADRF5132 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter Bias Voltage Range (VDD) Control Voltage Range (VCTL) RF Input Power1 Channel Temperature Storage Temperature Range Operating Temperature Range Peak Reflow Temperature (MSL3) ESD Sensitivity Human Body Model (HBM) Charged Device Model (CDM) 1 Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Rating -0.3 V to +5.5 V -0.3 V to VDD 43 dBm 135C -65C to +150C -40C to +105C 260C JC is the junction to case bottom (channel to package bottom) thermal resistance. Table 3. Thermal Resistance Package Type CP-16-35 2 kV (Class 2) 1.25 kV ESD CAUTION For recommended operating conditions, see Table 1. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 4 of 12 JC 17 Unit C/W Data Sheet ADRF5132 13 GND 14 VCTL 16 VDD 15 GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GND 1 12 GND RF1 2 ADRF5132 11 RF2 NIC 3 TOP VIEW (Not to Scale) 10 NIC 9 NOTES 1. NIC = NOT INTERNALLY CONNECTED. THESE PINS ARE NOT CONNECTED INTERNALLY; HOWEVER, ALL DATA SHOWN HEREIN WAS MEASURED WITH THESE PINS CONNECTED TO RF/DC GROUND EXTERNALLY. 2. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO RF/DC GROUND. 16424-002 RFC 7 GND GND 8 GND 6 GND 5 GND 4 Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1, 4, 5, 6, 8, 9, 12, 13, 15 2 3, 10 Mnemonic GND RF1 NIC 7 RFC 11 14 RF2 VCTL 16 VDD EPAD Description Ground. See Figure 3 for the GND interface schematic. RF Port 1. This pin is dc-coupled and matched to 50 . A dc blocking capacitor is required on this pin. Not Internally Connected. These pins are not connected internally; however, all data shown herein was measured with these pins connected to RF/dc ground externally. RF Common Port. This pin is dc-coupled and matched to 50 . A dc blocking capacitor is required on this pin. RF Port 2. This pin is dc-coupled and matched to 50 . A dc blocking capacitor is required on this pin. Control Input. See Figure 4 for the VCTL interface schematic. Refer to Table 5 and the recommended digital input control voltage range in Table 1. Supply Voltage. Exposed Pad. The exposed pad must be connected to RF/dc ground. Table 5. Truth Table Control Input, VCTL State High Low RFC to RF1 Off On Signal Path State RFC to RF2 On Off INTERFACE SCHEMATICS VCTL Figure 3. Ground Interface 16424-004 GND 16424-003 VDD Figure 4. Control Interface Rev. B | Page 5 of 12 ADRF5132 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS INSERTION LOSS, ISOLATION, RETURN LOSS, THIRD-ORDER INTERCEPT, AND POWER COMPRESSION VDD = 5 V, VCTL = 0 V or VDD, TA = 25C, and 50 system, unless otherwise noted. 0 0 RF1 RF2 +105C +85C +25C -40C -0.2 -0.2 INSERTION LOSS (dB) -0.6 -0.8 -1.0 -0.8 -1.0 -1.2 -1.2 1 2 3 4 6 5 FREQUENCY (GHz) -1.6 16424-005 0 0 2 3 4 5 6 FREQUENCY (GHz) Figure 5. Insertion Loss of RF1 and RF2 vs. Frequency at VDD = 5 V -20 1 16424-008 -1.4 -1.4 Figure 8. Insertion Loss vs. Frequency over Temperature, VDD = 5 V -20 RF1 RF2 -30 -30 -40 -40 ISOLATION (dB) ISOLATION (dB) -0.6 -50 -60 -70 RF1 ON RF2 ON -50 -60 -70 0 1 2 3 4 5 6 FREQUENCY (GHz) -80 16424-006 -80 0 1 2 3 4 5 6 FREQUENCY (GHz) Figure 6. Isolation Between RFC and RF1/RF2 vs. Frequency at VDD = 5 V 16424-009 INSERTION LOSS (dB) -0.4 -0.4 Figure 9. Isolation Between RF1 and RF2 vs. Frequency at VDD = 5 V, Switch Mode On 0 80 RFC RF1 RF2 -5 +105C +85C +25C -40C 75 INPUT IP3 (dBm) -15 -20 -25 70 65 60 -30 -40 0 1 2 3 4 5 FREQUENCY (GHz) 6 Figure 7. Return Loss vs. Frequency at VDD = 5 V 50 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 FREQUENCY (GHz) Figure 10. Input IP3 vs. Frequency over Temperature, VDD = 5 V Rev. B | Page 6 of 12 16424-010 55 -35 16424-007 RETURN LOSS (dB) -10 Data Sheet ADRF5132 55 55 +105C +85C +25C -40C 50 INPUT P0.1dB (dBm) 45 40 35 40 35 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FREQUENCY (GHz) 4.5 5.0 5.5 6.0 30 0.5 16424-011 30 0.5 45 Figure 11. Input 0.1 dB Power Compression (P0.1dB) vs. Frequency over Temperature, VDD = 5 V 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FREQUENCY (GHz) 4.5 5.0 5.5 6.0 16424-012 INPUT P0.1dB (dBm) 50 RF1 RF2 Figure 12. Input 0.1 dB Power Compression (P0.1dB) vs. Frequency, VDD = 5 V Rev. B | Page 7 of 12 ADRF5132 Data Sheet THEORY OF OPERATION The ADRF5132 requires a single-supply voltage applied to the VDD pin. Bypass capacitors are recommended on the supply line to minimize RF coupling. The ADRF5132 is controlled via a digital control voltage applied to the VCTL pin. A small bypassing capacitor is recommended on the VCTL signal line to improve the RF signal isolation. The ideal power-up sequence is as follows: 1. 2. 3. 4. The ADRF5132 is internally matched to 50 at the RF input port (RFC) and the RF output ports (RF1 and RF2); therefore, no external matching components are required. The RFx (RFC, RF1, and RF2) pins are dc-coupled, and dc blocking capacitors are required on the RFx lines. The design is bidirectional; the input and outputs are interchangeable. Connect the device to ground. Power up VDD. Power up the digital control input. Powering the digital control input before the VDD supply can inadvertently forward bias and damage ESD protection structures. Power up the RF input. Depending on the logic level applied to the VCTL pin, one RF output port (for example, RF1) is set to on mode, by which an insertion loss path is provided from RFC to the output, while the other RF output port (for example, RF2) is set to off mode, by which the output is isolated from RFC. Table 6. Switch Operation Mode Digital Control Input, VCTL 1 0 Switch Mode RFC to RF1 RFC to RF2 Off mode: the RF1 port is isolated from RFC and is On mode: a low insertion loss path from RFC to the RF2 reflective. port. On mode: a low insertion loss path from RFC to the RF1 Off mode: the RF2 port is isolated from RFC and is port. reflective. Rev. B | Page 8 of 12 Data Sheet ADRF5132 APPLICATIONS INFORMATION EVALUATION BOARD The ADRF5132-EVALZ can handle high power levels and temperatures at which the device operates. The ADRF5132-EVALZ evaluation board is constructed with eight metal layers and dielectrics between each layer as shown in Figure 13. Each metal layer has 1 oz (1.3 mil) copper thickness, whereas the external layers are 1.5 oz copper. The top dielectric material is 10 mil Rogers RO4350, which exhibits a very low thermal coefficient, offering control over the thermal rise of the board. The dielectrics between the other metal layers are FR4. The total board thickness achieved is 60 mil. To ensure maximum heat dissipation and reduce thermal rise on the evaluation board, some application considerations are essential. Attach the ADRF5132-EVALZ to a copper support plate at the bottom of the evaluation board. The ADRF5132EVALZ comes with this support plate attachment. Attach the ADRF5132-EVALZ with its support plate to a big heat sink using thermal grease during all high power operations. Figure 14 shows the evaluation board temperature vs. RF power input tested with the preceding conditions and precautions (evaluation board and support plate attached to a big heat sink). The temperature rise is less than 5C up to 43 dBm RF power input, which provides the required thermal dissipation when operated at high power levels. 81 G = 13mil W = 18mil 1.5oz Cu (2.1mil) RO4350 = 10mil 1.5oz Cu (2.1mil) T = 2.1 mil H = 10mil 1oz Cu (1.3mil) FR4 80 BOARD TEMPERATURE (C) 1.5oz Cu (2.1mil) 79 78 77 76 75 38.0 FR4 38.5 39.0 39.5 40.0 40.5 41.0 41.5 42.0 42.5 43.0 RF POWER INPUT (dBm) 16424-014 TOTAL THICKNESS = 60mil 1oz Cu (1.3mil) Figure 14. ADRF5132-EVALZ Evaluation Board Temperature Rise (Oven Temperature Set to 75C) 1oz Cu (1.3mil) FR4 1oz Cu (1.3mil) FR4 1oz Cu (1.3mil) FR4 1oz Cu (1.3mil) 1.5oz Cu (2.1mil) 16424-013 FR4 The top copper layer has all RF and dc traces, whereas the other seven layers provide sufficient ground and help to handle the thermal rise on the ADRF5132-EVALZ. In addition, via holes are provided around transmission lines and under the exposed pad of package, as shown in Figure 15, for proper thermal grounding. RF transmission lines on the evaluation board are coplanar wave guide design with a width of 18 mil and ground spacing of 13 mil. Rev. B | Page 9 of 12 16424-015 Figure 13. ADRF5132-EVALZ Evaluation Board Cross Sectional View Figure 15. ADRF5132-EVALZ Evaluation Board Layout ADRF5132 Data Sheet impedance, and the package ground leads and backside ground slug must connect directly to the ground plane. The evaluation board shown in Figure 16 is available from Analog Devices, Inc., upon request. APPLICATION CIRCUIT 16424-017 Generate the evaluation printed circuit board (PCB) used in the application circuit shown in Figure 17 with proper RF circuit design techniques. Signal lines at the RF port must have a 50 Figure 16. ADRF5132-EVALZ Evaluation Board Component Placement Table 7. Bill of Materials for ADRF5132-EVALZ Evaluation Board Reference Designator J1 to J3 C1 to C5 C6 C7 C8, C9, C12 R1 U1 PCB1 1 2 Description PCB mount SMA connector 100 pF, 250 V capacitor, 0402 package 1000 pF capacitor, 0402 package 1 F capacitor, 0402 package Do not insert 0 resistor, 0402 package ADRF5132 SPDT switch ADRF5132-EVALZ2 evaluation PCB Circuit board material: Roger 4350 or Arlon 25FR. Reference this evaluation board number when ordering the complete evaluation board. Rev. B | Page 10 of 12 Data Sheet ADRF5132 VDD C0402_A GND J1 C8 1pF DNI GND 100pF 2345 GND 1 12 GND RF1 2 11 RF2 NIC 3 ADRF5132 GND 4 1 RFC C3 RF2 1 J3 C12 1pF DNI GND 10 NIC 9 GND 5 GND GND GND 100pF 5432 GND GND 8 C1 TP1 1 C4 100pF 13 GND GND 14 VCTL GND 0 16 VDD C5 100pF 15 GND C6 1000pF RFC 7 1 RF1 VCTL R1 C7 1F PAD 1 GND 6 TP2 GND C2 J2 GND C9 1pF DNI GND 16424-016 100pF 2345 Figure 17. Application Circuit Rev. B | Page 11 of 12 ADRF5132 Data Sheet OUTLINE DIMENSIONS 0.32 0.25 0.20 0.50 BSC P IN 1 IN D IC ATO R AR E A OP T IO N S (SEE DETAIL A) 16 13 1 12 1.80 1.70 SQ 1.60 EXPOSED PAD 4 9 TOP VIEW 0.80 0.75 0.70 SIDE VIEW PKG-004326 SEATING PLANE 0.50 0.40 0.25 5 8 0.20 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WEED-2 08-28-2018-B PIN 1 INDICATOR AREA DETAIL A (JEDEC 95) 3.10 3.00 SQ 2.90 Figure 18. 16-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm x 3 mm Body and 0.75 mm Package Height (CP-16-35) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADRF5132BCPZN ADRF5132BCPZN-R7 ADRF5132-EVALZ 1 Temperature Range -40C to +105C -40C to +105C Package Description 16-Lead Lead Frame Chip Scale Package [LFCSP] 16-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board Z = RoHS Compliant Part. (c)2017-2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16424-0-8/19(B) Rev. B | Page 12 of 12 Package Option CP-16-35 CP-16-35