High Power, 20 W Peak, Silicon SPDT,
Reflective Switch, 0.7 GHz to 5.0 GHz
Data Sheet
ADRF5132
Rev. B Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2017–2019 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Reflective, 50 Ω design
Low insertion loss: 0.6 dB typical at 2.7 GHz
High power handling at TCASE = 105°C
Long-term (>10 years operation)
Peak power: 43 dBm
CW power: 38 dBm
LTE power average (8 dB PAR): 35 dBm
Single event (<10 sec operation)
LTE power average (8 dB PAR): 41 dBm
High linearity
P0.1dB: 42.5 dBm typical
IP3: 65 dBm typical at 2.0 GHz to 4.0 GHz
ESD ratings
HBM: 2 kV, Class 2
CDM: 1.25 kV
Single positive supply: 5 V
Positive control, CMOS/TTL compatible
16-lead, 3 mm × 3 mm LFCSP package
APPLICATIONS
Cellular/4G infrastructure
Wireless infrastructure
Military and high reliability applications
Test equipment
Pin diode replacement
FUNCTIONAL BLOCK DIAGRAM
16424-001
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
GND
RF1
NIC
GND
GND
GND
VCTL
GND
VDD
RF2
NIC
GND
GND
RFC
GND
GND
ADRF5132
Figure 1.
GENERAL DESCRIPTION
The ADRF5132 is a high power, reflective, 0.7 GHz to 5.0 GHz,
silicon, single-pole, double-throw (SPDT) reflective switch in a
leadless, surface-mount package. The switch is ideal for high
power and cellular infrastructure applications, like long-term
evolution (LTE) base stations. The ADRF5132 has high power
handling of 35 dBm LTE (average typical at 105°C), a low insertion
loss of 0.6 dB at 2.7 GHz, input third-order intercept of 65 dBm
(typical), and 0.1 dB compression (P0.1dB) of 42.5 dBm.
The on-chip circuitry operates at a single, positive supply
voltage of 5 V and a typical supply current of 1.1 mA typical,
making the ADRF5132 an ideal alternative to pin diode-based
switches.
The device is in a RoHS compliant, compact, 16-lead, 3 mm ×
3 mm LFCSP package.
ADRF5132 Data Sheet
Rev. B | Page 2 of 12
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution .................................................................................. 4
Pin Configuration and Function Descriptions ............................. 5
Interface Schematics .....................................................................5
Typical Performance Characteristics ..............................................6
Insertion Loss, Isolation, Return Loss, Third-Order Intercept,
and Power Compression ...............................................................6
Theory of Operation .........................................................................8
Applications Information .................................................................9
Evaluation Board ...........................................................................9
Application Circuit ..................................................................... 10
Outline Dimensions ....................................................................... 12
Ordering Guide .......................................................................... 12
REVISION HISTORY
8/2019—Rev. A to Rev. B
Changes to Figure 11 and Figure 12 ............................................... 7
Updated Outline Dimensions ....................................................... 12
4/2018—Rev. 0 to Rev. A
Changes to Figure 1 .......................................................................... 1
Changes to Figure 2 and Table 2 ..................................................... 5
Changes to Figure 17 ...................................................................... 11
12/2017—Revision 0: Initial Version
Data Sheet ADRF5132
Rev. B | Page 3 of 12
SPECIFICATIONS
VDD = 5 V, V CTL = 0 V or VDD, TA = 25°C, and 50 Ω system, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
FREQUENCY RANGE 0.7 5.0 GHz
INSERTION LOSS 0.9 GHz 0.5 dB
2.7 GHz 0.6 dB
3.8 GHz
dB
5.0 GHz 0.9 dB
ISOLATION
RFC to RF1/RF2 (Worst Case)
0.7 GHz to 2.0 GHz
dB
2.0 GHz to 5.0 GHz 45 dB
RF1 to RF2 (Worst Case) 0.7 GHz to 2.0 GHz 50 dB
2.0 GHz to 5.0 GHz 35 dB
RETURN LOSS
RFC 0.7 GHz to 4.0 GHz 25 dB
4.0 GHz to 5.0 GHz 15 dB
RFC to RF1/RF2 0.7 GHz to 4.0 GHz 25 dB
4.0 GHz to 5.0 GHz 15 dB
SWITCHING SPEED
Rise and Fall Time (tRISE, tFALL) 90% to 10% of radio frequency (RF) output 140 ns
On and Off Time (tON, tOFF) 50% VCTL to 10% to 90% of RF output 550 ns
INPUT POWER
0.1 dB Compression (P0.1dB) 42.5 dB
INPUT THIRD-ORDER INTERCEPT (IP3) Two-tone input power = 30 dBm per tone at 10 MHz tone spacing
0.7 GHz to 2.0 GHz 68 dBm
2.0 GHz to 4.0 GHz 65 dBm
4.0 GHz to 5.0 GHz
dBm
RECOMMENDED OPERATING CONDITIONS 0.7 GHz to 4.0 GHz
Bias Voltage Range (VDD) 4.5 5.4 V
Control Voltage Range (V
CTL
)
0
V
DD
V
Maximum RF Input Power
TCASE = 105°C1 Continuous wave (CW) 38 dBm
8 dB peak average ratio (PAR), long-term (>10 years operation),
average
35 dBm
8 dB PAR LTE, single event (<10 sec), average
41
dBm
TCASE = 85°C CW 40 dBm
8 dB PAR LTE, long-term (>10 years operation), average 35 dBm
8 dB PAR LTE, single event (<10 sec), average 41 dBm
TCASE = 25°C CW 43 dBm
8 dB PAR LTE, long-term (>10 years operation), average 35 dBm
8 dB PAR LTE, single event (<10 sec), average
41
dBm
Case Temperature Range (TCASE) −40 +105 °C
DIGITAL INPUT CONTROL VOLTAGE VDD = 4.5 V to 5.4 V, TCASE = −40°C to +105°C, at <1 µA typical
Low (V
IL
)
0
0.8
V
High (VIH) 1.3 5.0 V
SUPPLY CURRENT (IDD) VDD = 5 V 1.1 mA
1 Peak power is 43 dBm, corresponding to PAR of 8 dB at LTE long-term.
ADRF5132 Data Sheet
Rev. B | Page 4 of 12
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Bias Voltage Range (VDD) −0.3 V to +5.5 V
Control Voltage Range (VCTL) −0.3 V to VDD
RF Input Power1 43 dBm
Channel Temperature 135°C
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +105°C
Peak Reflow Temperature (MSL3)
260°C
ESD Sensitivity
Human Body Model (HBM) 2 kV (Class 2)
Charged Device Model (CDM) 1.25 kV
1 For recommended operating conditions, see Table 1.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJC is the junction to case bottom (channel to package bottom)
thermal resistance.
Table 3. Thermal Resistance
Package Type θJC Unit
CP-16-35
17
°C/W
ESD CAUTION
Data Sheet ADRF5132
Rev. B | Page 5 of 12
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
GND
RF1
NIC
GND
GND
GND
V
CTL
GND
V
DD
RF2
NIC
GND
GND
RFC
GND
GND
ADRF5132
TOP VIEW
(No t t o Scal e)
NOTES
1. NI C = NOT INT E RNALL Y CONNECTED. THE S E P INS ARE NOT
CONNECTED INT E RNALL Y ; HOW E V E R, AL L DAT A S HO WN
HEREI N WAS M E AS URE D WI TH T HE S E P INS CONNECTED
TO RF/DC G ROUND EX TERNALL Y .
2. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED
TO RF/DC G ROUND.
16424-002
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1, 4, 5, 6, 8, 9, 12, 13, 15 GND Ground. See Figure 3 for the GND interface schematic.
2 RF1 RF Port 1. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required on this pin.
3, 10 NIC Not Internally Connected. These pins are not connected internally; however, all data shown herein
was measured with these pins connected to RF/dc ground externally.
7 RFC RF Common Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required
on this pin.
11 RF2 RF Port 2. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required on this pin.
14 VCTL Control Input. See Figure 4 for the VCTL interface schematic. Refer to Table 5 and the recommended
digital input control voltage range in Table 1.
16 VDD Supply Voltage.
EPAD Exposed Pad. The exposed pad must be connected to RF/dc ground.
Table 5. Truth Table
Signal Path State
Control Input, VCTL State RFC to RF1 RFC to RF2
High Off On
Low On Off
INTERFACE SCHEMATICS
GND
16424-003
Figure 3. Ground Interface
V
DD
V
CTL
16424-004
Figure 4. Control Interface
ADRF5132 Data Sheet
Rev. B | Page 6 of 12
TYPICAL PERFORMANCE CHARACTERISTICS
INSERTION LOSS, ISOLATION, RETURN LOSS, THIRD-ORDER INTERCEPT, AND POWER COMPRESSION
VDD = 5 V, V CTL = 0 V or VDD, TA = 25°C, and 50 Ω system, unless otherwise noted.
0
–1.4 02
13 4 56
INSERTION LOSS (dB)
FRE Q UE NCY ( GHz)
–1.2
–1.0
–0.8
–0.6
–0.4
–0.2
16424-005
RF1
RF2
Figure 5. Insertion Loss of RF1 and RF2 vs. Frequency at VDD = 5 V
–20
–80
ISOLATION (dB)
–70
–60
–50
–40
–30
0 21 3 4 5 6
FREQUENCY ( GHz)
RF1
RF2
16424-006
Figure 6. Isolation Between RFC and RF1/RF2 vs. Frequency at VDD = 5 V
0
–40
–5
RET URN LOS S ( dB)
–35
–30
–25
–20
–15
–10
0 21 3 4 5 6
FREQUENCY ( GHz)
RFC
RF1
RF2
16424-007
Figure 7. Return Loss vs. Frequency at VDD = 5 V
0
–1.6
INSERTION LOSS (dB)
–1.4
–1.2
–1.0
–0.8
–0.6
–0.4
–0.2
0 21 3 4 5 6
FRE Q UE NCY ( GHz)
+105°C
+85°C
+25°C
–40°C
16424-008
Figure 8. Insertion Loss vs. Frequency over Temperature, VDD = 5 V
–20
–80
ISOLATION (dB)
–70
–60
–50
–40
–30
0 21 3 4 5 6
FRE Q UE NCY ( GHz)
RF1 ON
RF2 ON
16424-009
Figure 9. Isolation Between RF1 and RF2 vs. Frequency at VDD = 5 V,
Switch Mode On
80
500.5 6.0
INPUT I P 3 ( dBm)
FREQUENCY ( GHz)
55
60
65
70
75
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
+105°C
+85°C
+25°C
–40°C
16424-010
Figure 10. Input IP3 vs. Frequency over Temperature, VDD = 5 V
Data Sheet ADRF5132
Rev. B | Page 7 of 12
55
300.5 6.04.0 4.5 5.0 5.5
INPUT P0.1d B ( dBm)
FRE Q UE NCY ( GHz)
35
40
45
50
1.0 1.5 2.0 2.5 3.0 3.5
+105°C
+85°C
+25°C
–40°C
16424-011
Figure 11. Input 0.1 dB Power Compression (P0.1dB) vs. Frequency over
Temperature, VDD = 5 V
55
300.5 6.0
4.0 5.0 5.5
4.5
INPUT P0.1d B ( dBm)
FRE Q UE NCY ( GHz)
35
40
45
50
1.0 1.5 2.0 2.5 3.0 3.5
16424-012
RF1
RF2
Figure 12. Input 0.1 dB Power Compression (P0.1dB) vs. Frequency, VDD = 5 V
ADRF5132 Data Sheet
Rev. B | Page 8 of 12
THEORY OF OPERATION
The ADRF5132 requires a single-supply voltage applied to the
VDD pin. Bypass capacitors are recommended on the supply line
to minimize RF coupling.
The ADRF5132 is controlled via a digital control voltage
applied to the VCTL pin. A small bypassing capacitor is
recommended on the VCTL signal line to improve the RF signal
isolation.
The ADRF5132 is internally matched to 50 Ω at the RF input
port (RFC) and the RF output ports (RF1 and RF2); therefore,
no external matching components are required. The RFx (RFC,
RF1, and RF2) pins are dc-coupled, and dc blocking capacitors
are required on the RFx lines. The design is bidirectional; the
input and outputs are interchangeable.
The ideal power-up sequence is as follows:
1. Connect the device to ground.
2. Power up VDD.
3. Power up the digital control input. Powering the digital
control input before the VDD supply can inadvertently
forward bias and damage ESD protection structures.
4. Power up the RF input. Depending on the logic level
applied to the VCTL pin, one RF output port (for example,
RF1) is set to on mode, by which an insertion loss path is
provided from RFC to the output, while the other RF
output port (for example, RF2) is set to off mode, by which
the output is isolated from RFC.
Table 6. Switch Operation Mode
Digital Control Input,
VCTL
Switch Mode
RFC to RF1 RFC to RF2
1 Off mode: the RF1 port is isolated from RFC and is
reflective.
On mode: a low insertion loss path from RFC to the RF2
port.
0 On mode: a low insertion loss path from RFC to the RF1
port.
Off mode: the RF2 port is isolated from RFC and is
reflective.
Data Sheet ADRF5132
Rev. B | Page 9 of 12
APPLICATIONS INFORMATION
EVALUATION BOARD
The ADRF5132-EVALZ can handle high power levels and
temperatures at which the device operates.
The ADRF5132-EVALZ evaluation board is constructed with
eight metal layers and dielectrics between each layer as shown
in Figure 13. Each metal layer has 1 oz (1.3 mil) copper
thickness, whereas the external layers are 1.5 oz copper.
The top dielectric material is 10 mil Rogers RO4350, which
exhibits a very low thermal coefficient, offering control over the
thermal rise of the board. The dielectrics between the other
metal layers are FR4. The total board thickness achieved is
60 mil.
W = 18mil
G = 13mil
T = 2.1 mil
TOTAL THICKNESS = 60mil
H = 10mil
1.5oz Cu (2.1mil)
RO4350 = 10mil
FR4
FR4
FR4
FR4
FR4
FR4
1oz Cu (1.3mil)
1oz Cu (1.3mil)
1oz Cu (1.3mil)
1oz Cu (1.3mil)
1oz Cu (1.3mil)
1oz Cu (1.3mil)
1.5oz Cu (2.1mil)
1.5oz Cu (2.1mil) 1.5oz Cu (2.1mil)
16424-013
Figure 13. ADRF5132-EVALZ Evaluation Board Cross Sectional View
The top copper layer has all RF and dc traces, whereas the other
seven layers provide sufficient ground and help to handle the
thermal rise on the ADRF5132-EVALZ. In addition, via holes
are provided around transmission lines and under the exposed
pad of package, as shown in Figure 15, for proper thermal
grounding. RF transmission lines on the evaluation board are
coplanar wave guide design with a width of 18 mil and ground
spacing of 13 mil.
To ensure maximum heat dissipation and reduce thermal rise
on the evaluation board, some application considerations are
essential. Attach the ADRF5132-EVALZ to a copper support
plate at the bottom of the evaluation board. The ADRF5132-
EVALZ comes with this support plate attachment. Attach the
ADRF5132-EVALZ with its support plate to a big heat sink
using thermal grease during all high power operations. Figure 14
shows the evaluation board temperature vs. RF power input
tested with the preceding conditions and precautions
(evaluation board and support plate attached to a big heat sink).
The temperature rise is less than 5°C up to 43 dBm RF power
input, which provides the required thermal dissipation when
operated at high power levels.
81
80
79
78
77
76
75
38.0 38.5 39.0 39.5 40.0 40.5 41.0 41.5 42.0 42.5 43.0
BOARD TEMPERATURE (°C)
RF POWER INPUT (dBm)
16424-014
Figure 14. ADRF5132-EVALZ Evaluation Board Temperature Rise
(Oven Temperature Set to 75°C)
16424-015
Figure 15. ADRF5132-EVALZ Evaluation Board Layout
ADRF5132 Data Sheet
Rev. B | Page 10 of 12
APPLICATION CIRCUIT
Generate the evaluation printed circuit board (PCB) used in the
application circuit shown in Figure 17 with proper RF circuit
design techniques. Signal lines at the RF port must have a 50 Ω
impedance, and the package ground leads and backside ground
slug must connect directly to the ground plane. The evaluation
board shown in Figure 16 is available from Analog Devices,
Inc., upon request.
16424-017
Figure 16. ADRF5132-EVALZ Evaluation Board Component Placement
Table 7. Bill of Materials for ADRF5132-EVALZ Evaluation Board
Reference Designator Description
J1 to J3 PCB mount SMA connector
C1 to C5 100 pF, 250 V capacitor, 0402 package
C6 1000 pF capacitor, 0402 package
C7 1 μF capacitor, 0402 package
C8, C9, C12 Do not insert
R1 0 Ω resistor, 0402 package
U1 ADRF5132 SPDT switch
PCB1 ADRF5132-EVALZ2 evaluation PCB
1 Circuit board material: Roger 4350 or Arlon 25FR.
2 Reference this evaluation board number when ordering the complete evaluation board.
Data Sheet ADRF5132
Rev. B | Page 11 of 12
TP1
1
V
CTL
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
GND
TP2 1
RF1
NIC
GND
GND
GND
V
CTL
GND
V
DD
V
DD
PAD
C0402_A
RF2
NIC
GND
GND
RFC
RFC
GND
GND
ADRF5132
GND GND GND
C7
1µF C6
1000pF C5
100pF
GND
C8
1pF
DNI GND
C12
1pF
DNI
GND
C4
100pF
R1
0Ω
1RF1
J1 RF2 1J3
GND
2 3 4 5
GND
2345
C1
100pF
C3
100pF
GND
GND
C9
1pF
DNI
1
J2
GND
2 3 4 5
C2
100pF
16424-016
Figure 17. Application Circuit
ADRF5132 Data Sheet
Rev. B | Page 12 of 12
OUTLINE DIMENSIONS
3.10
3.00 SQ
2.90
0.32
0.25
0.20
1.80
1.70 SQ
1.60
1
0.50
BSC
BOTTOM VIEWTOP VIEW
16
5
8
9
12
13
4
0.50
0.40
0.25
0.05 M AX
0.02 NO M
0.20 REF
0.20 M IN
COPLANARITY
0.08
0.80
0.75
0.70
COMPLIANT
TO
JEDEC STANDARDS M O-220- WEE D- 2
08-28-2018-B
PKG-004326
SEATING
PLANE
SIDE VIEW
FOR PRO P E R CONNECTI ON O F
THE EXPOSED PAD, REFER TO
THE PIN CO NFI GURAT IO N AND
FUNCTION DES CRIPTI ONS
SECTION OF THIS DATA SHEET.
PIN 1
INDIC ATORAR EAOPTIONS
(SEEDETAIL A)
DETAIL A
(JEDEC 95)
PIN 1
INDICATOR
AREA
EXPOSED
PAD
Figure 18. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-35)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADRF5132BCPZN
−40°C to +105°C
16-Lead Lead Frame Chip Scale Package [LFCSP]
CP-16-35
ADRF5132BCPZN-R7 −40°C to +105°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-35
ADRF5132-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
©2017–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16424-0-8/19(B)