NCV6356 AOT Step Down Converter, Configurable 5.0 A Description The NCV6356 is a synchronous AOT (Adaptive On-time) buck converter optimized to supply the different sub systems of automotive applications post regulation system up to 5 V input. The device is able to deliver up to 5.0 A, with programmable output voltage from 0.6 V to 1.4 V. Operation at up to 2.4 MHz switching frequency allows the use of small components. Synchronous rectification and automatic PFM Pseudo-PWM (PPWM) transitions improve overall solution efficiency. The NCV6356 is in low profile 3.0 x 4.0 mm DFN-14 package. www.onsemi.com 1 WDFNW14 4x3, 0.5P CASE 511CM MARKING DIAGRAM Features * Input Voltage Range from 2.5 V to 5.5 V : Battery, 3.3 V and 5.0 V * * * * * * * * * * * * Rail Powered Applications Power Capability : 3.0 A Ta = 105C - 5.0 A Ta = 85C Programmable Output Voltage : 0.6 V to 1.4 V in 6.25 mV Steps Up to 2.4 MHz Switching Frequency with On Chip Oscillator Uses 330 nH Inductor and at least 22 mF Capacitors for Optimized Footprint and Solution Thickness PFM/PPWM Operation for Optimum Efficiency Low 60 mA Quiescent Current I2C Control Interface with Interrupt and Dynamic Voltage Scaling Support Enable / VSEL Pins, Power Good / Interrupt Signaling Thermal Protections and Temperature Management Transient Load Helper: Share the Same Rail with Another Rail 3.0 x 4.0 mm / 0.5 mm Pitch DFN 14 Package AEC-Q100 Qualified and PPAP Capable 6356 xx AYWW G 6356 xx A Y WW G = Specific Device Code = C: 1.150 V / 1.150 V = B: 1.200 V / 1.200 V = Q: 0.875 V / 0.906 V = Assembly Location = Year = Work Week = Pb-Free Package* (Note: Microdot may be in either location) Typical Applications * * * * * Snap Dragon Automotive POL Instrumentation, Clusters Infotainment ADAS System (Vision, Radar) (Top View) 14-Pin 0.50 mm pitch DFN ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 32 of this data sheet. (c) Semiconductor Components Industries, LLC, 2017 August, 2019 - Rev. 0 1 Publication Order Number: NCV6356/D NCV6356 Supply Input 4.7uF NCV6356 AVIN PVIN Core AGND DCDC 5A Enable Control EN Input VSEL Voltage Selection Operating Mode Control Interrupt PGND INTB Output Monitoring SDA I@C Processor I@C Control InterfaceSCL Supply Input 10uF Thermal Protection SW Modular Driver 330 nH 2x 22uF PGND DCDC 2.4MHz Controller FB Sense Processor Core Figure 1. Typical Application Circuit PVIN POWER INPUT PVIN SUPPLY INPUT AVIN ANALOG GROUND AGND Core 5.0 A DC-DC Thermal Protection SW SW SWITCH NODE SW Output Voltage Monitoring ENABLE CONTROL INPUTEN VOLTAGE SELECTION VS EL INTB PROCESSOR I2C CONTROL INTERFACE SCL SDA Up to 2.4 MHz DC-DC converter Controller Operating Mode Control Logic Control Interrupt I2C Sense Figure 2. Simplified Block Diagram www.onsemi.com 2 PGND POWER GROUND PGND VOUT FEEDBACK NCV6356 Figure 3. Pin Out (Top View) Table 1. PIN FUNCTION DESCRIPTION Pin Name Type Description REFERENCE 4 AVIN Analog Input Analog Supply. This pin is the device analog and digital supply. Could be connected directly to the VIN plane with a dedicated 4.7 mF ceramic capacitor. Must be equal to PVIN 15 AGND Analog Ground Analog Ground. Analog and digital modules ground. Must be connected to the system ground. CONTROL AND SERIAL INTERFACE 14 EN Digital Input Enable Control. Active high will enable the part. There is an internal pull down resistor on this pin. 13 VSEL Digital Input Output voltage / Mode Selection. The level determines which of two programmable configurations to utilize (operating mode / output voltage). There is an internal pull down resistor on this pin; could be left open if not used. 3 INTB Digital Output 1 SCL Digital Input I2C interface Clock line. There is an internal pull down resistor on this pin; could be left open if not used 12 SDA Digital Input/Output I2C interface Bi-directional Data line. There is an internal pull down resistor on this pin; could be left open if not used Interrupt open drain output. Must be connected to the ground plane if not used. DC to DC CONVERTER 8, 9 PVIN Power Input Switch Supply. These pins must be decoupled to ground by at least a 10 mF ceramic capacitor. It should be placed as close as possible to these pins. All pins must be used with short heavy connections. Must be equal to AVIN 5, 6, 7 SW Power Output Switch Node. These pins supply drive power to the inductor. Typical application uses 0.33 mH inductor; refer to application section for more information. All pins must be used with short heavy connections. 10, 11 PGND Power Ground Switch Ground. This pin is the power ground and carries the high switching current. High quality ground must be provided to prevent noise spikes. To avoid high-density current flow in a limited PCB track, a local ground plane that connects all PGND pins together is recommended. Analog and power grounds should only be connected together in one location with a trace. 2 VOUT Analog Input Feedback Voltage Input. Must be connected to the output capacitor positive terminal with a trace, not to a plane. This is the positive input to the error amplifier. www.onsemi.com 3 NCV6356 Table 2. MAXIMUM RATINGS Rating Symbol Analog and power pins (Note 1): AVIN, PVIN, SW, INTB, VOUT, DC non switching PVIN-PGND pins, transient 3 ns - 2.4 MHz Value Unit VA V -0.3 to +6.0 -0.3 to +7.5 I2C pins: SDA, SCL VI2C -0.3 to +6.0 V Digital pins : EN, VSEL Input Voltage Input Current VDG IDG -0.3 to VA +0.3 6.0 10 V mA Human Body Model (HBM) ESD Rating (Note 2) ESD HBM 2500 V Charged Device Model (CDM) ESD Rating (Note 2) ESD CDM 1000 V 100 100 mA Latch Up Current: (Note 3) Digital Pins All Other Pins ILU Storage Temperature Range TSTG -65 to +150 C Maximum Junction Temperature TJMAX -40 to +150 C MSL Level 1 Moisture Sensitivity (Note 4) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe Operating parameters. 2. This device series contains ESD protection and passes the following ratings: Human Body Model (HBM) 2.5 kV per JEDEC standard: JESD22*A114. Charged Device Model (CDM) 1.0 kV per JEDEC standard: JESD22-C101 Class IV 3. Latch up Current per JEDEC standard: JESD78 class II. 4. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J-STD-020A. Table 3. OPERATING CONDITIONS Symbol Parameter AVIN, PVIN TJ RqJA PD L Conditions Power Supply AVIN = PVIN Junction Temperature Range (Note 6) Min Typ 2.5 Max Unit 5.5 V -40 25 +125 C Thermal Resistance Junction to Ambient (Note 7) DFN-14 on Demo-board - 30 - C/W Power Dissipation Rating (Note 8) TA 105C, RqJA = 30C/W - 666 - mW TA 85C RqJA = 30C/W - 1333 - mW TA = 65C RqJA = 30C/W - 2000 - mW 0.15 0.33 0.47 mH 15 - 200 mF 6.0 10.0 - mF Inductor for DC to DC converter (Note 5) Co Output Capacitor for DC to DC Converter (Note 5) Cin Input Capacitor for DC to DC Converter (Note 5) Per 1.0 A of IOUT Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 5. Including de-ratings (Refer to the Application Information section of this document for further details) 6. The thermal shutdown set to 150C (typical) avoids potential irreversible damage on the device due to power dissipation 7. The RqJA is dependent of the PCB heat dissipation. Board used to drive this data was a NCV6356EVB board. It is a multilayer board with 1-once internal power and ground planes and 2-once copper traces on top and bottom of the board 8. The maximum power dissipation (PD) is dependent on input voltage, maximum output current, pcb stack up and layout, and external components selected. R qJA + 125 * T A , by taking R qJA + 30 oC PD www.onsemi.com 4 NCV6356 Table 4. ELECTRICAL CHARACTERISTICS (Note 9) Min and Max Limits apply for TJ = -40C to +125C, AVIN = PVIN = 3.3 V and default configuration, unless otherwise specified. Typical values are referenced to TA = + 25C, AVIN = PVIN = 3.3 V and default configuration, unless otherwise specified. Parameter Symbol Conditions Min Typ Max Unit Supply Current: Pins AVIN - PVINx IQ-PPWM Operating quiescent current PPWM DCDC active in Forced PPWM no load - 22 25 mA IQ PFM Operating quiescent current PFM DCDC active in Auto mode no load - minimal switching - 60 90 mA ISLEEP Product sleep mode current Product in sleep mode VIN = 5.5 V, TJ up to 85C - 5 10 mA IOFF Product in off mode EN, VSEL and Sleep_Mode low, No I2C pull up VIN = 5.5 V, TJ up to 85C - 0.8 3 mA 2.5 - 5.5 V DC to DC Converter PVIN Input Voltage Range IOUT Load Current Range DVOUT Output Voltage DC Error A NCV6356B and NCV6356C (Note 11, 12) Ipeak[1..0] = 00 Ipeak[1..0] = 01 Ipeak[1..0] = 10 Ipeak[1..0] = 11 0 0 0 0 - - - - 3.5 4.0 4.5 5.0 NCV6356Q (Note 11, 12) Ipeak[1..0] = 00 Ipeak[1..0] = 01 Ipeak[1..0] = 10 Ipeak[1..0] = 11 0 0 0 0 - - - - 5.3 5.8 6.3 6.8 Forced PPWM mode, VIN range, No load -1.5 - 1.5 Forced PPWM mode, VIN range, IOUT up to IOUTMAX (Note 11) -2 - 2 Auto mode, VIN range, IOUT up to IOUTMAX (Note 11) -3 - 2 2.16 2.4 2.64 MHz % FSW Switching Frequency RONHS P-Channel MOSFET On Resistance From PVIN to SW VIN = 5.0 V - 38 50 mW RONLS N-Channel MOSFET On Resistance From SW to PGND VIN = 5.0 V - 29 40 mW IPK Peak Inductor Current NCV6356B and NCV6356C Open loop - Ipeak[1..0] = 00 Open loop - Ipeak[1..0] = 01 Open loop - Ipeak[1..0] = 10 Open loop - Ipeak[1..0] = 11 4.6 5.2 5.6 6.2 5.2 5.8 6.2 6.8 5.8 6.4 6.8 7.4 NCV6356QM Open loop - Ipeak[1..0] = 00 Open loop - Ipeak[1..0] = 01 Open loop - Ipeak[1..0] = 10 Open loop - Ipeak[1..0] = 11 6.4 7.2 7.6 8.4 7.0 7.8 8.2 9.0 7.7 8.4 8.8 9.6 A DCLOAD Load Regulation IOUT from 0 A to IOUTMAX (Note 11) Forced PPWM mode - 5 - mV DCLINE Line Regulation 2.5 V VIN 5.5 V Forced PPWM mode - 6 - mV www.onsemi.com 5 NCV6356 Table 4. ELECTRICAL CHARACTERISTICS (Note 9) Min and Max Limits apply for TJ = -40C to +125C, AVIN = PVIN = 3.3 V and default configuration, unless otherwise specified. Typical values are referenced to TA = + 25C, AVIN = PVIN = 3.3 V and default configuration, unless otherwise specified. Symbol ACLOAD Parameter Transient Load Response Conditions Min Typ Max Unit - 20 - mV NCV6356Q tr = tf = 200 ns, VOUT = 1.0 V L = 0.24 mH, COUT = 4 x 47 mF Load step 0.4A / 6.6 A (Note 11) -60 50 67 tr = tf = 10 ms Line step 3.3 V / 3.9 V (Note 11) - 20 - tr = tf = 100 ns Load step 1.5 A (Note 11) ACLINE Transient Line Response mV D Maximum Duty Cycle - 100 - % tSTART Turn on time Time from EN transitions from Low to High to 90% of Output Voltage (DVS[1..0] = 00b) - 100 130 Us RDISDCDC DCDC Active Output Discharge Vout = 1.15 V - 12 20 W 1.05 - - V EN, VSEL VIH High input voltage VIL Low input voltage TFTR Digital input X Filter EN, VSEL rising and falling DBN_Time = 01 (Note 11) IPD Digital input X Pull-Down (input bias current) - - 0.4 V 0.5 - 4.5 ms For EN and VSEL pins - 0.05 1.00 mA INTB (Optional) VINTBL INTB low output voltage IINT = 5 mA 0 - 0.2 VINTBH INTB high output voltage Open drain - - 5.5 INTBLK INTB leakage current 3.6V at INTB pin when INTB valid - - 100 1.7 - 4.5 V I2C VI2CINT High level at SCL/SCA line VI2CIL SCL, SDA low input voltage SCL, SDA pin (Note 10) - - 0.4 V VI2CIH SCL high input voltage SCL pin (Note 10, 11) 1.6 - - V SDA high input voltage SDA pin (Note 10, 11) 1.2 - - VI2COL SDA low output voltage ISINK = 3 mA - - 0.4 V FSCL I2C clock frequency (note 11) - - 3.4 MHz TOTAL DEVICE VUVLO Under Voltage Lockout VIN falling - - 2.5 V VUVLOH Under Voltage Lockout Hysteresis VIN rising 60 - 200 mV TSD Thermal Shut Down Protection - 150 - C TWARNING Warning Rising Edge - 135 - C I2C TPWTH Pre - Warning Threshold - 105 - C TSDH Thermal Shut Down Hysteresis default value - 30 - C TWARNINGH Thermal warning Hysteresis - 15 - C TPWTH H Thermal pre-warning Hysteresis - 6 - C Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 9. Refer to the Application Information Section of this data sheet for more details. 10. Devices that use non-standard supply voltages which do not conform to the intent I2C bus system levels must relate their input levels to the VDD voltage to which the pull-up resistors RP are connected. 11. Guaranteed by design and characterized. 12. Junction temperature must be maintained below 125C. Output load current capability depends on the application thermal capability. www.onsemi.com 6 NCV6356 Typical Operating Characteristics AVIN = PVIN = 3.3 V, TJ=+25C DCDC=1.15 V, Ipeak =6.8 A (Unless otherwise noted). L=0.33 uH DFE252012F - Cout = 2 x 22uF 0603, Cin = 4.7 uF 0603. Figure 4. Efficiency vs ILOAD and VIN, VOUT = 1.39375 V, SPM5030 Inductor Figure 5. Efficiency vs ILOAD and Temperature, VOUT = 1.39375 V, SPM5030 Inductor Figure 6. Efficiency vs ILOAD and VIN, VOUT = 1.15 V, SPM5030 Inductor Figure 7. Efficiency vs ILOAD and Temperature, VOUT = 1.15 V, SPM5030 Inductor Figure 8. Efficiency vs ILOAD and VIN, VOUT = 0.60 V, SPM5030 Inductor Figure 9. Efficiency vs ILOAD and Temperature, VOUT = 0.60 V, SPM5030 Inductor www.onsemi.com 7 NCV6356 Figure 10. Efficiency vs ILOAD and VIN, VOUT = 1.150 V Figure 11. Efficiency vs ILOAD and Temperature, VOUT = 1.150 V Figure 12. Efficiency vs ILOAD and VIN, VOUT = 0.600 V Figure 13. Efficiency vs ILOAD and Temperature, VOUT = 0.875 V, HEI201612A-R24M Inductor Figure 14. Efficiency vs ILOAD and Temperature, VOUT = 0.906 V, HEI201612A-R24M Inductor Figure 15. Efficiency vs ILOAD and Temperature, VOUT = 1.394 V www.onsemi.com 8 NCV6356 Figure 16. VOUT Accuracy vs ILOAD and VIN, VOUT = 1.150 V Figure 17. VOUT Accuracy vs VIN and Temperature, VOUT = 1.150 V Figure 18. VOUT Accuracy vs ILOAD and VIN, VOUT = 0.600 V Figure 19. VOUT Accuracy vs ILOAD and VIN, VOUT = 0.875 V, HEI201612A-R24M Inductor Figure 20. VOUT Accuracy vs ILOAD and VIN, VOUT = 0.906 V, HEI201612A-R24M Inductor Figure 21. VOUT Accuracy vs ILOAD and VIN, VOUT = 1.394 V www.onsemi.com 9 NCV6356 Figure 22. HSS RON vs VIN and Temperature Figure 23. LSS RON vs VIN and Temperature Figure 24. IOFF vs VIN and Temperature Figure 25. ISLEEP vs VIN and Temperature Figure 26. IQPFM vs VIN and Temperature Figure 27. IQPPWM vs VIN and Temperature www.onsemi.com 10 NCV6356 Figure 28. Switchover Point VOUT = 1.15 V Figure 29. Switchover Point VOUT = 1.4 V Figure 30. Switching Frequency vs ILOAD and VIN, VOUT = 1.150 V Figure 31. Switching Frequency vs ILOAD and Temperature, VOUT = 1.150 V www.onsemi.com 11 NCV6356 Figure 32. Ripple Figure 33. Normal Power Up, VOUT = 1.15 V, DVS[1..0] = 00 Figure 34. Transient Load 0.4 to 6.6 A - Auto Mode, VIN = 3.3 V - VOUT = 1.0 V - L = 0.24 uH - COUT = 4 x 47 uF Figure 35. Transient Load 0.4 to 6.6 A - Forced PPWM, VIN = 3.3 V - VOUT = 1.0 V - L = 0.24 uH - COUT = 4 x 47 uF www.onsemi.com 12 NCV6356 Figure 36. Transient Load 0.05 to 1.5 A, Transient Line 3.0 - 3.6 V Auto Mode Figure 37. Transient Load 0.05 to 1.5 A, Transient Line 3.6 - 3.0 V Auto Mode Figure 38. Transient Load 1 to 2.5 A, Transient Line 3.0 - 3.6 V Auto Mode Figure 39. Transient Load 1 to 2.5 A, Transient Line 3.6 - 3.0 V Auto Mode www.onsemi.com 13 NCV6356 DETAILED OPERATING DESCRIPTION Detailed Descriptions Output Stage The NCV6356 is voltage mode stand-alone DC to DC converter optimized to supply different sub systems of automotive applications post regulation system up to 5 V input. It can deliver up to 5 A at an I2C selectable voltage ranging from 0.6 V to 1.40 V. The switching frequency up to 2.4 MHz allows the use of small output filter components. Power Good indicator and Interrupt management are available. Operating modes, configuration, and output power can be easily selected either by using digital I/O pins or by programming a set of registers using an I2C compatible interface capable of operation up to 3.4 MHz. Default I2C settings are factory programmable. NCV6356 is a 3.5 A to 5.0 A output current capable DC to DC converter with both high side and low side (synchronous) switches integrated. Inductor Peak Current Limitation / Short Protection During normal operation, peak current limitation monitors and limits the inductor current by checking the current in the P-MOSFET switch. When this current exceeds the Ipeak threshold, the P-MOSFET is immediately opened. To protect again excessive load or short circuit, the number of consecutive Ipeak is counted. When the counter reaches 16, the DCDC is powered down during about 2 ms and the ISHORT interrupt is flagged. It will re-start following the REARM bit in the LIMCONF register: * If REARM = 0, then NCV6356 does not re-start automatically, an EN pin toggle is required. * If REARM = 1, NCV6356 re-starts automatically after the 2 ms with register values set prior the fault condition. DC to DC Converter Operation The converter integrates both high side and low side (synchronous) switches. Neither external transistors nor diodes are required for NCV6356 operation. Feedback and compensation network are also fully integrated. It uses the AOT (Adaptive On-Time) control scheme and can operate in two different modes: PFM and PPWM (Pseudo-PWM). The transition between modes can occur automatically or the switcher can be placed in forced PPWM mode by I2C programming (PPWMVSEL0 / PPWMVSEL1 bits of COMMAND register). This current limitation is particularly useful to protect the inductor. The peak current can be set by writing IPEAK[1..0] bits in the LIMCONF register. PPWM (Pseudo Pulse Width Modulation) Operating Mode In medium and high load conditions, NCV6356 operates in PPWM mode to regulate the desired output voltage. In this mode, the inductor current is in CCM (Continuous Conduction Mode) and the AOT guaranties a pseudo-fixed frequency with 10% accuracy. The internal N-MOSFET switch operates as synchronous rectifier and is driven complementary to the P-MOSFET switch. Table 5. IPEAK VALUES OPN IPEAK[1..0] Inductor Peak Current (A) NCV6356B NCV6356C 00 5.2 - for 3.5 output current 01 5.8 - for 4.0 output current 10 6.2 - for 4.5 output current 11 6.8 - for 5.0 output current 00 7.0 - for 5.3 output current 01 7.7 - for 5.8 output current 10 8.2 - for 6.3 output current 11 8.8 - for 6.8 output current NCV6356Q PFM (Pulse Frequency Modulation) Operating Mode In order to save power and improve efficiency at low loads, the NCV6356 operates in PFM mode as the inductor current drops into DCM (Discontinuous Conduction Mode). The upper FET on-time is kept constant and the switching frequency becomes proportional to the loading current. As it does in PPWM mode, the internal N-MOSFET operates as a synchronous rectifier after each P-MOSFET on-pulse until there is no longer current in the coil. When the load increases and the current in the inductor become continuous again, the controller automatically turns back to PPWM mode. Output Voltage The output voltage is set internally by an integrated resistor bridge and no extra components are needed to set the output voltage. Writing in the VoutVSEL0[6..0] bits of the PROGVSEL0 register or VoutVSEL1[6..0] bits of the PROGVSEL1 register will change the output voltage. The output voltage level can be programmed by 6.26 mV steps between 0.6 V to 1.39375 V. The VSEL pin and VSELGT bit will determine which register between PROGVSEL0 and PROGVSEL1 will set the output voltage. * If VSELGT = 1 AND VSEL=0 Output voltage is set by VoutVSEL0[6..0] bits (PROGVSEL0 register) * Else Output voltage is set by VoutVSEL1[6..0] bits (PROGVSEL1 register) Forced PPWM The NCV6356 can be programmed to only use PPWM and the transition to PFM can be disabled if so desired, thanks to the PPWMVSEL0 or PPWMVSEL1 I2C bits (COMMAND register). www.onsemi.com 14 NCV6356 Under Voltage Lock Out (UVLO) Enabling NCV6356 core does not operate for voltages below the Under Voltage Lock Out (UVLO) level. Below the UVLO threshold, all internal circuitry (both analog and digital) is held in reset. NCV6356 operation is guaranteed down to UVLO as the battery voltage is dropping off. To avoid erratic on / off behavior, a maximum 200 mV hysteresis is implemented. Restart is guaranteed at 2.7 V when the VBAT voltage is recovering or rising. The EN pin controls NCV6356 start up. EN pin Low to High transition starts the power up sequencer. If EN is low, the DC to DC converter is turned off and device enters: * Sleep Mode if Sleep_Mode I2C bit is high or VSEL is high or I2C pull up present, * Off Mode if Sleep_Mode I2C bit and VSEL are low and no I2C pull up. When EN pin is set to a high level, the DC to DC converter can be enabled / disabled by writing the ENVSEL0 or ENVSEL1 bit of the PROGVSEL0 and PROGVSEL1 registers: * Enx I2C bit is high, the DC to DC converter is activated. * Enx I2C is low, the DC to DC converter is turned off and the device enters in Sleep Mode. Thermal Management Thermal Shut Down (TSD) The thermal capability of the NCV6356 can be exceeded due to the step down converter output stage power level. A thermal protection circuitry with associated interrupt is therefore implemented to prevent the IC from damage. This protection circuitry is only activated when the core is in active mode (output voltage is turned on). During thermal shut down, output voltage is turned off. During thermal shut down, the output voltage is turned off. When NCV6356 returns from thermal shutdown, it can re-start in 2 different configurations depending on the REARM bit in the LIMCONF register (refer to the register description section): * If REARM = 0 then NCV6356 does not re-start after TSD. To restart, an EN pin toggle is required. * If REARM = 1, NCV6356 re-starts with register values set prior to thermal shutdown. A built in pull down resistor disables the device when this pin is left unconnected or not driven. EN pin activity does not generate any digital reset. Power Up Sequence (PUS) In order to power up the circuit, the input voltage AVIN has to rise above the VUVLO threshold. This triggers the internal core circuitry power up which is the "Wake Up Time" (including "Bias Time") This delay is internal and cannot be bypassed. EN pin transition within this delay corresponds to the "Initial power up sequence" (IPUS): The thermal shut down threshold is set at 150C (typical) and a 30C hysteresis is implemented in order to avoid erratic on / off behavior. After a typical 150C thermal shut down, NCV6356 will resume to normal operation when the die temperature cools to 120C. AVIN UVLO POR EN Thermal Warnings In addition to the TSD, the die temperature monitoring circuitry includes a thermal warning and thermal pre-warning sensor and interrupts. These sensors can inform the processor that NCV6356 is close to its thermal shutdown and preventive measures to cool down die temperature can be taken by software. The Warning threshold is set by hardware to 135C typical. The Pre-Warning threshold is set by default to 105C but it can be changed by setting the TPWTH[1..0] bits in the LIMCONF register. IIIII IIIII VOUT ~ 80 us Wake up Time DELAY[2..0] 32 us Init DVS ramp Time Time Figure 40. Initial Power Up Sequence In addition a user programmable delay will also take place between the Wake Up Time and the Init time: The DELAY[2..0] bits of the TIME register will set this user programmable delay with a 2 ms resolution. With default delay of 0 ms, the NCV6356 IPUS takes roughly 100 ms, and the DC to DC converter output voltage will be ready within 150 ms. The power up output voltage is defined by the VSEL state. NOTE: During the Wake Up time, the I2C interface is not active. Any I2C request to the IC during this time period will result in a NACK reply. Active Output Discharge To make sure that no residual voltage remains in the power supply rail when disabled, an active discharge path can ground the NCV6356 output voltage. For maximum flexibility, this feature can be easily disabled or enabled with the DISCHG bit in the PGOOD register. By default the discharge path is enabled and is activated during the first 100 ms after battery insertion. www.onsemi.com 15 NCV6356 In addition the delay set in DELAY[2..0] bits in TIME register will apply only for the EN pins turn ON sequence (NPUS and QPUS). The power up output voltage is defined by VSEL state. Normal, Quick and Fast Power Up Sequence The previous description applies only when the EN transitions during the internal core circuitry power up (Wake up and calibration time). Otherwise 3 different cases are possible: * Enabling the part by setting the EN pin from Off Mode will result in "Normal power up sequence" (NPUS, with DELAY;[2..0]). * Enabling the part by setting the EN pin from Sleep Mode will result in "Quick power up sequence" (QPUS, with DELAY;[2..0]). * Enabling the DC to DC converter, whereas EN is already high, either by setting the ENVSEL0 or ENVSEL1 bits or by VSEL pin transition will results in "Fast power up sequence" (FPUS, without DELAY[2..0]). DC to DC Converter Shut Down When shutting down the device, no shut down sequence is required. The output voltage is disabled and, depending on the DISCHG bit state of the PGOOD register, the output may be discharged. DC to DC converter shutdown is initiated by either grounding the EN pin (Hardware Shutdown) or, depending on the VSEL internal signal level, by clearing the ENVSEL0 or ENVSEL1 bits (Software shutdown) in the PROGVSEL0 or PROGVSEL1 registers. In hardware shutdown (EN = 0), the internal core is still active and I C accessible. The internal core of the NCV6356 shuts down when AVIN falls below UVLO. AVIN Dynamic Voltage Scaling (DVS) UVLO POR EN The NCV6356 supports dynamic voltage scaling (DVS) allowing the output voltage to be reprogrammed via I2C commands and provides the different voltages required by the processor. The change between set points is managed in a smooth fashion without disturbing the operation of the processor. When programming a higher voltage, the output raises with controlled dV/dt defined by DVS[1..0] bits in the TIME register. When programming a lower voltage the output voltage will decrease accordingly. The DVS step is fixed and the speed is programmable. The DVS sequence is automatically initiated by changing the output voltage settings. There are two ways to change these settings: * Directly change the active setting register value (VoutVSEL0[6..0] of the PROGVSEL0 register or VoutVSEL1[6..0] of the PROGVSEL1 register) via an I2C command * Change the VSEL internal signal level by toggling the VSEL pin. O F F DELAY[2..0] M O D E 60 us 32 us TFTR Bias Time Init Time DVS ramp Time Figure 41. Normal Power Up Sequence AVIN UVLO POR EN S L E E P DELAY[2..0] M O D E 10 us 32 us TFTR Bias Time Init Time DVS ramp Time Figure 42. Quick Power Up Sequence The second method eliminates the I2C latency and is therefore faster. The DVS transition mode can be changed with the DVSMODE bit in the COMMAND register: * In forced PPWM mode when accurate output voltage control is needed. Rise and fall time are controlled with the DVS[1..0] bits. AVIN UVLO POR VSEL VOUT S L E E P M O D E 32 us T Init Time DVS ramp Time Figure 43. Fast Power Up Sequence www.onsemi.com 16 NCV6356 V2 Internal Reference Internal DVS ramp Output Voltage nV V2 nt V1 V1 DVS up Figure 44. DVS in Forced PPWM Mode Diagram * In Auto mode when the output voltage must not be PG discharged. Rise time is controlled by the DVS[1..0], and fall time depends of the load and cannot be faster than the DVS[1..0] settings. Figure 47. Power Good during DVS Transition Output Voltage V2 Internal Reference Digital IO Settings nV VSEL Pin By changing VSEL pin levels, the user has a latency free way to change NCV6356 configuration: operating mode (Auto or PWM forced), the output voltage as well as enable. nt V1 Figure 45. DVS in Auto Mode Diagram Table 6. VSEL PIN PARAMETERS Power Good Indicator To indicate the output voltage level is established, a power good signal is available. The power good signal is low when the DC to DC converter is off. Once the output voltage reaches 95% of the expected output level, the power good logic signal becomes high (ACK_PG, SEN_PG bits). During operation, when the output drops below 90% of the programmed level, the power good logic signal goes low, indicating a power failure. When the voltage rises again to above 95%, the power good signal goes high again. During a DVS sequence, the Power Good signal is set low during the transition and goes back high once the transition is completed. The Power Good signal during normal operation can be disabled by clearing the PGDCDC bit in the PGOOD register. The Power good operation during DVS can be activated with PGDVS bit if the PGOOD register. DCDC 3.5 us REGISTER VSEL = LOW REGISTER VSEL = HIGH ENABLE ENVSEL0 PROGVSEL0[7] ENVSEL1 PROGVSEL1[7] VOUT VoutVSEL0[6..0] VoutVSEL1[6..0] OPERATING MODE (Auto / PPWM Forced) PWMVSEL0 COMMAND[7] PWMVSEL1 COMMAND[6] EN pin The EN pin can be gated by writing the ENVSEL0 or ENVSEL1 bits of the PROGVSEL0 and PROGVSEL1 registers, depending on which register is activated by the VSEL internal signal. Interrupt Pin (Optional) The interrupt controller continuously monitors internal interrupt sources, generating an interrupt signal when a system status change is detected (dual edge monitoring). 95% 90% 3.5- 14 us Parameter VSEL Pin Can Set VSEL pin action can be masked by writing 0 to the VSELGT bit in the COMMAND register. In that case I2C bit corresponding to VSEL high will be taken into account. DCDC _EN 32 us DVS down 3.5 - 14 us PG Table 7. INTERRUPT SOURCES Figure 46. Power Good Signal when PGDCDC = 1 Interrupt Name TSD Thermal Shut Down TWARN Thermal Warning TPREW Thermal Pre Warning UVLO Under Voltage Lock Out IDCDC DC to DC converter Current Over / below limit ISHORT DC to DC converter Short-Circuit Protection PG www.onsemi.com 17 Description Power Good NCV6356 Individual bits generating interrupts will be set to 1 in the INT_ACK register (I2C read only registers), indicating the interrupt source. INT_ACK register is automatically reset by an I2C read. The INT_SEN register (read only register) contains real time indicators of interrupt sources. All interrupt sources can be masked by writing in the register INT_MSK. Masked sources will never generate an interrupt request on the INTB pin. The INTB pin is an open drain output. A non-masked interrupt request will result in the INTB pin being driven low. When the host reads the INT_ACK registers the INTB pin is released to high impedance and the interrupt register INT_ACK is cleared. Figure 48 is an example of a TWARN event of the INTB pin with INT_SEN/INT_MSK/INT_ACK and an I2C read access behavior. TWARN SEN_TWARN MSK_TWARN ACK_TWARN INTB I@C access on INT_ACK read read read read Figure 48. TWARN Interrupt Operation Example Configurations Default output voltages, enables, DCDC modes, current limit and other parameters can be factory programmed upon request. Below is the default configurations pre-defined: Table 8. NCV6356 CONFIGURATION Configuration 5.0 A NCV6356CM 5.0 A NCV6356BM 6.8 A NCV6356QM Default I2C address PID product identification RID revision identification FID feature identification ADD1 - 14h : 0010100R/W 20h Metal 00h ADD1 - 14h : 0010100R/W 20h Metal 01h ADD6 - 68h : 1101000R/W 20h Metal 02h Default VOUT - VSEL=1 1.15 V 1.20 V 0.90625 V Default VOUT - VSEL=0 1.15 V 1.20 V 0.875 V Default MODE - VSEL=1 Forced PPWM Forced PPWM Forced PPWM Default MODE - VSEL=0 Auto mode Auto mode Forced PPWM 6.8 A 6.8 A 8.8 A NCV6356CMTWTXG NCV6356BMTWTXG NCV6356QMTWTXG 6356C 6356B 6356Q Default IPEAK OPN Marking www.onsemi.com 18 NCV6356 I2C Compatible Interface NCV6356 can support a subset of the I2C protocol as detailed below. I2C Communication Description FROM MCU to NCPxxxx FROM NCPxxxx to MCU START IC ADDRESS 1 ACK 0 ACK ACK DATA 1 DATA n /ACK STOP READ OUT FROM PART STOP WRITE INSIDE PART 1 a READ START IC ADDRESS /ACK ACK DATA 1 DATA n ACK If PART does not Acknolege , the /NACK will be followed by a STOP or (repeated Sr start ). If PART Acknoleges , the ACK can be followed by another data or Stop or Sr 0 a WRITE Figure 49. General Protocol Description last write operation. Like the writing process, the reading process is auto-incremental. The first byte transmitted is the Chip address (with the LSB bit set to 1 for a read operation, or set to 0 for a Write operation). The following data will be: * During a Write operation, the register address (@REG) is written in followed by the data. The writing process is auto-incremental, so the first data will be written in @REG, the contents of @REG are incremented and the next data byte is placed in the location pointed to by @REG + 1 ..., etc. * During a Read operation, the NCV6356 will output the data from the last register that has been accessed by the Read Sequence The Master will first make a "Pseudo Write" transaction with no data to set the internal address register. Then, a stop then start or a Repeated Start will initiate the read transaction from the register address the initial write transaction has pointed to: FROM MCU to NCPxxxx FROM NCPxxxx to MCU SETS INTERNAL REGISTER POINTER START IC ADDRESS 0 ACK REGISTER ADDRESS ACK STOP 0 a WRITE START IC ADDRESS 1 ACK ACK DATA 1 REGISTER ADDRESS VALUE n REGISTERS READ 1 a READ Figure 50. Read Sequence The first WRITE sequence will set the internal pointer to the register that is selected. Then the read transaction will start at the address the write transaction has initiated. www.onsemi.com 19 DATA n REGISTER ADDRESS + (n - 1) VALUE /ACK STOP NCV6356 Write Sequence following data will be the data we want to write in REG, REG + 1, REG + 2, ..., REG +n. Write n Registers: Write operation will be achieved by only one transaction. After chip address, the REG address has to be set, then FROM MCU to NCPxxxx FROM NCPxxxx to MCU SETS INTERNAL REGISTER POINTER START IC ADDRESS ACK 0 WRITE VALUE IN REGISTER REG0 + (n-1) WRITE VALUE IN REGISTER REG0 REGISTER REG0 ADDRESS ACK ACK REG VALUE REG+ (n - 1) VALUE ACK n REGISTERS WRITE 0 a WRITE Figure 51. Write Sequence Write then Read Sequence With Stop Then Start FROM MCU to NCPxxxx FROM NCPxxxx to MCU SETS INTERNAL REGISTER POINTER START IC ADDRESS 0 ACK REGISTER REG0 ADDRESS WRITE VALUE IN REGISTER REG0 + (n-1) WRITE VALUE IN REGISTER REG0 ACK ACK REG VALUE REG + (n - 1) VALUE n REGISTERS WRITE 0 a WRITE START IC ADDRESS 1 ACK DATA 1 ACK DATA k REGISTER REG+ (n - 1) VALUE REGISTER ADDRESS + (n - 1) + (k - 1) VALUE k REGISTERS READ 1 a READ Figure 52. Write Followed by Read Transaction www.onsemi.com 20 /ACK STOP ACK STOP STOP NCV6356 I2C Address settings can be generated upon request to ON Semiconductor. See Table 8 (NCV6356 Configuration) for the default I2C address. The NCV6356 has 8 available I2C addresses selectable by factory settings (ADD0 to ADD7). Different address Table 9. I2C ADDRESS I2C Address Hex A7 A6 A5 A4 A3 A2 A1 A0 ADD0 W 0x20 R 0x21 0 0 1 0 0 0 0 R/W ADD1 W 0x28 R 0x29 0 0 1 1 0 0 R/W ADD2 W 0x30 R 0x31 0 0 1 0 0 0 R/W Add 0x10 Add W 0x38 R 0x39 0 0 1 W 0xC0 R 0xC1 1 1 0 W 0xC8 R 0xC9 1 1 0 1 0 0 0 0 W 0xD0 R 0xD1 1 1 0 1 0 0 0 1 1 Add 0 1 0x6C www.onsemi.com 21 R/W - 1 0 0 R/W - 0 0 0 0x68 W 0xD8 R 0xD9 R/W - 0x64 Add ADD7 1 - 0x60 Add ADD6 - 0x1C Add ADD5 1 0x18 Add ADD4 - 0x14 Add ADD3 0 R/W - 1 0 0 R/W - NCV6356 Register Map The tables below describe the I2C registers. Registers / bits Operations: R Read only register RC Read then Clear RW Read and Write register Reserved Address is reserved and register / bit is not physically designed Spare Address is reserved and register / bit is physically designed Table 10. I2C REGISTERS MAP CONFIGURATION (NCV6356C) Add. Register Name Type Def. Function 00h INT_ACK RC 00h Interrupt register 01h INT_SEN R 01h Sense register (real time status) 02h INT_MSK RW FFh Mask register to enable or disable interrupt sources (trim) 03h PID R 20h Product Identification 04h RID R Metal Revision Identification 05h FID R 00h Features Identification (trim) 06h to 0Fh - - - Reserved for future use 10h PROGVSEL1 RW D8h Output voltage settings and EN for VSEL pin = High (trim) 11h PROGVSEL0 RW D8h Output voltage settings and EN for VSEL pin = Low (trim) 12h PGOOD RW 10h Power good and active discharge settings (trim) 13h TIME RW 09h Enabling and DVS timings (trim) 14h COMMAND RW 43h Enabling and Operating mode Command register (trim) 15h - - - Reserved for future use 16h LIMCONF RW E3h Reset and limit configuration register (trim) 17h to 1Fh - - - Reserved for future use 20h to FFh - - - Reserved. Test Registers Table 11. I2C REGISTERS MAP CONFIGURATION (NCV6356B) Add. Register Name Type Def. Function 00h INT_ACK RC 00h Interrupt register 01h INT_SEN R 01h Sense register (real time status) 02h INT_MSK RW FFh Mask register to enable or disable interrupt sources (trim) 03h PID R 20h Product Identification 04h RID R Metal Revision Identification 05h FID R 01h Features Identification (trim) 06h to 0Fh - - - Reserved for future use 10h PROGVSEL1 RW E0h Output voltage settings and EN for VSEL pin = High (trim) 11h PROGVSEL0 RW E0h Output voltage settings and EN for VSEL pin = Low (trim) 12h PGOOD RW 10h Power good and active discharge settings (trim) 13h TIME RW 09h Enabling and DVS timings (trim) 14h COMMAND RW 43h Enabling and Operating mode Command register (trim) 15h - - - Reserved for future use 16h LIMCONF RW E3h Reset and limit configuration register (trim) 17h to 1Fh - - - Reserved for future use 20h to FFh - - - Reserved. Test Registers www.onsemi.com 22 NCV6356 Table 12. I2C REGISTERS MAP CONFIGURATION (NCV6356Q) Add. Register Name Type Def. Function 00h INT_ACK RC 00h Interrupt register 01h INT_SEN R 01h Sense register (real time status) 02h INT_MSK RW FFh Mask register to enable or disable interrupt sources (trim) 03h PID R 20h Product Identification 04h RID R Metal Revision Identification 05h FID R 02h Features Identification (trim) 06h to 0Fh - - - Reserved for future use 10h PROGVSEL1 RW B1h Output voltage settings and EN for VSEL pin = High (trim) 11h PROGVSEL0 RW ACh Output voltage settings and EN for VSEL pin = Low (trim) 12h PGOOD RW 10h Power good and active discharge settings (trim) 13h TIME RW 09h Enabling and DVS timings (trim) 14h COMMAND RW C3h Enabling and Operating mode Command register (trim) 15h - - - Reserved for future use 16h LIMCONF RW E3h Reset and limit configuration register (trim) 17h to 1Fh - - - Reserved for future use 20h to FFh - - - Reserved. Test Registers Registers Description Table 13. INTERRUPT ACKNOWLEDGE REGISTER Name: INTACK Address: 00h Type: RC Default: 00000000b (00h) Trigger: Dual Edge [D7..D0] D7 ACK_TSD D6 D5 D4 D3 D2 D1 D0 ACK_TWARN ACK_TPREW Spare = 0 ACK_ISHORT ACK_UVLO ACK_IDCDC ACK_PG Bit ACK_PG Bit Description Power Good Sense Acknowledgement 0: Cleared 1: DCDC Power Good Event detected ACK_IDCDC DCDC Over Current Sense Acknowledgement 0: Cleared 1: DCDC Over Current Event detected ACK_UVLO Under Voltage Sense Acknowledgement 0: Cleared 1: Under Voltage Event detected ACK_ISHORT DCDC Short-Circuit Protection Sense Acknowledgement 0: Cleared 1: DCDC Short circuit protection detected ACK_TPREW Thermal Pre Warning Sense Acknowledgement 0: Cleared 1: Thermal Pre Warning Event detected ACK_TWARN Thermal Warning Sense Acknowledgement 0: Cleared 1: Thermal Warning Event detected ACK_TSD Thermal Shutdown Sense Acknowledgement 0: Cleared 1: Thermal Shutdown Event detected www.onsemi.com 23 NCV6356 Table 14. INTERRUPT SENSE REGISTER Name: INTSEN Address: 01h Type: R Default: 00000000b (00h) Trigger: N/A D7 D6 D5 D4 D3 D2 D1 D0 SEN_TSD SEN_TWARN SEN_TPREW Spare = 0 SEN_ISHORT SEN_UVLO SEN_IDCDC SEN_PG Bit SEN_PG Bit Description Power Good Sense 0: DCDC Output Voltage below target 1: DCDC Output Voltage within nominal range SEN_IDCDC DCDC over current sense 0: DCDC output current is below limit 1: DCDC output current is over limit SEN_UVLO Under Voltage Sense 0: Input Voltage higher than UVLO threshold 1: Input Voltage lower than UVLO threshold SEN_ISHORT DCDC Short-Circuit Protection Sense 0: Short-Circuit detected not detected 1: Short-Circuit not detected SEN_TPREW Thermal Pre Warning Sense 0: Junction temperature below thermal pre-warning limit 1: Junction temperature over thermal pre-warning limit SEN_TWARN Thermal Warning Sense 0: Junction temperature below thermal warning limit 1: Junction temperature over thermal warning limit SEN_TSD Thermal Shutdown Sense 0: Junction temperature below thermal shutdown limit 1: Junction temperature over thermal shutdown limit www.onsemi.com 24 NCV6356 Table 15. INTERRUPT MASK REGISTER Name: INTMSK Address: 02h Type: RW Default: See Register map Trigger: N/A D7 MSK_TSD D6 D5 D4 D3 D2 D1 D0 MSK_TWARN MSK_TPREW Spare = 1 MSK_ISHORT MSK_UVLO MSK_IDCDC MASK_PG Bit Bit Description MSK_PG Power Good interrupt source mask 0: Interrupt is Enabled 1: Interrupt is Masked MSK_IDCDC DCDC over current interrupt source mask 0: Interrupt is Enabled 1: Interrupt is Masked MSK_UVLO Under Voltage interrupt source mask 0: Interrupt is Enabled 1: Interrupt is Masked MSK_ISHORT DCDC Short-Circuit Protection source mask 0: Interrupt is Enabled 1: Interrupt is Masked MSK_TPREW Thermal Pre Warning interrupt source mask 0: Interrupt is Enabled 1: Interrupt is Masked MSK_TWARN Thermal Warning interrupt source mask 0: Interrupt is Enabled 1: Interrupt is Masked MSK_TSD Thermal Shutdown interrupt source mask 0: Interrupt is Enabled 1: Interrupt is Masked Table 16. PRODUCT ID REGISTER Name: PID Address: 03h Type: R Default: 00011011b (20h) Trigger: N/A Reset on N/A D7 D6 D5 D4 D3 D2 D1 D0 PID_7 PID_6 PID_5 PID_4 PID_3 PID_2 PID_1 PID_0 Table 17. REVISION ID REGISTER Name: RID Address: 04h Type: R Default: Metal Trigger: N/A D7 D6 D5 D4 D3 D2 D1 D0 RID_7 RID_6 RID_5 RID_4 RID_3 RID_2 RID_1 RID_0 Bit RID[7..0] Bit Description Revision Identification 00000000: First Silicon 00000001: Final Silicon www.onsemi.com 25 NCV6356 Table 18. FEATURE ID REGISTER Name: FID Address: 05h Type: R Default: See Register map Trigger: N/A D7 D6 D5 D4 D3 D2 D1 D0 Spare Spare Spare Spare FID_3 FID_2 FID_1 FID_0 D1 D0 Bit FID[3..0] Bit Description Feature Identification 00000000: NCV6356C 5.0 A, 1.15 V configuration 00000001: NCV6356B 5.0 A, 1.20 V configuration 00000010: NCV6356Q 6.8 A, 0.875 V - 0.906 V configuration Table 19. DC TO DC VOLTAGE PROG (VSEL = 1) REGISTER Name: PROGVSEL1 Address: 10h Type: RW Default: See Register map Trigger: N/A D7 D6 D5 D4 D3 ENVSEL1 Bit VoutVSEL1[6..0] ENVSEL1 D2 VoutVSEL1[6..0] Bit Description Sets the DC to DC converter output voltage when VSEL pin = 1 and VSEL pin function is enabled in register COMMAND.D0, or when VSEL pin function is disabled in register COMMAND.D0 0000000b = 600 mV - 1111111b = 1393.75 mV (steps of 6.25 mV) EN Pin Gating for VSEL internal signal = High 0: Disabled 1: Enabled Table 20. DC TO DC VOLTAGE PROG (VSEL = 0) REGISTER Name: PROGVSEL0 Address: 11h Type: RW Default: See Register map Trigger: N/A D7 D6 D5 D4 D3 ENVSEL0 D2 D1 D0 VoutVSEL0[6..0] Bit Bit Description VoutVSEL0[6..0] Sets the DC to DC converter output voltage when VSEL pin = 0 and VSEL pin function is enabled in register COMMAND.D0 0000000b = 600 mV - 1111111b = 1393.75 mV (steps of 6.25 mV) ENVSEL0 EN Pin Gating for VSEL internal signal = Low 0: Disabled 1: Enabled www.onsemi.com 26 NCV6356 Table 21. POWER GOOD REGISTER Name: PGOOD Address: 12h Type: RW Default: See Register map Trigger: N/A D7 D6 D5 D4 Spare = 0 Spare = 0 Spare = 0 DISCHG Bit D3 D2 D1 D0 Spare = 0 Spare = 0 PGDVS PGDCDC Bit Description PGDCDC Power Good Enabling 0 = Disabled 1 = Enabled PGDVS Power Good Active On DVS 0 = Disabled 1 = Enabled DISCHG Active discharge bit Enabling 0 = Discharge path disabled 1 = Discharge path enabled Table 22. TIMING REGISTER Name: TIME Address: 13h Type: RW Default: See Register map Trigger: N/A D7 D6 D5 D4 DELAY[2..0] D3 DVS[1..0] Bit Spare = 0 Bit Description DBN_Time[1..0] EN and VSEL debounce time 00 = No debounce 01 = 1-2 us 10 = 2-3 us 11 = 3-4 us DVS[1..0] DVS Speed 00 = 6.25 mV step / 0.333 us 01 = 6.25 mV step / 0.666 us 10 = 6.25 mV step / 1.333 us 11 = 6.25 mV step / 2.666 us DELAY[2..0] D2 Delay applied upon enabling (ms) 000b = 0 ms - 111b = 14 ms (Steps of 2 ms) www.onsemi.com 27 D1 D0 DBN_Time[1..0] NCV6356 Table 23. COMMAND REGISTER Name: COMMAND Address: 14h Type: RW Default: See Register map Trigger: N/A D7 PPWMVSEL0 D6 D5 D4 D3 D2 D1 D0 PPWMVSEL1 DVSMODE Sleep_Mode Spare = 0 Spare = 0 Spare VSELGT Bit Bit Description VSELGT VSEL Pin Gating 0 = Disabled 1 = Enabled Sleep_Mode Sleep mode 0 = Low Iq mode when EN and VSEL low 1 = Force product in sleep mode (when EN and VSEL are low) DVSMODE DVS transition mode selection 0 = Auto 1 = Forced PPWM PPWMVSEL1 Operating mode for MODE internal signal = High 0 = Auto 1 = Forced PPWM PPWMVSEL0 Operating mode for MODE internal signal = Low 0 = Auto 1 = Forced PPWM Table 24. LIMITS CONFIGURATION REGISTER Name: LIMCONF Address: 16h Type: RW Default: See Register map Trigger: N/A D7 D6 IPEAK[1..0] D5 D4 TPWTH[1..0] D3 D2 D1 D0 Spare = 0 FORCERST RSTSTATUS REARM Bit Bit Description REARM Rearming of device after TSD / ISHORT 0: No re-arming after TSD / ISHORT 1: Re-arming active after TSD / ISHORT with no reset of I2C registers: new power-up sequence is initiated with previously programmed I2C registers values RSTSTATUS Reset Indicator Bit 0: Must be written to 0 after register reset 1: Default (loaded after Registers reset) FORCERST Force Reset Bit 0 = Default value. Self cleared to 0 1: Force reset of internal registers to default TPWTH[1..0] Thermal pre-Warning threshold settings 00 = 83C 01 = 94C 10 = 105C 11 = 116C IPEAK Inductor peak current settings 00 = 5.2 A (for 3.5 A output current) 01 = 5.8 A (for 4.0 A output current) 10 = 6.2 A (for 4.5 A output current) 11 = 6.8 A (for 5.0 A output current) www.onsemi.com 28 NCV6356 APPLICATION INFORMATION Supply Input 4.7 uF NCV6356 AVIN PVIN Core AGND Supply Input 10 uF Thermal Protection Enable Control Input Voltage Selection DCDC 5A EN Operating Mode Control VSEL SW 330 nH Modular Driver 2x 22uF Interrupt Output Monitoring PGND INTB SDA PGND I@C Processor I@C Control Interface SCL FB DCDC 2.4 MHz Controller Processor Core Sense Figure 53. Typical Application Schematic Output Filter Considerations the FB pin to the system decoupling capacitor positive terminal. The output filter introduces a double pole in the system at a frequency of: f LC = Components Selection 1 Inductor Selection The inductance of the inductor is chosen such that the peak-to-peak ripple current IL_PP is approximately 20% to 50% of the maximum output current IOUT_MAX. This provides the best trade-off between transient response and output ripple. The inductance corresponding to a given current ripple is: 2 p L C The NCV6356 internal compensation network is optimized for a typical output filter comprising a 330 nH inductor and 47 uF capacitor as describes in the basic application schematic in Figure 53. Voltage Sensing Considerations In order to regulate the power supply rail, the NCV6356 must sense its output voltage. The IC can support two sensing methods: * Normal sensing: The FB pin should be connected to the output capacitor positive terminal (voltage to regulate). * Remote sensing: The power supply rail sense should be made close to the system powered by the NCV6356. The voltage to the system is more accurate, since the PCB line impedance voltage drop is within the regulation loop. In this case, we recommend connecting L= (V IN - V OUT ) V OUT V IN f SW I L _ PP The selected inductor must have a saturation current rating higher than the maximum peak current which is calculated by: I L _ MAX = I OUT _ MAX + I L _ PP 2 The inductor must also have a high enough current rating to avoid self-heating. A low DCR is therefore preferred. Refer to Table 25 for recommended inductors. Table 25. INDUCTOR SELECTION Supplier Part # Value (uH) Size (L x l x T) (mm) Saturation Current Max (A) DCR Max at 255C (mW) Cyntec PIFE20161B-R33MS-11 0.33 2.0 x 1.6 x 1.2 4.0 33 Cyntec PIFE25201B-R33MS-11 0.33 2.5 x 2.0 x 1.2 5.2 17 Cyntec PIFE32251B-R33MS-11 0.33 3.2 x 2.5 x 1.2 6.5 14 www.onsemi.com 29 NCV6356 Table 25. INDUCTOR SELECTION Part # Value (uH) Size (L x l x T) (mm) Saturation Current Max (A) DCR Max at 255C (mW) TOKO DFE252012F-H-R33M 0.33 2.5 x 2.0 x 1.2 5.1 13 TOKO DFE201612E-H-R33M 0.33 2.0 x 1.6 x 1.2 4.8 21 TOKO FDSD0412-H-R33M 0.33 4.2 x 4.2 x 1.2 7.5 19 TDK VLS252012HBX-R33M 0.33 2.5 x 2.0 x 1.2 5.3 25 TDK SPM5030T-R35M 0.35 7.1 x 6.5 x 3.0 14.9 4 Chilisin HEI201612A-R24M-AUDG 0.24 2.0 x 1.6 x 1.2 4.8 13.5 Supplier The minimum input capacitance with respect to the input ripple voltage VIN_PP is Output Capacitor Selection The output capacitor selection is determined by output voltage ripple and load transient response requirement. For high transient load performance a high output capacitor value must be used. For a given peak-to-peak ripple current IL_PP in the inductor of the output filter, the output voltage ripple across the output capacitor is the sum of three components as shown below. C IN _ MIN = I L _ PP 8 C f SW VOUT _ PP(ESR) = I L _ PP ESR ) = L ESL V IN L (V IN - VOUT ) VOUT V IN f SW L T PT = VOUT I OUT _ PP 1 - 1 h where h is the efficiency and PL 2 the simplified inductor power losses PL = I LOAD DCR . Now the junction temperature TJ can easily be calculated as TJ = R q JA PIC + T A I L _ PP 8 V OUT VOUT V IN The NCV6356's power capability is driven by the difference in temperature between the junction (TJ) and ambient (TA), the junction-to-ambient thermal resistance (RqJA), and the on-chip power dissipation (PIC). The on-chip power dissipation PIC can be determined as PIC = PT - PL with the total power losses P being In applications with all ceramic output capacitors, the main ripple component of the output ripple is VOUT_PP(C). The minimum output capacitance can be calculated based on a given output ripple requirement VOUT_PP in PPWM operation mode. C MIN = V IN _ PP f SW D= Power Capability Where the peak-to-peak ripple current is given by I L _ PP = ) The input capacitor also must be sufficient to protect the device from over voltage spikes, and a 4.7 uF capacitor or greater is required. The input capacitor should be located as close as possible to the IC. All PGND pins must be connected together to the ground terminal of the input cap which then must be connected to the ground plane. All PVIN pins must be connected together to the Vbat terminal of the input cap which then connects to the Vbat plane. With: _ PP (ESL ( D - D2 I IN _ RMS = IOUT_ MAX D - D2 , V OUT _ MAX Where In addition, the input capacitor must be able to absorb the input current, which has a RMS value of VOUT_ PP [VOUT_ PP(C ) + VOUT_ PP(ESR) + VOUT_ PP(ESL) V OUT _ PP (C ) = I OUT f SW Please note that the TJ should stay within the recommended operating conditions. The RqJA is a function of the PCB layout (number of layers and copper and PCB size). For example, the NCV6356 mounted on the EVB has a RqJA about 30C/W. Input Capacitor Selection One of the input capacitor selection requirements is the input voltage ripple. To minimize the input voltage ripple and get better decoupling at the input power supply rail, a ceramic capacitor is recommended due to low ESR and ESL. www.onsemi.com 30 NCV6356 * AGND directly connected to the GND plane. * PGND directly connected to Cin input capacitor, and Layout Considerations Electrical Rules Good electrical layout is key to proper operation, high efficiency, and noise reduction. Electrical layout guidelines are: * Use wide and short traces for power paths (such as PVIN, VOUT, SW, and PGND) to reduce parasitic inductance and high-frequency loop area. It is also good for efficiency improvement. * The device should be well decoupled by input capacitor and the input loop area should be as small as possible to reduce parasitic inductance, input voltage spike, and noise emission. * SW track should be wide and short to reduce losses and noise radiation. * It is recommended to have separated ground planes for PGND and AGND and connect the two planes at one point. Try to avoid overlap of input ground loop and output ground loop to prevent noise impact on output regulation. * Arrange a "quiet" path for output voltage sense, and make it surrounded by a ground plane. then connected to the GND plane: Local mini planes used on the top layer (green) and the layer just below the top layer (yellow) with laser vias. Thermal Rules Good PCB layout improves the thermal performance and thus allows for high power dissipation even with a small IC package. Thermal layout guidelines are: * A four or more layers PCB board with solid ground planes is preferred for better heat dissipation. * Use multiple vias around the IC to connect the inner ground layers to reduce thermal impedance. * Use a large and thick copper area especially in the top layer for good thermal conduction and radiation. * Use two layers or more for the high current paths (PVIN, PGND, SW) in order to split current into different paths and limit PCB copper self-heating. Figure 54. Placement Recommendation Component Placement * Input capacitor placed as close as possible to the IC. * PVIN directly connected to Cin input capacitor, and then connected to the Vin plane. Local mini planes used on the top layer (green) and the layer just below the top layer (yellow) with laser vias. * AVIN connected to the Vin plane just after the capacitor. Figure 55. Demo Board Example (INTB not used) www.onsemi.com 31 NCV6356 Table 26. ORDERING INFORMATION OPN Marking Configuration Package Shipping NCV6356CMTWTXG 6356C 5.0 A 1.150 V / 1.150 V DFN 3.0 x 4.0 mm (Pb-Free) 3,000 Tape & Reel NCV6356BMTWTXG 6356B 5.0 A 1.200 V / 1.200 V DFN 3.0 x 4.0 mm (Pb-Free) 3,000 Tape & Reel NCV6356QMTWTXG 6356Q 5.0 A 0.875 V / 0.906 V DFN 3.0 x 4.0 mm (Pb-Free) 3,000 Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Demo board available: * The NCV6356GEVB/D evaluation board that configures the device in typical application to supply constant voltage. www.onsemi.com 32 NCV6356 PACKAGE DIMENSIONS WDFNW14 4x3, 0.5P CASE 511CM ISSUE O A B D PIN ONE REFERENCE CCCC CCCC CCCC L L3 0.05 C DETAIL B A4 A C NOTE 4 A3 DETAIL A D2 1 EEE CCC CCC 14X 7 PLATING A4 EE CC CC SEATING PLANE A4 PLATED SURFACES L EXPOSED COPPER ALTERNATE CONSTRUCTION DETAIL B C A1 SIDE VIEW L3 DETAIL A EXPOSED COPPER C L ALTERNATE CONSTRUCTION E TOP VIEW 0.10 C NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMESNION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. THIS DEVICE CONTAINS WETTABLE FLANK DESIGN FEATURES TO AID IN FILLET FORMATION ON THE LEADS DURING MOUNTING. L3 DIM A A1 A3 A4 b D D2 E E2 e K L L3 SECTION C-C RECOMMENDED SOLDERING FOOTPRINT* E2 3.20 K 14 e BOTTOM VIEW 8 MILLIMETERS MIN NOM MAX 0.80 0.70 0.75 0.00 0.03 0.05 0.20 REF 0.10 REF 0.20 0.25 0.30 3.90 4.00 4.10 2.90 3.00 3.10 2.90 3.00 3.10 1.60 1.70 1.80 0.50 BSC 0.25 --- --- 0.30 0.40 0.50 0.00 0.05 0.10 14X 14X 0.75 b 0.07 M C A B 0.05 M C NOTE 3 1.85 0.50 PITCH 3.60 14X 0.33 DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. 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