Microprocessor
Supervisory Circuits
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
Rev. B
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FEATURES
Upgrade for ADM690 to ADM695, MAX690 to MAX695
Specified over temperature
Low power consumption (0.7 mW)
Precision voltage monitor
Reset assertion down to 1 V VCC
Low switch on resistance 0.7 Ω normal, 7 Ω in backup
High current drive (100 mA)
Watchdog timer: 100 ms, 1.6 s, or adjustable
400 nA standby current
Automatic battery backup power switching
Extremely fast gating of chip enable signals (3 ns)
Voltage monitor for power fail
Available in TSSOP package
APPLICATIONS
Microprocessor systems
Computers
Controllers
Intelligent instruments
Automotive systems
PRODUCT HIGHLIGHTS
The ADM8690 and ADM8692 are available in 8-lead, PDIP
packages and provide:
1. Power-on reset output during power-up, power-down, and
brownout conditions. The RESET output remains
operational with VCC as low as 1 V.
2. Battery backup switching for CMOS RAM, CMOS
microprocessor, or other low power logic.
3. A reset pulse if the optional watchdog timer has not been
toggled within a specified time.
4. A 1.3 V threshold detector for power-fail warning, low battery
detection, or to monitor a power supply other than 5 V.
The ADM8691, ADM8693, and ADM8695 are available in 16-lead
PDIP and small outline packages (including TSSOP) and
provide three additional functions:
1. Write protection of CMOS RAM or EEPROM.
2. Adjustable reset and watchdog timeout periods.
3. Separate watchdog timeout, backup battery switchover, and
low VCC status outputs.
FUNCTIONAL BLOCK DIAGRAMS
RESET
1.3V
RESET
GENERATOR
2
WATCHDOG
TRANSITION DETECTOR
(1.6s)
4.65V
1
ADM8690/
ADM8692
WATCHDOG
INPUT (WDI )
POWER FAIL
INPUT (PFI)
V
CC
V
BATT
V
OUT
POWER FAIL
OUTPUT (PFO)
1
VOLT AGE DE TECT OR = 4.65V ( ADM 8690)
4.40V ( ADM 8692)
2
RESET PULSE WIDTH = 50ms ( AD8690, ADM8692)
00093-001
Figure 1. ADM8690/ADM8692
1.3V
LOW LINE
RESET
RESET
OSC IN
OSC SEL
BATT ON
ADM8691/
ADM8693/
ADM8695
4.65V
1
RESET AND
WATCHDOG
TIME BASE
RESET
GENERATOR
WATCHDOG
TRANSITION DETECTOR WATCHDOG
TIMER
POWER FAIL
INPUT (PFI)
WATCHDOG
INPUT (WDI )
CE
IN
V
CC
V
BATT
V
OUT
POWER FAIL
OUTPUT (PFO)
WATCHDOG
OUTPUT (WDO)
CE
OUT
1
VOLT AGE DE TECT OR = 4.65V ( ADM 8691, ADM8695)
00093-002
4.40V ( ADM 8693)
Figure 2. ADM8691/ADM8693/ADM8695
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
Rev. B | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Product Highlights ........................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications ..................................................................................... 4
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Circuit Information ........................................................................ 10
Battery Switchover Section ........................................................ 10
Power-Fail RESET Output ......................................................... 10
Watchdog Timer RESET ............................................................ 11
Watchdog Output (WDO) ........................................................ 12
CE Gating and RAM Write Protection
(ADM8691/ADM8693/ADM8695) ......................................... 12
Power-Fail Warning Comparator ............................................. 13
Application Information ................................................................ 14
Increasing the Drive Current .................................................... 14
Using a Rechargeable Battery for Backup ............................... 14
Adding Hysteresis to the Power-Fail Comparator ................. 14
Monitoring the Status of the Battery ....................................... 14
Alternate Watchdog Input Drive Circuits ............................... 15
Typical Applications ....................................................................... 16
ADM8690 and ADM8692 ......................................................... 16
ADM8691, ADM8693, and ADM8695 ................................... 16
RESET Output ............................................................................ 16
Power-Fail Detector ................................................................... 17
RAM Write Protection............................................................... 17
Watchdog Timer ......................................................................... 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 19
REVISION HISTORY
6/11—Rev. A to Rev. B
Deleted ADM8694 ......................................................... Throughout
Updated Figure 11, Figure 12, and Figure 13 ................................ 9
Updated Outline Dimensions ....................................................... 18
9/06—Rev. 0 to Rev. A
Updated Format .................................................................. Universal
Changes to Absolute Maximum Ratings ....................................... 6
Updated Ordering Guide ............................................................... 20
2/97—Revision 0: Initial Version
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
Rev. B | Page 3 of 20
GENERAL DESCRIPTION
The ADM869x family of supervisory circuits offers complete
single- chip solutions for power supply monitoring and battery
control functions in microprocessor systems. These functions
include microprocessor reset, backup battery switchover,
watchdog timer, CMOS RAM write protection, and power
failure warning. The complete family provides a variety of
configurations to satisfy most microprocessor system
requirements.
The ADM869x family is fabricated using an advanced epitaxial
CMOS process combining low power consumption (0.7 mW),
extremely fast chip enable gating (3 ns), and high reliability.
RESET assertion is guaranteed with VCC as low as 1 V. In
addition, the power switching circuitry is designed for minimal
voltage drop thereby permitting increased output current drive
of up to 100 mA without the need of an external pass transistor.
See Table 1 for a product selection guide listing the characteristics
of each device in the ADM869x family. To place an order, use
the Ordering Guide provided as the last section of this data sheet.
Table 1. Product Selection Guide
Part
Number
Nominal
Reset Time
Nominal VCC Reset
Threshold
Nominal Watchdog
Timeout Period
Battery Backup
Switching
Base Drive
Ext PNP
Chip Enable
Signals
ADM8690 50 ms 4.65 V 1.6 s Yes No No
ADM8691 50 ms or ADJ 4.65 V 100 ms, 1.6 s, ADJ Yes Yes Yes
ADM8692 50 ms 4.4 V 1.6 s Yes No No
ADM8693 50 ms or ADJ 4.4 V 100 ms, 1.6 s, ADJ Yes Yes Yes
ADM8695 200 ms or ADJ 4.65 V 100 ms, 1.6 s, ADJ Yes Yes Yes
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
Rev. B | Page 4 of 20
SPECIFICATIONS
VCC = full operating range, VBATT = 2.8 V, TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
BATTERY BACKUP SWITCHING
VCC Operating Voltage Range
ADM8690, ADM8691, ADM8695 4.75 5.5 V
ADM8692, ADM8693 4.5 5.5 V
VB AT T Operating Voltage Range
ADM8690, ADM8691, ADM8695 2.0 4.25 V
ADM8692, ADM8693 2.0 4.0 V
VOUT Output Voltage VCC − 0.005 VCC − 0.0025 V IOUT = 1 mA
VCC − 0.2 VCC − 0.125 V IOUT ≤ 100 mA
VOUT in Battery Backup Mode VB AT T − 0.005 VB AT T − 0.002 V IOUT = 250 µA, VCC < VBAT T − 0.2 V
Supply Current (Excludes IOUT) 140 200 µA IOUT = 100 µA
Supply Current in Battery Backup Mode 0.4 1 µA VCC = 0 V, VB AT T = 2.8 V
Battery Standby Current 5.5 V > VCC > VB AT T + 0.2 V
+ = Discharge, − = Charge −0.1 +0.02 µA TA = 25°C
Battery Switchover Threshold 70 mV Power-up
VCC – VB AT T 50 mV Power-down
Battery Switchover Hysteresis 20 mV
BATT ON Output Voltage 0.3 V ISINK = 3.2 mA
BATT ON Output Short-Circuit Current 55 mA BATT ON = VOUT = 4.5 V sink current
0.5 2.5 25 µA BATT ON = 0 V source current
RESET AND WATCHDOG TIMER
Reset Voltage Threshold
ADM8690, ADM8691, ADM8695 4.5 4.65 4.73 V
ADM8692, ADM8693 4.25 4.4 4.48 V
Reset Threshold Hysteresis 40 mV
Reset Timeout Delay
ADM8690, ADM8691, ADM8692,
ADM8693,
35 50 70 ms OSC SEL = high
ADM8695 140 200 280 ms OSC SEL = high
Watchdog Timeout Period, Internal Oscillator 1.0 1.6 2.25 s Long period
70 100 140 ms Short period
Watchdog Timeout Period, External Clock 3840 4064 4097 cycles Long period
768 1011 1025 cycles Short period
Minimum WDI Input Pulse Width 50 ns VIL = 0.4, VIH = 3.5 V
RESET Output Voltage @ VCC = 1 V 4 20 mV ISINK = 10 µA, VCC = 1 V
RESET, LOW LINE Output Voltage 0.05 0.4 V ISINK = 1.6 mA, VCC = 4.25 V
3.5 V ISOURCE = 1 µA
RESET, WDO Output Voltage 0.4 V ISINK = 1.6 mA
3.5 V ISOURCE = 1 µA
Output Short-Circuit Source Current 1 10 25 µA
Output Short-Circuit Sink Current 25 mA
WDI Input Threshold1
Logic Low 0.8 V
Logic High 3.5 V
WDI Input Current 1 10 µA WDI = VOUT
−10 −1 µA WDI = 0 V
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
Rev. B | Page 5 of 20
Parameter Min Typ Max Unit Test Conditions/Comments
POWER-FAIL DETECTOR
PFI Input Threshold 1.25 1.3 1.35 V VCC = 5 V
PFI Input Current −25 ±0.01 +25 nA
PFO Output Voltage 0.4 V ISINK = 3.2 mA
3.5 V ISOURCE = 1 µA
PFO Short-Circuit Source Current 1 3 25 A PFI = low, PFO = 0 V
PFO Short-Circuit Sink Current 25 mA PFI = high, PFO = VOUT
CHIP ENABLE GATING
CEIN Threshold 0.8 V VIL
3.0 V VIH
CEIN Pull-Up Current 3 µA
CEOUT Output Voltage 0.4 V ISINK = 3.2 mA
V
OUT − 1.5 V ISOURCE = 3.0 mA
V
OUT − 0.05 V ISOURCE = 1 µA, VCC = 0 V
CE Propagation Delay 3 7 ns
OSCILLATOR
OSC IN Input Current ±2 µA
OSC SEL Input Pull-Up Current 5 µA
OSC IN Frequency Range 0 500 kHz OSC SEL = 0 V
OSC IN Frequency with External Capacitor 4 kHz OSC SEL = 0 V, COSC = 47 pF
1 WDI is a three-level input that is internally biased to 38% of VCC and has an input impedance of approximately 5 MΩ.
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
Rev. B | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
VCC −0.3 V to +6 V
VB AT T −0.3 V to +6 V
All Other Inputs −0.3 V to VOUT + 0.5 V
Input Current
VCC 200 mA
V
B AT T
50 mA
GND 20 mA
Digital Output Current 20 mA
Power Dissipation, N-8 PDIP 400 mW
θJA Thermal Impedance 120°C/W
Power Dissipation, R-8 SOIC 400 mW
θJA Thermal Impedance 120°C/W
Power Dissipation, N-16 PDIP 600 mW
θJA Thermal Impedance 135°C/W
Power Dissipation, RU-16 TSSOP 600 mW
θJA Thermal Impedance 158°C/W
Power Dissipation, R-16 SOIC_N 600 mW
θJA Thermal Impedance 110°C/W
Power Dissipation, RW-16 SOIC_W 600 mW
θJA Thermal Impedance 73°C/W
Operating Temperature Range
Industrial (A Version) −40°C to +85°C
Lead Temperature (Soldering, 10 sec) 300°C
Storage Temperature Range −65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
Rev. B | Page 7 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
8
7
6
5PFO
WDI
RESET
GND
PFI
ADM8690/
ADM8692
TOP VIEW
(Not t o Scale)
V
OUT
V
CC
V
BATT
00093-003
Figure 3. ADM8690 and ADM8692,
Pin Configuration
14
13
12
11
16
15
10
9
8
1
2
3
4
7
6
5
WDO
RESET
RESET
GND
PFO
WDI
BATT ON
LOW LINE
OSC IN
OSC SEL PFI
ADM8691/
ADM8693/
ADM8695
TOP VI EW
(No t t o Scal e)
VBATT
VOUT
VCC
CEIN
CEOUT
00093-004
Figure 4. ADM8691, ADM8693, and ADM8695
Pin Configuration
Table 4. Pin Function Descriptions
Mnemonic Function
V
CC
Power Supply Input. 5 V nominal.
VB AT T Backup Battery Input.
VOUT Output Voltage. VCC or VBAT T is internally switched to VOUT, depending on which is at the highest potential. VOUT can supply up to
100 mA to power CMOS RAM. Connect VOUT to VCC if VOUT and VB AT T are not used.
GND Ground. This is the 0 V ground reference for all signals.
RESET Logic Output. RESET goes low if VCC falls below the reset threshold, or the watchdog timer is not serviced within its timeout
period. The reset threshold is typically 4.65 V for the ADM8690/ADM8691/ADM8695 and 4.4 V for the ADM8692 and
ADM8693. RESET remains low for 50 ms (ADM8690/ADM8691/ADM8692/ADM8693) or 200 ms (ADM8695) after VCC returns
above the threshold. RESET also goes low for 50 ms (ADM8690/ADM8691/ADM8692/ADM8693) or 200 ms (ADM8695) if the
watchdog timer is enabled but not serviced within its timeout period. The RESET pulse width can be adjusted on the
ADM8691/ADM8693/ADM8695, as shown in Table 5. The RESET output has an internal 3 µA pull-up, and can either connect to
an open collector reset bus or directly drive a CMOS gate without an external pull-up resistor.
WDI Watchdog Input. WDI is a three-level input. If WDI remains either high or low for longer than the watchdog timeout period,
RESET pulses low and WDO goes low. The timer resets with each transition on the WDI line. The watchdog timer can be
disabled if WDI is left floating or is driven to midsupply.
PFI Power-Fail Input. PFI is the noninverting input to the power-fail comparator. When PFI is less than 1.3 V, PFO goes low.
Connect PFI to GND or VOUT when not used.
PFO Power-Fail Output. PFO is the output of the power-fail comparator. It goes low when PFI is less than 1.3 V. The comparator is
turned off and PFO goes low when VCC is below VBAT T .
CEIN Logic Input. The input to the CE gating circuit. When not in use, connect this pin to GND or VOUT.
CEOUT Logic Output. CEOUT is a gated version of the CEIN signal. CEOUT tracks CEIN when VCC is above the reset threshold. If VCC is below
the reset threshold, CEOUT is forced high. See Figure 21 and Figure 22.
BAT T ON Logic Output. BATT ON goes high when VOUT is internally switched to the VBAT T input. It goes low when VOUT is internally
switched to VCC. The output typically sinks 35 mA and can directly drive the base of an external PNP transistor to increase the
output current above the 100 mA rating of VOUT.
LOW LINE Logic Output. LOW LINE goes low when VCC falls below the reset threshold. It returns high as soon as VCC rises above the reset
threshold.
RESET Logic Output. RESET is an active high output. It is the inverse of RESET.
OSC SEL Logic Oscillator Select Input. When OSC SEL is unconnected (floating) or driven high, the internal oscillator sets the reset
active time and watchdog timeout period. When OSC SEL is low, the external oscillator input, OSC IN, is enabled. OSC SEL has
a 3 µA internal pull-up (see Table 5).
OSC IN Oscillator Logic Input. With OSC SEL low, OSC IN can be driven by an external clock signal or an external capacitor can be
connected between OSC IN and GND. This sets both the reset active pulse timing and the watchdog timeout period (see
Table 5 and Figure 17, Figure 18, Figure 19, and Figure 20). With OSC SEL high or floating, the internal oscillator is enabled and
the reset active time is fixed at 50 ms typical (ADM8691/ADM8693) or 200 ms typical (ADM8695). In this mode, the OSC IN pin
selects between fast (100 ms) and slow (1.6 s) watchdog timeout periods. In both modes, the timeout period immediately
after a reset is 1.6 s typical.
WDO Logic Output. The watchdog output, WDO, goes low if WDI remains either high or low for longer than the watchdog timeout
period. WDO is set high by the next transition at WDI. If WDI is unconnected or at midsupply, the watchdog timer is disabled
and WDO remains high. WDO also goes high when LOW LINE goes low.
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
Rev. B | Page 8 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
5.00
4.94
4.99
4.98
4.97
4.96
4.95
VOUT (V)
I
OUT
(mA)
10 20 30 40 50 60 70 80 90 100
00093-015
Figure 5. VOUT vs. IOUT Normal Operation
2.800
2.786
2.798
2.794
2.792
2.790
2.788
2.796
V
OUT
(V)
I
OUT
(µA)
150 250 350 450 550 650 750 850 950 1050
00093-016
Figure 6. VOUT vs. IOUT Battery Backup
10
90
100
0%
A4 3.36V
1V 1V 500ms
00093-017
Figure 7. Reset Output Voltage vs. Supply Voltage
TEMPERATURE (°C)
1.315
1.295
1.280
1.290
1.285
1.310
1.305
1.300
PFI INPUT THRESHOLD (V)
–60 –30 030 60 90 120
00093-018
Figure 8. PFI Input Threshold vs. Temperature
TEMPERATURE (°C)
53
52
49
51
50
RESET ACTIVE TIME (ms)
V
CC
= 5V
ADM8690/
ADM8691/
ADM8692/
ADM8693
20 40 60 80 100 120
00093-019
Figure 9. Reset Active Time vs. Temperature
4.69
4.67
4.55
4.65
4.63
RESET VOLT AGE T HRESHOLD (V)
4.61
4.59
4.57
TEMPERATURE (°C)
V
CC
= 5V
–60 –30 030 60 90 120
00093-020
Figure 10. Reset Voltage Threshold vs. Temperature
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
Rev. B | Page 9 of 20
TIME (µs)
6
5
0
1.35
1.25
2
1
4
3
V
CC
= 5V
T
A
= 25° C
PFO
V
PFI
1.3V 30pF
00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
00093-021
PFI
PFO
Figure 11. Power-Fail Comparator Response Time Falling
TIME (µs)
6
5
0
1.35
1.25
2
1
4
3
010 20 30 40 50 60 70 80
PFO
PFI
PFO
V
PFI
1.3V 30pF
V
CC
= 5V
T
A
= 25° C
90
00093-022
Figure 12. Power-Fail Comparator Response Time Rising
TIME (µs)
6
5
0
1.35
1.25
2
1
4
3
00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
PFO
5V
V
PFI
1.3V
10kΩ
30pF
V
CC
= 5V
T
A
= 25° C
00093-023
PFI
PFO
Figure 13. Power-Fail Comparator Response Time with Pull-Up Resistor
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
Rev. B | Page 10 of 20
CIRCUIT INFORMATION
BATTERY SWITCHOVER SECTION
The battery switchover circuit compares VCC to the VBATT input,
and connects VOUT to whichever is higher. Switchover occurs
when VCC is 50 mV higher than VBATT as VCC falls, and when VCC
is 70 mV greater than VBATT as VCC rises. This 20 mV of
hysteresis prevents repeated rapid switching if VCC falls very
slowly or remains nearly equal to the battery voltage.
GATE DRIV E
V
CC
V
BATT
V
OUT
BATT ON
(ADM8690,
ADM8695)
100
mV
700
mV
INTERNAL
SHUTDO WN SIGNAL
WHEN
V
BATT
> (V
CC
+ 0. 7V)
0
0093-005
Figure 14. Battery Switchover Schematic
During normal operation, with VCC higher than VBATT, VCC
is internally switched to VOUT through an internal PMOS tran-
sistor switch. This switch has a typical on resistance of 0.7 Ω
and can supply up to 100 mA at the VOUT terminal. VOUT is
normally used to drive a RAM memory bank, requiring
instantaneous currents of greater than 100 mA. If this is the
case, a bypass capacitor should be connected to VOUT. The
capacitor provides the peak current transients to the RAM.
A capacitance value of 0.1 μF or greater can be used.
If the continuous output current requirement at VOUT exceeds
100 mA, or if a lower VCC − VOUT voltage differential is desired,
an external PNP pass transistor can be connected in parallel
with the internal transistor. The BATT ON output (ADM8691/
ADM8693/ADM8695) can directly drive the base of the
external transistor.
A 7 Ω MOSFET switch connects the VBATT input to VOUT during
battery backup. This MOSFET has very low input-to-output
differential (dropout voltage) at the low current levels required
for battery back up of CMOS RAM or other low power CMOS
circuitry. The supply current in battery back up is typically 0.4 μA.
The ADM8690/ADM8691/ADM8695 operate with battery
voltages from 2.0 V to 4.25 V, and the ADM8692/
ADM8693 operate with battery voltages from 2.0 V to 4.0 V.
High value capacitors, either standard electrolytic or the farad-
size, double-layer capacitors, can also be used for short-term
memory backup. A small charging current of typically 10 nA
(0.1 μA maximum) flows out of the VBATT terminal. This current
is useful for maintaining rechargeable batteries in a fully
charged condition. This extends the life of the backup battery by
compensating for its self-discharge current. Also note that this
current poses no problem when lithium batteries are used for
backup because the maximum charging current (0.1 μA) is safe
for even the smallest lithium cells.
If the battery switchover section is not used, VBATT should be
connected to GND and VOUT should be connected to VCC.
POWER-FAIL RESET OUTPUT
RESET is an active low output that provides a RESET signal to
the microprocessor whenever VCC is at an invalid level. When
VCC falls below the reset threshold, the RESET output is forced
low. The nominal reset voltage threshold is 4.65 V (ADM8690/
ADM8691/ADM8695) or 4.4 V (ADM8692/ADM8693).
RESET
LOW LINE
V1
V2V2 V1
V
CC
t
1
t
1
t1 = RESET T I ME
V1 = RESE T VO LT AGE T HRE SHO LD LOW
V2 = RESE T VO LT AGE T HRE SHO LD HI GH
HYSTERESIS = V2–V1
00093-006
Figure 15. Power-Fail Reset Timing
On power-up, RESET remains low for 50 ms (200 ms for
ADM8695) after VCC rises above the appropriate reset threshold.
This allows time for the power supply and microprocessor to
stabilize. On power-down, the RESET output remains low with
VCC as low as 1 V. This ensures that the microprocessor is held
in a stable shutdown condition.
This RESET active time is adjustable on the ADM8691/ADM8693/
ADM8695 by using an external oscillator or by connecting an
external capacitor to the OSC IN pin. Refer to Table 5 and
Figure 17, Figure 18, Figure 19, and Figure 20.
The guaranteed minimum and maximum thresholds of the
ADM8690/ADM8691/ADM8695 are 4.5 V and 4.73 V, and the
guaranteed thresholds of the ADM8692/ADM8693 are 4.25 V and
4.48 V. The ADM8690/ADM8691/ADM8695 are, therefore,
compatible with 5 V supplies with a +10%, −5% tolerance and
the ADM8692/ADM8693 are compatible with 5 V ± 10%
supplies. The reset threshold comparator has approximately
50 mV of hysteresis. The response time of the reset voltage
comparator is less than1 μs. If glitches are present on the VCC line
that could cause spurious reset pulses, VCC should be decoupled
close to the device.
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
Rev. B | Page 11 of 20
In addition to RESET, the ADM8691/ADM8693/ADM8695
contain an active high RESET output. This is the complement of
RESET and is intended for processors requiring an active high
reset signal.
WATCHDOG TIMER RESET
The watchdog timer circuit monitors the activity of the micro-
processor to check that it is not stalled in an indefinite loop. An
output line on the processor is used to toggle the watchdog input
(WDI) line. If this line is not toggled within the selected timeout
period, a RESET pulse is generated. The nominal watchdog
timeout period is preset at 1.6 seconds on the ADM8690 and
ADM8692. The ADM8691/ADM8693/ADM8695 can be
configured for either a fixed short 100 ms, or a long 1.6 second
timeout period, or for an adjustable timeout period. If the short
period is selected, some systems are unable to service the
watchdog timer immediately after a reset, so the ADM8691/
ADM8693/ADM8695 automatically select the long timeout
period directly after a reset is issued. The watchdog timer is
restarted at the end of reset, whether the reset was caused by
lack of activity on WDI or by VCC falling below the reset
threshold.
The normal (short) timeout period becomes effective following
the first transition of WDI after RESET has gone inactive. The
watchdog timeout period restarts with each transition on the
WDI pin. To ensure that the watchdog timer does not time out,
either a high-to-low or low-to-high transition on the WDI pin
must occur at, or less than, the minimum timeout period. If
WDI remains permanently either high or low, reset pulses are
issued after each long (1.6 s) timeout period. The watchdog
monitor can be deactivated by floating the watchdog input
(WDI) or by connecting it to midsupply.
WDI
WDO
RESET
t
2
t
1
t
1
t
3
t
1
t1
= RESET TIME
t2
= NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD
t3
= WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET
00093-007
Figure 16. Watchdog Timeout Period and Reset Active Time
Table 5. ADM8691, ADM8693, ADM8695 Reset Pulse Width and Watchdog Timeout Selections
Watchdog Timeout Period Reset Active Period
OSC SEL OSC IN Normal Immediately After Reset ADM8691/ADM8693 ADM8695
Low1 External clock input 1024 CLKs 4096 CLKs 512 CLKs 2048 CLKs
Low1 External capacitor 400 ms × C/47 pF 1.6 s × C/47 pF 200 ms × C/47 pF 520 ms × C/47 pF
Floating or high Low 100 ms 1.6 s 50 ms 200 ms
Floating or high Floating or high 1.6 s 1.6 s 50 ms 200 ms
1 With the OSC SEL pin low, OSC IN can be driven by an external clock signal, or an external capacitor (C) can be connected between OSC IN and GND. The nominal
internal oscillator frequency is 10.24 kHz. The nominal oscillator frequency with external capacitor is: FOSC (Hz) = 184,000/C (pF).
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
Rev. B | Page 12 of 20
On the ADM8690/ADM8692 the watchdog timeout period is
fixed at 1.6 seconds and the reset pulse width is fixed at 50 ms.
The ADM8691/ADM8693/ADM8695 allow these times to be
adjusted, as shown in Table 5. Figure 17, Figure 18, Figure 19,
and Figure 20 show the various oscillator configurations that
can be used to adjust the reset pulse width and watchdog
timeout period.
The internal oscillator is enabled when OSC SEL is high or
floating. In this mode, OSC IN selects between the 1.6 second
and 100 ms watchdog timeout periods. With OSC IN connected
high or floating, the 1.6 second timeout period is selected; and
with it connected low, the 100 ms timeout period is selected. In
either case, the timeout period is 1.6 seconds immediately after
a reset. This gives the microprocessor time to reinitialize the
system. If OSC IN is low, the 100 ms watchdog period becomes
effective after the first transition of WDI. The software should
be written such that the input/output port driving WDI is left in
its power-up reset state until the initialization routines are
completed and the microprocessor is able to toggle WDI at the
minimum watchdog timeout period of 70 ms.
WATCHDOG OUTPUT (WDO)
The Watchdog Output WDO (ADM8691/ADM8693/ADM8695)
provides a status output that goes low if the watchdog timer
times out and remains low until set high by the next transition
on the watchdog input. WDO is also set high when VCC goes
below the reset threshold.
8
7
OSC SEL
OSC IN
ADM8691/
ADM8693/
ADM8695
CLOCK
0 TO 500kHz
00093-008
Figure 17. External Clock Source
8
7
COSC
00093-009
OSC SEL
OSC IN
ADM8691/
ADM8693/
ADM8695
Figure 18. External Capacitor
NC
NC
8
7
00093-010
OSC SEL
OSC IN
ADM8691/
ADM8693/
ADM8695
Figure 19. Internal Oscillator (1.6 Second Watchdog)
NC
8
7
00093-011
OSC SEL
OSC IN
ADM8691/
ADM8693/
ADM8695
Figure 20. Internal Oscillator (100 ms Watchdog)
CE GATING AND RAM WRITE PROTECTION
(ADM8691/ADM8693/ADM8695)
The ADM8691/ADM8693/ADM8695 products include
memory protection circuitry that ensures the integrity of data
in memory by preventing write operations when VCC is at an
invalid level. There are two additional pins (CEIN and CEOUT)
that can be used to control the chip enable or write inputs of
CMOS RAM. When VCC is present, CEOUT is a buffered replica
of CEIN, with a 3 ns propagation delay. When VCC falls below the
reset voltage threshold or VBATT, an internal gate forces CEOUT
high, independent of CEIN.
CEOUT typically drives the CE, CS, or write input of battery
backed up CMOS RAM. This ensures the integrity of the data in
memory by preventing write operations when VCC is at an
invalid level. Similar protection of EEPROMs can be achieved
using the CEOUT to drive the store or write inputs.
ADM8691
ADM8693
ADM8695
CE
OUT
V
CC
LOW = 0
V
CC
OK = 1
CE
IN
00093-012
Figure 21. Chip Enable Gating
RESET
LOW LINE
V1
V2V2 V1
V
CC
t
1
t
1
t1 = RESET TIME
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1
CE
IN
CE
OUT
00093-013
Figure 22. Chip Enable Timing
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
Rev. B | Page 13 of 20
POWER-FAIL WARNING COMPARATOR
An additional comparator is provided for early warning of
failure in the microprocessor power supply. The power-fail
input (PFI) is compared to an internal 1.3 V reference. The
power-fail output (PFO) goes low when the voltage at PFI is less
than 1.3 V. Typically, PFI is driven by an external voltage divider
that senses either the unregulated dc input to the system 5 V
regulator or the regulated 5 V output. The voltage divider ratio
can be chosen such that the voltage at PFI falls below 1.3 V
several milliseconds before the 5 V power supply falls below the
reset threshold. PFO is normally used to interrupt the
microprocessor so that data can be stored in RAM and the shut-
down procedure executed before power is lost.
ADM869x
1.3V PFO
R1
R2
POWER
FAIL
OUTPUT
POWER
FAIL
INPUT
INPUT
POWER
00093-014
Figure 23. Power-Fail Comparator
Table 6. Input and Output Status in Battery Backup Mode
Signal Status
VOUT VOUT is connected to VB AT T via an internal PMOS
switch.
RESET Logic low.
RESET Logic high. The open-circuit output voltage is equal
to VOUT.
LOW LINE Logic low.
BAT T ON Logic high. The open-circuit voltage is equal to VOUT.
WDI WDI is ignored. It is internally disconnected from the
internal pull-up resistor and does not source or sink
current as long as its input voltage is between GND
and VOUT. The input voltage does not affect supply
current.
WDO Logic high. The open circuit voltage is equal to VOUT.
PFI The power-fail comparator is turned off and has no
effect on the power-fail output.
PFO Logic low.
CEIN CEIN is ignored. It is internally disconnected from its
internal pull-up and does not source or sink current
as long as its input voltage is between GND and
VOUT. The input voltage does not affect supply
current.
CEOUT Logic high. The open circuit voltage is equal to VOUT.
OSC IN OSC IN is ignored.
OSC SEL OSC SEL is ignored.
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
Rev. B | Page 14 of 20
APPLICATION INFORMATION
INCREASING THE DRIVE CURRENT
If the continuous output current requirements at VOUT exceed
100 mA, or if a lower VCC – VOUT voltage differential is desired,
an external PNP pass transistor can be connected in parallel
with the internal transistor. The BATT ON output (ADM8691/
ADM8693/ADM8695) can directly drive the base of the
external transistor.
PNP T RANS ISTO R
0.1µF 0.1µF
BATTERY
V
BATT
V
CC
V
OUT
BATT
ON
5V INP UT
POWER
00093-024
ADM8691/
ADM8693/
ADM8695
Figure 24. Increasing the Drive Current
USING A RECHARGEABLE BATTERY FOR BACKUP
If a capacitor or a rechargeable battery is used for backup then
the charging resistor should be connected to VOUT because this
eliminates the discharge path that would exist during power-
down if the resistor is connected to VCC.
ADM869x
R
0.1µF 0.1µF
V
BATT
V
CC
V
OUT
5V INP UT
POWER
RECHARGEABLE
BATTERY
V
OUT
– V
BATT
R
I =
00093-025
Figure 25. Rechargeable Battery
ADDING HYSTERESIS TO THE POWER-FAIL
COMPARATOR
For increased noise immunity, hysteresis can be added to the
power-fail comparator. Because the comparator circuit is
noninverting, hysteresis can be added simply by connecting a
resistor between the PFO output and the PFI input as shown in
Figure 26. When PFO is low, Resistor R3 sinks current from the
summing junction at the PFI pin. When PFO is high, the series
combination of R3 and R4 sources current into the PFI
summing junction. This results in differing trip levels for the
comparator.
5V
0V
PFO
0V V
L
V
H
V
IN
V
H
= 1.3V
V
L
= 1.3V
ASSUMING R
4
< < R
3
THEN
HYSTERESIS V
H
– V
L
= 5V
1+ R
1
R
2
R
1
R
3
)(
+
1+ R
1
R
2
R
1
(5V – 1. 3V )
R
3
(1.3V (R
3
+ R
4
))
)(
–
ADM869x
1.3V
PFI PFO
TO
MICROPROCESSOR
NMI
5V
VCC
7V TO 15V
INPUT
POWER 7805
R
1
R
2
R
3
R
4
00093-026
R
1
R
2
)(
Figure 26. Adding Hysteresis to the Power-Fail Comparator
MONITORING THE STATUS OF THE BATTERY
The power-fail comparator can be used to monitor the status of
the backup battery instead of the power supply, if desired. This
is shown in Figure 27. The PFI input samples the battery voltage
and generates an active low PFO signal when the battery voltage
drops below a chosen threshold. It can be necessary to apply a
test load to determine the loaded battery voltage. This is done
under processor control using CEOUT. Because CEOUT is forced
high during the battery backup mode, the test load is not
applied to the battery while it is in use, even if the
microprocessor is not powered.
ADM869x
PFI
BATTERY 10MΩ
10MΩ
R
1
R
2
5V INP UT
POWER
20kΩ
OPTIONAL
TEST LOAD
LOW BATTERY
SIGNAL TO
MICROPROCESSOR
I/O PIN
V
BATT
V
CC
CE
OUT
CE
IN
PFO
00093-027
FROM
MICROPROCESSOR
I/O PIN APPLIES
TEST LOAD
TO BATTERY
Figure 27. Monitoring the Battery Status
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
Rev. B | Page 15 of 20
ALTERNATE WATCHDOG INPUT DRIVE CIRCUITS
The watchdog feature can be enabled and disabled under
program control by driving WDI with a three-state buffer (see
Figure 28). When three-stated, the WDI input floats, thereby
disabling the watchdog timer.
WDI
ADM869x
WATCHDOG
STROBE
CONTROL
INPUT
00093-028
Figure 28. Programming the Watchdog Input
This circuit is not entirely foolproof, and it is possible for a
software fault to erroneously three-state the buffer preventing
the ADM869x from detecting that the microprocessor is no
longer operating correctly. In most cases, a better method is to
extend the watchdog period rather than disable the watchdog.
This can be done under program control using the circuit
shown in Figure 29. When the control input is high, the
OSC SEL pin is low and the watchdog timeout is set by the
external capacitor. A 0.01 µF capacitor sets a watchdog time-
out delay of 100 seconds. When the control input is low, the
OSC SEL pin is driven high, selecting the internal oscillator.
The 100 ms or the 1.6 s period is chosen, depending on which
diode is used, as shown in Figure 29. With D1 inserted, the
internal timeout is set at 100 ms; with D2 inserted, the timeout
is set at 1.6 seconds.
ADM869x
OSC SEL
OSC IN
CONTROL
INPUT1
1LOW = INTERNAL TIMEOUT
HIG H = E X TERNAL TIMEOUT
D1 D2
00093-029
Figure 29. Programming the Watchdog Input
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
Rev. B | Page 16 of 20
TYPICAL APPLICATIONS
ADM8690 AND ADM8692
Figure 30 shows the ADM8690/ADM8692 in a typical power
monitoring, battery backup application. VOUT powers the CMOS
RAM. Under normal operating conditions with VCC present,
VOUT is internally connected to VCC. If a power failure occurs,
VCC decays and VOUT is switched to VBATT, thereby maintaining
power for the CMOS RAM. A RESET pulse is also generated
when VCC falls below 4.65 V for the ADM8690 or 4.4 V for the
ADM8692. RESET remains low for 50 ms after VCC returns to 5 V.
The watchdog timer input (WDI) monitors an input/output line
from the microprocessor system. This line must be toggled once
every 1.6 seconds to verify correct software execution. Failure to
toggle the line indicates that the microprocessor system is not
correctly executing its program and can be tied up in an endless
loop. If this happens, a reset pulse is generated to initialize the
microprocessor.
If the watchdog timer is not needed, the WDI input should be
left floating.
The power-fail input, PFI, monitors the input power supply via
a resistive divider network. The voltage on the PFI input is
compared with a precision 1.3 V internal reference. If the input
voltage drops below 1.3 V, a power-fail output (PFO) signal is
generated. This warns of an impending power failure and can
be used to interrupt the processor so that the system can be shut
down in an orderly fashion. The resistors in the sensing
network are ratioed to give the desired power-fail threshold
voltage (VT).
VT = (1.3 R1/R2) + 1.3 V
R1/R2 = (VT/1.3) − 1
+
5V
0.1µF
WDI
GND
PFI
BATTERY
R1
R2
VBATT
VCC
PFO
ADM8690/
ADM8692
CMOS RAM
POWER
POWER
MICROPROCESSOR
SYSTEM
NMI
I/O LINE
VOUT
RESET
RESET
00093-030
Figure 30. ADM8690/ADM8692 Typical Application Circuit A
Figure 31 shows a similar application, but in this case the PFI
input monitors the unregulated input to the 7805 voltage
regulator. This gives an earlier warning of an impending power
failure. It is useful with processors operating at low speeds or
where there are a significant number of housekeeping tasks to
be completed before the power is lost.
+
INPUT
POWER
V > 8V
0.1µF
WDI
GND
PFI
BATTERY
R
1
R
2
V
BATT
V
CC
PFO
ADM8690/
ADM8692
CMOS RAM
POWER
POWER
MICROPROCESSOR
SYSTEM
NMI
I/O LINE
V
OUT
RESET
RESET
7805
0.1µF
00093-031
5V
Figure 31. ADM8690/ADM8692 Typical Application Circuit B
ADM8691, ADM8693, AND ADM8695
A typical connection for the ADM8691/ADM8693/ADM8695
is shown in Figure 32. CMOS RAM is powered from VOUT.
When 5 V power is present, this is routed to VOUT. If VCC fails,
VBATT is routed to VOUT. VOUT can supply up to 100 mA from
VCC, but if more current is required, an external PNP transistor
can be added. When VCC is higher than VBATT, the BATT ON
output goes low, providing up to 25 mA of base drive for the
external transistor. A 0.1 µF capacitor is connected to VOUT to
supply the transient currents for CMOS RAM. When VCC is
lower than VBATT, an internal 20 Ω MOSFET connects the
backup battery to VOUT.
RESET
NC
A0 TO 15
I/O LINE
NMI
RESET
MICROPROCESSOR
SYSTEM
PFI
GND
OSC IN
OSC SEL
WDI
WDO
R
1
R
2
V
BATT
V
CC
ADM8691/
ADM8693/
ADM8695
V
OUT
0.1µF
SYSTEM STATUS
INDICATORS
BATT
ON
3V
BATTERY
INPUT POWER
5V
0.1µF
0.1µF
CMOS
RAM
ADDRESS
DECODE
LOW LINE
RESET
CE
OUT
CE
IN
PFO
00093-032
Figure 32. ADM8691/ADM8693/ADM8695 Typical Application
RESET OUTPUT
The internal voltage detector monitors VCC and generates a
RESET output to hold the microprocessor reset line low when
VCC is below 4.65 V (4.4 V for ADM8693). An internal timer
holds RESET low for 50 ms (200 ms for the ADM8695) after
VCC rises above 4.65 V (4.4 V for the ADM8693). This prevents
repeated toggling of RESET, even if the 5 V power drops out
and recovers with each power line cycle.
The crystal oscillator normally used to generate the clock for
microprocessors can take several milliseconds to stabilize.
Because most microprocessors need several clock cycles to
reset, RESET must be held low until the microprocessor clock
oscillator has started. The power-up RESET pulse lasts 50 ms
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
Rev. B | Page 17 of 20
(200 ms for the ADM8695) to allow for this oscillator start-up
time. If a different reset pulse width is required, a capacitor
should be connected to OSC IN, or an external clock can be
used. Refer to Table 5 and Figure 17, Figure 18, Figure 19, and
Figure 20. The manual reset switch and the 0.1 µF capacitor
connected to the reset line can be omitted if a manual reset is
not needed. An inverted, active high, RESET output is also
available.
POWER-FAIL DETECTOR
The 5 V VCC power line is monitored via a resistive potential
divider connected to the power-fail input (PFI). When the
voltage at PFI falls below 1.3 V, the power-fail output (PFO)
drives the processor’s NMI input low. If, for example, a power-
fail threshold of 4.8 V is set with Resistor R1 and Resistor R2, the
microprocessor has the time when VCC falls from 4.8 V to 4.65 V
to save data into RAM. An earlier power-fail warning can be
generated if the unregulated dc input to the 5 V regulator is
available for monitoring. This allows more time for microprocessor
housekeeping tasks to be completed before power is lost.
RAM WRITE PROTECTION
The ADM8691/ADM8693/ADM8695 CEOUT line drives the
chip select inputs of the CMOS RAM. CEOUT follows CEIN as
long as VCC is above the 4.65 V (4.4 V for the ADM8693) reset
threshold.
If VCC falls below the reset threshold, CEOUT goes high,
independent of the logic level at CEIN. This prevents the
microprocessor from writing erroneous data into RAM during
power-up, power-down, brownouts, and momentary power
interruptions.
WATCHDOG TIMER
The microprocessor drives the watchdog input (WDI) with an
input/output line. When OSC IN and OSC SEL are unconnected,
the microprocessor must toggle the WDI pin once every
1.6 seconds to verify proper software execution. If a hardware
or software failure occurs such that WDI is not toggled, the
ADM8691/ADM8693 issues a 50 ms (200 ms for the ADM8695)
RESET pulse after 1.6 seconds. This typically restarts the micro-
processor power-up routine. A new RESET pulse is issued every
1.6 seconds until WDI is again strobed. If a different watchdog
timeout period is required, a capacitor should be connected to
OSC IN or an external clock can be used. Refer to Table 5 and
Figure 17, Figure 18, Figure 19, and Figure 20.
The watchdog output (WDO) goes low if the watchdog timer is
not serviced within its timeout period. Once WDO goes low, it
remains low until a transition occurs at WDI. The watchdog
timer feature can be disabled by leaving WDI unconnected.
The RESET output has an internal 3 µA pull-up and can either
connect to an open collector reset bus or directly drive a CMOS
gate without an external pull-up resistor.
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
Rev. B | Page 18 of 20
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC S TANDARDS MS-001
CONTROLLING DIMENSIONSARE IN INCHES; MILLI MET ER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH E QUI VALENTS FOR
REFE RE NCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONF IGURE D AS WHOLE O R HALF LEADS.
070606-A
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
SEATING
PLANE
0.015
(0.38)
MIN
0.210 (5.33)
MAX
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
8
14
50.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.100 (2.54)
BSC
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
0.060 (1.52)
MAX
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
0.005 (0.13)
MIN
Figure 33. 8-Lead Plastic Dual In-Line Package [PDIP]
(N-8)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONSARE IN INCHES; MILL I MET ER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH E QUI VALENTS FOR
REFE RE NCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURE D AS WHOLE O R HALF LEADS.
COMPLIANT TO JEDEC STANDARDS MS-001-AB
073106-B
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
16
18
9
0.100 (2.54)
BSC
0.800 (20.32)
0.790 (20.07)
0.780 (19.81)
0.210 (5.33)
MAX
SEATING
PLANE
0.015
(0.38)
MIN
0.005 (0.13)
MIN
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.060 (1.52)
MAX
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.015 (0.38)
GAUGE
PLANE
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
Figure 34. 16-Lead Plastic Dual In-Line Package [PDIP]
(N-16)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
8 5
5.00(0.1968)
4.80(0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 35. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLYAND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AA
10.50 (0.4134)
10.10 (0.3976)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75 (0.0295)
0.25 (0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
16 9
8
1
1.27 (0.0500)
BSC
03-27-2007-B
Figure 36. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
Rev. B | Page 19 of 20
CONTROLLING DIMENSIONSARE IN M ILLI M E TERS; INCH DIM E NS IONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFE RE NCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC S TANDARDS MS-012-AC
10.00 (0.3937)
9.80 (0.3858)
16 9
8
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
BSC
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
1.75 (0.0689)
1.35 (0.0531)
0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COPLANARITY
0.10
8°
0°
060606-A
45°
Figure 37. 16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-16)
Dimensions shown in millimeters and (inches)
16 9
81
PI N 1
SEATING
PLANE
8°
0°
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX 0.20
0.09 0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COM P LIANT T O JEDE C S TANDARDS M O-153-AB
Figure 38. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADM8690AN −40°C to +85°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8
ADM8690ANZ −40°C to +85°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8
ADM8690ARN −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM8690ARN-REEL −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM8690ARNZ −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM8691ANZ −40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16
ADM8691ARN −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADM8691ARN-REEL −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADM8691ARNZ −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADM8691ARW −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
ADM8691ARW-REEL −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
ADM8691ARWZ −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
ADM8691ARU −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADM8691ARU-REEL −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADM8691ARUZ −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADM8692ARNZ −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM8693AN −40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16
ADM8693ANZ −40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16
ADM8693ARN −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADM8693ARN-REEL −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADM8693ARNZ −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADM8693ARW −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
ADM8693ARW-REEL −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
ADM8693ARWZ −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
ADM8693ARU-REEL −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADM8693ARUZ −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADM8695ARW −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
ADM8695ARW-REEL −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
ADM8695ARWZ −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
1 Z = RoHS Compliant Part.
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
Rev. B | Page 20 of 20
NOTES
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registered trademarks are the property of their respective owners.
D00093-0-6/11(B)
