512x9, 2Kx9, and 4Kx9 Cascadable
Clocked FIFOs with Programmable
CY7C451
CY7C453
CY7C454
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06033 Rev. *A Revised December 27, 2002
54
Features
• High-speed, low-power, first-in first-out (FIFO)
memories
• 512 x 9 (CY7C451)
• 2,048 x 9 (CY7C453)
• 4,096 x 9 (CY7C454)
• 0.65 micron CMOS for optimum speed/power
• High-spe ed 83-M Hz operation (12 ns read/write cyc le
time)
• Low power — ICC=70 mA
• Fully asynchronous and simultaneous read and write
operation
• Empty , Full, Half Full, and programmable Almost Empty
and Almost Full status flags
• TTL compatible
• Retransmit function
• Parity generation/checking
• Output Enable (OE) pins
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Supports free-running 50% duty cycle clock inputs
• Width Expansion Capability
• Depth Expansion Capability
• Available in PLCC packages
Functional Description
The CY7C451, CY7C453, and CY7C454 are high-speed,
low-power, first-in first-o ut (FIFO) memories with clocked read
and write interfaces. Both FIFOs are 9 bits wide. The
CY7C451 has a 512-word by 9-bit memory array, the
CY7C453 has a 2048-word by 9-bit memory array, and the
CY7C454 has a 4096-word by 9-bit memory array. Devices
can be c as cad ed to in cre as e FIFO d ep th. Prog ram ma ble fe a-
tures include Almost Full/Empty flags and generation/checking
of parity. These FIFOs provide solutions for a wide variety of data
buffering needs, including high-speed data acquisiti on, multiproces-
sor interfaces, and communications buffering.
Both FIFOs have 9-bit input and output ports that are con-
trolled by separa te cl oc k an d ena bl e si gna ls . The i nput port is
controlled by a free-running clock (CKW) and a write enable
pin (ENW). When ENW is asserted, data is written into the FIFO on
the rising edge of the CKW signal. While ENW is held active, data is
continually written into the FIFO on each CKW cycle. The output port
is controlled in a similar manner by a free-running read clock (CKR)
and a read enable pin (ENR). The read (CKR) and write (CKW)
clocks may be tied together for single-clock operation or the two
clocks may be run independently for asynchronous read/write appli-
cations. Clock frequencies up to 83.3 MHz are achievable in the stan-
dalone configuration, and up to 83.3 MHz is achievable when FIFOs
are cascaded for depth expansion.
Depth expansion is possible using the cascade input (XI) and
cascade output (XO). The XO signal is connected to the XI of the next
device, and the XO of the last device should be connected to the XI
of the first device. In standalone mode, the input (XI) pin is simply tied
to VSS.
In the st and alone and wid th ex pan sion conf igu rations , a LOW
on the retransmit (RT) input causes the FIFOs to retransmit
the data. Read enable (ENR) and the write enable (ENW) must
both be HIGH during the retransmit, and then ENR is used to
access the data.
7C451
D3
Logic Block Diagram Pin Configurations
C451-1
C451-2
PARITY
TRI–STATE
OUTPUT REGISTER READ
CONTROL
FLAG
LOGIC
WRITE
CONTROL
WRITE
POINTER READ
POINTER
RESET
LOGIC
EXPANSION
LOGIC
INPUT
REGISTER
FLAG/PARITY
PROGRAM
REGISTER
D0–8
ENRCKR
HF
E/F
PAFE/XO
Q0–7,Q8/PG/PE
ENWCKW
MR
FL/RT
XI
OE
12
314
5
6
7
8
9
10
32130
1314 15 16 17
26
25
24
23
22
21
11
Top View
PLCC/LCC
1819 20
27
28
29
32
7C453
FL/RT
MR
CKR
ENR
OE
/PG/PE
XI
ENW
CKW
VCC
VSS
HF
E/F
PAFE/XO
D0
RAM
ARRAY
512x9
2048x9
7C454
4096x9
RETRANSMIT
LOGIC
D1D2D4D5D6
D7
D8
Q4
Q1Q2Q3Q5Q6Q7
Q8
VSS
Q0
CY7C451
CY7C453
CY7C454
Document #: 38-06033 Rev. *A Page 2 of 24
Functional Description (continued)
The CY7C451, CY7C453, and CY7C454 provi de thre e st at us pin s
to the user. These pins are decoded to determine one of six states:
Empty, Almost Empty, Less than or Equal to Half Full, Gr eater tha n
Half Full, Almost Full, and Full (see Table 1). The Almost Empty/Full
flag (PAFE) and XO functions share the same pin. The Almost Emp-
ty/Full flag is val id in the st andalone and wid th expansion con-
figurations. In the depth expansion, this pin provides the
expansion out (XO) information that is used to signal the
next FIFO when it will be activated.
The flags are synchronous, i.e., they change state relative to
either the read c lock (CKR) or the write clock (CKW). When
entering or exiting the Empty and Almost Empty states, the
flags are updated exclusively by the CKR. The flags denoting
Half Full, Almost Full, and Full states are updated exclusively
by CKW. The synchronous flag architecture guarantees that
the flags maintain their status for some minimum time.
The CY7C451, CY7C453, and the CY7C454 use center power
and ground for reduced noise. Both configurations are fabri-
cated using an advanced RAM 2.8 technology. Input ESD
prot ecti on is gr eater than 20 01V, and la tch- up is pr even ted
by the us e of r elia ble la yout techni ques and gu ard r ings .
Maximum Ratings[1]
(Above which the useful life may be impaired. For user guide-
lines, not tes ted .)
Storage Temperature ....................................−65°C to +150°C
Ambient Temperature with
Power Applied.................................................−55°C to +125°C
Supply Voltage to Ground Potential.................−0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State.....................................................−0.5V to +7.0V
DC Input Voltage.................................................−3.0V to +7.0V
Output Current into Outputs (LOW).............................20 mA
St at ic Disc ha rge Voltage..... ...... ..... ...... ................. .....>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current....................................................> 200 mA
Notes:
1. The Voltage on any input or I/O pin cannot exceed the power pin during
power-up.
Selection Guide
7C451-12
7C453-12
7C454-12
7C451-14
7C453-14
7C454-14
7C451-20
7C453-20
7C454-20
7C451-30
7C453-30
7C454-30
Maximu m Frequency (MHz ) 83.3 71.4 50 33.3
Maximum Cascad abl e Fr equ enc y 83.3 71.4 50 33.3
Maximum Access Time (ns) 910 15 20
Minimum Cycle Time (ns) 12 14 20 30
Minimum Clock HIGH Time (ns) 56.5 912
Minimum Clock LOW Time (ns) 56.5 912
Minimum Data or Enable Set-Up (ns) 4 5 6 7
Minimum Data or Enable Hold (ns) 0 0 0 0
Maximum Flag Delay (ns) 910 15 20
Maximum Current (mA) Commercial 140 140 120 100
Military/Industrial 150 150 130 110
Selection Guide (continued)
CY7C451 CY7C453 CY7C454
Density 512 x 9 2,048 x 9 4,096 x 9
OE, Depth Cascadable Yes Yes Yes
Package 32-Pin PLCC 32-Pin PLCC 32-Pin PLCC
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +70°C 5V ± 10%
Industrial −40°C to +85°C 5V ± 10%
CY7C451
CY7C453
CY7C454
Document #: 38-06033 Rev. *A Page 3 of 24
Pin Definitions
Signal
Name I/O Description
D0 – 8 IData Input s: When the FIFO is not full an d ENW is active, CKW (rising edge) writes data (D0 – 8) into
the FIFO ’s me m o ry. If MR is asserted at the rising edge of CKW then data is written into the FIFO’s
programming register. D8 is ignored if the device is configured for parity generation.
Q0 – 7 OData Ou tputs: When th e FIFO is not empty and ENR is active, CKR (rising edge) reads data (Q0 – 7)
out of the FIFO’s memor y. If MR is active at the rising edge of CKR then data is read from the
programming register.
Q8/PG/PE OFunction v aries according to mo de:
Parity disabled - same function as Q0 – 7
Pari ty en able d, ge nera tion - parity gener ati on bi t (PG)
Parity enabled, check - Parity Error Flag (PE)
ENW IEnable Write: enables the CKW input (for both non-program and program modes)
ENR IEnable Read: enables the CKR input (for both non-program and program modes)
CKW IWrite Clock: the rising edge clocks data into the FIFO when ENW is LOW; updates Half Full, Almost
Full, and F ull fl ag stat es. W hen MR is ass erted , CKW w rite s da ta into th e pro gra m regi ster.
CKR IRead Clock: the rising edge clocks data out of the FIFO when ENR is LOW; updates the Empty and
Almost Empty flag states. When MR is asserted, CKR reads data out of the program register.
HF OHalf Full Flag - synchronized to CKW.
E/F OEmpty or Full Flag - E is synchronized to CKR; F is synch ronized t o CKW
PAFE/XO OD ual-Mode Pin:
Not Cascaded - Programmable Almost Full is synchronized to CKW; Programmable Almost Empty is
synchronized to CKR
Cascaded - Expansion Out signal, connected to XI of next device
XI INot Cascaded - X I is tied to VSS
Casca ded - Expans ion In put, co nnec ted to XO of pr evio us de vice
FL/RT IFirst Load/ Retransmit Pin:
Cascaded - the first device in the daisy chain will have FL tied to VSS; all oth er devi ces wil l have FL
tied to VCC (Figure 2)
Not Cascaded - tied to VCC;
Retransmit function is also available in stand alone mode by strobing RT
MR IMaster Reset: resets device to empty condition.
Non-Progra mmin g Mo de: pro gram regi ste r is reset to def aul t con diti on of no p arit y and PAFE ac tive at
16 or less locations from Full/Empty.
Programmi ng Mo de: Data present on D0 – 8 is written into the programmable register on the rising
edge of CKW. Pro gram regist er co ntents ap pear on Q0 – 8 after the rising edge of CKR.
OE IOutput Enable for Q0 – 7 and Q8/PG/PE pins
CY7C451
CY7C453
CY7C454
Document #: 38-06033 Rev. *A Page 4 of 24
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions
7C451-12
7C453-12
7C454-12
7C451-14
7C453-14
7C454-14
7C451-20
7C453-20
7C454-20
7C451-30
7C453-30
7C454-30
Min. Max. Min. Max. Min. Max. Min. Max. Unit
VOH Out put HI GH
Voltage VCC = Min., IOH = −2.0 mA 2.4 2.4 2.4 2.4 V
VOL Output LO W
Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 0.4 0.4 V
VIH[2] Input HIGH Vo ltage 2.2 VCC 2.2 VCC 2.2 VCC 2.2 VCC V
VIL[2] Input LOW Voltage −0.5 0.8 −0.5 0.8 −0.5 0.8 −0.5 0.8 V
IIX Input Leakage
Current VCC = Max. −10 +10 −10 +10 −10 +10 −10 +10 µA
IOS[3] Output Short
Circuit Current VCC = Max., VOUT = GND −90 −90 −90 −90 mA
IOZL
IOZH Output OFF , High Z
Current OE > VIH, VSS < VO < VCC −10 +10 −10 +10 −10 +10 −10 +10 µA
ICC1[4] O pe rati ng Curren t VCC = Max.,
IOUT = 0 mA Com’l140 140 120 100 mA
Mil/Ind 150 150 130 110 mA
ICC2[5] O pe rati ng Curren t VCC = Max.,
IOUT = 0 mA Com’l70 70 70 70 mA
Mil/Ind 80 80 80 80 mA
ISB[6] Standby Current VCC = Max.,
IOUT = 0 mA Com’l30 30 30 30 mA
Mil/Ind 30 30 30 30 mA
Capacitance[7]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitan c e TA = 2 5°C, f = 1 MHz,
VCC = 5. 0V 10 pF
COUT Output Capacitance 12 pF
Notes:
2. The VIH and VIL specifications apply for all inputs except XI. The XI pin is not a TTL input. It is connected to either XO of the previous device or VSS.
3. Test no more than one output at a time for not more than one second.
4. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at maximum frequency (fMAX), while data inputs
switch at f MAX/2. Outputs are unloaded.
5. Input signals switch from 0V to 3V with a rise/fall time less than 3 ns, clocks and clock enables switch at 20 MHz, while the data inputs switch at 10 MHz.
Outputs are unloaded.
6. All input signals are connected to VCC. All outputs are unloaded. Read and write clocks switch at maximum frequency (fMAX).
7. Tested initially and after any design or process changes that may affect these parameters.
CY7C451
CY7C453
CY7C454
Document #: 38-06033 Rev. *A Page 5 of 24
AC Test Loads and Waveforms[8, 9, 10, 11 , 12]
Switching Characteristics Over the Operating Range[13]
Parameter Description
7C451-12
7C453-12
7C454-12
7C451-14
7C453-14
7C454-14
7C451-20
7C453-20
7C454-20
7C451-30
7C453-30
7C454-30
UnitMin. Max. Min. Max. Min. Max. Min. Max.
tCKW Write Clock Cycle 12 14 20 30 ns
tCKR Read Clock Cycle 12 14 20 30 ns
tCKH Clock HIGH 56.5 912 ns
tCKL Clock LOW 56.5 912 ns
tA[14] Data Access Time 910 15 20 ns
tOH Previous Output Data Hold After Read HIGH 0 0 0 0 ns
tFH Previous Flag Hold After Read/Write HIGH 0 0 0 0 ns
tSD Data Set-Up 4 5 6 7 ns
tHD Data Hold 0 0 0 0 ns
tSEN Enable Set-Up 4 5 6 7 ns
tHEN Enable Hold 0 0 0 0 ns
tOE OE LOW to Output Data Valid 910 15 20 ns
tOLZ[7,15] OE LOW to Output Data in Low Z 0 0 0 0 ns
tOHZ[7,15] OE HIGH to Output Data in High Z 910 15 20 ns
tPG Read HIGH to Parity Generation 910 15 20 ns
tPE Read HIGH to Parity Error Flag 910 15 20 ns
tFD Flag Delay 910 15 20 ns
tSKEW1[16] Opposite Cloc k After Cloc k 0 0 0 0 ns
Notes:
8. CL = 30 pF for all AC parameters except for tOHZ.
9. CL = 5 pF fo r tOHZ.
10. All AC measurements are referenced to 1.5V except tOE, tOLZ, and tOHZ.
11. tOE and tOLZ are measured at ± 100 mV from the steady state.
12. tOHZ is measured at +500 mV from VOL and – 500 mV from VOH.
13. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and output loading as shown in AC Test Loads and Waveforms
and capacitance as in notes 8 and 9, unless otherwise specified.
14. Access time includes all data outputs switching simultaneously.
15. At any given temperature and voltage condition, tOLZ is greater than tOHZ for any given device.
16. tSKEW1 is the minimum time an oppos ite clock can oc cur after a cl ock and still be guaranteed not to b e included in the current clock cycle (for purposes
of flag update) . If the opposi te clock occ urs less than tSKEW1 after the clock, th e decision of whe ther or not to includ e the opposite clo ck in the current
clock c ycle is arbi tr ary. Note: The o pposite cl ock i s the s igna l to w hich a fl ag is no t s ynchroni zed ; i.e. , C KW is t he op posite cl o c k fo r E mpty and A lmos t
Empty flags, CKR is the opposite clock for the Almost Full, Half Full, and Full flags. The clock is the signal to which a flag is synchronized; i.e., CKW is the
clock for the Half Full, Almost Full, and Full flags, CKR is the clock for Empty and Almost Empty flags.
3.0V
5V
OUTPUT
R1500Ω
R2
333Ω
CL
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
<3ns <3ns
OUTPUT 2V
Equivalentto: THÉ VENIN EQUIVALENT
C451-4
200Ω
ALL INPUT PULSES
C451-5
CY7C451
CY7C453
CY7C454
Document #: 38-06033 Rev. *A Page 6 of 24
tSKEW2[17] Opposite Cloc k Befo re Clock 12 14 20 30 ns
tPMR Master Reset P ulse Width (MR LOW) 12 14 20 30 ns
tSCMR Last Valid Clock LOW Set-Up to MR LOW 0 0 0 0 ns
tOHMR Data Hold From MR LOW 0 0 0 0 ns
tMRR Master Reset Recovery
(MR HIGH Set-Up to First Enabled
Write/Read)
12 14 20 30 ns
tMRF MR HIGH to Flags Valid 12 14 20 30 ns
tAMR MR HIGH to Data Outpu ts LOW 12 14 20 30 ns
tSMRP Program Mode—MR LOW Set-Up 12 14 20 30 ns
tHMRP Program Mode —MR LOW Hol d 910 15 25 ns
tFTP Program Mode—Write HIGH to Read HIGH 12 14 20 30 ns
tAP Program Mode—Data Access Time 12 14 20 30 ns
tOHP Program Mode—Data Hold Time from MR
HIGH 0 0 0 0 ns
tPRT Retransmit Pulse Width 12 14 20 30
tRTR Re transmit Recovery Time 12 14 20 30
17. tSKEW2 is the minimum time an oppos it e cloc k c an occur before a cl ock an d st il l be guar antee d to b e i ncluded i n t he current cl ock cycl e (f or pur poses
of flag update). If the opposite clock occurs less than tSKEW2 before the clock, the decision of whether or not to include the opposite clock in the
current clock cycle is arbitrary. See Note 16 for definition of clock and opposite clock.
Switching Characteristics Over the Operating Range[13] (continued)
Parameter Description
7C451-12
7C453-12
7C454-12
7C451-14
7C453-14
7C454-14
7C451-20
7C453-20
7C454-20
7C451-30
7C453-30
7C454-30
UnitMin. Max. Min. Max. Min. Max. Min. Max.
CY7C451
CY7C453
CY7C454
Document #: 38-06033 Rev. *A Page 7 of 24
Switching Waveforms
Notes:
18. To only perform reset (no programming), the following criteria must be met: ENW or CKW must be inactive while MR is LOW.
19. To only perform reset (no programming), the following criteria must be met: ENR or CKR must be inactive while MR is LOW.
20. All data outputs (Q0 – 8) go LOW as a result of the rising edge of MR after tAMR.
21. In this example, Q0 – 8 will remain valid until tOHMR if either the first read shown d id not occur or if the read occurred soon enough such that the valid
data was caused by it.
Write Clock TimingDiagram
Read Clock Timing Diagram
tCKW
C451-6
C451-7
tCKH tCKL
tHD
tSD
ENABLED WRITE DISABLE D WRITE
VALID DATA IN
tSEN tHEN
tSEN tHEN
ENABLED READ DISABLED READ
PREVIOUS WORD
tCKR
tCKH tCKL
tOH
tSEN tHEN
tSEN tHEN
NEW WORD
tA
Master Reset (Default with Free-Running Clocks) Timing Diagram
tPMR
tMRR
tSCMR
tMRR
tOHMR
VALID DATA
tAMR
tMRF
ALL DATA
OUTPUTS L OW
tSCMR
tMRF
CKW
MR
ENW
CKR
ENR
Q0–8
E/F,PAFE
HF
FIRST
WRITE
tFH
tFH
tFH tFD
tFD
tFH
tFH tFD
tFD
tFH
CKR
Q0–8
ENR
E/F,PAFE
CKW
D0–8
ENW
E/F,PAFE,HF
[18,19,20,21]
CY7C451
CY7C453
CY7C454
Document #: 38-06033 Rev. *A Page 8 of 24
Switching Waveforms (continued)
Master Reset(Programming Mode) Timing Diagram
tSMRP
tMRR
tSCMR
tHMRP
tCKH
tSCMR
tFTP
tSD tHD
tSMRP tHMRP
tCKH
tAP
tOHMR tOHP tAMR
CKW
MR
ENW
D0–8
CKR
ENR
Q0–8VALID DATA PGM WORD ALL DATA
OUTPUTS LOW
LAST
VALID
READ
PGM
READ
LAST
WORD PGM
WORD WORD 1 WORD 2
LAST
VALID
WRITE
PGM
WRITE FIRST
WRITE SECOND
WRITE
C451-9
Master Reset (Programming Mode with Free-Running Clocks) Timing
tSMRP
C451-10
tMRR
tSCMR
tHMRP
tCKH
tSCMR
tHEN
tFTP
tSMRP
tAP
tOHMR tOHP tAMR
MR
VALID DATA PGM WORD ALL DATA
OUTPUTS LOW
LAST
WORD PGM
WORD WORD 1 WORD 2
tCKL
tCKW
tSEN
tCKR
tCKL
tCKH tHEN
tSEN
PGM
READ
CKW
D0–8
Q0–8
ENW
CKR
ENR
LAST
VALID
WRITE PGM
WRITE FIRST
WRITE SECOND
WRITE
LAST
VALID
READ
tHMRP
LOW
LOW
MR
tMRR
Diagram
[20,21]
[20,21]
CY7C451
CY7C453
CY7C454
Document #: 38-06033 Rev. *A Page 9 of 24
Notes:
22. “Count” is the number of words in the FIFO.
23. The FIFO is assumed to be programmed with P>0 (i.e., PAFE does not transition at Empty or Full).
24. R2 is ignored because the FIFO is empty (count = 0). It is important to note that R3 is also ignored because W3, the first enabled write after empty, occurs
less than tSKEW2 before R3. The refore, the FI FO still appears empty when R3 oc curs. Becaus e W3 occurs grea ter than tSKEW2 before R4 , R4 includes
W3 in the flag update.
25. CKR is clock; CKW is opposite clock.
26. R 3 up d at e s th e f lag t o t he Emp t y s t at e by ass e rt in g E/F. Because W1 occurs greater than tSKEW1 after R3, R3 does not recognize W1 when updating
flag stat us. But beca use W1 occ urs greate r than tSKEW2 before R4, R4 includes W1 in the flag updat e and, theref ore, updates FIFO to Almost Empty
state. It is import ant to note that R4 is a latent cyc l e; i.e., it only upda tes the flag st a tus rega rdle ss of the st ate of EN R . It does not change t he count
or the FIFO’s data outputs.
Switching Waveforms (continued)
Read to Empty Timing Diagram with Free-Running Clocks
LATENTCYCLE
tSKEW1 tSKEW2
tFD tFD
tFD
COUNT 1 0 1 0
ENABLED
READ FLAG
UPDATE ENABLED
READ IGNORED
READ
ENABLED
WRITE
IGNORED
READ IGNORED
READ READ
CKR
ENR
CKW
ENW
PAFE
E/F
HF
C451-11
HIGH
LOW
Read to Empty Timing Diagram
COUNT 32 0 1 (NO CHANGE)
tFD tFD
R1
ENABLED FLAG
UPDATE
11
0
LATENTCYCLE
READ
ENABLED
WRITE
tSKEW2
tSKEW1
CKW
ENR
ENW
E/F
CKR
LOW
tFD
C451-12
READ
R2
ENABLED
READ
R3
ENABLED
READ
R5
ENABLED
READ
R4
W1
R1 R2 R3 R4 R5 R6
W1 W2 W4 W5 W6
W3
tSKEW2
PAFE LOW
[22,25,26]
[22,23,24,25]
CY7C451
CY7C453
CY7C454
Document #: 38-06033 Rev. *A Page 10 of 24
Notes:
27. The FIFO in this example is assumed to be programmed to its default flag values. Almost Empty is 16 words from Empty; Almost Full is 16 locations from Full.
28. R4 only updates the flag status. It does not affect the count because ENR is HIGH.
29. When making the transition from Almost Empty to Intermediate, the count must increase by two (16 =>18; two enabled writes: W2, W3) before a read
(R4) can update flags to the Less Than Half Full state.
Switching Waveforms (continued)
Read to Almost Empty Timing Diagram with Free-Running Clocks
Read to Almost Empty Timing Diagram with Read Flag UpdateCycle and Free-Running Clocks
tSKEW1 tSKEW2
tFD tFD
tFD
COUNT 17 16 18 16
ENABLED
READ
CKR
ENR
CKW
ENW
E/F
PAFE
HF
17 17 15
ENABLED
WRITE
CKR
CKW
COUNT 17 16 18 16
tSKEW1 tSKEW2
tFD tFD
tFD
ENR
ENW
PAFE
ENABLED
READ FLAG
UPDATE ENABLED
READ ENABLED
READ
17 17 15
HF
ENABLED
READ
READ
FLAG UPDATE CYCLE
C451-13
E/F
C451-14
HIGH
HIGH
HIGH
HIGH
R1 R2 R3 ENABLED
READ
R4 ENABLED
READ
R5 ENABLED
READ
R6
W1 W2 ENABLED
WRITE
W3 W4 W1W5 W6
R1 R2 R3 R4 R5 R6 R7
ENABLED
WRITE
W2 ENABLED
WRITE
W3
W1 W4 W5 W6 W7
18 (no change)
[22,25,27]
[22,25,27,28,29]
CY7C451
CY7C453
CY7C454
Document #: 38-06033 Rev. *A Page 11 of 24
Notes:
30. CKW is clock and CKR is opposite clock.
31. Count = 2,049 indicates Half Full for the CY7C454, count=1,025 indicates Half Full for the CY7C453, and count = 257 indicates Half Full for the CY7C451.
Values for CY7C451 count are shown in brackets.
32. When the FIFO contains 2048[1024,256] words, the rising edge of the next enabled write causes the HF to be true (LOW).
33. T he HF write flag update cycle does not affect the count because ENW is HIGH. It only updates HF to HIGH.
34. When making the transition from Half Full to Less Than Half Full, the count must decrease by two (1,025 =>1,023; two enabled reads: R2 and R3) before
a write (W4) can update flags to less than Half Full.
Switching Waveforms (continued)
Write to Half Full Timing Diagram with Free-Running Clocks
COUNT 1024 1025 1023 1025
tSKEW1 tSKEW2
tFD tFD
tFD
ENABLED
WRITE ENABLED
WRITE ENABLED
WRITE ENABLED
WRITE
ENABLED
READ ENABLED
READ
1024 1024 1026
C451-15
[256] [257] [256] [255] [256] [257] [258]
Write to Half Full Timing Diagramwith Write Flag Update Cycle with Free-Running Clocks
COUNT 1024 1025 1023 1025
tSKEW1 tSKEW2
tFD tFD
tFD
ENABLED
WRITE FLAG
UPDATE ENABLED
WRITE ENABLED
WRITE
1024 1024 1026
ENABLED
WRITE
ENABLED
READ ENABLED
READ
WRITE
FLAG UPDATE CYCLE
[256] [257] [256] [255] [256] [257] [258]
CKW
CKR
ENW
ENR
HF
E/F
PAFE
C451-16
CKW
CKR
ENW
ENR
HF
PAFE
E/F
HIGH
HIGH
HIGH
HIGH
W1 W2 W3 W4 W5 W6
R1 R4 R5 R6
R3R2
W1 W2 W3 W4 W5 W6 W7
R1 R4 R5 R6
R2 R3 R7
1023 (no change)
[255]
[22,30,31,32]
[22,30,31,32,33,34]
CY7C451
CY7C453
CY7C454
Document #: 38-06033 Rev. *A Page 12 of 24
Notes:
35. W2 updates the flag to the Almost Full state by asserting PAFE. Because R1 occurs greater than tSKEW1 after W2, W2 does not recognize R1 when
updating the flag status. W3 includes R2 in the flag update because R2 occurs greater than tSKEW2 before W3. Note that W3 does not have to be
enabled to update flags.
36. T he dashed lines show W3 as a flag update write rather than an enabled write because ENW i s deasserted.
Switching Waveforms (continued)
Write to Almost Full Timing Diagram
COUNT 2030 2031 2031 2032
tFD tFD
tFD
ENABLED
WRITE ENABLED
WRITE ENABLED
WRITE ENABLED
WRITE
2032 2031 2033
[495] [496] [495] [495] [496] [497]
ENABLED
WRITE
2030
[494]
W1 W2 W3 W4
2030
[494] 2031
[495] 2032
[496]
ENABLED
READ ENABLED
READ
R1 R2
tSKEW1 tSKEW2
tFD
LOW
HIGH
CKW
ENW
HF
PAFE
CKR
ENR
E/F
Write to Almost Full Timing Diagram with Free-Running Clocks
COUNT 2031 2032 2030 2032
tSKEW1 tSKEW2
tFD tFD
tFD
ENABLED
WRITE ENABLED
WRITE ENABLED
WRITE ENABLED
WRITE
ENABLED
READ ENABLED
READ
2031 2031 2033
[495] [496] [495] [494] [495] [496] [497]
C451-17
CKW
CKR
ENW
ENR
PAFE
HF
E/F
C451-18
HIGH
LOW
W5
W1 W2 W3 W4 W5 W6
R2 R3 R6
R5R4R1
[494]
FLAG UPDATE
[22,27,30,35,36]
[22,27,30]
CY7C451
CY7C453
CY7C454
Document #: 38-06033 Rev. *A Page 13 of 24
Notes:
37. W2 is ignored because the FIFO is full (count = 4096[2048,512]). It is important to note that W3 is also ignored because R3, the first enabled read after full,
occurs less than tSKEW2 before W3. Therefore, the FIFO still appears full when W3 occurs. Because R3 occurs greater than tSKEW2 before W4, W4
includes R3 in the flag update.
Switching Waveforms (continued)
Write to Almost Full Timing Diagram with Write Flag Update Cycle and Free-Running Clocks
COUNT 2031 2032 2030 2032
tSKEW1 tSKEW2
tFD tFD
tFD
ENABLED
WRITE FLAG
UPDATE ENABLED
WRITE ENABLED
WRITE
2031 2031 2033
C451-19
ENABLED
WRITE
ENABLED
READ ENABLED
READ
WRITE
FLAG UPDATE CYCLE
[495] [496] [495] [494] [495] [496] [497]
CKW
CKR
ENW
ENR
PAFE
HF
E/F
Write to Full Flag Timing Diagram with Free-Running Clocks
tSKEW1 tSKEW2
tFD tFD
tFD
COUNT 2047 2048 2047 2048
ENABLED
WRITE ENABLED
WRITE
ENABLED
READ
CKW
ENW
CKR
ENR
PAFE
E/F
HF
FLAG
UPDATE IGNORED
WRITE
C451-20
IGNORED
WRITE IGNORED
WRITE WRITE
[511] [512] [511] [512]
LATENT CYCLE
HIGH
LOW
LOW
LOW
W1 W2 W3 W4 W5 W6 W7
R2 R3 R6
R5R4R1
R1 R4 R5 R6 R7
R2 R3
W1 W2 W3 W4 W5 W6
2030 (no change)
[494]
tSKEW2
[22,27,30]
[22,23,30,37]
CY7C451
CY7C453
CY7C454
Document #: 38-06033 Rev. *A Page 14 of 24
Notes:
38. In this example, the FIFO is assumed to be programmed to generate even parity.
39. If Q0 – 7 “new word” also has an even number of 1s, then PG stays LOW.
40. If Q0 – 7 “new word” also has an odd number of 1s, then PG stays HIGH.
Switching Waveforms (continued)
Even ParityGenerationTiming Diagram
tPG
PREVIOUS WORD:
EVEN NUMBER OF 1s NEW WORD
ODD NUMBER OF 1s
CKR
Q0–7
Q8/PG/PE
ENR
ENABLED READ DISABLED READ
C451-21
PREVIOUS WORD:
ODD NUMBER OF 1s NEW WORD
EVEN NUMBER OF 1s
ENABLED READ DISABLED READ
Even Parity GenerationTiming Diagram
tPG
CKR
Q0–7
Q8/PG/PE
ENR
C451-22
[38,39]
[38,40]
CY7C451
CY7C453
CY7C454
Document #: 38-06033 Rev. *A Page 15 of 24
Notes:
41. In this example, the FIFO is assumed to be programmed to check for even parity.
42. This example assumes that the time from the CKR rising edge to valid word M+1 > tA.
43. If ENR was HIG H around t he ri sing edge of CKR (i .e ., read disabl ed), t he val id dat a at th e far r igh t w ould o nce agai n be w ord M ins tea d of word M+1.
44. Clocks are free running in this case.
45. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR.
Switching Waveforms (continued)
WORD M:
EVEN NUMBER
OF “1”s
Even Parity Checking
Output Enable Timing
WRITE M
C451-23
F1
READ M
WRITE M+1 WRITE M+2
WORD M+ 1:
ODD NUMBER
OF “1”s
WORD M+ 2:
EVEN NUMBER
OF “1”s
READ M+1 READ M+2
tPE tPE
8 LSBs OF
WORD M+2
8 LSBs OF
WORD M+1
8 LSBs OF
WORD M
8 LSBs OF
WORD M-1
Q8/PG/
PE
CKW
CKR
ENW
ENR
D0–8
Q0–7
VALID DATA
WORD M
READ M+1
CKR
Q0–8
OE
ENR
tOHZtOE
tOLZ
VALID DATA
WORD M+1
C451-24
LOW
[41]
[42,43]
Retransmit Timing
ENR/ENW
FL/RT tPRT
tRTR
C451–25
E/F,HF,PAFE
[44, 45]
CY7C451
CY7C453
CY7C454
Document #: 38-06033 Rev. *A Page 16 of 24
Architecture
The CY7C451, CY7C453, and CY7C454 consist of an array
of 512/2048/4096 words of 9 bits each (implemented by an
array of dual-port RAM cells), a read pointer, a write pointer,
control s ignal s (CKR, CKW, ENR, ENW, MR, OE, FL/RT, XI,
XO), and flags (HF, E/F, PAFE ).
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Master Reset
(MR) cy cle. This cause s th e FI FO t o en ter t he Empty con-
diti on s ig ni fie d by E /F and PAFE being LOW and HF being
HIGH . All d ata out puts ( Q0 − 8) go low at the rising edge of
MR. In order for the FIFO to reset to its default state, a
falling edge must occur on MR and the us er mu st no t r e ad
or write while MR is LOW (unless ENR and ENW are HIGH
or unle ss the dev ice is be ing p rogra mmed). Upon comp le-
tion of the Master Reset cycle, all data outputs will go LOW
tAMR after MR is de as se rte d. All fl ag s are gu ara nteed t o b e
valid t MRF after MR is take n HI GH.
FIFO Operation
When the ENW signal is active (LOW), data pr esent on the
D0 − 8 pins is written into the FIFO on each rising edge of
the CKW signal. Similarly, when the ENR signal is active,
data in the FIFO memory will be presented on the Q0 − 8
outputs. N ew d ata wil l b e p r es en te d on ea ch risi ng ed ge o f
CKR while ENR is active. ENR must be set up tSEN before
CKR for it to be a valid read function. ENW must occur tSEN
before CKW for it to be a valid write function.
An output enable (OE ) pin is provided to tri-state the Q0 − 8
outputs when OE is not asserted. When OE is enabled,
data in t he o utp ut regi s ter w i ll b e av ai la bl e to Q0 − 8 outputs
after tO E. If devi ces are cas caded, th e OE function will only
outpu t data on the F IFO th at is read enable d.
The FIFO contains overflow circuitry to disallow additional
writes when the FIF O is f ull, and unde rflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q0 − 8 outputs
even af te r a ddi ti on al r ead s oc cur.
Programming
The CY7C451, CY7C453, and CY7C454 are programmed
during a master reset cycle. If MR and ENW are LOW, a
risin g edge on CKW wil l write D0 − 8 inpu ts into the pr ogram-
ming register. MR must be set up a minim um of tSMRP be-
fore the program write rising edge and held tHMRP after the
progr am wr it e fa ll in g e dg e. T he us er has t h e a bi li ty to a lso
perform a program read duri ng the ma ster reset c ycle. Th is
will o cc ur at the ris in g ed ge o f CK R w he n MR and EN R are
asserted. The program read must be performed a minimum
of tFTP after a program write, and the program word will be
available tAP after the read occurs. If a program write does
not occur, a program read may occur a minimum of tSMRP
after MR is asserted. This will read the default program
value.
When free- running clocks are tied to CKW and CKR, program-
ming can still occur during a master reset cycle with the adher-
ence to a few additional timing parameters. The enable pins
must be se t-up tSEN before the rising edge of CKW or CKR.
Hold times of tHEN must also be met for ENW and EN R.
Dat a present o n D0 − 5 duri ng a p rog ra m w ri te will de te rm in e
the distance from Empty (Full) that the Almost Empty (Al-
most Full) flags will become active. See Table 1 for a
descri pt io n o f th e si x p oss ib le FIF O stat es . P in 1 re fe r s to
the decimal equivalent of the binary number represented
by D0 − 5. Programming options for the CY7C451 and
CY7C453 are listed in Tab le 5. Programming resolution is
16 words for either device.
The programmable PAFE function is only valid when the
CY7C451/453/454 are not cascaded. If the user elects not
to program the FIFO’s flag s, the defa ult ( P=1) i s a s fo llows :
Almost Empty condition (Almost Full condition) is activated
when the CY7C451/453/454 contain 16 or less words
(empt y locati ons) .
Parity is programmed with the D6 − 8 bits. See Table 6 for a
summar y of the various pari ty pr ogramming options. D ata
present on D6 − 8 during a program write will determine
whether the FIFO will generate or check even/odd parity for
the data present on D0−8 thereafter. If the user elects not
to program the FIFO, the parity function is disabled. Flag
operation and parity are described in greater detail in sub-
sequen t sect ions .
Flag Operation
The CY7C451/453/454 provide three status pins when not
casc ade d. Th e thr e e pi ns , E /F, PAFE, an d H F, allow deco d-
ing of si x FIF O st at es ( Table 1). PAFE is not avai labl e whe n
FIFOs are cascaded for depth expansion. All flags are syn-
chronous, meaning that the change of states is relative to
one of the clocks (CKR or CKW , as appropriate. See Figure
1). The synchronous architecture guarantees some mini-
mum valid time for the flags. The Empty and Almost Empty
flag stat es are exc lusively up dated by eac h rising ed ge of
the read clock (CKR). For example, when the FIFO con-
tains 1 word, the next read (rising edge of CKR while
ENR=LOW) causes the flag pins to output a state that rep-
resents Empty. The Half Full, Almost Full, and Full flag
states are updated exclusively by the write clock (CKW).
For example, if the CY7C453 FIFO contains 2047 words
(2048 words indicate Full for the CY7C453), the next write
(risin g edge of CKW whil e ENW=LOW) ca uses the f lag pins
to output a state that is decoded as Full.
]
Table 1. Flag Truth Table[46].
E/F PAFE HF State
CY7C451 512 x 9
Number of Words
in FIFO
CY7C453 2K x 9
Number of Words
in FIFO
CY7C4 54 4K x 9
Number o f Words
in FIFO
0 0 1 Empty 0 0 0
1 0 1 Almost Empty 1⇒(16•P) 1 ⇒(16•P) 1 ⇒(16•P)
1 1 1 Less than or
Equal to Half Full (16•P)+1⇒256 (16•P)+1⇒1024 (16•P)+1⇒2048
CY7C451
CY7C453
CY7C454
Document #: 38-06033 Rev. *A Page 17 of 24
Flag Operation (conti nue d)
Since the flags denoting emptiness (Empty , Almost Empty) are
only updated by CKR and the flags signifying fullness (Half
Full, Almost Full, Full) are exclusively updated by CKW , careful
attention must be given to the flag operation. The user must
be aware that if a boundary (Empty, Almost Empty, Half Full,
Almost Full, or Full) is crossed due to an operation from a clock
that the flag is not synchronized to (i.e., CKW does not affect
Empty or Almost Empty), a flag update cycle is necessary to
represent the FIFO’s new state. The signal to which a flag is
not synchronized will be referred to as the opposite clock
(CKW is opposite clock for Empty and Almost Empty flags;
CKR is the opposite clock for Half Full, Almost Full, and Full
flags). Until a proper flag update cycle is executed, the syn-
chronous flags will not show the new state of the FIFO.
When upda ting f lags, the C Y7C451 /45 3/454 must make a d e-
cision as to w he ther or not the opp os ite clock wa s recogn ize d
when a clock updates the flag. For example (when updating
the Empt y fl ag), if a wri te oc cu rs at le ast tSKEW1 after a read,
the write is guaranteed not to be included when CKR up-
dates the flag. If a write occurs at least tSKEW2 before a
read, the write is guaranteed to be included when CKR
updates flag. If a write occurs within tSKEW1/tSKEW2 after or
before CKR, then the decision of whether or not to include
the wr ite when th e fla g is up date d by C KR is ar bit rary.
The update cycle for non-boundary flags (Almost Empty, Half
Full, Almost Full) is different from that used to update the
boundary flags (Empty, Full). Both operations are described
below.
Boundary and Non-Boundary Flags
Boundary Flags (Empty)
The Empty flag is synchronized to the CKR signal (i.e., the
Empty flag can only be updated by a clock pulse on the CKR
pin). An empty FIFO that is written to w ill be described with an
Empty flag state until a rising edge is presented to the CKR
pin. When making the transition from Empty to Almost Empty
(or Empty to Less than or Equal to Half Full), a clock cycle on
the CKR is necessary to update the flags to the current state.
In such a state (flags showing Empty even though data has
been w ritten to the FIF O), two read cycles are req uired to read
data out of FIFO. Th e first re ad serve s only to update the flag s
to the Almost Empty or Less than or Equal to Half Full state,
while the secon d read o utput s the dat a. This first r ead cycle i s
known as the latent or flag update cycle because it does not
affect the data in the FIFO or the count (number of words in
FIFO). It s im ply d eas se rt s the Emp t y flag. The flag is upd ate d
regardless of the EN R state. Therefore, the update occurs
even when ENR is unasserted (HI GH), so that a valid read
is not necessary to update the flags to correctly describe
the FIFO. In this example, the write must occur at least
tSKEW2 before the flag update cycle in order for the FIFO to
guara nt ee th at t he wri t e wil l b e in cl ud ed in th e coun t wh en
CKR updates the flags. When a free-running clock is con-
nected to CKR, the flag is updated each cycle. Table 2
show s an exam ple of a se quenc e of opera tions th at updat e
the Empty flag.
Boundary Flags (Full)
The Full flag is synchronized to the CKW signal (i.e., the Full
flag can on ly be upd ate d by a clo ck pul se on the C KW pi n). A
full FIFO that is read will be described with a Full flag until a
rising edge is presented to the CKW pin. When making the
transiti on from Fu ll to Al most Full (o r Full to Grea ter Tha n Half
Full), a clock cycle on the CKW is necessary to update the
flags to the current state. In such a state (flags showing Full
even through data has been read from the FIFO), two write
cycles are required to write data into the FIFO. The first write
serves only to update the flags to the Almost Full or Greater
1 1 0 Greater than Half
Full 257⇒511−(16•P) 1025⇒2047−(16•P) 2049 ⇒ 4095−(16•P)
1 0 0 Almost Full 512− (16•P) ⇒ 511 2048−(16•P) ⇒ 2047 4096−(16•P) ⇒4095
0 0 0 Full 512 2048 4096
Notes:
46. P is the decimal value of the binary number represented by D0 - 5. When programming the CY7C451/453/454, P can have values from 0 to 15 for the
CY7C451 and values from 0 to 63 for the CY7C45 3 and CY 7C454. See Table 5 for D0 - 5 representation. P = 0 signifies Almost Empty state = Empty
state.
Table 1. Flag Truth Table[46].
E/F PAFE HF State
CY7C451 512 x 9
Number of Words
in FIFO
CY7C453 2K x 9
Number of Words
in FIFO
CY7C4 54 4K x 9
Number o f Words
in FIFO
Figure 1. Flag Logic Diagram.
D Q
CKR
E
DQ
CKW
F
DQ
CKR
PAE
DQ
CKW
PAF
DQ
CKW
HF
INTERNAL LOGIC
HF
PAFE
E/F
PIN
CY7C451
CY7C453
CY7C454
Document #: 38-06033 Rev. *A Page 18 of 24
Than Half Full state, while the second write inputs the data.
This fi rst writ e cycle is kn own as th e latent or flag u pdate cy cle
because it does not affect the data in the FIFO or the count
(number of words in the FIFO). It simply deasserts the Full flag.
The flag is updated regardless of the E N W state. Therefore,
the update occurs even when ENW is deasserted (HIGH),
so that a valid write is not necessary to update the flags to
corr ectly d esc ribe t he FIF O. In this exam ple , the re ad m ust
occur at least tSKEW2 before t he flag updat e cycle in order
for the FIFO to guarantee that the read will be included in
the count when CKW updates the flags. When a free-run-
ning clo ck i s co nnec te d t o CK W, the fl ag upd ate s ea ch cy-
cle. Full flag operation is similar to the Empty flag operation
described in Table 2.
Non-Boundary Flags (Almost Empty, Half Full, Almost Full)
The CY7C451/453/454 feature programmable Almost Empty
and Almo st Full flags. Each flag can b e programmed a sp ecific
distance from the corresponding boundary flags (Empty or
Full). The flags can be programmed to be activated at the
Empty or Full boundary, or at a distance of up to 1008
words/locations for the CY7C453 and CY7C454 (240
words/ location s for the CY7C 451) from the Empty/Fu ll bound-
ary. The programming resolution is 16 words/locations. When
the FIFO con t ai ns the num be r of w o rds or fewer for whic h th e
flags hav e been programm ed, the P AFE flag will be asserted
signifying that the FIFO is Almost Empty. When the FIFO is
within that same number of empty locations from being Full,
the PAFE will also be asserted signifying that the FIFO is
Almost Full. The HF flag is decoded to distinguish the
states.
The default distance (CY7C451/453/454 not programmed)
from where PAFE becom es acti ve to the bo unda ry ( Empty,
Full) is 16 words/locations. The Almost Full and Almost
Empty flags can be programmed so that they are only ac-
tive at F ul l a nd Emp ty bo un da rie s. H owe ve r, the op era ti on
will remain consistent with the non-boundary flag operation
that is discusse d bel ow.
Almost Empty is only updated by CKR while Half Full and Al-
most Full are updated by CKW. Non-boundary flags employ
flag update cycles si mi lar to the boundary fla g la ten t cy cl es in
order t o up dat e the FIF O s t at us . For e xa mp le, if th e FI FO jus t
reaches the Greater than Half Full state, and then two words
are r ead fr om the FIFO , a wri te cl ock (CK W) wi ll be re quir ed
to update the flags to the Less than Half Full state. However,
unlike the boundary flag latent cycle, the state of the enable
pin (ENW in this case) affects the operation. Therefore,
set-up and hold times for the enable pins must be met (tSEN
and tHEN). If the enable pin is active during the flag update
cycle, the count and data are updated in addition to PAFE
and HF. If the enable pin is not asserted during the flag
update cycle, only the flags are updated. Table 3 and Table
4 show an examp le of a sequence of operations that update
the Almost Empty and Almost Full flags.
Programmable Parity
The CY7C451/453/454 also features even or odd parity check-
ing and generation. D6 − 8 are used during a program wri te
to describe the parity option desired. Table 6 gives a sum-
mary of prog rammable parity options. If the user elects not
to pr og ram th e de vi ce , then par i ty is d isa bl ed. P ari ty i nf or -
mation is provided on one multi-mode output pin
(Q8/PG/PE). The three possible modes are described in
the following paragraphs. Regardless of the mode select-
ed, the O E pin ret ai ns thre e- st ate co ntrol of all 9 Q0 − 8 bit s.
Parity Disabled (Q8 mode)
When parity is disabled (or user does not program parity op-
tion) the CY7C451/453/454 stores all 9 bits present on D 0 − 8
inputs internally and will output all 9 bits on Q0 − 8 Parity
Generate (PG mode).
This mode is used to generate either even or odd parity (as
progra mmed ) from D 0 − 7. D8 input is ignored. The parity bit
is sto red inte rnally as D8 an d during a subs equent read w ill
be available on the PG pin along with the data word from
which the parity was generated (Q0 − 7). For example, if
Table 2. Empty Flag (Boundary Flag) Operation Example.
Status B efore Operation
Operation
Status After Operat ion
Comments
Current
State of
FIFO E/F AFE HF
Number
of Words
in FIFO
Next
State
of FIFO E/F AFE HF
Number
of words
in FIFO
Empty 0 0 1 0 Write
(ENW = 0) Empty 0 0 1 1 Write
Empty 0 0 1 1 Write
(ENW = 0) Empty 0 0 1 2 Write
Empty 0 0 1 2 Read
(ENR = X) AE 1 0 1 2 Flag Update
AE 1 0 1 2 Read
(ENR = 0) AE 1 0 1 1 Read
AE 1 0 1 1 Read
(ENR = 0) Empty 0 0 1 0 Read (transition from
Almost Empty to Empty)
Empty 0 0 1 0 Write
(ENR = 0) Empty 0 0 1 1 Write
Empty 1 0 1 1 Read
(ENR = X) AE 1 0 1 1 Flag Update
AE 1 0 1 1 Read
(ENR = 0) Empty 0 0 1 0 Read (transition from
Almost Empty to Empty)
CY7C451
CY7C453
CY7C454
Document #: 38-06033 Rev. *A Page 19 of 24
pari ty genera te is se t to ODD and th e D0 − 7 inputs have an
EVEN nu mber of 1s, P G will be HIGH.
Parity Check (PE mode )
If the CY7C451/453/454 is programmed for parity checking,
the FIFO will compare the parity of D0 − 8 with the program
register. If the expected parity is present, D8 will be set
HIGH internally. When this word is later read, PE will be
HIGH. If a parity error occurs, D8 will be set LOW internally .
When this wo rd i s l ater re ad, P E will be LOW . For example,
if parity check is set to odd and D0 − 8 have an even number
of 1s, a parity error occurs. When that word is later read,
PE will be asserted (LOW).
Retransmit
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary.
The Retransmit (RT) input is active in the standalone and width
expansion modes. The retransmit feature is intended for use
when a numb er of wr ites equa l to or less than t he dep th of th e
FIFO have occurred sinc e the last MR cycle. A LOW pulse on RT
resets the internal read pointer to the first physical location of the
FIFO. WCLK and RCLK may be free running but must be disabled
during and tRTR after the retransmit pulse. With every valid read cycle
after retransmit, previously accessed data is read and the read point-
er is incremented until it is equal to the write pointer. Flags are gov-
erned by the relative locations of the read and write pointers and are
updated during a retransmit cycle. Data written to the FIFO after ac-
tivation of RT are transmitted also.
The full depth of the FIFO can be repeatedly retransmitted.
Width Expansion Modes
During width expansion all flags (programmable and nonpro-
grammable) are available. The CY7C451/453/454 can be ex-
panded in width to provide word width greater than nine in
increments of nine. During width expansion mode all control
line i nputs are common. Whe n the FIFO is being read near the
Empty (Full) boundary, it is important to note that both sets of
flags should be checked to see if they have been updated to
the No t Em pty (N ot F ull ) co nd itio n to insu re th at t he n ex t rea d
(write) will perform the same operation on all devices.
Checking all set s of flags is critical so that data is no t read from
the FIFOs “staggered” by one clock cycle. This situation could
occur when the first write to an empty FIFO and a read are very
close together. If the read occurs less than tSKEW2 after the
first wri te t o tw o widt h-ex panded dev ices, A and B, d evice
A may go Almost Empty (read recognized as flag update)
whil e devic e B s ta ys Emp ty (re ad ig nored ). Thi s oc curs be -
cause a read can be either recognized or ignored if it oc-
curs within tSKEW2 of a write. The next read cycle outputs
the first half of the first word on device A while device B
updates its flags to Almost Empty. Subsequent reads will
continue to output “staggered” data assuming more data
has been wri tten t o the FIFO s.
Depth Expansion Mode
The CY7C451/453/454 can operate up to 83.3 MHz when cas-
caded. Depth expansion is accomplished by connecting ex-
pansion out (XO) of the first device to expansion in (XI) of
the next device, wit h XO of the last device connected to XI
of the fi rs t de v ic e. The first devi ce ha s i ts first load pin (FL)
tied to VSS while all other devices must have this pin tied
to VCC. The first device will be the first to be write and read
enable d aft er a maste r reset .
Proper ope ration a lso requir es that all casc aded dev ices hav e
common CKW, CKR, ENW, ENR , D0 − 8, Q0 − 8, and MR pins.
When cascaded, one device at a time will be read enabled
so as to avoid bus contention. By asserting XO when ap-
propriate, the currently enabled FIFO alerts the next FIFO
that it should be enable d. The next rising edge on C KR put s
Q0 − 8 outputs of the first device into a high-impedance
state. This occurs regardless of the state of ENR or the next
FIFO’s Empty f lag. Ther efore, if the next FIF O is empty or
undergoing a latent cycle, the Q0 − 8 bus will be in a high-im-
pedanc e state until the next devic e receives its first read,
which brings its data to the Q0 − 8 bus.
Program Write/Read of Cascaded Devices
Programming of cascaded FIFOs is the same as for a single
device. Because the controls of the FIFOs are in parallel when
cascaded , they all get programme d the same. During program
mode, only parity is programmed since Almost Full and Almost
Empty flags are not available when CY7C451/453/454 are
cascaded. Only the “first device” (FIFO with FL=LOW) will
output its program register contents on Q0 − 8 du ring a pr o-
gram read. Q0 − 8 of all other devices will remain in a
high- impe dance stat e to av oid b us conte ntio n.
CY7C451
CY7C453
CY7C454
Document #: 38-06033 Rev. *A Page 20 of 24
Figure 2. Depth Expansion with CY7C451/3/4.
Table 3. Almost Empty Flag (Non-Boundary Flag) Operation Example[47] .
Status Before Operation Status After Operation
Current
State of
FIFO E/F AFE HF
Num-
ber of
Words
in FIFO Operation
Next
State
of FIFO E/F PAFE HF
Number
of words
in FIFO Comments
AE 1 0 1 32 Write
(ENW = 0) AE 101 33 Write
AE 1 0 1 33 Write
(ENW = 0) AE 101 34 Write
AE 1 0 1 34 Read
(ENR = 0) <HF 111 33 Flag Upd ate and Read
<HF 1 1 1 33 Read
(ENR = 1) <HF 111 33 Ignored Read
(ENR = 1)
<HF 1 1 1 33 Read
(ENR = 0) AE 101 32 Read (Transition from
<HF to AE)
Notes:
47. Applies to both CY7C451, CY7C453, and CY7C454 operations when devices are programmed so that Almost Empty becomes active when the FIFO contains
32 or fewer words.
MR ENR
E/F
DATA IN DATA OUT
D0–8
CKW
ENW
Q0–8
CKR
D0–8
CKW
ENW
Q0–8
CKR
ENR
MR
Q0–8
D0–8
MR PAFE/XO
XI
PAFE/XO
XI
VCC
VSS
HF
FL/RT
HF
E/F
FL/RT
CY7C451/3/4
CY7C451/3/4
CKW CKR
ENR
OE
ENW
OE
FULL EMPTY
OE
CY7C451
CY7C453
CY7C454
Document #: 38-06033 Rev. *A Page 21 of 24
.]
Table 4. Almost Full Flag Operation Example[48] .
Operation State
of FI FO E/F PAFE HF
Number of
Words in
FIFO
CY7C451
Number of
Words in
FIFO
CY7C453
Number
of Words
in FIFO
CY7C454 Comments
Read
(ENR=0) Current AF 1 0 0 496 2032 4080 Read
Next AF 1 0 0 495 2031 4079
Read
(ENR=0) Current AF 1 0 0 495 2031 4079 Read
Next AF 1 0 0 494 2030 4078
Write
(ENW=1) Current AF 1 0 0 494 2030 4078 Flag Update
Next AF 1 1 0 494 2030 4078
Write
(ENW=0) Current >HF 1 1 0 494 2030 4078 Write
Next >HF 1 1 0 495 2031 4079
Write
(ENW =0) Current >HF 1 1 0 495 2031 4079 Write (Transition
from >HF to A F)
Next >HF 1 0 0 496 2032 4080
Table 5. Programmable Almost Full/Almost Empty Options - CY7C451/CY7C453/CY7C454[49] .
D5 D4 D3 D2 D1 D0 PAFE Active when CY7C451/453/454 is: P[50]
000000Completely Full and Empty. 0
00000116 or less locations from Empty/Full (default) 1
00001032 or less locations from Empty/Full 2
00001148 or less locations from Empty/Full 3
001110224 or less locations from Empty/Full 14
001111240 or less locations from Empty/Full 15
.
.
..
.
..
.
..
.
..
.
..
.
..
.
..
.
.
.
.
..
.
..
.
..
.
..
.
..
.
..
.
..
.
.
111110992 or less locations from Empty/Full 62
1111111008 or less locations from Empty/Full 63
Table 6. Programmable Parity Options.
D8 D7 D6 Condition
0 X X Parity disabled.
100Generate even parity on PG output pin.
101Genera te odd p ari ty on PG output pin .
110Check for even parity. Indicate error on PE output pin.
111Check for odd parity. Indicate error on PE output pin.
Notes:
48. Programmed so that Almost Full becomes active when the FIFO contains 16 or less empty locations.
49. D4 and D5 are don’t care for CY7C451.
50. Referenced in Table 1.
CY7C451
CY7C453
CY7C454
Document #: 38-06033 Rev. *A Page 22 of 24
Ordering Information
512x9 Clocked FIFO
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
12 CY7C451-12JC J65 32-Lead Plastic Lead ed Ch ip Carrier Commercial
CY7C451-12JI J65 32-Lead Plastic Lead ed Ch ip Carrier Industrial
14 CY7C451-14JC J65 32-Lead Plastic Lead ed Ch ip Carrier Commercial
CY7C451-14JI J65 32-Lead Plastic Lead ed Ch ip Carrier Industrial
20 CY7C451-20JC J65 32-Lead Plastic Lead ed Ch ip Carrier Commercial
CY7C451-20JI J65 32-Lead Plastic Lead ed Ch ip Carrier Industrial
30 CY7C451-30JC J65 32-Lead Plastic Lead ed Ch ip Carrier Commercial
CY7C451-30JI J65 32-Lead Plastic Lead ed Ch ip Carrier Industrial
2Kx9 Clocked FIFO
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
12 CY7C453-12JC J65 32-Lead Plastic Lead ed Ch ip Carrier Commercial
CY7C453-12JI J65 32-Lead Plastic Lead ed Ch ip Carrier Industrial
14 CY7C453-14JC J65 32-Lead Plastic Lead ed Ch ip Carrier Commercial
CY7C453-14JI J65 32-Lead Plastic Lead ed Ch ip Carrier Industrial
20 CY7C453-20JC J65 32-Lead Plastic Lead ed Ch ip Carrier Commercial
CY7C453-20JI J65 32-Lead Plastic Lead ed Ch ip Carrier Industrial
30 CY7C453-30JC J65 32-Lead Plastic Lead ed Ch ip Carrier Commercial
CY7C453-30JI J65 32-Lead Plastic Lead ed Ch ip Carrier Industrial
4Kx9 Clocked FIFO
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
12 CY7C454-12JC J65 32-Lead Plastic Lead ed Ch ip Carrier Commercial
CY7C454-12JI J65 32-Lead Plastic Lead ed Ch ip Carrier Industrial
14 CY7C454-14JC J65 32-Lead Plastic Lead ed Ch ip Carrier Commercial
CY7C454-14JI J65 32-Lead Plastic Lead ed Ch ip Carrier Industrial
20 CY7C454-20JC J65 32-Lead Plastic Lead ed Ch ip Carrier Commercial
CY7C454-20JI J65 32-Lead Plastic Lead ed Ch ip Carrier Industrial
30 CY7C454-30JC J65 32-Lead Plastic Lead ed Ch ip Carrier Commercial
CY7C454-30JI J65 32-Lead Plastic Lead ed Ch ip Carrier Industrial
CY7C451
CY7C453
CY7C454
Document #: 38-06033 Rev. *A Page 23 of 24
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any ci rcuitry other th an circuitry embod ied in a Cypr ess Semiconductor pr oduct. Nor does it convey or imply any licen se under p atent or other rights. Cy press Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
Package Diagram
32-Lead Plastic LeadedChipCarrier J65
CY7C451
CY7C453
CY7C454
Document #: 38-06033 Rev. *A Page 24 of 24
Document Title: CY7C451, CY7C453, CY7C454 512 x 9, 2K x 9, and 4K x 9, Cascadable Clocked FIFOs with Program-
mable Flags
Document Number: 38-06033
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 110174 09/29/01 SZV Change from Spec number: 38-00125 to 38-06033
*A 122284 12/27/02 RBI Power up requirements added to Maximum Ratings Information
