CY7C43643-7AC - Cypress Semiconductor

CY7C43643

CY7C43663

CY7C43683

1K/4K/ 16K x36 Unid irec tio nal

Synchronous FIFO w/ Bus Matching

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

July 28, 2000

Features

• High-speed, lo w-power, Unidi rectional , Fi rst-i n Fir st-

out (FI FO ) mem o ries w/bus matchi ng capabilities

• 1Kx36 (CY7C43643)

• 4Kx36 (CY7C43663)

• 16K x36 (CY7C43683)

• 0.35-micron CMOS for optimum speed/po wer

• High- speed 133-MHz oper ati on (7. 5 ns read/writ e cycl e

times)

•Low power

—ICC = 100 mA

—ISB = 10 mA

• Fully asynchr onous and simultaneous read and write

operati on permitted

• Mailbox bypass register for each FIFO

• Parallel and Serial Programmable Almost Full and

Almost Empty flags

• Retransmit function

• Standard or FWFT mode user selectable

• Partial Reset

• Big or Little Endian for m at for word or b yte bus sizes

• 128-pin TQFP packaging

• Easily expandable in width and depth

Logic Block Dia gra m

Port A

Control

Logic Port B

Control

Logic

Mail1

Input

Output

Write

Pointer Read

Pointer

Status

Flag Logic

Programmable

Flag Offset Timing

Mode

1K/4K/16K

Dual Ported

Memory

Mail2

FIFO,

Mail1

CLKA

CSA

W/RA

ENA

MBA

MRS1

PRS

FF/IR

SPM

FS0/SD

FS1/SEN

A0–35

MBF2

BE/FWFT

B0–35

CLKB

CSB

W/RB

ENB

MBB

SIZE

EF/OR

MBF1

Mail2

Reset

Logic

Bus Matching

MRS2

Registers

x36

CY7C43643

CY7C43663

CY7C43683

CY7C43643

CY7C43663

CY7C43683

TQFP

Top View

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

FS0/SD

MRS2

FS1/SEN

GND

MRS1

MBA

MBF2

VCC

PRS

FF/IR

CSA

ENB

W/RB

CSB

GND

EF/OR

VCC

MBF1

MBB

102

101

100

B30

B26

B27

B28

B29

B31

GND

B32

B33

B34

B35

VCC

CLKB

GND

SIZE

B16

B17

B18

B19

B20

B21

B22

B23

GND

B24

B25

GND

VCC

SPM

GND

VCC

GND

VCC

A29

GND

A30

A31

A32

A34

A35

GND

CLKA

ENA

W/RA

A12

A20

GND

A18

A19

A21

VCC

A22

GND

BE/FWFT

A23

A24

A25

A26

A27

A28

A33

B12

B10

B11

GND

B13

B14

B15

VCC

A10

A11

GND

A13

A14

A15

A16

A17

Pin Configura tion

CY7C43643

CY7C43663

CY7C43683

Functional Description

The CY7C436x3 is a monolithic, high-speed, low-power,

CMOS Unidirectional Synchronous (clocked) FIFO memory

which su pports clock frequenci es up to 13 3 MHz an d has read

access times as fast as 6 ns. Two independent 1K/4K/16K x

36 dual-port SRAM FIFOs on board each chip buffer data in

opposite directions. FIFO data on Por t B can be output in 36-

bit, 18-b it , or 9-bit formats with a choice of Big or Lit tl e Endian

configurations.

The CY7C436x3 is a synchronous (clocked) FIFO, meaning

each port employs a synchronou s int erface. All data transfers

through a port are gated to the LOW-to-HIGH transition of a

por t clock by enable signals. The clocks for each port are in-

dependent of one another and can be asynchronous or coin-

cident. The enables for each port are arranged to provide a

simple unidirectional interface between mi croprocessors and/

or buses with synchronous cont rol .

Commu nicat ion betw een ea ch port may bypa ss t he FIFOs via

two mailbox registers. The mailbox registers’ width matches

the sel ected P ort B bu s width. Each mai lbo x register has a flag

(MBF1 and MBF2) to sign al when new mai l has been stored.

Two kinds of reset are available on the CY7C436x3: Master

Reset and P arti al Reset . Master Rese t init ializ es t he read and

write pointers to t he first location of the memor y array, config-

ures the FIFO for Big or Little Endian byte arrangement and

selects seri al f lag programmi ng, parallel flag prog ramming , or

one of the three possible default flag offset settings, 8, 16, or

64. The FIFO also has two Master Reset pins, MRS1 and

MRS2.

Partial Reset also sets the read and write pointers to the first

location of the mem ory. Unlike Master Reset, any set ti ngs ex-

ist in g prior to P artial Re set (i.e ., prog ramming method and pa r-

tial flag default offsets) are retained. Partial Reset is useful

sinc e it permits f lushi ng of the FI FO mem ory witho ut chang in g

any conf iguration settin gs. T he FIFO has its own independent

Pa rt ial Re set pin, P R S.

The CY7C4 36x3 ha ve two modes of o peration: In the CY Stan-

dard Mode, the first word written to an empty FIFO is deposited

into the memory array. A read operation is required to access

that word (along with all other words residing in memory). In

the Fi rst-Word Fall-Th rough Mode (FWFT), the first long-word

(36-bit wide) written t o an empty FIFO appears automatically

on the outputs, no read operation required (nevertheless, ac-

cessin g subse quent words doe s neces sitat e a f ormal read re -

quest). The state of the BE/FWFT pin during FIFO operation

determines t he mod e in use.

The FIFO has a com bined Empty/Output Ready flag (EF/OR)

and a combined Full/I nput Ready flag (FF/IR). The EF and FF

funct ions a re selected in the CY Standard Mode. EF i ndicat es

whether the me mory is f ull or not. The IR and OR functions ar e

selected in the First-Word Fall-Through Mode. IR indicates

whether or not the FIFO has available memory locations. OR

show s whether the FIFO has dat a av ai labl e f or re ading or not .

It marks the presence of valid data on the outputs. (See foot-

note #18)

The FIFO has a program m able Almost Empty fl ag (AE) and a

programmab le Almost Ful l flag (AF). AE indicates when a se-

lected number of words written to FIFO memory achieve a

predeter mined “almost empty state.” AF indicates when a se-

lected number of words written to the memory achieve a pre-

determined “almost full state.” (See f ootnote #34)

IR and AF are synchronized to the port clock that writes data

into its array. OR and AE are synchronized to the port clock

that r eads data f rom it s array. Progr ammab le of fset f or AE and

AF can be l oaded in parallel using Por t A or in serial via the

SD input. Three default offset settings are also provided. The

AE threshold can be set at 8, 16, or 64 locations from the

empty boundary and AF t hreshold can be set at 8, 16, or 64

locations from the full boundary. All these choices are made

using the FS0 and FS1 inputs during Master Reset.

Two or more devices m ay be used in parallel to create wider

data paths. If any time the FIFO is not actively performing a

function, the chip will automatically power down. During the

power-down state, supply current consumption (ICC) is at a

minimum . In itia ting a ny oper ati on ( by act iv at ing con trol inputs )

will immediately take the de vice out of the power-down st ate.

The CY7C436x3 are characterized for operation from 0°C to

70°C commercial, and from –40°C to 85°C industrial. Input

ESD protec tion is gr eat er tha n 2001V, and latch -up is pr e v ent -

ed by the use of guard rings.

Selection G uide

CY7C43643/63/83

–7CY7C43643/63/83

–10 CY7C43643/63/83

–15

Maximum Frequency (MHz) 133 100 66.7

Maximum Access Time (ns) 6 8 10

Minimum C ycle Time (ns) 7.5 10 15

Minimum Data or Enable Set-Up (ns) 3 4 5

Minimum Data or Enable Hold (ns) 0 0 0

Maximum Flag Delay (ns) 6 8 8

Active Power Supply

Current (ICC1) (mA ) Commercial 100 100 100

Industrial 100

CY7C43643 CY7C43663 CY7C43683

Density 1K x 36 4K x 36 16K x 36

Package 128 TQFP 128 TQFP 128 TQFP

CY7C43643

CY7C43663

CY7C43683

Pin Definitions

Signal Name Description I/O Function

A0–35 Port A Data I 36-bit unidirecti onal data port fo r si de A.

AE Almost Empty

Flag (Port B) O Programmable Al m ost Empt y flag sy nchronized to CLKA. It is LOW when the number

of words i n the FI FO 2 is less than or equal to the value in the Almost Em pty A offset

regist er, X. (See footnote #.)

AF Almost Full Flag O Programmable Al mo st Full fl ag synch ronized to CLKA. It i s LOW when the number of

empty loc ati ons in the FIFO is less tha n or eq ual to the v alue in the Almos t Full A offset

regist er, Y. (See foot note #.)

B0–35 Port B Data O 36-bit unidirectional data port for side B.

BE/FWFT Big Endi an/

First-W ord Fall-

Through Select

I This is a dual-purpose pi n. During Mas ter Reset, a HI GH on BE will selec t Big Endi an

operat ion. In this cas e, dependi ng on the bus siz e, the most significant byte o r word on

P ort A is transferred to Port B first . A LO W on BE wil l sel ect Little Endi an oper ation. In

this c ase, t he leas t signi fic ant b yte or w ord on P ort A is tr ansferred to Port B fir st. After

Master Res et, this pi n selects t he timing mode. A HI GH on FWFT se lects CY Sta ndard

Mode , a LO W sel ect s Firs t-W ord F al l-Thr ough Mode . Once th e timi ng mode h as bee n

selected, the level on FWFT must be static throughout device operation.

BM Bus Match

Select (Port B) I A HI GH on this pin enab l es eith er byt e or word bus width on Port B , dependi ng on the

state of SIZE. A LOW s elects lon g-word operation. BM works wit h SIZE and BE to

select the bus siz e and endian arrangement for Port B. The level of BM must be static

throughout device operation.

CLKA P ort A Clock I CLKA is a cont inuous c lock that synchroniz es all data transf ers t hrough P ort A and can

be asynchronous or coincident to CLKB. FF/IR and AF are all synchronized to the LOW-

to- HIGH transiti o n o f CLKA.

CLKB P ort B Clock I CLKB is a conti nuous cl ock that synchroni zes all data tr ansfer s through Port B and ca n

be asynchronous or coincident to CLKA. FB/IR, E F /OR, AF, and AE are all synchro-

nized to the LOW-to-H IGH tr ansiti on of CLKB.

CSA Port A Chip

Select ICSA must be LO W to enable a LOW-to HIGH transi tion of CLKA to read or write on

Port A. The A0–35 outputs ar e in the high-impedan ce state when CSA is HIGH .

CSB Port B Chip

Select ICSB must be LO W to enable a LOW-to HIGH transi tion of CLKB to read or write on

Port B. The B0–35 out puts are in the high-i mp edance state when CSB is HI GH.

EF/OR Empty/Output

Ready Flag

(Por t B)

O This is a dual-f unction pin. In the CY Standard M ode, the EF functi on is selected. EF

indicates whether or not the FIFO memory is empty . In the FWFT mode, the OR function

is selected. OR indicates the presence of valid data on A0–35 output s, a vailab le for

reading. EF/OR is syn chroniz ed to the LOW -to-HI GH transi tion of CLKB . ( See fo otnote

#34.)

ENA P ort A Enable I ENA m ust be HIGH t o enab le a LOW- to-HIGH t ransi tion of CLKA to r ead or write dat a

on Por t A.

ENB P ort B Enable I ENB m ust be HIGH t o enab le a LOW- to-HIGH t ransi tion of CLKB to r ead or write dat a

on Por t B.

FF/IR Port B Full/Input

Ready Flag O This is a dual-f unction pin. In the CY Standard Mode, the FF fun ction is selected. FF

indic ates whether or not the FIFO m emory is full . In the FWFT mode, t he IR function

is sele cted. I R i ndicat es whether or not the re is spac e a vai lab le f or writing to th e FIFO

memory. F F/IR is synchronized to the LOW-to-HIGH tr ansition of CLKA.

FS1/SEN Flag Offset

Select 1/ Seri al

Enable

I FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset regist er program-

ming. During M aster Res et, FS1/ SEN and FS0/ SD, toge ther wi th SPM, sel ect the f lag

offset programming method. Three offset register programming methods are available:

automaticall y load one of thr ee preset values (8, 16, or 64), parallel load from Port A,

and serial load. When s erial load i s select ed f or flag of fset r egist er prog ram ming, FS1/

SEN is used as an enable synchronous to th e LOW -to-HIGH tran sition of CLKA. When

FS1/SEN is LOW, a rising edge on CLKA loads the bit prese nt on FS0/ SD int o the X

and Y regi sters . The numbe r of bit wri tes r equire d t o progr am the o ff set re gister s is 2 0

for the CY7C43643, 24 for the CY7C43663, and 28 for the CY7C43683. The first bit

wri te stores t he Y-register MSB and the last bit write stores the X-r egister LSB.

FS0/SD Flag Offset

Select 0/ Seri al

Data

CY7C43643

CY7C43663

CY7C43683

MBA Port A Mailbox

Select I A HIGH level on MBA chooses a mailbox reg is ter for a Port A read o r write operation.

MBB Port B Mailbox

Select I A HIGH level on MBB chooses a mailbox reg is ter for a Port B read o r write operation.

When a read o peratio n is pe rformed on P ort B , a HIGH le vel on MBB selects dat a from

the Mail1 register for output and a LOW level selects FIFO output regis ter data for

output. Data can only be written into Mai l 2 reg ister through P ort B (MBB HIGH) and

not into the FIFO memory.

MBF1 Mail1 Regi ster

Flag OMBF1 is set LOW by a LO W-to-HI G H tr ansition of CLKA that writes dat a to th e Mail1

regist er. Writes to the Mail1 register are inhi bited whil e MBF1 is LO W. MBF1 is se t

HIGH by a LOW-to-HIG H transi tion of CLKB when a Port B read is select ed and MBB

is HIGH. MBF1 is set HIGH f ollowing either a Master or Partial Rese t.

MBF2 Mail2 Regi ster

Flag OMBF2 is set LOW by a LO W-to-HI G H tr ansition of CLKB that writes dat a to th e Mail2

regist er. Writes to the Mail2 register are inhi bited whil e MBF2 is LO W. MBF2 is se t

HIGH by a LOW-to-HIG H transi tion of CLKA when a Port A read is select ed and MBA

is HIGH. MBF2 is set HIGH f ollowing eit her a Master or Partial Reset of FIFO2.

MRS1 Maste r Reset I A LOW on thi s pin initializ es the FIFO read and write pointers to the first locat ion of

memory and sets the P ort B output register to all zeroes. A LOW pulse on MRS1 selects

the programming method (serial or parallel) and one of three programmable flag def ault

offset s. It al so configures Port B fo r bus size and endian arra ngement. Four LOW-to-

HIGH tr ansitions o f CLKA and four LO W-to- HIGH trans it ions of CLKB must occur while

MRS1 is LOW.

MRS2 Maste r Reset I A LOW on thi s pin init ializ es the Mail2 register.

PRS P artial Reset I A LOW on thi s pin initializ es the FIFO read and write pointers to the first locat ion of

memory and sets the Po rt B output register to all z eroes . During Partial Reset, the

current ly selected bus siz e, endian arrangem ent, program ming method (serial or par-

allel), and programmable fl ag settings are all retained.

RT Retran smit I A LOW st r obe on t his pi n will re tran smit data on the FIFO. This is achieved b y bringing

the read pointer bac k to loc ation zer o. T he user will still need to perf orm r ead operat ion

to retransmit the dat a. Retransmit func tion appli es to CY st andard mode only.

SIZE Bus Size Sel ect I A HIGH on thi s pin when BM is HIGH selects byte bus (9-bit ) si ze on P ort B. A LOW

on this pin when BM is HIGH selects wor d (18-bit) bus size. SIZE works wit h BM and

BE to select the bus size and endian arrangem ent for Port B. The level of SIZE mus t

be static throughout device operation.

SPM Serial

Programming I A LOW on this pin se le cts serial programming of pa rtial fl ag offsets. A HIGH on this pi n

selects paral lel programmi ng or default off sets (8, 16, or 64).

W/RA Port A Write/

Read Select I A HI GH selects a wri te operation and a LOW selects a read operation on Port A for a

LO W-to-HI GH transit ion of CLKA. The A0–35 outputs are i n the high-i m pedance st ate

when W/RA is HIGH.

W/RB Port B Write/

Read Select I A LO W s elects a write operation and a HIGH selects a read op eration on Port B for a

LO W-to-HI G H transit ion of CLKB. The B 0–35 outputs are in the high-impedance s tate

when W/RB is LOW.

Pin Definitions (continued)

Signal Name Description I/O Function

CY7C43643

CY7C43663

CY7C43683

Maximum Ratings[1]

(Abov e which the useful life may be impair ed. F or user guide-

li nes, not tested.)

Sto ra g e Temperatu re ...... ... .. ............... .. ... ....–65°C to +150°C

Ambient Temperature with

Power Applied...............................................–55°C to +125°C

Su pply Volt a ge to Gr o u nd Pot en t ia l ............... –0.5V to +7.0V

DC Volt age Applied to Outp uts

in High Z State[2]......................................–0.5V to VCC+0.5V

DC Input Voltage[2]...................................–0.5V to VCC+0.5V

Output Current into Outputs (LOW).............................20 mA

Static Discharge Voltage ........ ............ ............ ...........>2001 V

(per MIL- STD-883, Method 3015)

La tc h -U p C u rre n t....... .. .. .......... ... .. .......... .. ... ......... ... .>2 00 mA

Operating Range

Range Ambient

Temperature VCC[3]

Commercial 0°C to +70°C 5.0V ± 0.5V

Industrial –40°C to +85°C 5.0V ± 0.5V

Electrical Characteristics O ver t he Operating Range

Parameter Description Test Condi ti ons

CY7C43643/63/83

UnitMin. Max.

VOH Output HIGH Voltage VCC = 4.5V,

IOH = –4.0 mA 2.4 V

VOL Output LOW Vol tage VCC = 4.5V,

IOL = 8.0 mA 0.5 V

VIH Input HIGH Volt age 2.0 VCC V

VIL Input LO W Voltage –0.5 0.8 V

IIX Input Leakage Current VCC = Max. –10 +10 µA

IOZL

IOZH Output OFF, High Z

Current OE > VIH,

VSS < VO< VCC –10 +10 µA

ICC1[4] Active Power Supply

Current Com’l100 mA

Ind 100 mA

ISB[5] Average Standb y

Current Com’l10 mA

Ind 10 mA

Capacitance[6]

Parameter Description Test Conditions Max. Unit

CIN Input Capacitance TA = 25°C , f = 1 MHz,

VCC = 3.3V 4pF

COUT O utp u t Capaci tance 8pF

Notes:

1. Stresses be y ond those listed under “Absolute Max imum Ratings” may cause permanent damage to the device. These are stress ratings only and functional

operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not i mplied. Exposure to absolute-

maximum-rated conditions for extended periods may affect device reliability.

2. The input and output voltage ratings may be exceeded pro vided the input and output current ratings are observed.

3. Operating VCC range for -7 speed is 5.0V ±0.25V.

4. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and c lock enables switch at 20 MHz, while data inputs s witch at 10 MHz. Outputs

are unloaded.

5. All inputs = VCC – 0.2V, except RCLK and WCLK (which are at frequency = 0 MHz). All outputs are unloaded.

6. Tested initially and after any design or process changes that may affect these parameters.

CY7C43643

CY7C43663

CY7C43683

AC Test Loads and Waveforms (-7)

AC Test L o ads an d Waveforms (-10 & -15)

Switching Characteristics Ov er the Operating Range

Parameter Description

CY7C43643/

63/83

–7

CY7C43643/

63/83

–10

CY7C43643/

63/83

–15

UnitMin. Max. Min. Max. Min. Max.

fSClock Frequency, CLKA or CLKB 133 100 67 MHz

tCLK Clock Cycle Time, CLKA or CLKB 7.5 10 15 ns

tCLKH Pul se Duration, CLKA or CLKB HIGH 3.5 4 6 ns

tCLKL Pul se Durati on, CLKA or CLKB LO W 3.5 4 6 ns

tDS Set-Up Time, A0–35 before CLKA↑ and B0–35

before CLKB↑3 4 5 ns

tENS Set-Up Time, CSA, W/RA, ENA, and MBA bef ore

CLKA↑; CSB , W/RB, ENB, and MBB before

CLKB↑

3 4 5 ns

tRSTS Set-Up Time, MRS1 /MRS2 or PRS LOW before

CLKA↑ or CLKB↑[7] 2.5 4 5 ns

tFSS Set-Up Tim e, FS0 and FS1 before MRS1/MRS2

HIGH 6 7 7.5 ns

tBES Set-Up Ti m e, BE/FWFT before MRS1/MRS2

HIGH 5 7 7.5 ns

tSPMS Set-Up Time, SPM before MRS1/MRS2 HIGH 5 7 7.5 ns

tSDS Set-Up Time, FS0/SD before CLKA↑3 4 5 ns

tSENS Set-Up Time, FS1/SEN before CLK A↑3 4 5 ns

tFWS Set-Up Time, FWFT before CLKA↑0 0 0 ns

tDH Hold Time, A0–35 afte r CL K A↑ and B0–35 after

CLKB↑0 0 0 ns

tENH Hold Time, CSA, W/ R A , ENA, and MBA aft er

CLKA↑; CSB, W/RB, ENB, and MBB after CLKB↑0 0 0 ns

tRSTH Hold Time, MRS1/MRS2 or PRS LOW after

CLKA↑ or CLKB↑[7] 1 2 4 ns

Note:

7. Requirement to count the clock edge as one of at least f our needed to r eset a FIFO.

3.0V

OUTPUT

R2=680Ω

CL=30 pF

INCLUDING

JIG AND

SCOPE

GND

90%

10%

90%

10%

≤3ns ≤3ns

ALL INPUT PULSES

R1=1.1KΩ

3.0V

GND

90%

10%

90%

10%

≤3ns ≤3ns

ALL INPUT PULSES

I/O

50Ω

= 

Ω

CY7C43643

CY7C43663

CY7C43683

tFSH Hold Time, FS0 and FS1 after MRS1/MRS2 HIGH 1 1 2 ns

tBEH Hold Time, BE/FWFT after MRS1/MRS2 HIGH 1 1 2 ns

tSPMH Hold Time, SPM after MRS1/MRS2 HIGH 1 1 2 ns

tSDH Hold Time, FS0/SD after CLKA↑0 0 0 ns

tSENH Hold Time, FS1/SEN after CLKA↑0 0 0 ns

tSPH Hold Time, FS1/SEN HIGH after MRS1/MRS2

HIGH 0 1 2 ns

tSKEW1[8] Skew Time between CLKA↑ and CLKB↑ for E F/

OR and FF/IR 5 5 7.5 ns

tSKEW2[8] Skew Time between CLKA↑ and CLKB↑ for A E

and AF 7 8 12 ns

tAAcc ess Time, CLKA↑ to A0–35 and CLKB↑ to

B0–35 1 6 1 8 3 10 ns

tWFF Propagation Delay Time, CLKA↑ to FF /IR 1 6 1 8 2 8 ns

tREF Propagation Delay Time, CLKB↑ to EF/OR 1 6 1 8 1 8 ns

tPAE Propagation Delay Time, CLKB↑ to AE 1 6 1 8 1 8 ns

tPAF Propagation Delay Time, CLKA↑ to AF 1 6 1 8 1 8 ns

tPMF Propagation Delay Time, CLKA↑ to MBF1 LOW

or MBF2 HIGH and CLKB↑ to MB F2 LOW or

MBF1 HIGH

0 6 0 8 0 12 ns

tPMR Propagation Delay Time, CLKA↑ to B0–35[9] and

CLKB↑ to A0–35[10] 1 7 2 11 312 ns

tMDV Propagat ion Del ay Time , MBA to A0–35 Valid and

MBB to B0–35 Valid 1 6 2 9 3 11 ns

tRSF Propagat ion Delay Time, MRS1/MRS2 or PRS

LO W to AE LOW, AF HIGH, FF/IR LOW, EF/OR

LOW and MBF1/MBF2 HIGH

1 6 1 10 115 ns

tEN Enab le Ti me, CSA or W/RA LOW to A 0–35 Activ e

and CSB LOW and W/RB H IGH to B 0–35 Active 1 6 2 8 2 10 ns

tDIS Disable Time , CSA or W/RA HIGH to A0–35 at

High Impedance and CSB HIGH or W/RB LOW to

B0–35 at High Impedance

1 5 1 6 1 8 ns

tPRT Ret ransmit Pul se W idth 60 60 60 ns

tRTR Retr ansmit Recovery Time 90 90 90 ns

Notes:

8. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB

cycle.

9. Wri ting data to the Mail1 register when the B0–35 outputs are active and MBB is HIGH.

10. Wri ting data to the Mail2 register when the A0–35 outputs are active and MBA is HIGH.

Switching Characteristics Ov er the Operating Range (continued)

Parameter Description

CY7C43643/

63/83

–7

CY7C43643/

63/83

–10

CY7C43643/

63/83

–15

UnitMin. Max. Min. Max. Min. Max.

CY7C43643

CY7C43663

CY7C43683

Swi t ch ing Waveforms

Note:

11. PRS must be HIGH during Master Reset.

Master Reset Loading X and Y with a Preset Val ue of Eig ht

CLKA

tRSF

tWFF

tFSS tFSH

tSPMS tSPMH

tBES tBEH

tRSTH

tRSTS

tFWS

CLKB

MRS1,

MRS2

BE/FWFT

SPM

FS1/SEN,

FS0/SD

FF/IR

EF/OR

MBF1

[11]

tRSF

CY7C43643

CY7C43663

CY7C43683

Notes:

12. MRS1/MRS2 must be HIGH during Partial Reset

13. CSA=LOW, W/RA=HIGH, MBA=LOW. It is not necessary to program offset register on consecutive clock cycles.

14. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB for FF/IR to transition HIGH in the next cycle. If the time between the rising

edge of CLK A and rising edge of CLKB is less than tSKEW1, then FF/IR may transition HIGH one cycle later than shown.

Swi t ch ing Waveforms (continued)

Partial Reset (CY Standard and FWFT Modes)

tRSF

tRSTS tRSTH

CLKA

CLKB

PRS

FF/IR

EF/OR

MBF1

[12]

tWFF

tRSF

Parallel Progr am ming of t he Almost Full Flag and Almost Empty Flag Offset Value s aft er Reset

(CY Standard and FWFT Modes)

tWFF

tFSS

tDS

tFSS tFSH

tFSH

tENS tENH

tDH

tSKEW1[14]

AF Offset (Y) First Word to FIFO

CLKA

MRS1,

MRS2

SPM

FS1/SEN,

FS0/SD

FF/IR

ENA

A0−35

[13]

AE Offset (X)

CY7C43643

CY7C43663

CY7C43683

Notes:

15. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IR is set HIGH.

16. Programmable offsets are written serially to the S D input in the order AF offset (Y) then AE offset (X).

17. Read from FIFO.

18. When reading from the FIFO under FWFT, ORA/ORB signal should be included in the read logic to ensure proper operation. To read without gating the

boundary flag (e.g., in bursts), use CY standard mode.

Swi t ch ing Waveforms (continued)

Serial Programming of the Almost Full Flag and Almost Empty Fla g

Offse t Values (CY Standard and FWFT Modes)

tFSS tSPH tSENS tSENH tSENH

tSENS

tSDH

tSDS tSDH

tSDS

tWFF

AF Offset (Y) MSB

tFSS tFSH

CLKA

MRS1, MRS2

SPM

FF/IR

FS1/SEN

[15]

FS0/SD [16]

AE Offset (X) LSB

tCLKH tCLKL

tENS

tDIS

tENS tEN

tCLK

tDIS

tENH

tENS tENH

tEN

tMDV

W1[17] W2[17]

W3[17]

Previous Data

No Operation

CLKB

EF/OR

CSB

W/RB

MBB

ENB

B0–35

(Sta ndard Mo de)

B0–35

(FW FT Mode)

Port B Long-Wor d Read Cycl e Timing for FIFO (CY Standard and FWFT Modes)

[18]

CY7C43643

CY7C43663

CY7C43683

Notes:

19. Unused bytes B9–17, B18–26, and B27–35 contain all zeroes for byte-size reads.

20. Unused word B18–35 contai ns all zeroes for word-size reads.

Swi t ch ing Waveforms (continued)

CLKB

EF/OR

CSB

W/RB

MBB

ENB

Port B Word Read Cycle Timing f or FIFO (CY Standard and FW FT Mo des)

tDIS

tENS tENH

tEN

tMDV

tMDV tDIS

Previous Data

No Operation

B0–17

(Standard Mode)

B0–17

(FWFT Mode)

[18, 20]

CLKB

EF/OR

CSB

W/RB

MBB

ENB

Por t B Byte Read Cycle Timing for FIFO (CY Standard and FWFT Modes)

tDIS

tENStENH

tEN

tMDV

tMDV tDIS

Previous Data

No Operation

HIGH

B0–8

(Standard Mo de)

B0–8

(FWFT Mode)

[18, 19]

CY7C43643

CY7C43663

CY7C43683

Notes:

21. If Port B size is word or byte, EF is set LOW by the last word or byte read from the FIFO, respectively.

22. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition HIGH and to clock the next word to the FIFO output

register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of O R HIG H and load

of the first word to the output register may occur one CLKB cycle later than s hown.

Swi t ch ing Waveforms (continued)

tCLKH tCLKL

tENS

tCLK

tENH

tENS

tENH

tDS

LOW

tDH

HIGH

FIFO Empty

LOW

HIGH

LOW

Old Data in FIFO Output Register W1

tENS tENH

tREF tREF

tCLKH tCLKL

tCLK

tSKEW1[22]

CLKA

CSA

W/RA

MBA

ENA

FF/IR

A0–35

CLKB

EF/OR

CSB

W/RB

MBB

ENB

B0–35

OR Flag Timi ng and Fir st Data Word Fall Through when FIFO is Empty (FWFT Mode)[18, 21]

CY7C43643

CY7C43663

CY7C43683

Notes:

23. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to tr ansition HIGH in the next CLKB cycle. If the time between the

rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of EF HIGH may occur one CLKB cycle later than shown.

Swi t ch ing Waveforms (continued)

tCLKH tCLKL

tENS

tENH

tENS

tENH

tDS

LOW

tDH

HIGH

FIFO Empty

LOW

HIGH

LOW

tENStENH

tREF tREF

tCLKH tCLKL

tCLK

tSKEW[23]

CLKA

CSA

W/RA

MBA

ENA

FF/IR

A0–35

CLKB

EF/OR

CSB

W/RB

MBB

ENB

B0–35

EF Flag Timi ng and Fir st Data Read Fall Thr ough wh en FIFO is Empty (CY Standard Mod e)[21]

CY7C43643

CY7C43663

CY7C43683

Notes:

24. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that reads the last word or byte write of the long word, respectively.

25. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition HIGH in the next CLKA cyc le. If the time between the

rising CLKB edge and rising CLKA edge is less than tSKEW1, then IR may transition HIGH one CLKA cycle later than shown.

Swi t ch ing Waveforms (continued)

tCLKH tCLKL

tENStENH

LOW

HIGH

FIFO Full

LOW

HIGH

tENStENH

tWFF tWFF

tCLKH tCLKL

tCLK

tSKEW1[25]

tDH

tDS

tENH

tENS

Previous W ord in FIFO Output Register Next Word From FIFO

To FIFO

CLKB

CSB

W/RB

MBB

ENB

EF/OR

B0–35

CLKA

FF/IR

CSA

W/RA

MBA

ENA

A0–35

IR Flag Timing and First Available Write when FIFO is Full (FWFT Mode)[24]

CY7C43643

CY7C43663

CY7C43683

Notes:

26. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FF to trans ition HIGH in the next CLKA cycle. If the time between the

rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of FF HIGH may occur one CLKA cycle later than shown.

Swi t ch ing Waveforms (continued)

tCLKH tCLKL

tENStENH

LOW

HIGH

FIFO Full

LOW

HIGH

tENStENH

tWFF tWFF

tCLKH tCLKL

tCLK

tSKEW1[26]

tDH

tDS

tENH

tENS

Previous W ord in FIFO Output Register Next Word From FIFO

CLKB

CSB

W/RB

MBB

ENB

EF/OR

B0–35

CLKA

FF/IR

CSA

W/RA

MBA

ENA

A0−35

FF Flag Timing and First Available Write when FIFO is Full (CY Standard Mode) [24]

LOW

CY7C43643

CY7C43663

CY7C43683

Notes:

27. FIFO Write (CSA = LOW, W/RA = HIGH, MB A = LOW), FIFO Read (CSB = LO W, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been

read from the FIFO.

28. D = Maximum FIFO Depth 1K for the CY7C43643, 4K for the 43663, and 16K for the CY7C43683.

29. If Port B size is word or byte, tSKEW2 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.

30. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to tr ansition HIGH in the next CLKA cycle. If the time between the

rising CLKA edge and rising CLKB edge is less than tSKEW2, then AF may transition HIGH one CLKB cycle later than shown.

31. FIFO Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO Read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been

read from the FIFO.

32. If Port B size is word or byte, AE is set LOW by the last word or byte read from FIFO, respectively.

33. tSKEW2 is the minimum time between a ri sing CLKA edge and a rising CLK B edge for AE to transition HIGH in the next CLKB cycle. If the time between the

rising CLKA edge and rising CLKB edge is less than tSKEW2, then AE may transition HIGH one CLKB cycle later than shown.

34. When FIFO is operated at the almost empty/full boundary, there may be an uncertainty of up to 3 clock cycles for fl ag assertion and deassertion. Refer to

“Designing with CY7C436xx Synchronous FIFO” application notes for more details on flag uncertainties.

Swi t ch ing Waveforms (continued)

Timing for AF when FIFO is Almost Full (CY Standard and FWFT Mo des)

tSKEW2[30]

CLKA

ENA

CLKB

ENB

[27, 28, 29, 34]

tPAF

tENH

tENS

tPAF

tENS tENH

[D–( Y1+1)] Word s in FI FO 1 (D–Y1)Words in FIFO1

CLKA

ENA

CLKB

ENB

Timing for AE when FIFO is Almost Empty (CY Standard and FWFT Modes)[31, 32, 34]

tPAE

tENH

tENS

tSKEW2[33]

tENS tENH

X1 Word in FIFO1 (X1+1)Words in FIFO2

CY7C43643

CY7C43663

CY7C43683

Note:

35. If Port B is configured for word size, data can be written to the Mail1 register using A0–17 (A18–35 are “don’t care” inputs). In this first case B0–17 will have

valid data (B18–35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A0–8 (A9–35 are “don’t care”

inputs). In this second case, B0–8 will have valid data (B9–35 will be inde term ina te).

Swi t ch ing Waveforms (continued)

tENH

tENS

tENH

tENS

tENH

tENS

tENH

tENS

tDH

tDS

tPMF tPMF

tEN tMDV tPMR

tENS tENH

tDIS

FIFO Output Register W1 (Remains valid in Mail1 Register after read)

CLKA

CSA

W/RA

MBA

ENA

A0–35

CLKB

MBF1

CSB

W/RB

MBB

ENB

Timing for Mail1 Register and MBF1 Flag ( CY Standard and FWFT Modes) [35]

B0−35

CY7C43643

CY7C43663

CY7C43683

Notes:

36. If Port B is configured for word size, data can be written to the Mail2 register using B0–17 (B18–35 are “don’t care” inputs). In this first case, A0–17 will have

valid data (A18–35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B0–8 (B9–35 are “don’t care”

inputs). In this second case, A0–8 will have valid data (A9–35 will be inde term ina te).

37. Clocks are free-running in this case. CY standard mode only.

38. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR.

39. For the AF & AE flags, two clock cycles are necessary after tRTR to upda te the se fl ags.

Swi t ch ing Waveforms (continued)

tENH

tENS

tENH

tENS

tENH

tENS

tENH

tENS

tDH

tDS

tPMF tPMF

tEN tMDV tPMR

tENS tENH

tDIS

FIFO2 Output Register W1 (Remains valid in Mail2 Register after read)

CLKB

CSB

W/RB

MBB

ENB

B0–35

CLKA

MBF2

CSA

W/RA

MBA

ENA

A0−35

Timing for Mail2 Register and MBF2 Flag (CY Standar d and FWFT Modes)[36]

FIFO Retransmit Timing

ENB

tPRT tRTR

EF/FF

[ 37 , 38, 39 ]

CY7C43643

CY7C43663

CY7C43683

Signal Description

Master Reset (MRS1, MRS2)

The FIFO mem ory of the C Y7C436x3 undergoes a complete

reset by taking its associated Master Reset (MRS1, MRS2)

input LOW for at least four Port A clock (CLKA) and four Por t

B clock (CLKB) LOW-to-HIGH transitions. The Master Reset

input can switch asynchrono usly to the cloc ks. A Mas ter Reset

initializes the internal read and write pointers and forces the

Full/Input Ready flag (FF/IR) LOW, the Empty/Output Ready

flag (EF/OR) LOW, the Almost Empty flag (AE) LOW, and the

Almost Full flag (AF) HIGH. A Master Reset also forces the

Mailbox flag (MBF1, MBF2) of the parallel mailbox register

HIGH. After a Master Reset, the FIFO’s Full/Input Ready flag

is set HIGH after two clock cycles to begin normal operation.

A Master Reset must be performed on the FIFO after power

up, before data is written to its memory.

A LOW-to-HIGH transition on a FIFO Master Reset (MRS1,

MRS2) inp ut l atches the value of the Big Endian (BE) inpu t or

determining t he order by which bytes are transferred through

Port B.

A LOW-to-HIGH transition on a FIFO reset (MRS1, MRS2)

input lat ches the values of the Flag select (FS0, FS1) and Se-

rial Programm ing Mode (SPM) inputs for choosing the Alm ost

Full and Almost Empty offset programming method (see Al-

most Em pty and Almost Full flag offs et programming below).

Partial Reset (PRS)

Each of t he two FIFO memories o f t he CY7C436x3 undergoes

a limited reset by taking its associated Partial Reset (PRS)

input LOW for at least four Port A clock (CLKA) and four Por t

B clock (CLKB) LOW-to-HIGH transitions. The Partial Reset

input s can switch asy nchronous ly t o the clocks. A Partial Rest

initializes the internal read and write pointers and forces the

Full/Input Ready flag (FF/IR) LOW, the Empty/Output Ready

flag (EF/OR) LOW, the Almost Empty flag (AE) LOW, and the

Almost Full flag (AF) HIGH. A Partial Reset also forces the

Mailbox flag (MBF1, MBF2) of the parallel mailbox register

HIGH. After a Par tial Reset, the FIFO’s Full/Input Ready flag

is set HIGH aft e r t w o clock cycle s to begi n normal oper ation.

Whatev er flag offsets, programming method (parallel or serial),

and timing mode (FWFT or I DT Standard mo de) are curr ently

selected at the time a Partial R eset is initiated, those settings

wil l r emain unchanged upon comple ti on of the r eset operat ion.

A Par tial Reset may be useful in the case where reprogram-

ming a FIFO foll owi ng a M aster Reset would be i nconvenient.

Big Endian/First-Word Fall-Through (BE/FWFT)

This is a dual-purpose pin. At the time of Mas ter Reset, the BE

select function is active, permitting a choice of Big or Little

Endian byte arrangement for data written to or read from Port

B. This selection determines the order by which bytes (or

w ords) of data ar e tra nsf er red th rough t his port. F or th e f ollo w-

ing illustrations, assume that a byte (or word) bus size has

been sele cted for Po rt B. (Note that when Port B is configured

f or a long-wor d size, the Big Endia n function has no appli cation

and the BE inp ut i s a “Don’t Care.”

A HIGH on the BE/FWFT input when the Master Reset (MRS1,

MRS2) inputs go from LOW to HIGH will select a Big Endian

arrangem ent. When data is moving in the direction from Port

A to Por t B, the most significant byte (word) of the long-word

written to Port A will be transferred to Port B first; the least

signi ficant b yte ( word) of the long-w ord wri tt en to P ort A will be

transferred to Port B l ast.

A LOW on t he BE/FWFT i nput whe n t he Mast er Reset (MRS1,

MRS2) in puts go from LO W to HIGH will selec t a L ittl e Endian

arrangement. When data is moving in the direction from Por t

A to Por t B, the least significant byte (word) of the long-word

written to Port A will be transferred to Port B first; the most

signi ficant b yte ( word) of the long-w ord wri tt en to P ort A will be

tran sfer red to P o rt B last. After Maste r Reset , t he FWFT select

function is active, permitting a choice between two possible

timing modes: CY Standard Mode or First-Word Fall-Through

(FWFT) Mode. Once the Master Reset (MRS1, MRS2) input

is HIGH, a HI GH on the BE/FWFT input at the second LOW-

to-HIGH transition of CLKA will select CY Standard Mode. This

mode uses the Empty Flag function (EF) to indicate whether

or not the re are any words p res ent in the FIFO memory. It uses

the Full Flag functi on (FF) to indi cate whether or not t he FIFO

memory has an y free sp ace f or wri tin g. In CY Stan dard Mode ,

every word read from the FIFO, including the first, must be

requested using a formal read oper ati on.

Once the Master Reset (MRS1, MRS2) inp ut is HIG H, a LOW

on the BE/ FWFT input during the ne xt LO W-to-HIGH tran sition

of CLKA will select FWFT Mode. This mode uses the Output

Ready function (OR) to indicate whether or not there is valid

data at the data outputs (B0–35). It also uses the Input Ready

funct ion (IR) to indicate whether or not the FIFO memory has

any free space for writing. In the FWFT mode, the first word

written to an empty FIF O g oes directly to data o utputs, no read

request necessary. Subsequent words must be accessed by

performing a formal read operation.

Following Master Reset, the level applied to the BE/FWFT in-

put to choose the desired timing mode must remain static

throughout the FIF O ope ration.

Programming the Almost Empty and Al mos t Full Flags

Two registers in the CY7C436x3 are used to hold the offset

values for th e Almost Em pty and Almost Full flags. The Port B

Almost Empty f lag (AE) offse t regi ster is l abeled X. The Port A

Almost Full flag (AF) offset register is labeled Y. The index of

each regi ster name cor respond s with pr ese t va lu es during the

reset of a FIFO, prog rammed in parallel using the FIFO’s Port

A data inputs, or programmed in serial using the Serial Data

(SD) input (see Table 1).

To load a FIF O’s Almost Empty f lag and Almos t Full fl ag offse t

registers with one of the three preset values listed in Table 1,

the Serial Program Mode (SPM) and at least one of the flag-

select inputs must be HIGH d urin g the LOW -t o-HIGH tr ansition

of it s Master Reset i nput (MRS1 , MRS2). Fo r example , to l oad

the preset value of 64 into X and Y, SPM, FS0 and FS1 must

be HIGH when the FIFO reset (MRS1, MRS2) ret ur ns H IGH .

When using one of the preset values for the flag offsets, the

FIFO can be reset simultaneously or at different times.

To progr am the X and Y r egisters from Port A, p erform a Mas-

ter Reset on both FIFOs simultaneously with SPM HIGH and

FS0 and FS1 LOW during the LOW-to-HIGH transition of

MRS1/MRS2. Aft er this res et is comp let e, the fi rst tw o wr ites

to the FIFO do not stor e data in RAM but load the offse t regis -

ters in the order Y and X. The Port A data inputs used by the

offset registers are (A0–9), (A0–11), or (A0–13),for the

CY7C436x3, respectiv ely. The highest n umbered input is used

as the most significant bit of the binary number in each case.

Valid programming values for the registers range from 0 to

CY7C43643

CY7C43663

CY7C43683

1023 for the CY7C43643; 0to 4095 for the CY7C43663; 0 to

16383 fo r the CY7C43683. Bef ore p rog rammin g t he offset reg-

ister, FF/IR is set HIGH. FIFOs begin normal operation after

programming is done.

To program the X and Y registers serially, initiate a Master

Reset with SPM LO W , FS0 /SD LO W , and FS1/SEN HI GH du r-

ing th e LOW- to-HIGH transition of MRS1/MRS2. Af te r th is re -

set is complete , the X a nd Y reg is ter v alu es are lo aded bit- wis e

through the FS0/SD input on each LO W-to-HIGH transiti on of

CLKA that the FS1/SEN input is LOW. Twenty, twenty four, or

twenty eight bit writes are needed to complete the program-

ming for the CY7C436x3, respectively. The two registers are

written in the order Y then finally X. The first-bit write stores

the most significant bit of the Y register and the last-bit write

stores the least significant bit of the X register. Each register

v alu e can be prog r ammed from 0 to 1023 f or t he CY7C43643;

0to 4095 for the CY7C43663; 0 to 16383 (Cy7c43683).

When the opt ion t o p rogr am t he offset r egist ers seriall y is cho-

sen, the Port A Full/Input Ready (FF/IR) flag remains LOW

unti l a ll reg ister bits are written. FF/IR is set HIGH by the LOW-

to-HIGH trans it ion of CLKA after the l ast bit is loaded t o all ow

normal FIFO operation.

SPM, FS0/SD, and FS1/SEN function the same way in both

CY Standard and FWFT modes.

FIFO Write/Read Operat ion

The state of the Port A data (A0–35) lines is controlled by Port

A Chip Select (CSA) and Port A Write/Read Select (W/RA).

The A0–35 lines are in the high-impedance state when either

CSA or W/RA is HIGH. The A0–35 lines are active mail 2 reg-

ist er outputs when bot h CSA and W/RA are LOW.

Data i s loaded int o the FIFO fr om the A0–35 inputs on a LOW -

to- HIGH tr ansition of CLKA when CSA is LOW, W/RA is HIGH,

ENA is HIGH, MBA is LOW, and FF/IR is HIGH (see Table 2).

FIFO wri tes on Port A are independent of an y conc urrent Port

B operation.

The Port B control signals are ident ical to those of Port A with

the excepti on that the Port B Write/Read Select (W/RB) is the

inverse of the Por t A Write/Read Select (W/RA). The state of

the Por t B data (B0–35) lines is controlled by the Por t B Chip

Selec t ( CSB) and P ort B Write/Read Select (W/RB). The B0–35

lines are in the high-impedance state when either CSB is

HIGH or W/RB is LOW. The B0–35 lines are active outputs

when CSB is LOW and W/RB is HIG H.

Data is read from the FIFO to the B0–35 outputs by a LOW-to-

HIGH transition of CLKB when CSB is LOW, W/RB is HIGH,

ENB is HIGH, MBB is LO W, and EF/ OR is HI GH (see Table 3).

FIFO reads and writes on Port B are in dependent of any con-

current Por t A operation.

The set-up and hold time constraints to the po rt cloc ks for the

port Chip Sel ects and Wri te/Read Se lec ts are o nly f or enabling

write and read operations and are not related to high-

impedan ce co ntrol of th e dat a output s. If a po rt ena b le is LO W

during a clock cycle, the port’s Chip Select and Write/Read

Selec t may ch ange states during th e set-up and hold ti me win-

dow of the cycle.

When operating the FIFO in FWFT Mode with the Output

Ready fl ag LO W, the nex t wo rd written i s automatica lly sen t to

the FIFO’s output register by the LOW-to-HIGH transition of

the port clock that sets the Output Ready flag HIGH, data re-

siding in the FIF O’s mem ory a rray is cl ocked to t he outpu t reg-

ister only when a read i s selec ted usi ng the p ort’s Ch ip Sel ect,

Write/Rea d Selec t, Enab le, and Ma ilbox Select .

When ope rati ng the FIFO in CY St andard Mode , regar dless o f

whether t he Emp ty Fl ag is LOW or HIGH, data residing in the

FIFO’s memory array is clocked to the output register only

when a read is selected using the port’s Chip Select, Write/

Read Select, Enabl e, and Mailbox Select.

Synchronized FIFO Fl ags

Each FIFO is synchronized to its port clock through at least

two f lip- flop stages . This i s done t o im prove flag-s ignal re liabil -

ity by reducing the probability of the metastable events when

CLKA and CLKB operate asynchr onously to one another. EF/

OR an d AE are sy nchr oniz ed to CLKA. FF/IR and AF ar e syn -

chroni zed to CL KB. Table 4 shows th e relationship of ea ch port

flag to the FIFO .

Empty/Output Ready Flags (EF/OR)

These are dual-purpose flags. In t he FWFT Mode , the Output

Ready (OR) fun ction i s select ed. When t he Out put Ready flag

is HIGH, new data i s pr esent in t he FIFO output register . When

the Output Ready flag is LOW, the previous data word is

present in the FIFO output register and a ttempted FIFO reads

are ignored.(See footnote #18)

In the CY Standard Mode, the Empty Flag (EF) function is

selected. When the Empty Flag is HIGH, data is available in

the FIFO’s RAM memory for reading to the output register.

When the Empty Flag is LOW, the previous data word is

present in the FIFO output register and a ttempted FIFO reads

are ignored.

The Empty/Out put Ready fla g of a FI FO is sy nchroniz ed to the

port clock that reads data from its array. For both the FWFT

and CY St andard modes, the FIFO read pointer is increment-

ed each t ime a new word is clocked to its output register. The

state machine that controls an Output Ready flag monitors a

write po int er and read po int er comparator that indicates when

the FIFO SRAM status is empty, empty+1, or empty+2.

In FWFT Mode, from the ti me a word is written to a FIFO , it can

be shifted to the FIFO output register in a minimum of three

cycles of the Output Ready flag synchronizing clock. There-

fore, an Output Ready flag is LOW if a word in memory is the

next data to be sent to the FIFO output register and three cy-

cles ha v e not elapsed s in ce the time t he word was wri tt en. The

Output Ready flag of the FIFO remains LOW until the third

LOW-to-HIGH transition of the synchronizing clock occurs, si-

multa neous ly f orci ng the Outp ut Ready fl ag HIGH and shi f ting

the word to the FIFO output register.

In the CY Standard Mode, from the ti m e a word is written to a

FIFO, the Empty Flag will indicate the presence of data avail-

able for reading in a minimum of two cycles of the Em pty Flag

synchronizing clock. Therefore, an Empty Flag is LOW if a

word in memory is the next data to be se nt t o the F IFO outpu t

word was written. The Empty Flag of the FIFO remains LOW

until the second LOW-to-H IGH transition of the synchronizing

cloc k occurs , f orcin g t he Empty Fl ag HIGH; onl y then ca n data

be read.

A LOW-to-HIGH transition on an Empty/Output Ready flag

synchronizing clock begins the first synchronization cycle of a

write if the clock transition occurs at time tSKEW1 or greater

after the write. Otherwise, the subsequent clock cycle can be

the first synchronization cycle.

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CY7C43683

Full/Input Ready Flags (FF/IR)

This is a dual-purpose flag. In FWFT Mode, the Input Ready

(IR) function is selected. In CY Standard Mode, the Full Flag

(FF) function is selected. For both timing modes, when the

Full /Inpu t Ready fl ag is HI GH, a memory locat ion is free in th e

SRAM to receive new data. No memory locations are free

when the Full/Input Ready flag is LOW and attempted writes

to the FIFO are ignored.

The Full /Input Ready flag of a FIFO is synchronized to the port

cloc k that writes dat a to i ts arr ay. F or both FWFT a nd CY Stan-

dard modes, each time a word is written to a FIFO, its write

point er is increment ed. The st at e machine t hat cont ro ls a Full/

Input Ready flag monitors a write pointer and read pointer

comp arator t hat indicat es when the FIFO SRAM status is full,

full–1, or full –2. From the time a word is read from a FIFO, its

previous memory location is ready to be written to in a mini-

mum of two cycles of the Full/Input Ready flag synchronizing

clock. Therefore, an Full/Input Ready flag is LOW if less than

two cycles of the Full/Input Ready flag synchronizing clock

have elapsed since the next memory write location has been

read. The second LOW-to-HIGH transition on the Full/Input

Ready flag synchronizing clock after the read sets the Full/

Input Ready flag HIGH.

A LOW-to-HIG H transiti on on a Full /I nput Ready flag synchro-

nizing clock begins the first synchronization cycle of a read if

the clock transition occur s at time tSKEW1 or greater after t he

read. Otherwise, the subsequent clock cycle can be the first

synchronization cycle.

Almost Empty Fl ags (AE)

The Almost Empty flag of the FIFO is synchronized to port B

clock. The state machine that controls an Almost Empty flag

monit ors a wri te poi nter and read poi nter compar ator that i ndi-

cates when the FIFO SRAM status is almost empty, almost

empty+1, or almost empty+2. The Almost Empty state is de-

fined by the contents of register X f or AE. These register s are

loaded with preset values during a FIFO reset, programmed

from Port A, or programmed serially (see Almost Empty flag

and Almost Full flag offset programming above). An Almost

Empty f lag is LO W when its FIFO co ntains X or l ess words an d

is HIGH when its FIFO contains (X+1) or more words. (See

footnote #34)

Two LOW-to-HIGH transitions of the Almost Empty flag syn-

chronizing clock are required after a FIFO write for its Almost

Empty fl ag to reflec t the new l ev e l of fill . Theref or e , the Almost

empty flag of a FIFO containing (X+1) or more w ords rema ins

LOW i f two cycles of its synchronizing cl ock have not elapsed

since the write that filled the memory to the (X+1) level. An

Almost Empty flag is set HIGH by the second LOW-to-HIGH

transition of its synchronizing clock after the FIFO write that

fi lls memory to the (X+1) lev el. A LO W -to-HIGH t ransition of an

Almost Empty flag synchronizing clock begins the first syn-

chronization cycle if it occurs at time tSKEW2 or grea ter after

the write t hat f ills the FIF O to (X+1 ) words. Other wise, th e sub-

sequent synchronizing clock cycle may be the first synchroni-

zation cycle.

Almost Ful l Flags (AFA, AFB )

The Almost Full flag of the FIFO is synchronized to port A

cloc k. The state machine that controls an Almost Full flag mon-

it ors a write poi nter and read pointer comparator that indicates

when the FIFO SRAM status is almost full, almost full–1, or

almost full–2. The Alm ost Full s tate is defined by the contents

of register Y for AF. These registers are loaded with preset

values during a FIFO reset, programmed from Port A, or pro-

gramm ed serially (see Almost Empty flag and Almos t F ull flag

offset programming above). An Almost Full flag is LOW when

the number of words in its FIFO is greater than or equal to

(1024–Y) , ( 4096–Y), or (16384 –Y) f or the CY7C436x3 respec-

tively. An Almost Full flag is HIGH when the number of words

in its FIFO is less t han or equal to [1024–(Y+1 )] , [4096–(Y+1)],

or [16384–(Y+1)], for the CY7C436x3 respectively.(See foot-

note #34)

Two LO W-to-HIGH tr ansiti ons of the Almost Full flag synchro-

nizing clock are required after a FIFO read for its Al most Full

flag to reflect the new level of fill. Therefore, the Almost Full

flag of a FIFO containing [1024/4096/16384–(Y+1)] or less

words remains LOW if two cycles of its synchronizing clock

have not elapsed since the read that reduced the number of

words in memory to [ 102 4/4096/ 16384–(Y+ 1 )]. An Al most F ull

flag is set HIGH by the second LOW-to-HIGH transition of its

synchro nizin g cl ock after the FI FO re ad that re duces th e n um-

ber of words in memory to [1024/4096/163 84–(Y+1)]. A LOW-

to-HIGH transition of an Almost Full flag synchronizing clock

begins t he first synchronization cy cle if it o ccurs at t ime t SKEW2

or greater after the read that reduces the number of words in

memory to [1024/4096/16384–(Y+1)]. Otherwise, the subse-

quent synchronizing clock cycle may be the first synchroniza-

tion cycle.

Mailbox Registers

Each FIFO has a 36- bit bypas s register to pass command and

control information between Port A and Port B wit hout putti ng

it in queue. The Mailbox Select (MBA, MBB) inputs choose

between a mail register and a FIFO for a port data transfer

operation. The usable width of both th e Mail1 and Ma il 2 reg is-

ters matches the selected bus si ze fo r Port B.

A LOW-to-HIGH transition on CLKA writes A0−35 data to the

Mail1 Regist er when a P o rt A write i s selec ted b y CSA, W/RA,

and ENA with MBA HIGH. If the selected Port A bus size is

also 36 bits, then the usable width of the Mail1 Register em-

plo ys data l ines A0–35. If the selected P ort A b us size is 18 bits ,

then th e usab le wi dth of the M ail 1 Regist er employs data l ines

A0−17. (In th is c ase, A 18–35 are “don’t care” inputs.) If the se-

lected Port A bus size is 9 bits, then the usable width of the

Mail1 Register employs data lines A0–8. (In this case, A9–35 are

“don’t care” i nputs .)

A LOW-to-HIGH transition on CLKB writes B0−35 data to the

Mail2 reg is ter when a Port B wri te is selected by CSB, W/RB,

and ENB with MBB HIGH. If the selected Port B bus size is

also 36 bits, then the usable width of the Mail2 Register em-

plo ys data l ines B0–35. If the selected P ort B b us size is 18 bits ,

then the usable wid th of the Mail2 regi ster employs data lines

B0–17. ( In th is c ase, B 18–35 are “don’t care” inputs.) If the se-

lected Port B bus size is 9 bits, then the usable width of the

Mail2 Register employs data lines B0−8. (In this case, B9−35 ar e

“don’t care” i nputs .)

Writing data to a mail register sets its corresponding flag

(MBF1 or MBF2) LO W. Att empted writes to a mail register are

ignored while the mail flag is LOW.

When data outputs of a port are active, the data on the bus

comes from the FIFO output register when the port Mailbox

Select input is LOW and f rom the mail register when the port

Mailbox Select input is HI GH.

CY7C43643

CY7C43663

CY7C43683

The Mail1 Register flag (MBF1) is set HIGH by a LOW-to-

HIGH transition on CLKB when a Port B read is selected by

CSB, W/RB, and ENB with MBB HIGH. For a 36-bit bus size,

36 bi ts of mailbox data are placed on B0–35. For an 18-bi t bus

siz e , 18 bi ts of mailb o x data are placed on B0–17. ( In thi s case ,

B18–35 are indeterminate.) For a 9-bit bus size, 9 bits of mail-

box data are placed on B0–8. (In th is cas e, B9–35 are indeter-

minate.)

The Mail2 Register flag (MBF2) is set HIGH by a LOW-to-

HIGH transition on CLKA when a Port A read is selected by

CSA, W/RA, and ENA with MBA HIGH.

For a 36-bit bus size, 36 bits of mailbox data are placed on

A0–35. For an 18-bit bus size, 18 bits of mailbo x data are placed

on A0–17. (In t his c ase, A 18–35 are indeter minate.) For a 9-bit

bus size, 9 bits of mailbox data are placed on A0–8. (In this

case, A9–35 are indeterminate.)

The data in a mail register remains intact after it is read and

changes only when new data is written to the register. The

Endian Select feature has no effect on the mailbox data.

Bus Sizi ng

The Port B bus can be confi gured in a 36- bit long-word, 18-bit

word, or 9-bit byte format for data read from FIFO. The levels

applied to the Port B Bus Size Select (SIZE) and the Bus

Match Sel ect (BM) det ermine the P ort B bus size. These le vels

should be static t hrougho ut FIFO operation. Both b us size se-

lections are implemented at the completion of Master Reset,

by the time the Full/Input Ready flag is set HIGH .

Two different methods for sequencing data transfer are avail-

able for Port B when the bus size selection is either byte-or

w ord-siz e . The y ar e ref er re d to as Big End ian ( most sign ific ant

byte first) and Little Endian (least significant byte first). The

level applied to the Big Endian Select (BE) input during the

LOW-to-HIGH transition of MRS1/MRS2 selects the endian

method t hat wil l be act iv e du ri ng FIFO ope r ation. BE i s a don’t

care i nput when the bus size selected for Port B is long- word.

The endian met hod is implemented at the com pletion of M as-

ter Reset, by the time the Ful l/Input Ready flag is set HIGH.

Only 36-bit long-word data is written to or read from the two

FIFO m emories on the CY7C436 x3. Bus-matc hing ope r ations

are d one after data is read from the FIFO . Th ese b us-matchin g

oper ations ar e not a vai labl e when tr ansfer ring data via mail box

registers. Furthermore, both the word- and byte-size bus se-

lections l imit the widt h of t he data bus t hat can be used f or mail

regis ter oper a tions . In this c ase , onl y those b y te lan es belong -

ing to the selected word- or byte-size bus can carry mailbox

data. The remaining data outputs will be indeterminate. The

remaining data inputs will be don’t care inputs. For example,

when a word-size bus is selected, then mailbox data can be

transmitted only between A0–17 and B0–17. When a byte-size

bus i s select ed, t hen mai lbo x da ta can be tr ansmit ted on ly be-

tween A0–8 and B0–8.

Bus-Matching FIFO Reads

Data is read from the FIFO RAM in 36-bit long-word incre-

ments. I f a lon g-word b us siz e is implem ented, the ent ire l ong -

wo rd i mm ed iat el y sh ift s to th e FIF O ou t put re gist e r. If byt e or

word size is implemented on Por t B, only the first one or two

byt es appe ar on the se lected porti on of th e FIFO output reg is-

ter, with the rest of the long-word stored in auxiliary registers.

In this case, subsequent FIFO reads output the rest of the

long-word to the FIFO output regi ster.

When reading data from the FIFO in the byte or word format,

the unused B0–35 outputs are indeterminate.

Retransmit (RT)

The retransmit feature is beneficial when transferring packets

of data. It enables the receipt of data to be acknowledged by

the receiver and retransmitted if necessary. Retransmit func-

tion applies to CY standard mode only.

The retransmit feature is intended for use when a number of

writes equal to or less than the depth of the FIFO have oc-

curred and at l east one wor d has be en read si nce the l ast rese t

cycle. A LOW pulse on RT resets the internal read pointer to

the first phy sical locat ion o f th e FIFO . CLKA and CLKB ma y be

free-running but ENB must be disabled during and tRTR after

the ret rans mit pulse. Wi th every vali d read cy cle after retr ans-

mit, previously accessed data is read and the read pointer is

incre mented until i t i s equ al to the write po inter. Flags ar e gov -

erned by the relative locations of the read and write pointers

and are updated during a retr ansmit cycle. Data writ ten to the

FIFO after activation of RT are tran smitte d also. The full dept h

of the FIFO can be r epeatedly tr ansmitted.

CY7C43643

CY7C43663

CY7C43683

B27–35 B18–26 B9–17 B0–8

A27–35 B

A18–26 C

A9–17 D

A0–8

B27–35 B

B18–26 C

B9–17 D

B0–8

A B

C D

(a) LO NG WORD SIZE

(b) WORD SIZE – BIG ENDIAN

(d) BYTE SIZE – BIG ENDIAN

BE BM SIZE

XLX

BE BM SIZE

HHL

BE BM SIZE

LHL

BE BM SIZE

HHH

Writ e to FI FO

Read from

FIFO

1st: Read from

FIFO

2nd: Read from

FIFO

1st: Read from

FIFO

2nd: Read from

FIFO

1st: Read from

FIFO

2nd: Read from

FIFO

3rd: Read from

FIFO

4th: Read from

FIFO

BYTE ORDER ON

PORT A:

( e) BYT E SIZE – LITTLE ENDIAN

BE BM SIZE

LHH

1st: Read from

FIFO

2nd: Read from

FIFO

3rd: Read from

FIFO

4th: Read from

FIFO

B27–35 B18–26 B9–17 B0–8

CY7C43643

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CY7C43683

Table 1. Flag Programming[34]

SPM FS1/SEN FS0/SD MRS1/MRS2 X and Y Registers[



]

H H H ↑64

H H L ↑16

H L H ↑8

H L L ↑Parallel programming via Por t A

L H L ↑Serial program m ing via SD

L H H ↑Reserved

L L H ↑Reserved

L L L ↑Reserved

Table 2. Port A Enable Function

CSA W/RA ENA MBA CLKA A0–35 Outputs Port Function

H X X X X In high-impedance state None

L H L X X In high-impedance state None

LHHL↑In high-impedance state FIFO write

LHHH↑In high-impedan ce state Mail1 write

L L L L X Act ive, Mail2 regi ster None

LLHL↑Active , Mail2 regi ster None

L L L H X Act iv e, Mail2 register None

LLHH↑Active, Mail2 register Mail2 read (set MBF2 HI GH)

Table 3. Port B Enabl e Functi on

CSB W/RB ENB MBB CLKB B0–35 Out puts Port Function

H X X X X In hi gh-impe dance state None

L L L X X In high-impedance state None

LLHL↑In high-impedance state None

LLHH

↑In high-impedance state Mail2 write

L H L L X Active, FIFO output regist er None

LHHL↑Act ive, FIFO output regist er FIFO read

L H L H X Active, Mail1 reg ister None

LHHH↑Active, Mail 1 register Mail1 read (set MBF1 HIGH)

Note:

40. X regi ster holds the offset for AE; Y register holds the offset for AF.

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CY7C43683

Table 4. FIFO Flag Operation (CY Standard and FWFT Modes)[34]

Number of Words in FI FO Memory[41, 42, 43, 44] Synchronized to CLKB Synchron ized to CLKA

CY7C43643 CY7C43663 CY7C43683 EF/OR AE AF FF/IR

0 0 0 L L H H

1 TO X1 1 TO X1 1 TO X1 H L H H

(X1+1) to

[1024–(Y1+1)] (X1+1) to

[4096–(Y1+1)] (X 1 + 1) to

[16384–(Y1+1)] H H H H

(1024–Y1) to 1023 (4096–Y1) t o 4095 (16384–Y1) to 16383 H H L H

1024 4096 16384 H H L L

Table 5. Data Size for FIFO Long-Word Reads

Size Mode[45] Data Wri tten to FIFO Data Read From FIFO

BM SIZE BE A27–35 A18–26 A9–17 A0–8B27–35 B18–26 B9–17 B0–8

LXXABCDABCD

Table 6. Data Size for Wo rd Reads

Size Mode[45] Data Written to FIFO Read No. Data Read From FIFO

BM SIZE BE A27–35 A18–26 A9–17 A0–8B9–17 B0–8

HLHABCD1AB

2CD

HLLABCD1CD

2AB

Table 7. Data Size for Byte Reads from FIFO

Size Mode[45] Data Written to FIFO Read No. Data Read From

FIFO

BM SIZE BE A27–35 A18–26 A9–17 A0–8B0–8

HHHABCD1 A

HHLABCD1 D

Notes:

41. X is the Almost E m pty offset for FIFO used by AE. Y is the Almost Full offset for FIFO used by AF. Both X and Y are selected during a FIFO reset or port A

programming.

42. When a w ord loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.

43. Data i n the output register does not count as a “word in FIFO memory”. Since in FWFT Mode, the first word written to an empty FIFO goes unrequested to

the output register (no read operation necessary), it is not included in the FIFO memory count.

44. The OR and IR func tions are active during FWFT mode; the EF and FF functions are active in CY Standard Mode.

45. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.

CY7C43643

CY7C43663

CY7C43683

Ordering Information

1K x36 Unidirectional Synchronous F IFO w/ Bus Matching

Speed

(ns) Ordering Code Package

Name Package

Type Operating

Range

7 CY7C43643–7AC A128 128-Lead Thin Quad Flat Package Commercial

10 CY7C43643–10AC A128 128-Lead Thin Quad Fl at Package Commerci al

15 CY7C43643–15AC A128 128-Lead Thin Quad Fl at Package Commerci al

4K x36 Unidirectional Synchronous F IFO w/ Bus Matching

Speed

(ns) Ordering Code Package

Name Package

Type Operating

Range

7 CY7C43663–7AC A128 128-Lead Thin Quad Flat Package Commercial

10 CY7C43663–10AC A128 128-Lead Thin Quad Fl at Package Commerci al

15 CY7C43663–15AC A128 128-Lead Thin Quad Fl at Package Commerci al

16K x36 Unidirectional Synchronous FIFO w/ Bus Matching

Speed

(ns) Ordering Code Package

Name Package

Type Operating

Range

7 CY7C43683–7AC A128 128-Lead Thin Quad Flat Package Commercial

10 CY7C43683–10AC A128 128-Lead Thin Quad Fl at Package Commerci al

15 CY7C43683–15AC A128 128-Lead Thin Quad Fl at Package Commerci al

15 CY7C43683–15AI A128 128-Lead Thin Quad Fl at Package Industrial

Document #: 38-00699-D

CY7C43643

CY7C43663

CY7C43683

of any circui try other than circuitry embodied in a Cypress Semicon ductor product. Nor does it conv ey or imply any license under patent or oth er rights . Cypress Semiconductor does not authoriz e

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Package Di agram

128-Lead Thin Plasti c Quad Flatpack (14 x 20 x 1.4 mm) A128

51-85101-A