M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G 1GB, 512MB, 256MB PC3200 and PC2700 Unbuffered DDR DIMM 184 pin Unbuffered DDR DIMM Based on DDR400/333 512M bit Die B device Features * 184 Dual In-Line Memory Module (DIMM) * DRAM DLL aligns DQ and DQS transitions with clock transitions * Unbuffered DDR DIMM based on 110nm 512M bit die B device * Address and control signals are fully synchronous to positive * Performance: clock edge * Programmable Operation: PC2700 PC3200 6K 5T 2.5 3 fCK Clock Frequency 166 200 MHz tCK Clock Cycle 6 5 ns fDQ DQ Burst Frequency 333 400 - DIMM CAS Latency: 2, 2.5 (6K); 2, 2.5 (5T) Unit Speed Sort DIMM CAS Latency - Burst Type: Sequential or Interleave - Burst Length: 2, 4, 8 - Operation: Burst Read and Write * Auto Refresh (CBR) and Self Refresh Modes MHz * Automatic and controlled precharge commands * Intended for 200 and 166 MHz applications * 7.8 s Max. Average Periodic Refresh Interval * Inputs and outputs are SSTL-2 compatible * Serial Presence Detect EEPROM * VDD = VDDQ = 2.5V 0.2V (6K); VDD = VDDQ = 2.6V 0.1V (5T) * Gold contacts on module PCB * SDRAMs have 4 internal banks for concurrent operation * Available as Lead and Halogen free products * Differential clock inputs * Data is read or written on both clock edges Description M1U1G64DS8HB1G and M1Y1G64DS8HB1G (green part) are unbuffered 200-Pin Double Data Rate (DDR) Synchronous DRAM Unbuffered Dual In-Line Memory Module (UDIMM) and are organized as two ranks of 64Mbx64 high-speed memory array using sixteen 64Mx8 DDR SDRAMs TSOP packages. M1U51264DS88B1G and M1Y51264DS88B1G are unbuffered 200-Pin DDR Synchronous DRAM UDIMM and are organized as a single rank of 64Mbx64 high-speed memory array using eight 32Mx16 DDR SDRAMs TSOP packages. M1U25664DSH4B1G and M1Y25664DSH4B1G are unbuffered 200-Pin DDR Synchronous DRAM UDIMM and are organized as a single rank of 32Mbx64 high-speed memory array using four 32Mx16 DDR SDRAMs TSOP packages. Depending on the speed grade, these DIMMs are intended for use in applications operating up to 200 MHz clock speeds and achieves high-speed data transfer rates of up to 400 MHz. Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by address inputs and I/O inputs BA0 and BA1 using the mode register set cycle. The DIMM uses a serial EEPROM and through the use of a standard IIC protocol the serial presence-detect implementation (SPD) can be accessed. The first 128 bytes of the SPD data are programmed with the module characteristics as defined by JEDEC. REV 1.0 Sep 15, 2005 1 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G 1GB, 512MB, 256MB PC3200 and PC2700 Unbuffered DDR DIMM Ordering Information Part Number Size M1U1G64DS8HB1G-5T 128Mx64 M1U51264DS88B1G-5T 64x64 M1U25664DSH4B1G-5T 32x64 M1U1G64DS8HB1G-6K 128Mx64 M1U51264DS88B1G-6K 64x64 Speed DDR400 PC3200 Devices 3-3-3 Power 200MHz (5ns @ CL = 3) Leads 2.6V Gold M1U25664DSH4B1G-6K 32x64 Green Part Number Size M1Y1G64DS8HB1G-5T 128Mx64 M1Y51264DS88B1G-5T 64x64 M1Y25664DSH4B1G-5T DDR333 PC2700 Devices 2.5-3-3 166MHz (6ns @ CL = 2.5) Speed DDR400 PC3200 Devices 3-3-3 2.5V Power 200MHz (5ns @ CL = 3) Leads 2.6V Gold 32x64 lead free M1Y1G64DS8HB1G-6K 128Mx64 M1Y51264DS88B1G-6K 64x64 M1Y25664DSH4B1G-6K 32x64 halogen free DDR333 PC2700 Devices 2.5-3-3 166MHz (6ns @ CL = 2.5) 2.5V For the closest sales office or information, please visit: www.elixir-memory.com Nanya Technology Corporation Hwa Ya Technology Park 669 Fu Hsing 3rd Rd., Kueishan, Taoyuan, 333, Taiwan, R.O.C. Tel: +886-3-328-1688 REV 1.0 Sep 15, 2005 2 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G 1GB, 512MB, 256MB PC3200 and PC2700 Unbuffered DDR DIMM Pin Description CK0, CK1, CK2, Differential Clock Inputs. DQ0-DQ63 Data input/output Clock Enable DQS0-DQS7 Bidirectional data strobes RAS Row Address Strobe DM0-DM7 Input Data Mask CAS Column Address Strobe VDD Power WE Write Enable VDDQ Supply voltage for DQs CK0, CK1, CK2 CKE0, CKE1 S0, S1 Chip Selects VSS Ground A0-A9, A11, A12 Address Inputs NC No Connect A10/AP Address Input/Auto-precharge SCL Serial Presence Detect Clock Input BA0, BA1 SDRAM Bank Address Inputs SDA Serial Presence Detect Data input/output VREF Ref. Voltage for SSTL_2 inputs SA0-2 Serial Presence Detect Address Inputs VDDID VDD Identification flag. VDDSPD Serial EEPROM positive power supply Pinout Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 VREF 93 VSS 32 A5 124 VSS 62 VDDQ 154 RAS 2 DQ0 94 DQ4 33 DQ24 125 A6 63 WE 155 DQ45 3 VSS 95 DQ5 34 VSS 126 DQ28 64 DQ41 156 VDDQ 4 DQ1 96 VDDQ 35 DQ25 127 DQ29 65 CAS 157 S0 5 DQS0 97 DM0/DQS9 36 DQS3 128 VDDQ 66 VSS 158 S1 6 DQ2 98 DQ6 37 A4 129 DM3/DQS12 67 DQS5 159 DM5/DQS14 VSS 7 VDD 99 DQ7 38 VDD 130 A3 68 DQ42 160 8 DQ3 100 VSS 39 DQ26 131 DQ30 69 DQ43 161 DQ46 9 NC 101 NC 40 DQ27 132 VSS 70 VDD 162 DQ47 10 NC 102 NC 41 A2 133 DQ31 71 NC 163 NC 11 VSS 103 NC 42 VSS 134 NC 72 DQ48 164 VDDQ 12 DQ8 104 VDDQ 43 A1 135 NC 73 DQ49 165 DQ52 13 DQ9 105 DQ12 44 NC 136 VDDQ 74 VSS 166 DQ53 14 DQS1 106 DQ13 45 NC 137 CK0 75 CK2 167 NC 15 VDDQ 107 DM1/DQS10 46 VDD 138 CK0 76 CK2 168 VDD 16 CK1 108 VDD 47 NC 139 VSS 77 VDDQ 169 DM6/DQS15 17 CK1 109 DQ14 48 A0 140 NC 78 DQS6 170 DQ54 18 VSS 110 DQ15 49 NC 141 A10 79 DQ50 171 DQ55 19 DQ10 111 CKE1 50 VSS 142 NC 80 DQ51 172 VDDQ 20 DQ11 112 VDDQ 51 NC 143 VDDQ 81 VSS 173 NC 21 CKE0 113 NC 52 BA1 144 NC 82 VDDID 174 DQ60 22 VDDQ 114 DQ20 83 DQ56 175 DQ61 23 DQ16 115 A12 53 24 DQ17 116 VSS 25 DQS2 117 DQ21 26 VSS 118 A11 56 DQS4 148 VDD 87 DQ58 179 DQ63 27 A9 119 DM2/DQS11 57 DQ34 149 DM4/DQS13 88 DQ59 180 VDDQ 28 DQ18 120 VDD 58 VSS 150 DQ38 89 VSS 181 SA0 29 A7 121 DQ22 59 BA0 151 DQ39 90 WP 182 SA1 30 VDDQ 122 A8 60 DQ35 152 VSS 91 SDA 183 SA2 31 DQ19 123 DQ23 61 DQ40 153 DQ44 92 SCL 184 VDDSPD KEY KEY DQ32 145 VSS 84 DQ57 176 VSS 54 VDDQ 146 DQ36 85 VDD 177 DM7/DQS16 55 DQ33 147 DQ37 86 DQS7 178 DQ62 Note: All pin assignments are consistent for all 8-byte unbuffered versions. REV 1.0 Sep 15, 2005 3 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G 1GB, 512MB, 256MB PC3200 and PC2700 Unbuffered DDR DIMM Input/Output Functional Description Symbol CK0, CK1, CK2, CK0, CK1, CK2 CKE0, CKE1 Type (SSTL) (SSTL) Polarity Cross point Active High Function The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. Activates the DDR SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. Enables the associated DDR SDRAM command decoder when low and disables the S0, S1 (SSTL) Active Low command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Physical Bank 0 is selected by S0; Bank 1 is selected by S1. RAS, CAS, WE (SSTL) VREF Supply VDDQ Supply BA0, BA1 (SSTL) Active Low When sampled at the positive rising edge of the clock, RAS, CAS, WE define the operation to be executed by the SDRAM. Reference voltage for SSTL-2 inputs Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity - Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) A0 - A9 A10/AP A11, A12 when sampled at the rising clock edge. In addition to the column address, AP is used to (SSTL) - invoke auto-precharge operation at the end of the Burst Read or Write cycle. If AP is high, auto-precharge is selected and BA0/BA1 defines the bank to be precharged. If AP is low, auto-precharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge. DQ0 - DQ63 (SSTL) - DQS0 - DQS7, DQS9 - DQS16 (SSTL) Active High CB0 - CB7 (SSTL) - DM0 - DM8 Input Active High VDD, VSS Supply SA0 - SA2 - SDA - SCL - VDDSPD REV 1.0 Sep 15, 2005 Supply Data and Check Bit input/output pins operate in the same manner as on conventional DRAMs. Data strobes: Output with read data, input with write data. Edge aligned with read data, centered on write data. Used to capture write data. Data Check Bit Input/Output pins. Used on ECC modules and is not used on x64 modules. The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is not used on x64 modules. Power and ground for the DDR SDRAM input buffers and core logic Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V DD to act as a pull-up. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DD to act as a pull-up. Serial EEPROM positive power supply. 4 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G 1GB, 512MB, 256MB PC3200 and PC2700 Unbuffered DDR DIMM Functional Block Diagram 2 Ranks, 16 devices, 64Mx8 DDR SDRAMs, M1Y1G64DS8HB1G / M1U1G64DS8HB1G S1 S0 DQS0 DM0/DQS9 DQS4 DM4/DQS13 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQS D0 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D8 CS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D4 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D12 DQS5 DM5/DQS14 DQS1 DM1/DQS10 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS DQS D1 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D9 DQS D5 DQS D13 DQS6 DM6/DQS15 DQS2 DM2/DQS11 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 CS DQS D2 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D10 DQS D6 DQS D14 DQS7 DM7/DQS16 DQS3 DM3/DQS12 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 BA0-BA1 CS D3 DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 BA0-BA1 : SDRAMs D0-D15 A0-A13 A0-A13 : SDRAMs D0-D15 RAS RAS : SDRAMs D0-D15 CAS CAS : SDRAMs D0-D15 CKE0 CKE : SDRAMs D0-D7 CKE1 CKE : SDRAMs D8-D15 WE Notes : 1. 2. 3. 4. DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 WE : SDRAMs D0-D15 CS DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D11 Sep 15, 2005 Strap: see Note 4 DQS D15 * Clock Wiring Clock Input SDRAMs *CK0/CK0 4 SDRAMs *CK1/CK1 6 SDRAMs *CK2/CK2 6 SDRAMs * Wire per Clock Loading Table/ Wiring Diagrams Serial PD SCL WP DQ-to-I/O wiring is shown as recommended but may be changed. DQ/DQS/DM/CKE/S relationships must be maintained as shown. DQ, DQS, DM/DQS resistors: 22 Ohms. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD is not equal to VDDQ. REV 1.0 SPD D0-D15 D0-D15 D0-D15 VDDSPD VDD/VDDQ VREF VSS VDDID D7 DQS A0 A1 A2 SA0 SA1 SA2 SDA 5 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G 1GB, 512MB, 256MB PC3200 and PC2700 Unbuffered DDR DIMM Functional Block Diagram 1 Rank, 8 devices, 64Mx8 DDR SDRAMs, M1Y51264DS88B1G / M1U51264DS88B1G S0 DQS0 DM0/DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS4 DM4/DQS13 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D0 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D1 DQS2 DM2/DQS11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D2 CS DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D3 RAS RAS : SDRAMs D0-D7 CAS : SDRAMs D0-D7 CKE0 CKE : SDRAMs D0-D7 WE DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D6 DQS D7 * Wire per Clock Loading Table/ Wiring Diagrams WE : SDRAMs D0-D7 VDDSPD VDD/VDDQ VREF VSS VDDID Serial PD Sep 15, 2005 CS D5 * Clock Wiring Clock Input SDRAMs *CK0/CK0 2 SDRAMs *CK1/CK1 3 SDRAMs *CK2/CK2 3 SDRAMs A0-A13 : SDRAMs D0-D7 CAS REV 1.0 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQS BA0-BA1 : SDRAMs D0-D7 A0-A13 Notes : 1. 2. 3. 4. CS D4 DQS7 DM7/DQS16 BA0-BA1 SCL WP DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQS DQS6 DM6/DQS15 DQS3 DM3/DQS12 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CS DQS5 DM5/DQS14 DQS1 DM1/DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 A0 A1 A2 SA0 SA1 SA2 SDA SPD D0-D7 D0-D7 D0-D7 Strap: see Note 4 DQ-to-I/O wiring is shown as recommended but may be changed. DQ/DQS/DM/CKE/S relationships must be maintained as shown. DQ, DQS, DM/DQS resistors: 22 Ohms. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD is not equal to VDDQ. 6 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G 1GB, 512MB, 256MB PC3200 and PC2700 Unbuffered DDR DIMM Functional Block Diagram 1 Rank, 4 devices, 32Mx16 DDR SDRAMs, M1Y25664DSH4B1G / M1U25664DSH4B1G S0 DQS1 DM1/DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LDQS DQS0 DM0/DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQS CS LDM I/O 6 I/O 4 I/O 1 I/O 3 I/O 2 I/O 0 I/O 5 I/O 7 D0 UDM I/O 8 I/O 10 I/O 15 I/O 13 I/O 12 I/O 14 I/O 11 I/O 9 DQS3 DM3/DQS12 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 LDQS DQS2 DM2/DQS11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 UDQS CS LDM I/O 6 I/O 4 I/O 1 I/O 3 I/O 2 I/O 0 I/O 5 I/O 7 D1 UDM I/O 8 I/O 10 I/O 15 I/O 13 I/O 12 I/O 14 I/O 11 I/O 9 BA0-BA1 LDQS DQS4 DM4/DQS13 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 UDQS CS LDM I/O 6 I/O 4 I/O 1 I/O 3 I/O 2 I/O 0 I/O 5 I/O 7 D2 UDM I/O 8 I/O 10 I/O 15 I/O 13 I/O 12 I/O 14 I/O 11 I/O 9 DQS7 DM7/DQS16 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 LDQS DQS6 DM6/DQS15 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 UDQS CS LDM I/O 6 I/O 4 I/O 1 I/O 3 I/O 2 I/O 0 I/O 5 I/O 7 D3 UDM I/O 8 I/O 10 I/O 15 I/O 13 I/O 12 I/O 14 I/O 11 I/O 9 BA0-BA1 : SDRAMs D0-D3 * Clock Wiring Clock Input SDRAMs *CK0/CK0 NC *CK1/CK1 2 SDRAMs *CK2/CK2 2 SDRAMs A0-A13 : SDRAMs D0-D3 A0-A13 RAS RAS : SDRAMs D0-D3 CAS CAS : SDRAMs D0-D3 CKE0 * Wire per Clock Loading Table/ Wiring Diagrams CKE : SDRAMs D0-D3 WE WE : SDRAMs D0-D3 VDDSPD VDD/VDDQ VREF VSS VDDID Serial PD SCL WP Notes : 1. 2. 3. 4. DQS5 DM5/DQS14 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 A0 A1 A2 SA0 SA1 SA2 SDA SPD D0-D3 D0-D3 D0-D3 Strap: see Note 4 DQ-to-I/O wiring is shown as recommended but may be changed. DQ/DQS/DM/CKE/S relationships must be maintained as shown. DQ, DQS, DM/DQS resistors: 22 Ohms. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD is not equal to VDDQ. REV 1.0 Sep 15, 2005 7 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G 1GB, 512MB, 256MB PC3200 and PC2700 Unbuffered DDR DIMM Serial Presence Detect SPD Description Byte 0 Description Number of Serial PD Bytes Written during Production Byte 27 Description Minimum Row Precharge Time (tRP) 1 Total Number of Bytes in Serial PD device 28 Minimum Row Active to Row Active delay (tRRD) 2 Fundamental Memory Type 29 Minimum RAS to CAS delay (tRCD) 3 Number of Row Addresses on Assembly 30 Minimum RAS Pulse Width (tRAS) 4 Number of Column Addresses on Assembly 31 Module Bank Density 5 Number of DIMM Rank 32 Address and Command Setup Time Before Clock 6 Data Width of Assembly 33 Address and Command Hold Time After Clock 7 Data Width of Assembly (cont') 34 Data Input Setup Time Before Clock 8 Voltage Interface Level of this Assembly 35 Data Input Hold Time After Clock 9 10 DDR SDRAM Device Cycle Time 36-40 CL=2.5 DDR SDRAM Device Access Time from Clock 41 CL=2.5 11 DIMM Configuration Type 42 12 Refresh Rate/Type 43 Reserved Minimum Active/Auto-refresh Time (tRC) Auto-refresh to Active/Auto-refresh Command Period (tRFC) Max Cycle Time (tCK max) 13 Primary DDR SDRAM Width 44 Maximum DQS-DQ Skew Time (tDQSQ) 14 Error Checking DDR SDRAM Device Width 45 Maximum Read Data Hold Skew Factor (tQHS) 46 Reserved 47 UDIMM Height 15 16 17 18 DDR SDRAM Device Attr: Min CLK Delay, Random Col Access DDR SDRAM Device Attributes: Burst Length Supported DDR SDRAM Device Attributes: Number of Device 48-61 Banks DDR SDRAM Device Attributes: CAS Latencies Supported Reserved 62 SPD Revision Checksum Data 19 DDR SDRAM Device Attributes: CS Latency 63 20 DDR SDRAM Device Attributes: WE Latency 64-71 Manufacturer's JEDEC ID Code 21 DDR SDRAM Device Attributes: 72 Module Manufacturing Location 22 23 DDR SDRAM Device Attributes: General Minimum Clock Cycle CL=2.5 73-90 Module Part number 91-92 Module Revision Code Module Manufacturing Data 24 yy= Binary coded decimal year code, 0-99(Decimal), Maximum Data Access Time from Clock at 93-94 CL=2 00-63(Hex) ww= Binary coded decimal year code, 01-52(Decimal), 01-34(Hex) 25 Minimum Clock Cycle Time at CL=1 95-98 Module Serial Number 26 Maximum Data Access Time from Clock at CL=1 99-127 Reserved REV 1.0 Sep 15, 2005 8 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G 1GB, 512MB, 256MB PC3200 and PC2700 Unbuffered DDR DIMM SPD Values for M1Y1G64DS8HB1G / M1U1G64DS8HB1G PC3200 (5T) PC2700 (6K) Byte Byte Value Value Hex 0 128 80 128 80 1 256 08 256 08 2 DDR SDRAM 07 DDR SDRAM 07 3 13 0D 13 0D 4 11 0B 11 0B 5 2 02 2 02 6 x64 40 x64 40 7 x64 00 x64 00 8 SSTL 2.5V 04 SSTL 2.5V 04 60 9 5.0ns 50 6.0ns 10 0.65ns 65 0.70ns 70 11 Parity 00 Parity 00 12 SR/1x(7.8us) 82 SR/1x(7.8us) 82 13 x8 08 x8 08 14 N/A 00 N/A 00 15 1 Clock 01 1 Clock 01 16 2,4,8 0E 2,4,8 0E 17 4 04 4 04 18 2.5/3 18 2/2.5 0C 19 0 01 0 01 20 1 02 1 02 21 Diff. clock 20 Diff. clock 20 22 0.2V Tolerance C0 0.2V Tolerance C0 23 6.0ns 60 7.5ns 75 24 0.70ns 70 0.75ns 75 25 N/A 00 N/A 00 00 26 N/A 00 N/A 27 15ns 3C 18ns 48 28 10ns 28 12ns 30 29 15ns 3C 18ns 48 30 40ns 28 42ns 2A 31 1GB 80 1GB 80 32 0.60ns 60 0.75ns 75 33 0.60ns 60 0.75ns 75 34 0.40ns 40 0.45ns 45 35 0.40ns 40 0.45ns 45 36-40 Reserved 00 Reserved 00 41 55ns 37 60ns 3C 42 70ns 46 72ns 48 43 12 30 12 30 44 0.40 28 0.45 2D 45 0.50 50 0.55 55 46 N/A 00 N/A 00 47 1.0 01 1.0 01 48-61 Reserved 00 Reserved 00 62 SPD Version 10 SPD Version 10 63 Checksum C8 Checksum 7F7F7F0B 64-71 Nanya 72 Assembly -- Assembly -- 73-90 Module PN -- Module PN -- 91-92 Revision -- Revision -- 93-94 Year/Week Code -- Year/Week Code -- 95-98 Serial Number -- Serial Number -- 99-127 Reserved -- Reserved -- REV 1.0 Sep 15, 2005 00000000 Nanya 58 7F7F7F0B 00000000 9 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G 1GB, 512MB, 256MB PC3200 and PC2700 Unbuffered DDR DIMM SPD Values for M1Y51264DS88B1G / M1U51264DS88B1G PC2700 (5T) Byte Value 0 128 1 PC3200 (6K) Hex Byte Value 80 128 80 256 08 256 08 2 DDR SDRAM 07 DDR SDRAM 07 3 13 0D 13 0D 4 11 0B 11 0B 5 1 01 1 01 6 X64 40 X64 40 7 X64 00 X64 00 8 SSTL 2.5V 04 SSTL 2.5V 04 9 5ns 50 6ns 60 10 .65ns 65 .70ns 70 00 11 Non-Parity 00 Non-Parity 12 SR/1x(7.8us) 82 SR/1x(7.8us) 82 13 X8 08 X8 08 14 N/A 00 N/A 00 15 1 Clock 01 1 Clock 01 16 2,4,8 0E 2,4,8 0E 17 4 04 4 04 18 2.5/3 18 2/2.5 0C 19 0 01 0 01 20 1 02 1 02 21 Differential Clock 20 Differential Clock 20 22 +/-0.2V Tolerance C0 +/-0.2V Tolerance C0 23 6.0ns 60 7.5ns 75 24 0.70ns 70 0.75ns 75 25 N/A 00 N/A 00 26 N/A 00 N/A 00 27 15ns 3C 18ns 48 28 10ns 28 12ns 30 29 15ns 3C 18ns 48 30 40ns 28 42ns 2A 31 512MB 80 512MB 80 32 0.60ns 60 0.75ns 75 33 0.60ns 60 0.75ns 75 34 0.40ns 40 0.45ns 45 35 0.40ns 40 0.45ns 45 36-40 N/A 00 N/A 00 41 55ns 37 60ns 3C 42 70ns 46 72ns 48 43 12 30 12 30 44 0.40 28 0.45 2D 45 0.50 50 0.55 55 46 N/A 00 N/A 00 47 Height 31.75mm 01 Height 31.75mm 01 48-61 N/A 00 N/A 00 62 SPD 1.0 10 SPD 1.0 10 63 Checksum C7 Checksum 57 Nanya 7F7F7F0B 00000000 Nanya 7F7F7F0B 00000000 64-71 72 Assembly -- Assembly -- 73-90 Module PN -- Module PN -- 91-92 Revision -- Revision -- 93-94 Year/Week Code -- Year/Week Code -- 95-98 Serial Number -- Serial Number -- 99-127 Reserved -- Reserved -- REV 1.0 Sep 15, 2005 10 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G 1GB, 512MB, 256MB PC3200 and PC2700 Unbuffered DDR DIMM SPD Values for M1Y25664DSH4B1G / M1U25664DSH4B1G PC2700 (5T) Byte Value 0 128 1 PC3200 (6K) Hex Byte Value 80 128 80 256 08 256 08 2 DDR SDRAM 07 DDR SDRAM 07 3 13 0D 13 0D 4 10 0A 10 0A 5 1 01 1 01 6 X64 40 X64 40 7 X64 00 X64 00 8 SSTL 2.5V 04 SSTL 2.5V 04 60 9 5ns 50 6ns 10 .65ns 65 .7ns 70 11 Non-Parity 00 Non-Parity 00 12 SR/1x(7.8us) 82 SR/1x(7.8us) 82 13 X16 10 X16 10 14 N/A 00 N/A 00 15 1 Clock 01 1 Clock 01 16 2,4,8 0E 2,4,8 0E 17 4 04 4 04 18 2.5/3 18 2/2.5 0C 19 0 01 0 01 20 1 02 1 02 21 Differential Clock 20 Differential Clock 20 22 +/-0.2V Tolerance C0 +/-0.2V Tolerance C0 23 6.0ns 60 7.5ns 75 24 0.75ns 70 0.75ns 75 25 N/A 00 N/A 00 26 N/A 00 N/A 00 27 15ns 3C 18ns 48 28 10ns 28 12ns 30 29 15ns 3C 18ns 48 30 40ns 28 42ns 2A 31 256MB 40 256MB 40 32 0.6ns 60 0.75ns 75 33 0.6ns 60 0.75ns 75 34 0.4ns 40 0.45ns 45 35 0.4ns 40 0.45ns 45 36-40 N/A 00 N/A 00 41 55ns 37 60ns 3C 42 70ns 46 72ns 48 43 12 30 12 30 44 0.4 28 0.45 2D 45 0.5 50 0.55 55 46 N/A 00 N/A 00 01 47 Height 31.75mm 01 Height 31.75mm 48-61 N/A 00 N/A 00 62 SPD 1.0 10 SPD 1.0 10 63 Checksum 8E Checksum 1E Nanya 7F7F7F0B 00000000 Nanya 7F7F7F0B 00000000 64-71 72 Assembly -- Assembly -- 73-90 Module PN -- Module PN -- 91-92 Revision -- Revision -- 93-94 Year/Week Code -- Year/Week Code -- 95-98 Serial Number -- Serial Number -- 99-127 Reserved -- Reserved -- REV 1.0 Sep 15, 2005 11 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G 1GB, 512MB, 256MB PC3200 and PC2700 Unbuffered DDR DIMM Absolute Maximum Ratings Symbol VIN, VOUT Parameter Units -0.5 to VDDQ +0.5 V VIN Voltage on Input relative to VSS -0.5 to +3.6 V VDD Voltage on VDD supply relative to VSS -0.5 to +3.6 V VDDQ Voltage on VDDQ supply relative to VSS -0.5 to +3.6 V 0 to +70 C -55 to +150 C TA TSTG Voltage on I/O pins relative to VSS Rating Operating Temperature (Ambient) Storage Temperature (Plastic) PD Power Dissipation (per device component) 1 W IOUT Short Circuit Output Current 50 mA Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC Electrical Characteristics and Operating Conditions TA= 0C ~ 70C; VDDQ= VDD= 2.5V0.2V(6K); TA= 0C ~ 70C; VDDQ= VDD= 2.6V0.1V(5T) Symbol VDD VDDQ VSS, VSSQ Parameter Min Supply Voltage I/O Supply Voltage Supply Voltage, I/O Supply Voltage 6K 2.3 5T 2.5 6K 2.3 5T 2.5 Max Units Notes 2.7 V 1 2.7 V 1 0 0 V VREF I/O Reference Voltage 0.49 x VDDQ 0.51 x VDDQ V 1, 2 VTT I/O Termination Voltage (System) VREF - 0.04 VREF + 0.04 V 1, 3 Input High (Logic1) Voltage VREF + 0.15 VDDQ + 0.3 V 1 VIH (DC) VIL (DC) Input Low (Logic0) Voltage -0.3 VREF - 0.15 V 1 VIN (DC) Input Voltage Level, CK and CK Inputs -0.3 VDDQ + 0.3 V 1 VID (DC) Input Differential Voltage, CK and CK Inputs 0.30 VDDQ + 0.6 V 1, 4 -10 10 A 1 -10 10 A 1 -16.8 - mA 1 16.8 - mA 1 II IOZ IOH IOL Input Leakage Current Any input 0V VIN VDD; (All other pins not under test = 0V) Output Leakage Current (DQs are disabled; 0V Vout VDDQ Output High Current (VOUT = VDDQ -0.373V, min VREF, min VTT) Output Low Current (VOUT = 0.373, max VREF, max VTT) 1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. 3. VTT is not applied directly to the DIMM. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 4. VID is the magnitude of the difference between the input level on CK and the input level on CK. REV 1.0 Sep 15, 2005 12 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G 1GB, 512MB, 256MB PC3200 and PC2700 Unbuffered DDR DIMM AC Characteristics Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, Operating, Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.) 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below. 4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL (AC) and VIH (AC) unless otherwise specified. 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW (HIGH) level. AC Output Load Circuits VTT 50 ohms Output Timing Reference Point VOUT 30 pF AC Operating Conditions Symbol Parameter/Condition Min VIH (AC) Input High (Logic 1) Voltage. VIL (AC) Input Low (Logic 0) Voltage. VID (AC) Input Differential Voltage, CK and CK Inputs VIX (AC) Input Differential Pair Cross Point Voltage, CK and CK Inputs Max Unit Notes V 1, 2 VREF - 0.31 V 1, 2 0.62 VDDQ + 0.6 V 1, 2, 3 (0.5* VDDQ) - 0.2 (0.5* VDDQ) + 0.2 V 1, 2, 4 VREF + 0.31 1. Input slew rate = 1V/ ns. 2. Inputs are not recognized as valid until VREF stabilizes. 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. REV 1.0 Sep 15, 2005 13 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G 1GB, 512MB, 256MB PC3200 and PC2700 Unbuffered DDR DIMM Operating, Standby, and Refresh Currents TA = 0 C ~ 70 C; VDDQ= VDD= 2.5V 0.2V (6K); VDDQ= VDD= 2.6V 0.1V (5T) Symbol IDD0 IDD1 IDD2P IDD2N IDD3P IDD3N IDD4R IDD4W Parameter/Condition Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) IDD5 Auto-Refresh Current: tRC = tRFC (MIN) IDD6 Self-Refresh Current: CKE 0.2V IDD7 Notes 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2,3 1,2 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 1,2 1. IDD specifications are tested after the device is properly initialized. 2. Input slew rate = 1V/ ns. 3. Current at 7.8 s is time averaged value of IDD5 at tRFC (MIN) and IDD2P over 7.8 s. All IDD current values are calculated from device level. Symbol M1Y1G64DS8HB1G M1Y51264DS88B1G M1Y25664DSH4B1G M1U1G64DS8HB1G M1U51264DS88B1G M1U25664DSH4B1G PC3200 PC2700 PC3200 PC2700 PC3200 PC2700 (mA) (5T) (6K) (5T) (6K) (5T) (6K) IDD0 1651 1575 801 765 400 382 mA IDD1 1702 1634 826 794 413 397 mA IDD2P 60 57 28 27 14 13 mA IDD2N 476 420 224 198 112 99 mA IDD3P 211 195 99 92 50 46 mA IDD3N 852 767 401 361 200 180 mA IDD4R 2010 1705 980 830 490 415 mA IDD4W 2195 1910 1072 932 536 466 mA IDD5 3225 3125 1587 1540 794 770 mA IDD6 37 38 17 18 9 9 mA IDD7 5863 4961 2907 2458 1453 1229 mA REV 1.0 Sep 15, 2005 14 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G 1GB, 512MB, 256MB PC3200 and PC2700 Unbuffered DDR DIMM Package Dimensions M1Y1G64DS8HB1G / M1U1G64DS8HB1G, 16 TSOP devices FRONT 133.35 5.250 17.80 0.700 31.75 1.250 10.0 0.394 (2x)4.00 0.157 128.93 5.076 Detail A 2.30 0.91 2.50 0.098 Detail B Side BACK 4.00 0.157 MAX Detail A 1.27+/- 0.10 0.050 +/- 0.004 3.80 0.150 4.00 0.157 Detail B 6.35 0.250 1.80 0.071 1.00 Width 0.039 1.27 Pitch 0.05 Note: All dimensions are typical with tolerances of +/- 0.15 (0.006) unless otherwise stated. Units: Millimeters (Inches) Note: Device packaging not drawn to scale. Placed only for references REV 1.0 Sep 15, 2005 15 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G 1GB, 512MB, 256MB PC3200 and PC2700 Unbuffered DDR DIMM Package Dimensions M1Y51264DS88B1G / M1U51264DS88B1G, 8 TSOP devices FRONT 133.35 5.250 17.80 0.700 31.75 1.250 10.0 0.394 (2x)4.00 0.157 128.93 5.076 Detail A 2.30 0.91 2.50 0.098 Detail B Side BACK Detail A 3.18 0.125 MAX 1.27+/- 0.10 0.050 +/- 0.004 3.80 0.150 4.00 0.157 Detail B 6.35 0.250 1.80 0.071 1.00 Width 0.039 1.27 Pitch 0.05 Note: All dimensions are typical with tolerances of +/- 0.15 (0.006) unless otherwise stated. Units: Millimeters (Inches) Note: Device packaging not drawn to scale. Placed only for references REV 1.0 Sep 15, 2005 16 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G 1GB, 512MB, 256MB PC3200 and PC2700 Unbuffered DDR DIMM Package Dimensions M1Y25664DSH4B1G / M1U25664DSH4B1G, 4 TSOP devices FRONT 133.35 5.250 17.80 0.700 31.75 1.250 10.00 0.394 (2x)4.00 0.157 128.93 5.076 Detail A 2.30 0.91 2.50 0.098 Detail B Side BACK Detail A 3.18 0.125 MAX 1.27+/- 0.10 0.050 +/- 0.004 3.80 0.150 4.00 0.157 Detail B 6.35 0.250 1.80 0.071 1.00 Width 0.039 1.27 Pitch 0.05 Note: All dimensions are typical with tolerances of +/- 0.15 (0.006) unless otherwise stated. Units: Millimeters (Inches) Note: Device packaging not drawn to scale. Placed only for references REV 1.0 Sep 15, 2005 17 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G 1GB, 512MB, 256MB PC3200 and PC2700 Unbuffered DDR DIMM Revision Log Rev Date Modification Initial release: 1.0 Sep 15 ,2005 1GB: M1Y1G64DS8HB1G - 5T/6K, M1U1G64DS8HB1G - 5T/6K 512MB: M1Y51264DS88B1G - 5T/6K; M1U51264DS88B1G - 5T/6K 256MB: M1Y25664DSH4B1G - 5T/6K; M1U25664DSH4B1G - 5T/6K REV 1.0 Sep 15, 2005 18 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice.