M1U1G64DS8HB1G-5T - Nanya Technology Corporation

M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G

M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G

1GB, 512MB, 256MB

PC3200 and PC2700 Unbuffered DDR DI MM

REV 1.0 1

Sep 15, 2005

NANYA reserves the right to change products and specifications without notice.

184 pin Unbuffered DDR DIMM

Based on DDR400/333 512M bit Die B device

Features

• 184 Dual In-Line Memory Module (DIMM)

• Unbuffered DDR DIMM based on 110nm 512M bit die B device

• Performance:

PC2700 PC3200

Speed Sort 6K 5T

DIMM CAS Latency 2.5 3

Unit

fCK Clock Frequency 166 200 MHz

tCK Clock Cycle 6 5 ns

fDQ DQ Burst Frequency 333 400 MHz

• Intended for 200 and 166 MHz applications

• Inputs and outputs are SSTL-2 compatible

• VDD = VDDQ = 2.5V ± 0.2V (6K); VDD = VDDQ = 2.6V ± 0.1V (5T)

• SDRAMs have 4 internal banks for concurrent operation

• Differential clock inputs

• Data is read or written on both clock edges

• DRAM DLL aligns DQ and DQS transitions with clock transitions

• Address and control signals are fully synchronous to positive

clock edge

• Programmable Operation:

- DIMM CAS Latency: 2, 2.5 (6K); 2, 2.5 (5T)

- Burst Type: Sequential or Interleave

- Burst Length: 2, 4, 8

- Operation: Burst Read and Write

• Auto Refresh (CBR) and Self Refresh Modes

• Automatic and controlled precharge commands

• 7.8 µs Max. Average Periodic Refresh Interval

• Serial Presence Detect EEPROM

• Gold contacts on module PCB

• Available as Lead and Halogen free products

Description

M1U1G64DS8HB1G and M1Y1G64DS8HB1G (green part) are unbuffered 200-Pin Double Data Rate (DDR) Synchronous DRAM Unbuffered

Dual In-Line Memory Module (UDIMM) and are organized as two ranks of 64Mbx64 high-speed memory array using sixteen 64Mx8 DDR

SDRAMs TSOP packages. M1U51264DS88B1G and M1Y51264DS88B1G are unbuffered 200-Pin DDR Synchronous DRAM UDIMM and are

organized as a single rank of 64Mbx64 high-speed memory array using eight 32Mx16 DDR SDRAMs TSOP packages. M1U25664DSH4B1G

and M1Y25664DSH4B1G are unbuffered 200-Pin DDR Synchronous DRAM UDIMM and are organized as a single rank of 32Mbx64 high-speed

memory array using four 32Mx16 DDR SDRAMs TSOP packages.

Depending on the speed grade, these DIMMs are intended for use in applications operating up to 200 MHz clock speeds and achieves

high-speed data transfer rates of up to 400 MHz. Prior to any access operation, the device CAS latency and burst type/ length/operation type

must be programmed into the DIMM by address inputs and I/O inputs BA0 and BA1 using the mode register set cycle.

The DIMM uses a serial EEPROM and through the use of a standard IIC protocol the serial presence-detect implementation (SPD) can be

accessed. The first 128 bytes of the SPD data are programmed with the module characteristics as defined by JEDEC.

M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G

M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G

1GB, 512MB, 256MB

PC3200 and PC2700 Unbuffered DDR DI MM

REV 1.0 2

Sep 15, 2005

NANYA reserves the right to change products and specifications without notice.

Ordering Information

Part Number Size Speed Power Leads

M1U1G64DS8HB1G-5T 128Mx64

M1U51264DS88B1G-5T 64x64

M1U25664DSH4B1G-5T 32x64

DDR400

Devices

PC3200

3-3-3

200MHz (5ns @ CL = 3) 2.6V

M1U1G64DS8HB1G-6K 128Mx64

M1U51264DS88B1G-6K 64x64

M1U25664DSH4B1G-6K 32x64

DDR333

Devices

PC2700

2.5-3-3

166MHz (6ns @ CL = 2.5) 2.5V

Gold

Green Part Number Size Speed Power Leads

M1Y1G64DS8HB1G-5T 128Mx64

M1Y51264DS88B1G-5T 64x64

M1Y25664DSH4B1G-5T 32x64

DDR400

Devices

PC3200

3-3-3

200MHz (5ns @ CL = 3) 2.6V

M1Y1G64DS8HB1G-6K 128Mx64

M1Y51264DS88B1G-6K 64x64

M1Y25664DSH4B1G-6K 32x64

DDR333

Devices

PC2700

2.5-3-3

166MHz (6ns @ CL = 2.5) 2.5V

Gold

lead free

halogen free

For the closest sales office or information, please visit: www.elixir-memory.com

Nanya Technology Corporation

Hwa Ya Technology Park 669

Fu Hsing 3rd Rd., Kueishan,

Taoyuan, 333, Taiwan, R.O.C.

Tel: +886-3-328-1688

M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G

M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G

1GB, 512MB, 256MB

PC3200 and PC2700 Unbuffered DDR DI MM

REV 1.0 3

Sep 15, 2005

NANYA reserves the right to change products and specifications without notice.

Pin Description

CK0, CK1, CK2,

CK0, CK1, CK2 Differential Clock Inputs. DQ0-DQ63 Data input/output

CKE0, CKE1 Clock Enable DQS0-DQS7 Bidirectional data strobes

RAS Row Address Strobe

DM0-DM7 Input Data Mask

CAS Column Address Strobe VDD Power

WE Write Enable VDDQ Supply voltage for DQs

S0, S1 Chip Selects VSS Ground

A0-A9, A11, A12 Address Inputs NC No Connect

A10/AP Address Input/Auto-precharge SCL Serial Presence Detect Clock Input

BA0, BA1 SDRAM Bank Address Inputs SDA Serial Presence Detect Data input/output

VREF Ref. Voltage for SSTL_2 inputs SA0-2 Serial Presence Detect Address Inputs

VDDID V

DD Identification flag. VDDSPD Serial EEPROM positive power supply

Pinout

Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back

1 VREF 93 VSS 32 A5 124 VSS 62 VDDQ 154

RAS

2 DQ0 94 DQ4 33 DQ24 125 A6 63

WE 155 DQ45

3 VSS 95 DQ5 34 VSS 126 DQ28 64 DQ41 156 VDDQ

4 DQ1 96 VDDQ 35 DQ25 127 DQ29 65

CAS 157 S0

5 DQS0 97 DM0/DQS9 36 DQS3 128 VDDQ 66 VSS 158

6 DQ2 98 DQ6 37 A4 129 DM3/DQS12 67 DQS5 159 DM5/DQS14

7 VDD 99 DQ7 38 VDD 130 A3 68 DQ42 160 VSS

8 DQ3 100 VSS 39 DQ26 131 DQ30 69 DQ43 161 DQ46

9 NC 101 NC 40 DQ27 132 VSS 70 VDD 162 DQ47

10 NC 102 NC 41 A2 133 DQ31 71 NC 163 NC

11 VSS 103 NC 42 VSS 134 NC 72 DQ48 164 VDDQ

12 DQ8 104 VDDQ 43 A1 135 NC 73 DQ49 165 DQ52

13 DQ9 105 DQ12 44 NC 136 VDDQ 74 VSS 166 DQ53

14 DQS1 106 DQ13 45 NC 137 CK0 75 CK2 167 NC

15 VDDQ 107 DM1/DQS10 46 VDD 138 CK0 76 CK2 168 VDD

16 CK1 108 VDD 47 NC 139 VSS 77 VDDQ 169 DM6/DQS15

17 CK1 109 DQ14 48 A0 140 NC 78 DQS6 170 DQ54

18 VSS 110 DQ15 49 NC 141 A10 79 DQ50 171 DQ55

19 DQ10 111 CKE1 50 VSS 142 NC 80 DQ51 172 VDDQ

20 DQ11 112 VDDQ 51 NC 143 VDDQ 81 VSS 173 NC

21 CKE0 113 NC 52 BA1 144 NC 82 VDDID 174 DQ60

22 VDDQ 114 DQ20 KEY KEY 83 DQ56 175 DQ61

23 DQ16 115 A12 53 DQ32 145 VSS 84 DQ57 176 VSS

24 DQ17 116 VSS 54 VDDQ 146 DQ36 85 VDD 177 DM7/DQS16

25 DQS2 117 DQ21 55 DQ33 147 DQ37 86 DQS7 178 DQ62

26 VSS 118 A11 56 DQS4 148 VDD 87 DQ58 179 DQ63

27 A9 119 DM2/DQS11 57 DQ34 149 DM4/DQS13 88 DQ59 180 VDDQ

28 DQ18 120 VDD 58 VSS 150 DQ38 89 VSS 181 SA0

29 A7 121 DQ22 59 BA0 151 DQ39 90 WP 182 SA1

30 VDDQ 122 A8 60 DQ35 152 VSS 91 SDA 183 SA2

31 DQ19 123 DQ23 61 DQ40 153 DQ44 92 SCL 184 VDDSPD

Note: All pin assignments are consistent for all 8-byte unbuffered versions.

M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G

M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G

1GB, 512MB, 256MB

PC3200 and PC2700 Unbuffered DDR DI MM

REV 1.0 4

Sep 15, 2005

NANYA reserves the right to change products and specifications without notice.

Input/Output Functional Description

Symbol Type Polarity Function

CK0, CK1, CK2,

CK0, CK1, CK2 (SSTL) Cross

point

The system clock inputs. All address and command lines are sampled on the cross point of

the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven

from the clock inputs and output timing for read operations is synchronized to the input

clock.

CKE0, CKE1 (SSTL) Active

High

Activates the DDR SDRAM CK signal when high and deactivates the CK signal when low.

By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh

mode.

S0, S1 (SSTL) Active

Low

Enables the associated DDR SDRAM command decoder when low and disables the

command decoder when high. When the command decoder is disabled, new commands are

ignored but previous operations continue. Physical Bank 0 is selected by S0; Bank 1 is

selected by S1.

RAS, CAS, WE (SSTL) Active

Low When sampled at the positive rising edge of the clock, RAS, CAS, WE define the operation to

be executed by the SDRAM.

VREF Supply

Reference voltage for SSTL-2 inputs

VDDQ Supply Isolated power supply for the DDR SDRAM output buffers to provide improved noise

immunity

BA0, BA1 (SSTL) -

Selects which SDRAM bank is to be active.

A0 - A9

A10/AP

A11, A12 (SSTL) -

During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when

sampled at the rising clock edge.

During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)

when sampled at the rising clock edge. In addition to the column address, AP is used to

invoke auto-precharge operation at the end of the Burst Read or Write cycle. If AP is high,

auto-precharge is selected and BA0/BA1 defines the bank to be precharged. If AP is low,

auto-precharge is disabled.

During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control

which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the

state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.

DQ0 - DQ63 (SSTL) -

Data and Check Bit input/output pins operate in the same manner as on conventional

DRAMs.

DQS0 - DQS7,

DQS9 – DQS16 (SSTL) Active

High Data strobes: Output with read data, input with write data. Edge aligned with read data,

centered on write data. Used to capture write data.

CB0 – CB7 (SSTL) - Data Check Bit Input/Output pins. Used on ECC modules and is not used on x64 modules.

DM0 – DM8 Input Active

High

The data write masks, associated with one data byte. In Write mode, DM operates as a byte

mask by allowing input data to be written if it is low but blocks the write operation if it is high.

In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is

not used on x64 modules.

VDD, VSS Supply

Power and ground for the DDR SDRAM input buffers and core logic

SA0 – SA2 -

Address inputs. Connected to either VDD or VSS on the system board to configure the Serial

Presence Detect EEPROM address.

SDA -

This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor

must be connected from the SDA bus line to V DD to act as a pull-up.

SCL -

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be

connected from the SCL bus time to V DD to act as a pull-up.

VDDSPD Supply

Serial EEPROM positive power supply.

M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G

M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G

1GB, 512MB, 256MB

PC3200 and PC2700 Unbuffered DDR DI MM

REV 1.0 5

Sep 15, 2005

NANYA reserves the right to change products and specifications without notice.

Functional Block Diagram

2 Ranks, 16 devices, 64Mx8 DDR SDRAMs, M1Y1G64DS8HB1G / M1U1G64DS8HB1G

Serial PD

A0 A2A1

SCL

WP SDA

SA0 SA2SA1

A0-A13

RAS

BA0-BA1 BA0-BA1 : SDRAMs D0-D15

A0-A13 : SDRAMs D0-D15

RAS : SDRAMs D0-D15

CKE0

CAS CAS : SDRAMs D0-D15

CKE : SDRAMs D0-D7

CKE : SDRAMs D8-D15

WE : SDRAMs D0-D15

CKE1

VDDSPD

VSS

VREF

VDDID

VDD/VDDQ

Strap: see Note 4

SPD

D0-D15

* Wire per Clock Loading Table/

Wiring Diagrams

* Clock Wiring

Clock Input SDRAMs

*CK0/CK0

*CK1/CK1

*CK2/CK2

4 SDRAMs

6 SDRAMs

Notes :

1. DQ-to-I/O wiring is shown as recommended but may be changed.

2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.

3. DQ, DQS, DM/DQS resistors: 22 Ohms.

4. VDDID strap connections (for memory device VDD, VDDQ):

STRAP OUT (OPEN): VDD = VDDQ

STRAP IN (VSS): VDD is not equal to VDDQ.

DM0/DQS9

DQ0

DQ1

DQ2

DQ7

DQ4

DQ6

DQ5

DQ3

DQ8

DQ9

DQ10

DQ15

DQ12

DQ14

DQ13

DQ11

DQ16

DQ17

DQ18

DQ23

DQ20

DQ22

DQ21

DQ19

DQ24

DQ25

DQ26

DQ31

DQ28

DQ30

DQ29

DQ27

I/O 7

I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DM CS

I/O 7

I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DM CS

DQS0

DM4/DQS13

DQS4

I/O 7

I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DM CS

DM1/DQS10

DQS1

DQS

DM2/DQS11

DQS2

DM3/DQS12

DQS3

DQS

DQ32

DQ33

DQ34

DQ39

DQ36

DQ38

DQ37

DQ35

DQ40

DQ41

DQ42

DQ47

DQ44

DQ46

DQ45

DQ43

I/O 7

I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DM CS

DQS

DQS5

DM5/DQS14

DQ48

DQ49

DQ50

DQ55

DQ52

DQ54

DQ53

DQ51

DQ56

DQ57

DQ58

DQ63

DQ60

DQ62

DQ61

DQ59

DQS6

DM6/DQS15

DQS7

DM7/DQS16

DQS

I/O 0

I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

DM CS

DQS

I/O 0

I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

DM CS

DQS

I/O 0

I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

DM CS

D10

DQS

I/O 0

I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

DM CS

D11

DQS

I/O 7

I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DM CS

I/O 7

I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DM CS

I/O 7

I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DM CS

DQS

I/O 7

I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DM CS

DQS

I/O 0

I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

DM CS

D12

DQS

I/O 0

I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

DM CS

D13

DQS

I/O 0

I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

DM CS

D14

DQS

I/O 0

I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

DM CS

D15

DQS

M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G

M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G

1GB, 512MB, 256MB

PC3200 and PC2700 Unbuffered DDR DI MM

REV 1.0 6

Sep 15, 2005

NANYA reserves the right to change products and specifications without notice.

Functional Block Diagram

1 Rank, 8 devices, 64Mx8 DDR SDRAMs, M1Y51264DS88B1G / M1U51264DS88B1G

Serial PD

A0 A2A1

SCL

WP SDA

SA0 SA2SA1

A0-A13

RAS

BA0-BA1 BA0-BA1 : SDRAMs D0-D7

A0-A13 : SDRAMs D0-D7

RAS : SDRAMs D0-D7

CKE0

CAS CAS : SDRAMs D0-D7

CKE : SDRAMs D0-D7

WE WE : SDRAMs D0-D7

VDDSPD

VSS

VREF

VDDID

VDD/VDDQ

Strap: see Note 4

SPD

D0-D7

* Wire per Clock Loading Table/

Wiring Diagrams

* Clock Wiring

Clock Input SDRAMs

*CK0/CK0

*CK1/CK1

*CK2/CK2

2 SDRAMs

3 SDRAMs

Notes :

1. DQ-to-I/O wiring is shown as recommended but may be changed.

2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.

3. DQ, DQS, DM/DQS resistors: 22 Ohms.

4. VDDID strap connections (for memory device VDD, VDDQ):

STRAP OUT (OPEN): VDD = VDDQ

STRAP IN (VSS): VDD is not equal to VDDQ.

DM0/DQS9

DQ0

DQ1

DQ2

DQ7

DQ4

DQ6

DQ5

DQ3

DQ8

DQ9

DQ10

DQ15

DQ12

DQ14

DQ13

DQ11

DQ16

DQ17

DQ18

DQ23

DQ20

DQ22

DQ21

DQ19

DQ24

DQ25

DQ26

DQ31

DQ28

DQ30

DQ29

DQ27

I/O 7

I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DM CS

I/O 7

I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DM CS

I/O 7

I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DM CS

DQS0

DM4/DQS13

DQS4

DQS

I/O 7

I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DM CS

DQS

DM1/DQS10

DQS1

DQS

DM2/DQS11

DQS2

DM3/DQS12

DQS3

DQS

DQ32

DQ33

DQ34

DQ39

DQ36

DQ38

DQ37

DQ35

DQ40

DQ41

DQ42

DQ47

DQ44

DQ46

DQ45

DQ43

I/O 7

I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DM CS

DQS

I/O 7

I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DM CS

DQS

DQS5

DM5/DQS14

DQ48

DQ49

DQ50

DQ55

DQ52

DQ54

DQ53

DQ51

I/O 7

I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DM CS

DQS

DQ56

DQ57

DQ58

DQ63

DQ60

DQ62

DQ61

DQ59

I/O 7

I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DM CS

DQS

DQS6

DM6/DQS15

DQS7

DM7/DQS16

M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G

M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G

1GB, 512MB, 256MB

PC3200 and PC2700 Unbuffered DDR DI MM

REV 1.0 7

Sep 15, 2005

NANYA reserves the right to change products and specifications without notice.

Functional Block Diagram

1 Rank, 4 devices, 32Mx16 DDR SDRAMs, M1Y25664DSH4B1G / M1U25664DSH4B1G

Serial PD

A0 A2A1

SCL

WP SDA

SA0 SA2SA1

A0-A13

RAS

BA0-BA1 BA0-BA1 : SDRAMs D0-D3

A0-A13 : SDRAMs D0-D3

RAS : SDRAMs D0-D3

CKE0

CAS CAS : SDRAMs D0-D3

CKE : SDRAMs D0-D3

WE WE : SDRAMs D0-D3

VDDSPD

VSS

VREF

VDDID

VDD/VDDQ

Strap: see Note 4

SPD

D0-D3

* Wire per Clock Loading Table/

Wiring Diagrams

* Clock Wiring

Clock Input SDRAMs

*CK0/CK0

*CK1/CK1

*CK2/CK2

2 SDRAMs

DM1/DQS10

DQ8

DQ9

DQ10

DQ15

DQ12

DQ14

DQ13

DQ11

DQ0

DQ1

DQ2

DQ7

DQ4

DQ6

DQ5

DQ3

DQ24

DQ25

DQ26

DQ31

DQ28

DQ30

DQ29

DQ27

DQ16

DQ17

DQ18

DQ23

DQ20

DQ22

DQ21

DQ19

DQS1

DM5/DQS14

DQS5

DM0/DQS9

DQS0

DM3/DQS12

DQS3

DM2/DQS11

DQS2

DQ40

DQ41

DQ42

DQ47

DQ44

DQ46

DQ45

DQ43

DQ32

DQ33

DQ34

DQ39

DQ36

DQ38

DQ37

DQ35

DQS4

DM4/DQS13

DQ56

DQ57

DQ58

DQ63

DQ60

DQ62

DQ61

DQ59

DQ48

DQ49

DQ50

DQ55

DQ52

DQ54

DQ53

DQ51

DQS7

DM7/DQS16

DQS6

DM6/DQS15

I/O 6

I/O 4

I/O 5

I/O 0

I/O 2

I/O 3

I/O 1

I/O 7

LDM

I/O 8

I/O 10

I/O 11

I/O 14

I/O 12

I/O 13

I/O 15

I/O 9

UDM

UDQS

LDQS

I/O 6

I/O 4

I/O 5

I/O 0

I/O 2

I/O 3

I/O 1

I/O 7

LDM

I/O 8

I/O 10

I/O 11

I/O 14

I/O 12

I/O 13

I/O 15

I/O 9

UDM

UDQS

LDQS

I/O 6

I/O 4

I/O 5

I/O 0

I/O 2

I/O 3

I/O 1

I/O 7

LDM

I/O 8

I/O 10

I/O 11

I/O 14

I/O 12

I/O 13

I/O 15

I/O 9

UDM

UDQS

LDQS

I/O 6

I/O 4

I/O 5

I/O 0

I/O 2

I/O 3

I/O 1

I/O 7

LDM

I/O 8

I/O 10

I/O 11

I/O 14

I/O 12

I/O 13

I/O 15

I/O 9

UDM

UDQS

LDQS

Notes :

1. DQ-to-I/O wiring is shown as recommended but may be changed.

2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.

3. DQ, DQS, DM/DQS resistors: 22 Ohms.

4. VDDID strap connections (for memory device VDD, VDDQ):

STRAP OUT (OPEN): VDD = VDDQ

STRAP IN (VSS): VDD is not equal to VDDQ.

M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G

M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G

1GB, 512MB, 256MB

PC3200 and PC2700 Unbuffered DDR DI MM

REV 1.0 8

Sep 15, 2005

NANYA reserves the right to change products and specifications without notice.

Serial Presence Detect

SPD Description

Byte Description Byte Description

0 Number of Serial PD Bytes Written during Production 27 Minimum Row Precharge Time (tRP)

1 Total Number of Bytes in Serial PD device 28 Minimum Row Active to Row Active delay (tRRD)

2 Fundamental Memory Type 29 Minimum RAS to CAS delay (tRCD)

3 Number of Row Addresses on Assembly 30 Minimum RAS Pulse Width (tRAS)

4 Number of Column Addresses on Assembly 31 Module Bank Density

5 Number of DIMM Rank 32 Address and Command Setup Time Before Clock

6 Data Width of Assembly 33 Address and Command Hold Time After Clock

7 Data Width of Assembly (cont’) 34 Data Input Setup Time Before Clock

8 Voltage Interface Level of this Assembly 35 Data Input Hold Time After Clock

9 DDR SDRAM Device Cycle Time

CL=2.5 36-40 Reserved

10 DDR SDRAM Device Access Time from Clock

CL=2.5 41 Minimum Active/Auto-refresh Time (tRC)

11 DIMM Configuration Type 42 Auto-refresh to Active/Auto-refresh Command Period

(tRFC)

12 Refresh Rate/Type 43 Max Cycle Time (tCK max)

13 Primary DDR SDRAM Width 44 Maximum DQS-DQ Skew Time (tDQSQ)

14 Error Checking DDR SDRAM Device Width 45 Maximum Read Data Hold Skew Factor (tQHS)

15 DDR SDRAM Device Attr: Min CLK Delay, Random Col

Access 46 Reserved

16 DDR SDRAM Device Attributes: Burst Length

Supported 47 UDIMM Height

17 DDR SDRAM Device Attributes: Number of Device

Banks 48-61 Reserved

18 DDR SDRAM Device Attributes:

CAS Latencies Supported 62 SPD Revision

19 DDR SDRAM Device Attributes: CS Latency 63 Checksum Data

20 DDR SDRAM Device Attributes: WE Latency 64-71 Manufacturer’s JEDEC ID Code

21 DDR SDRAM Device Attributes: 72 Module Manufacturing Location

22 DDR SDRAM Device Attributes: General 73-90 Module Part number

23 Minimum Clock Cycle

CL=2.5 91-92 Module Revision Code

24 Maximum Data Access Time from Clock at

CL=2 93-94

Module Manufacturing Data

yy= Binary coded decimal year code, 0-99(Decimal),

00-63(Hex)

ww= Binary coded decimal year code, 01-52(Decimal),

01-34(Hex)

25 Minimum Clock Cycle Time at CL=1 95-98 Module Serial Number

26 Maximum Data Access Time from Clock at CL=1 99-127 Reserved

M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G

M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G

1GB, 512MB, 256MB

PC3200 and PC2700 Unbuffered DDR DI MM

REV 1.0 9

Sep 15, 2005

NANYA reserves the right to change products and specifications without notice.

SPD Values for M1Y1G64DS8HB1G / M1U1G64DS8HB1G

PC3200 (5T) PC2700 (6K)

Byte Byte Value Value He

0 128 80 128 80

1 256 08 256 08

2 DDR SDRAM 07 DDR SDRAM 07

3 13 0D 13 0D

4 11 0B 11 0B

5 2 02 2 02

6 x64 40 x64 40

7 x64 00 x64 00

8 SSTL 2.5V 04 SSTL 2.5V 04

9 5.0ns 50 6.0ns 60

10 0.65ns 65 0.70ns 70

11 Parit

00 Parit

12 SR/1x

(

7.8us

)

82 SR/1x

(

7.8us

)

13 x8 08 x8 08

14 N/A 00 N/A 00

15 1 Clock 01 1 Clock 01

16 2

8 0E 2

8 0E

17 4 04 4 04

18 2.5/3 18 2/2.5 0C

19 0 01 0 01

20 1 02 1 02

21 Diff. clock 20 Diff. clock 20

22 ±0.2V Tolerance C0 ±0.2V Tolerance C0

23 6.0ns 60 7.5ns 75

24 0.70ns 70 0.75ns 75

25 N/A 00 N/A 00

26 N/A 00 N/A 00

27 15ns 3C 18ns 48

28 10ns 28 12ns 30

29 15ns 3C 18ns 48

30 40ns 28 42ns 2A

31 1GB 80 1GB 80

32 0.60ns 60 0.75ns 75

33 0.60ns 60 0.75ns 75

34 0.40ns 40 0.45ns 45

35 0.40ns 40 0.45ns 45

36-40 Reserved 00 Reserved 00

41 55ns 37 60ns 3C

42 70ns 46 72ns 48

43 12 30 12 30

44 0.40 28 0.45 2D

45 0.50 50 0.55 55

46 N/A 00 N/A 00

47 1.0 01 1.0 01

48-61 Reserved 00 Reserved 00

62 SPD Version 10 SPD Version 10

63 Checksum C8 Checksum 58

64-71 Nanya 7F7F7F0B

00000000

Nanya 7F7F7F0B

00000000

72 Assembl

-- Assembl

73-90 Module PN -- Module PN --

91-92 Revision -- Revision --

93-94 Year/Week Code -- Year/Week Code --

95-98 Serial Numbe

-- Serial Numbe

99-127 Reserved -- Reserved --

M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G

M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G

1GB, 512MB, 256MB

PC3200 and PC2700 Unbuffered DDR DI MM

REV 1.0 10

Sep 15, 2005

NANYA reserves the right to change products and specifications without notice.

SPD Values for M1Y51264DS88B1G / M1U51264DS88B1G

PC2700 (5T) PC3200 (6K)

Byte Value He

Byte Value

0 128 80 128 80

1 256 08 256 08

2 DDR SDRAM 07 DDR SDRAM 07

3 13 0D 13 0D

4 11 0B 11 0B

5 1 01 1 01

6 X64 40 X64 40

7 X64 00 X64 00

8 SSTL 2.5V 04 SSTL 2.5V 04

9 5ns 50 6ns 60

10 .65ns 65 .70ns 70

11 Non-Parity 00 Non-Parity 00

12 SR/1x(7.8us) 82 SR/1x(7.8us) 82

13 X8 08 X8 08

14 N/A 00 N/A 00

15 1 Clock 01 1 Clock 01

16 2,4,8 0E 2,4,8 0E

17 4 04 4 04

18 2.5/3 18 2/2.5 0C

19 0 01 0 01

20 1 02 1 02

21 Differential Clock 20 Differential Clock 20

22 +/-0.2V Tolerance C0 +/-0.2V Tolerance C0

23 6.0ns 60 7.5ns 75

24 0.70ns 70 0.75ns 75

25 N/A 00 N/A 00

26 N/A 00 N/A 00

27 15ns 3C 18ns 48

28 10ns 28 12ns 30

29 15ns 3C 18ns 48

30 40ns 28 42ns 2A

31 512MB 80 512MB 80

32 0.60ns 60 0.75ns 75

33 0.60ns 60 0.75ns 75

34 0.40ns 40 0.45ns 45

35 0.40ns 40 0.45ns 45

36-40 N/A 00 N/A 00

41 55ns 37 60ns 3C

42 70ns 46 72ns 48

43 12 30 12 30

44 0.40 28 0.45 2D

45 0.50 50 0.55 55

46 N/A 00 N/A 00

47 Height 31.75mm 01 Height 31.75mm 01

48-61 N/A 00 N/A 00

62 SPD 1.0 10 SPD 1.0 10

63 Checksum C7 Checksum 57

64-71

Nanya

7F7F7F0B

00000000 Nanya

7F7F7F0B

00000000

72 Assembl

-- Assembl

73-90 Module PN -- Module PN --

91-92 Revision -- Revision --

93-94 Year/Week Code -- Year/Week Code --

95-98 Serial Numbe

-- Serial Numbe

99-127 Reserved -- Reserved --

M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G

M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G

1GB, 512MB, 256MB

PC3200 and PC2700 Unbuffered DDR DI MM

REV 1.0 11

Sep 15, 2005

NANYA reserves the right to change products and specifications without notice.

SPD Values for M1Y25664DSH4B1G / M1U25664DSH4B1G

PC2700 (5T) PC3200 (6K)

Byte Value He

Byte Value

0 128 80 128 80

1 256 08 256 08

2 DDR SDRAM 07 DDR SDRAM 07

3 13 0D 13 0D

4 10 0A 10 0A

5 1 01 1 01

6 X64 40 X64 40

7 X64 00 X64 00

8 SSTL 2.5V 04 SSTL 2.5V 04

9 5ns 50 6ns 60

10 .65ns 65 .7ns 70

11 Non-Parity 00 Non-Parity 00

12 SR/1x(7.8us) 82 SR/1x(7.8us) 82

13 X16 10 X16 10

14 N/A 00 N/A 00

15 1 Clock 01 1 Clock 01

16 2,4,8 0E 2,4,8 0E

17 4 04 4 04

18 2.5/3 18 2/2.5 0C

19 0 01 0 01

20 1 02 1 02

21 Differential Clock 20 Differential Clock 20

22 +/-0.2V Tolerance C0 +/-0.2V Tolerance C0

23 6.0ns 60 7.5ns 75

24 0.75ns 70 0.75ns 75

25 N/A 00 N/A 00

26 N/A 00 N/A 00

27 15ns 3C 18ns 48

28 10ns 28 12ns 30

29 15ns 3C 18ns 48

30 40ns 28 42ns 2A

31 256MB 40 256MB 40

32 0.6ns 60 0.75ns 75

33 0.6ns 60 0.75ns 75

34 0.4ns 40 0.45ns 45

35 0.4ns 40 0.45ns 45

36-40 N/A 00 N/A 00

41 55ns 37 60ns 3C

42 70ns 46 72ns 48

43 12 30 12 30

44 0.4 28 0.45 2D

45 0.5 50 0.55 55

46 N/A 00 N/A 00

47 Height 31.75mm 01 Height 31.75mm 01

48-61 N/A 00 N/A 00

62 SPD 1.0 10 SPD 1.0 10

63 Checksum 8E Checksum 1E

64-71

Nanya

7F7F7F0B

00000000 Nanya

7F7F7F0B

00000000

72 Assembl

-- Assembl

73-90 Module PN -- Module PN --

91-92 Revision -- Revision --

93-94 Year/Week Code -- Year/Week Code --

95-98 Serial Numbe

-- Serial Numbe

99-127 Reserved -- Reserved --

M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G

M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G

1GB, 512MB, 256MB

PC3200 and PC2700 Unbuffered DDR DI MM

REV 1.0 12

Sep 15, 2005

NANYA reserves the right to change products and specifications without notice.

Absolute Maximum Ratings

Symbol Parameter Rating Units

VIN, VOUT Voltage on I/O pins relative to VSS -0.5 to VDDQ +0.5 V

VIN Voltage on Input relative to VSS -0.5 to +3.6 V

VDD Voltage on VDD supply relative to VSS -0.5 to +3.6 V

VDDQ Voltage on VDDQ supply relative to VSS -0.5 to +3.6 V

TA Operating Temperature (Ambient) 0 to +70 °C

TSTG Storage Temperature (Plastic) -55 to +150 °C

PD Power Dissipation (per device component) 1 W

IOUT Short Circuit Output Current 50 mA

Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is stress

rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC Electrical Characteristics and Operating Conditions

TA= 0°C ~ 70°C; VDDQ= VDD= 2.5V±0.2V(6K); TA= 0°C ~ 70°C; VDDQ= VDD= 2.6V±0.1V(5T)

Symbol Parameter Min Max Units Notes

6K 2.3

VDD Supply Voltage

5T 2.5

2.7 V 1

6K 2.3

VDDQ I/O Supply Voltage

5T 2.5

2.7 V 1

VSS, VSSQ Supply Voltage, I/O Supply Voltage 0 0 V

VREF I/O Reference Voltage 0.49 x VDDQ 0.51 x VDDQ V 1, 2

VTT I/O Termination Voltage (System) VREF – 0.04 VREF + 0.04 V 1, 3

VIH (DC) Input High (Logic1) Voltage VREF + 0.15 VDDQ + 0.3 V 1

VIL (DC) Input Low (Logic0) Voltage -0.3 VREF - 0.15 V 1

VIN (DC) Input Voltage Level, CK and CK Inputs -0.3 VDDQ + 0.3 V 1

VID (DC) Input Differential Voltage, CK and CK Inputs 0.30 VDDQ + 0.6 V 1, 4

Input Leakage Current

Any input 0V ≤ VIN ≤ VDD; (All other pins not under test = 0V)

-10 10 µA1

IOZ

Output Leakage Current

(DQs are disabled; 0V ≤ Vout ≤ VDDQ

-10 10 µA1

IOH

Output High Current

(VOUT = VDDQ -0.373V, min VREF, min VTT) -16.8 - mA 1

IOL

Output Low Current

(VOUT = 0.373, max VREF, max VTT) 16.8 - mA 1

1. Inputs are not recognized as valid until VREF stabilizes.

2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak

noise on VREF may not exceed 2% of the DC value.

3. VTT is not applied directly to the DIMM. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF,

and must track variations in the DC level of VREF.

4. VID is the magnitude of the difference between the input level on CK and the input level on CK.

M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G

M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G

1GB, 512MB, 256MB

PC3200 and PC2700 Unbuffered DDR DI MM

REV 1.0 13

Sep 15, 2005

NANYA reserves the right to change products and specifications without notice.

AC Characteristics

Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating

Conditions, Operating, Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.)

1. All voltages referenced to VSS.

2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the

related specifications and device operation are guaranteed for the full voltage range specified.

3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below.

4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the

crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The

minimum slew rate for the input signals is 1V/ns in the range between VIL (AC) and VIH (AC) unless otherwise specified.

5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the signal

crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW (HIGH) level.

AC Output Load Circuits

Timing Reference Point

50 ohms

30 pF

Output

OUT

AC Operating Conditions

Symbol Parameter/Condition Min Max Unit Notes

VIH (AC) Input High (Logic 1) Voltage. VREF + 0.31 V 1, 2

VIL (AC) Input Low (Logic 0) Voltage. VREF - 0.31 V 1, 2

VID (AC) Input Differential Voltage, CK and CK Inputs 0.62 VDDQ + 0.6 V 1, 2, 3

VIX (AC) Input Differential Pair Cross Point Voltage, CK and CK Inputs (0.5* VDDQ) - 0.2 (0.5* VDDQ) + 0.2 V 1, 2, 4

1. Input slew rate = 1V/ ns.

2. Inputs are not recognized as valid until VREF stabilizes.

3. VID is the magnitude of the difference between the input level on CK and the input level on CK.

4. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.

M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G

M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G

1GB, 512MB, 256MB

PC3200 and PC2700 Unbuffered DDR DI MM

REV 1.0 14

Sep 15, 2005

NANYA reserves the right to change products and specifications without notice.

Operating, Standby, and Refresh Currents

TA = 0 °C ~ 70 °C; VDDQ= VDD= 2.5V ± 0.2V (6K); VDDQ= VDD= 2.6V ± 0.1V (5T)

Symbol Parameter/Condition Notes

IDD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per

clock cycle; address and control inputs changing once per clock cycle 1,2

IDD1 Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and

control inputs changing once per clock cycle 1,2

IDD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE ≤ VIL (MAX); tCK = tCK (MIN) 1,2

IDD2N Idle Standby Current: CS ≥ VIH (MIN); all banks idle; CKE ≥ VIH (MIN); tCK = tCK (MIN); address and control inputs changing once

per clock cycle 1,2

IDD3P Active Power-Down Standby Current: one bank active; power-down mode; CKE ≤ VIL (MAX); tCK = tCK (MIN) 1,2

IDD3N Active Standby Current: one bank; active/precharge; CS ≥ VIH (MIN); CKE ≥ VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and

DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 1,2

IDD4R Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle;

DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA 1,2

IDD4W Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle;

DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) 1,2

IDD5 Auto-Refresh Current: tRC = tRFC (MIN) 1,2,3

IDD6 Self-Refresh Current: CKE ≤ 0.2V 1,2

IDD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of

data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 1,2

1. IDD specifications are tested after the device is properly initialized.

2. Input slew rate = 1V/ ns.

3. Current at 7.8 µs is time averaged value of IDD5 at tRFC (MIN) and IDD2P over 7.8 µs.

All IDD current values are calculated from device level.

M1Y1G64DS8HB1G

M1U1G64DS8HB1G M1Y51264DS88B1G

M1U51264DS88B1G M1Y25664DSH4B1G

M1U25664DSH4B1G

Symbol

(mA)

PC3200

(5T)

PC2700

(6K)

PC3200

(5T)

PC2700

(6K)

PC3200

(5T)

PC2700

(6K)

IDD0 1651 1575 801 765 400 382

IDD1 1702 1634 826 794 413 397

IDD2P 60 57 28 27 14 13

IDD2N 476 420 224 198 112 99

IDD3P 211 195 99 92 50 46

IDD3N 852 767 401 361 200 180

IDD4R 2010 1705 980 830 490 415

IDD4W 2195 1910 1072 932 536 466

IDD5 3225 3125 1587 1540 794 770

IDD6 37 38 17 18 9 9

IDD7 5863 4961 2907 2458 1453 1229

M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G

M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G

1GB, 512MB, 256MB

PC3200 and PC2700 Unbuffered DDR DI MM

REV 1.0 15

Sep 15, 2005

NANYA reserves the right to change products and specifications without notice.

Package Dimensions

M1Y1G64DS8HB1G / M1U1G64DS8HB1G, 16 TSOP devices

Note: Device packaging not drawn to scale. Placed only for references

133.35

128.93

1.250

0.157

0.700

FRONT

Side

0.394

1.27+/- 0.10

Detail A

1.27 Pitch

Detail B

1.00 Width

4.00

Detail A Detail B

0.91

θ 2.50

3.80

1.80

6.35

5.250

5.076

2.30

(2x)4.00

17.80

31.75

10.0

0.098

0.157 MAX

0.050 +/- 0.004

0.05

0.039

0.071

0.250

0.150

4.00

0.157

BACK

Note: All dimensions are typical with tolerances of +/- 0.15 (0.006) unless otherwise stated.

Units: Millimeters (Inches)

M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G

M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G

1GB, 512MB, 256MB

PC3200 and PC2700 Unbuffered DDR DI MM

REV 1.0 16

Sep 15, 2005

NANYA reserves the right to change products and specifications without notice.

Package Dimensions

M1Y51264DS88B1G / M1U51264DS88B1G, 8 TSOP devices

Note: Device packaging not drawn to scale. Placed only for references

133.35

128.93

1.250

0.157

0.700

FRONT

Side

0.394

1.27+/- 0.10

Detail A

1.27 Pitch

Detail B

1.00 Width

3.18

Detail A Detail B

0.91

θ 2.50

3.80

1.80

6.35

5.250

5.076

2.30

(2x)4.00

17.80

31.75

10.0

0.098

0.125 MAX

0.050 +/- 0.004

0.05

0.039

0.071

0.250

0.150

4.00

0.157

BACK

Note: All dimensions are typical with tolerances of +/- 0.15 (0.006) unless otherwise stated.

Units: Millimeters (Inches)

M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G

M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G

1GB, 512MB, 256MB

PC3200 and PC2700 Unbuffered DDR DI MM

REV 1.0 17

Sep 15, 2005

NANYA reserves the right to change products and specifications without notice.

Package Dimensions

M1Y25664DSH4B1G / M1U25664DSH4B1G, 4 TSOP devices

Note: Device packaging not drawn to scale. Placed only for references

133.35

128.93

1.250

0.157

0.700

FRONT

Side

0.394

1.27+/- 0.10

Detail A

1.27 Pitch

Detail B

1.00 Width

3.18

Detail A Detail B

0.91

θ 2.50

3.80

1.80

6.35

5.250

5.076

2.30

(2x)4.00

17.80

31.75

10.00

0.098

0.125 MAX

0.050 +/- 0.004

0.05

0.039

0.071

0.250

0.150

4.00

0.157

BACK

Note: All dimensions are typical with tolerances of +/- 0.15 (0.006) unless otherwise stated.

Units: Millimeters (Inches)

M1Y1G64DS8HB1G / M1Y51264DS88B1G / M1Y25664DSH4B1G

M1U1G64DS8HB1G / M1U51264DS88B1G / M1U25664DSH4B1G

1GB, 512MB, 256MB

PC3200 and PC2700 Unbuffered DDR DI MM

REV 1.0 18

Sep 15, 2005

NANYA reserves the right to change products and specifications without notice.

Revision Log

Rev Date Modification

1.0 Sep 15 ,2005

Initial release:

1GB: M1Y1G64DS8HB1G – 5T/6K, M1U1G64DS8HB1G – 5T/6K

512MB: M1Y51264DS88B1G – 5T/6K; M1U51264DS88B1G – 5T/6K

256MB: M1Y25664DSH4B1G – 5T/6K; M1U25664DSH4B1G – 5T/6K