A1384EUA-T - Allegro Microsystems

A1381-DS, Rev. 8

Features and Benefits

▪ Customer programmable offset, sensitivity, sensitivity

temperature coefficient, and polarity

▪ Programmability at end-of-line

▪ Ratiometric sensitivity, quiescent voltage output, and

clamps for interfacing with application DAC

▪ Temperature-stable quiescent voltage output

and sensitivity

▪ Precise recoverability after temperature cycling

▪ Output voltage clamps provide short circuit

diagnostic capabilities

▪ Wide ambient temperature range: –40°C to 150°C

▪ Immune to mechanical stress

▪ Miniature package options

Functional Block Diagram

Not to scale

A1381, A1382, A1383, and A1384

Continued on the next page…

Packages: 3 pin SOT23W (suffix LH), and

3 pin SIP (suffix UA)

Programmable Linear Hall Ef fect Sensor ICs with Analog Output

Available in a Miniature Thin Profile Surface Mount Package

Amp

To all subcircuits

Out

VCC

V+

VOUT

(Programming)

GND

Filter

Dynamic Offset

Cancellation

Gain Gain Temperature

Coefficient

Offset

Trim Control

Hall Drive Circuit

CBYPASS

Description

New applications for linear output Hall effect sensing, such

as displacement, angular position, and current measurement,

require high accuracy in conjunction with small package size.

The Allegro® A138x family of programmable linear Hall effect

sensor ICs was designed specifically to achieve both goals.

These temperature-stable devices are available in a miniature

surface mount package (SOT23-W) and an ultramini through-

hole single-in-line package. The accuracy of these devices is

enhanced via programmability on the output pin for end-of-line

optimization without the added complexity and cost of a fully

programmable device.

These ratiometric Hall effect devices provide a voltage output

that is proportional to the applied magnetic field. Both the

quiescent voltage output and magnetic sensitivity are user-

adjustable. The quiescent voltage output can be set around

50% of the supply voltage, and the sensitivity adjusted between

2 mV/G and 9 mV/G over the device family. Programming

selections also exist for output polarity and temperature

compensation. The features of this linear family make it ideal

for high accuracy requirements of automotive and industrial

applications, and performance is guaranteed over an extended

temperature range, –40°C to 150°C.

Programmable Linear Hall Ef fect Sensor ICs with Analog Output

Available in a Miniature Thin Profile Surface Mount Package

A1381, A1382,

A1383, and A1384

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Each BiCMOS monolithic circuit integrates a Hall element,

temperature-compensating circuitry to reduce the intrinsic sensitivity

drift of the Hall element, a small-signal high-gain amplifier, a clamped

low-impedance output stage, and a proprietary dynamic

offset cancellation technique.

The A138x devices are provided in a 3 pin ultramini single-in-line

package (UA suffix), and a 3 pin surface mount SOT-23W package

(LH suffix).

Absolute Maximum Ratings

Characteristic Symbol Notes Rating Units

Forward Supply Voltage VCC 8V

Reverse Supply Voltage VRCC –0.1 V

Forward Output Voltage VOUT 28 V

Reverse Output Voltage VROUT –0.1 V

Output Source Current IOUT(SOURCE) VOUT to GND 2 mA

Output Sink Current IOUT(SINK) VCC to VOUT 10 mA

Operating Ambient Temperature TA

Range E –40 to 85 ºC

Range L –40 to 150 ºC

Storage Temperature Tstg –65 to 165 ºC

Maximum Junction Temperature TJ(max) 165 ºC

Description (continued)

Selection Guide

Part Number Packing1Package TA

(°C)

Internal Bandwidth

(kHz)

Sensitivity Range

(mV/G)

A1381ELHLT-T Tape and reel, 3000 pieces/reel Surface mount –40 to 85

12 6.00 to 9.00

A1381EUA-T Bulk bag, 500 pieces/bag Through hole

A1381LLHLT-T Tape and reel, 3000 pieces/reel Surface mount –40 to 150

A1381LUA-T Bulk bag, 500 pieces/bag Through hole

A1382ELHLT-T2Tape and reel, 3000 pieces/reel Surface mount –40 to 85

17 4.00 to 6.25

A1382EUA-T2Bulk bag, 500 pieces/bag Through hole

A1382LLHLT-T2Tape and reel, 3000 pieces/reel Surface mount –40 to 150

A1382LUA-T2Bulk bag, 500 pieces/bag Through hole

A1383ELHLT-T Tape and reel, 3000 pieces/reel Surface mount –40 to 85

21 2.75 to 4.25

A1383EUA-T Bulk bag, 500 pieces/bag Through hole

A1383LLHLT-T Tape and reel, 3000 pieces/reel Surface mount –40 to 150

A1383LUA-T Bulk bag, 500 pieces/bag Through hole

A1384ELHLT-T Tape and reel, 3000 pieces/reel Surface mount –40 to 85

27 2.00 to 3.00

A1384EUA-T Bulk bag, 500 pieces/bag Through hole

A1384LLHLT-T Tape and reel, 3000 pieces/reel Surface mount –40 to 150

A1384LUA-T Bulk bag, 500 pieces/bag Through hole

1Contact Allegro for additional packing options.

2This variant is in production, however, it has been deemed Pre-End of Life. The product is approaching end of life. Within a minimum of 6 months,

the device will enter its final, Last Time Buy, order phase. Status change: January 30, 2012.

Number Name Description

LH UA

1 1 VCC Input power supply; use bypass capacitor to connect to ground

3 2 GND Ground

2 3 VOUT Output signal; also used for programming

Pin-out Diagrams

LH Package UA Package

123

Programmable Linear Hall Ef fect Sensor ICs with Analog Output

Available in a Miniature Thin Profile Surface Mount Package

A1381, A1382,

A1383, and A1384

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Continued on the next page...

OPERATING CHARACTERISTICS, valid over full operating temperature range, TA; CBYPASS= 0.1 μF, VCC = 5 V, unless otherwise specified

Characteristic Symbol Test Conditions Min. Typ. Max. Units

ELECTRICAL CHARACTERISTICS

Supply Voltage VCC 4.5 5.0 5.5 V

Supply Current ICC No load on VOUT – 6.9 8 mA

Power-On Time1tPO

A1381 TA = 25 °C, CBYPASS = open,

CL (of test probe) = 10 pF, Sens = 7.5 mV/G –32 –μs

A1382 TA = 25 °C, CBYPASS = open,

CL (of test probe) = 10 pF, Sens = 5.0 mV/G –27 –μs

A1383 TA = 25 °C, CBYPASS = open,

CL (of test probe) = 10 pF, Sens = 3.125 mV/G –23 –μs

A1384 TA = 25 °C, CBYPASS = open,

CL (of test probe) = 10 pF, Sens = 2.5 mV/G –19 –μs

Delay to Clamp1tCLP TA = 25°C, CL = 10 nF – 30 – μs

Supply Zener Clamp Voltage VZTA = 25°C, ICC = 11 mA 6 8.3 – V

Internal Bandwidth BWi

A1381

Small signal –3 dB

– 12 – kHz

A1382 – 17 – kHz

A1383 – 21 – kHz

A1384 – 27 – kHz

Chopping Frequency2fCTA = 25°C – 170 – kHz

OUTPUT CHARACTERISTICS

Noise (peak to peak) VN(p-p)

A1381 TA=25°C; CL = 10 nF,

Sens = 7.5 mV/G; no external filter –34 –mV

A1382 TA=25°C; CL = 10 nF,

Sens = 5.0 mV/G; no external filter –27 –mV

A1383 TA=25°C; CL = 10 nF,

Sens = 3.125 mV/G; no external filter –20 –mV

A1384 TA=25°C; CL = 10 nF,

Sens = 2.5 mV/G; no external filter –18 –mV

A138x TA=25°C; Sens = 2.5 mV/G; external 2 kHz low

pass filter with R = 1.69 kΩ, C = 47 nF – 4.7 – mV

DC Output Resistance ROUT –< 1 –Ω

Output Load Resistance RL

VOUT to VCC 4.7 – – kΩ

VOUT to GND 4.7 – – kΩ

Output Load Capacitance CLVOUT to GND – – 10 nF

Phase Shift3∆Φ No load on VOUT, magnetic input signal frequency =

1 kHz, with 1 V(p-p) output signal – 3 – deg.

Output Voltage Clamp4

VCLP(HIGH)

TA = 25°C, B = 600 G, Sens = 5.0 mV/G,

RL = 10 kΩ (VOUT to GND) 4.35 4.5 4.65 V

VCLP(LOW)

TA = 25°C, B = –600 G, Sens = 5.0 mV/G,

RL = 10 kΩ (VCC to VOUT) 0.40 0.55 0.70 V

Output Slew Rate SR CL = 10 nF – 175 – V/ms

Programmable Linear Hall Ef fect Sensor ICs with Analog Output

Available in a Miniature Thin Profile Surface Mount Package

A1381, A1382,

A1383, and A1384

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

PRE-PROGRAMMING TARGET5

Pre-Programming Quiescent

Voltage Output VOUT(Q)init B = 0 G, TA = 25°C – 2.1 – V

Pre-Programming Sensitivity Sensinit

A1381

TA = 25°C

– 4.2 – mV/G

A1382 – 2.9 – mV/G

A1383 – 2.1 – mV/G

A1384 – 1.4 – mV/G

Pre-Programming Sensitivity

Temperature Coefficient6TCSensinit TA = 150°C – –0.05 – %/°C

QUIESCENT VOLTAGE OUTPUT PROGRAMMING

Guaranteed Quiescent Voltage

Output Range4,7 VOUT(Q) B = 0 G, TA = 25°C 2.3 – 2.6 V

Quiescent Voltage Output

Programming Bits – 6 – bit

Average Quiescent Voltage

Output Step Size8,9 StepVOUT(Q) TA = 25°C 8 11.5 15 mV

Quiescent Voltage Output

Programming Resolution10 ErrPGVOUT(Q) TA = 25°C – StepVOUT(Q) ×

±0.5 –mV

SENSITIVITY PROGRAMMING

Guaranteed Sensitivity Range4,11 Sens

A1381

TA = 25°C

6.00 – 9.00 mV/G

A1382 4.00 – 6.25 mV/G

A1383 2.75 – 4.25 mV/G

A1384 2.00 – 3.00 mV/G

Sensitivity Programming Bits – 6 – bit

Average Sensitivity Step Size8,9 StepSENS

A1381

TA = 25°C

90 110 130 μV/G

A1382 55 75 95 μV/G

A1383 35 55 75 μV/G

A1384 28 35 42 μV/G

Sensitivity Programming

Resolution10 ErrPGSENS TA = 25°C – StepSENS ×

±0.5 – mV/G

SENSITIVITY TC PROGRAMMING

Guaranteed Sensitivity Tem-

perature Coefficient Range6TCSens TA = 150°C 0.00 – 0.095 %/°C

Sensitivity Temperature Coef-

ficient Programming Bits – 3 – bit

Average Sensitivity Tempera-

ture Coefficient Step Size6StepTCSENS TA = 150°C – 0.03 – %/°C

Sensitivity Temperature Coeffi-

cient Programming Resolution6ErrPGTCSENS TA = 150°C – StepTCSENS x

±0.5 – %/°C

POLARITY PROGRAMMING

Polarity Programming Bit12 POL – 1 – bit

LOCK BIT PROGRAMMING

Overall Programming Lock Bit LOCK – 1 – bit

OPERATING CHARACTERISTICS (continued), valid over full operating temperature range, TA; CBYPASS= 0.1 μF, V CC = 5 V, unless otherwise specified

Characteristic Symbol Test Conditions Min. Typ. Max. Units

Continued on the next page...

Programmable Linear Hall Ef fect Sensor ICs with Analog Output

Available in a Miniature Thin Profile Surface Mount Package

A1381, A1382,

A1383, and A1384

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

ERROR COMPONENTS

Linearity Sensitivity Error LinERR – ±1.5 – %

Symmetry Sensitivity Error SymERR – ±1.5 – %

Ratiometry Quiescent Voltage

Output Error13 RatERRVOUT(Q) – ±1.5 – %

Ratiometry Sensitivity Error13 RatERRSens – ±1.5 – %

Ratiometry Clamp Error14

RatERRCLP

TA = 25°C – ±1.5 – %

DRIFT CHARACTERISTICS

Quiescent Voltage Output Drift

Through Temperature Range ∆VOUT(Q)

A1381

TA = 150°C

– – ±60 mV

A1382 – – ±50 mV

A1383 – – ±40 mV

A1384 – – ±40 mV

Sensitivity Drift Through

Temperature Range15 ∆SensTC –±3 –%

Sensitivity Drift Due to Package

Hysteresis1∆SensPKG TA = 25°C; after temperature cycling – ±2 – %

1See Characteristic Definitions section.

2fC varies up to approximately ± 20% over the full operating ambient temperature range, TA, and process.

3Unit of measure (phase degrees) in reference to the magnetic input signal.

4Sens, VOUT(Q), VCLP(LOW) , and VCLP(HIGH) scale with VCC due to ratiometry.

5Raw device characteristic values before any programming.

6Programmed at 150°C and calculated relative to 25°C.

7VOUT(Q)(max) is the value available with all programming fuses blown (maximum programming code set). The VOUT(Q) range is the total range from

VOUT(Q)init up to and including VOUT(Q)(max). See Characteristic Definitions section.

8Step size is larger than required, in order to provide for manufacturing spread. See Characteristic Definitions section.

9Non-ideal behavior in the programming DAC can cause the step size at each significant bit rollover code to be greater than twice the maximum

specified value of StepVOUT(Q) , StepSENS , or StepTCSENS.

10Overall programming value accuracy. See Characteristic Definitions section.

11Sens(max) is the value available with all programming fuses blown (maximum programming code set). Sens range is the total range from Sensinit up

to and including Sens(max). See Characteristic Definitions section.

12Default polarity is for VOUT voltage to increase with a positive (south polarity) field applied to the branded face of the device.

13Percent change from actual value at VCC = 5 V, for a given temperature, over the guaranteed supply voltage operating range.

14Percent change from actual value at VCC = 5 V, TA = 25°C, over the guaranteed supply voltage operating range.

15Sensitivity drift from expected value at TA after programming TCSENS. See Characteristic Definitions section.

OPERATING CHARACTERISTICS (continued), valid over full operating temperature range,TA; CBYPASS= 0.1 μF, V CC = 5 V, unless otherwise specified

Characteristic Symbol Test Conditions Min. Typ. Max. Units

Programmable Linear Hall Ef fect Sensor ICs with Analog Output

Available in a Miniature Thin Profile Surface Mount Package

A1381, A1382,

A1383, and A1384

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information

Characteristic Symbol Test Conditions* Value Units

Package Thermal Resistance RθJA

Package LH, 1-layer PCB with copper limited to solder pads 228 ºC/W

Package LH, 2-layer PCB with 0.463 in.2 of copper area each side

connected by thermal vias 110 ºC/W

Package UA, 1-layer PCB with copper limited to solder pads 165 ºC/W

*Additional thermal information available on Allegro website.

020 40 60 80 100 120 140 160 180

Temperature (ºC)

Maximum Allowable V

(V)

Power Derating Curve

QJA

= 228 ºC/W)

1-layer PCB, Package LH

QJA

= 110 ºC/W)

2-layer PCB, Package LH

QJA

= 165 ºC/W)

1-layer PCB, Package UA

VCC(min)

VCC(max)

100

200

300

400

500

600

700

800

900

1000

1100

1200

1300

1400

1500

1600

1700

1800

1900

20 40 60 80 100 120 140 160 180

Temperature (°C)

Power Dissipation, P

(mW)

Power Dissipation versus Ambient Temperature

QJA

= 165 ºC/W)

1-layer PCB, Package UA

(RQJA = 228 ºC/W)

1-layer PCB, Package LH

(RQJA = 110 ºC/W)

2-layer PCB, Package LH

Programmable Linear Hall Ef fect Sensor ICs with Analog Output

Available in a Miniature Thin Profile Surface Mount Package

A1381, A1382,

A1383, and A1384

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Characteristic Definitions

Power-On Time When the supply is ramped to its operating

voltage, the device requires a finite time to power its inter-

nal components before responding to an input magnetic field.

Power-On Time, tPO

, is defined as: the time it takes for the out-

put voltage to settle within ±10% of its steady state value under

an applied magnetic field, after the power supply has reached its

minimum specified operating voltage, VCC(min), as shown in the

following chart.

Delay to Clamp A large magnetic input step may cause the

clamp to overshoot its steady state value. The Delay to Clamp,

tCLP

, is defined as: the time it takes for the output voltage to

settle within ±1% of its steady state value, after initially passing

through its steady state voltage, as shown in the following chart.

Quiescent Voltage Output In the quiescent state (no significant

magnetic field: B = 0 G), the output, VOUT(Q), has a constant

ratio to the supply voltage, VCC, throughout the entire operating

ranges of VCC and ambient temperature, TA.

Guaranteed Quiescent Voltage Output Range The quiescent

voltage output, VOUT(Q), can be programmed around its nominal

value of 2.5 V, within the guaranteed quiescent voltage range

limits: VOUT(Q)(min) and VOUT(Q)(max). The available guaran-

teed programming range for VOUT(Q) falls within the distributions

of the initial, VOUT(Q)init, and the maximum programming code

for setting VOUT(Q), as shown in the following diagram.

Average Quiescent Voltage Output Step Size The average qui-

escent voltage output step size for a single device is determined

using the following calculation:

VOUT(Q)maxcode –VOUT(Q)init

2n–1

StepVOUT(Q) =.

(1)

where:

n is the number of available programming bits in the trim

range,

2n–1 is the value of the maximum programming code in the

range, and

VOUT(Q)maxcode is the quiescent voltage output at code 2n–1.

Quiescent Voltage Output Programming Resolution The pro-

gramming resolution for any device is half of its programming

step size. Therefore, the typical programming resolution will be:

ErrPGVOUT(Q)(typ) =0.5 × StepVOUT(Q)(typ) . (2)

VCC

VCC(min.)

VOUT

90% VOUT

t1= time at which power supply reaches

minimum specified operating voltage

t2=

time at which output voltage settles

within ±10% of its steady state value

under an applied magnetic field

t1t2

tPO

(typ.)

Magnetic Input

VOUT

t1= time at which output voltage initially

reaches steady state clamp voltage

t2= time at which output voltage settles to

within 1% of steady state clamp voltage

Note: Times apply to both high clamp

(shown) and low clamp.

CLP(HIGH)

t1t2

tCLP

VOUT(Q)(max)VOUT(Q)(min)

VOUT(Q)init(typ)

Guaranteed Output

Programming

Range, VOUT(Q)

Distribution for

Max Code VOUT(Q)

Distribution for

VOUT(Q)init

Programmable Linear Hall Ef fect Sensor ICs with Analog Output

Available in a Miniature Thin Profile Surface Mount Package

A1381, A1382,

A1383, and A1384

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Quiescent Voltage Output Drift Through Temperature Range

Due to internal component tolerances and thermal considerations,

the quiescent voltage output, VOUT(Q), may drift from its nominal

value over the operating ambient temperature, TA. For purposes

of specification, the Quiescent Voltage Output Drift Through

Temperature Range, ∆VOUT(Q) (mV), is defined as:

∆VOUT(Q) VOUT(Q)(TA) –VOUT(Q)(25°C)

(3)

Sensitivity The presence of a south polarity magnetic field, per-

pendicular to the branded surface of the package face, increases

the output voltage from its quiescent value toward the supply

voltage rail (assuming that the polarity bit, POL, is in its initial

state of logic 0). The amount of the output voltage increase is

proportional to the magnitude of the magnetic field applied.

Conversely, the application of a north polarity field decreases the

output voltage from its quiescent value. This proportionality is

specified as the magnetic sensitivity, Sens (mV/G), of the device,

and it is defined as:

VOUT(BPOS) – VOUT(BNEG)

BPOS – BNEG

Sens =,

(4)

where BPOS and BNEG are two magnetic fields with opposite

polarities.

Guaranteed Sensitivity Range The magnetic sensitivity, Sens,

can be programmed around its nominal value, 2.5 to 7.5 mV/G

depending on device type, within the sensitivity range limits:

Sens(min) and Sens(max). Refer to the Guaranteed Quiescent

Voltage Output Range section for a conceptual explanation of

how value distributions and ranges are related.

Average Sensitivity Step Size Refer to the Average Quiescent

Voltage Output Step Size section for a conceptual explanation.

Sensitivity Programming Resolution Refer to the Quiescent

Voltage Output Programming Resolution section for a conceptual

explanation.

Sensitivity Temperature Coefficient Device sensitivity changes

as temperature changes, with respect to its programmed sensitiv-

ity temperature coefficient, TCSENS. TCSENS is programmed at

150°C, and calculated relative to the nominal sensitivity program

ming temperature of 25°C. TCSENS (%/°C) is defined as:

SensT2 – SensT1

SensT1 T2–T1

TCSens =×

100% ,

⎟

⎠

⎞

⎜

⎝

⎛

⎟

⎠

⎞

⎜

⎝

⎛

(5)

where T1 is the nominal Sens programming temperature of 25°C,

and T2 is the TCSENS programming temperature of 150°C. The

ideal value of Sens over the full ambient temperature range,

SensIDEAL(TA), is defined as:

SensT1 [100% + TCSENS (TA –T1)]

SensIDEAL(TA) = (6)

Guaranteed Sensitivity Temperature Coefficient Range The

magnetic sensitivity temperature coefficient can be programmed

within its limits: TCSens(max) and TCSens(min). Refer to the

Guaranteed Quiescent Voltage Output Range section for a con-

ceptual explanation of how value distributions and ranges are

related.

Average Sensitivity Temperature Coefficient Step Size Refer

to the Average Quiescent Voltage Output Step Size section for a

conceptual explanation.

Sensitivity Temperature Coefficient Programming Resolution

Refer to the Quiescent Voltage Output Programming Resolution

section for a conceptual explanation.

Sensitivity Drift Through Temperature Range Second order

sensitivity temperature coefficient effects cause the magnetic

sensitivity, Sens, to drift from its ideal value over the operating

ambient temperature range, TA. For purposes of specification, the

sensitivity drift through temperature range, ∆SensTC, is defined

as:

SensTA – SensIDEAL(TA)

SensIDEAL(TA)

∆SensTC =×

100% .

(7)

Sensitivity Drift Due to Package Hysteresis Package stress and

relaxation can cause the device sensitivity at TA = 25°C to change

during and after temperature cycling.

Programmable Linear Hall Ef fect Sensor ICs with Analog Output

Available in a Miniature Thin Profile Surface Mount Package

A1381, A1382,

A1383, and A1384

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

For purposes of specification, the sensitivity drift due to package

hysteresis, ∆SensPKG, is defined as:

Sens(25°C)2 – Sens(25°C)1

Sens(25°C)1

∆SensPKG =×

100% ,

(8)

where Sens(25°C)1 is the programmed value of sensitivity at TA

= 25°C, and Sens(25°C)2 is the value of sensitivity at TA = 25°C,

after temperature cycling TA up to 150°C, down to –40°C, and

back to up 25°C.

Linearity Sensitivity Error The 138x family is designed to

provide a linear output in response to a ramping applied magnetic

field. Consider two magnetic fields, B1 and B2. Ideally, the sen-

sitivity of a device is the same for both fields, for a given supply

voltage and temperature. Linearity error is present when there is a

difference between the sensitivities measured at B1 and B2.

Linearity Error is calculated separately for the positive

(LinERRPOS) and negative (LinERRNEG

) applied magnetic fields.

Linearity error (%) is measured and defined as:

SensBPOS2

SensBPOS1

SensBNEG2

SensBNEG1

1–

LinERRPOS =×

100% ,

⎟

⎠

⎞

⎜

⎝

⎛

1–

LinERRNEG =×

100% ,

⎟

⎠

⎞

⎜

⎝

⎛

(9)

where:

|VOUT(Bx) – VOUT(Q)|

SensBx=,

(10)

and BPOSx and BNEGx are positive and negative magnetic fields,

with respect to the quiescent voltage output such that

LinERR max(

|LinERRPOS | , |LinERRNEG | )

=. (11)

Symmetry Sensitivity Error The magnetic sensitivity of an

A138x device is constant for any two applied magnetic fields of

equal magnitude and opposite polarities.

Symmetry error, SymERR (%), is measured and defined as:

SensBPOS

SensBNEG

1–

SymERR =×

100% ,

⎟

⎠

⎞

⎜

⎝

⎛

(12)

where SensBx is as defined in equation 10, and BPOS and BNEG

are positive and negative magnetic fields such that |BPOS| = |BNEG|.

Ratiometry Error The A138x devices feature ratiometric output.

This means that the quiescent voltage output, VOUT(Q)

, magnetic

sensitivity, Sens, and clamp voltage, VCLP(HIGH) and VCLP(LOW),

are proportional to the supply voltage, VCC. In other words, when

the supply voltage increases or decreases by a certain percent-

age, each characteristic also increases or decreases by the same

percentage. Error is the difference between the measured change

in the supply voltage relative to 5 V, and the measured change in

each characteristic.

The ratiometric error in quiescent voltage output, RatERRVOUT(Q)

(%), for a given supply voltage, VCC, is defined as:

VOUT(Q)(VCC) / VOUT(Q)(5V)

VCC / 5 V

1–

RatERRVOUT(Q) =×

100% .

⎟

⎠

⎞

⎜

⎝

⎛

(13)

The ratiometric error in magnetic sensitivity, RatERRSens (%), for

a given supply voltage, VCC, is defined as:

Sens(VCC) / Sens(5V)

VCC / 5 V

1–

RatERRSens =×

100% .

⎟

⎠

⎞

⎜

⎝

⎛

(14)

The ratiometric error in the clamp voltages, RatERRCLP (%), for a

given supply voltage, VCC, is defined as:

VCLP(VCC) / VCLP(5V)

VCC / 5 V

1–

RatERRCLP =×

100% .

⎟

⎠

⎞

⎜

⎝

⎛

(15)

where VCLP is either VCLP(HIGH) or VCLP(LOW).

Programmable Linear Hall Ef fect Sensor ICs with Analog Output

Available in a Miniature Thin Profile Surface Mount Package

A1381, A1382,

A1383, and A1384

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Amp

Regulator

Clock/Logic

Hall Element

Sample and

Hold

Low-Pass

Filter

Concept of Chopper Stabilization Technique

When using Hall-effect technology, a limiting factor for

switchpoint accuracy is the small signal voltage developed across

the Hall element. This voltage is disproportionally small relative

to the offset that can be produced at the output of the Hall ele-

ment. This makes it difficult to process the signal while main-

taining an accurate, reliable output over the specified operating

temperature and voltage ranges. Chopper stabilization is a unique

approach used to minimize Hall offset on the chip. The patented

Allegro technique, namely Dynamic Quadrature Offset Cancella-

tion, removes key sources of the output drift induced by thermal

and mechanical stresses. This offset reduction technique is based

on a signal modulation-demodulation process. The undesired

offset signal is separated from the magnetic field-induced signal

in the frequency domain, through modulation. The subsequent

demodulation acts as a modulation process for the offset, causing

the magnetic field-induced signal to recover its original spectrum

at base band, while the DC offset becomes a high-frequency

signal. The magnetic-sourced signal then can pass through a

low-pass filter, while the modulated DC offset is suppressed. The

chopper stabilization technique uses a 170 kHz high frequency

clock. For the demodulation process, a sample and hold technique

is used, where the sampling is performed at twice the chop-

per frequency (340 kHz). This high-frequency operation allows

a greater sampling rate, which results in higher accuracy and

faster signal-processing capability. This approach desensitizes

the chip to the effects of thermal and mechanical stresses, and

produces devices that have extremely stable quiescent Hall output

voltages and Precise recoverability after temperature cycling.

This technique is made possible through the use of a BiCMOS

process, which allows the use of low-offset, low-noise amplifiers

in combination with high-density logic integration and sample-

and-hold circuits.

Chopper Stabilization Technique

Typical Application Drawing

V+

VCC VOUT

GND

BYPASS L

Programmable Linear Hall Ef fect Sensor ICs with Analog Output

Available in a Miniature Thin Profile Surface Mount Package

A1381, A1382,

A1383, and A1384

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Programming Pulse Requirements, Protocol at TA = 25°C

Characteristic Symbol Notes Min. Typ. Max. Units

Programming Voltage

VP(LOW)

Measured at the VOUT pin.

- - 5.5 V

VP(MID) 14 15 16 V

VP(HIGH) 26 27 28 V

Programming Current IP

Minimum supply current required to ensure proper fuse blowing. In addition, a min-

imum capacitance, CBLOW = 0.1 μF, must be connected between the VOUT and

GND pins during programming to provide the current necessary for fuse blowing.

300 - - mA

Pulse Width

tOFF(HIGH) Duration at VP(LOW) level following a VP(HIGH) level. 30 - - μs

tOFF(MID) Duration at VP(LOW) level following a VP(MID) level. 5 - - μs

tACTIVE(HIGH) Duration of VP(HIGH) level for VPH pulses during key/code selection. 30 - - μs

tACTIVE(MID) Duration of VP(MID) level for VPH pulses during key/code selection. 15 - - μs

tBLOW Duration at VP(HIGH) level for fuse blowing. 30 - - μs

Pulse Rise Time tPr Rise time required for transitions from VP(LOW) to either VP(MID) or VP(HIGH). 1 - 100 μs

Pulse Fall Time tPf Fall time required for transitions from VP(HIGH) to either VP(MID) to VP(LOW). 1 - 100 μs

Overview

Programming is accomplished by sending a series of input volt-

age pulses serially through the VOUT pin of the device. A unique

combination of different voltage level pulses controls the internal

programming logic of the device to select a desired program-

mable parameter and change its value. There are two program-

ming pulses, referred to as a high voltage pulse, VPH, consisting

of a VP(LOW) –VP(HIGH) –VP(LOW) sequence and a mid voltage

pulse, VPM, consisting of a VP(LOW) –VP(MID) –VP(LOW) sequence.

The 138x features Try mode, Blow mode, and Lock mode:

In Try mode, the value of a single programmable parameter may •

be set and measured. The parameter value is stored temporar-

ily, and resets after cycling the supply voltage. Note that other

parameters cannot be accessed simultaneously in this mode.

In Blow mode, the value of a single programmable parameter •

may be permanently set by blowing solid-state fuses internal to

the device. Additional parameters may be blown sequentially.

In Lock mode, a device-level fuse is blown, blocking the fur-•

ther programming of all parameters.

The programming sequence is designed to help prevent the

device from being programmed accidentally; for example, as a

result of noise on the supply line.

Although any programmable variable power supply can be

used to generate the pulse waveforms, Allegro highly recom-

mends using the Allegro Sensor IC Evaluation Kit, available on

the Allegro Web site On-line Store. The manual for that kit is

available for download free of charge, and provides additional

information on programming these devices.

Definition of Terms

choice of programmable modes and parameters.

Bit Field. The internal fuses unique to each register, represented

as a binary number. Incrementing the bit field of a particular

the internal programming logic.

Key. A series of VPM voltage pulses used to select a register, with

a value expressed as the decimal equivalent of the binary value.

The LSB of a register is denoted as key 1, or bit 0.

Code. The number used to identify the combination of fuses

activated in a bit field, expressed as the decimal equivalent of the

binary value. The LSB of a bit field is denoted as code 1, or bit 0.

Addressing. Incrementing the bit field code of a selected register

by serially applying a pulse train through the VOUT pin of the

device. Each parameter can be measured during the addressing

process, but the internal fuses must be blown before the program-

ming code (and parameter value) becomes permanent.

Fuse Blowing. Applying a VPH voltage pulse of sufficient dura-

tion at the VP(HIGH) level to permanently set an addressed bit by

blowing a fuse internal to the device. Once a bit (fuse) has been

blown, it cannot be reset.

Blow Pulse. A VPH voltage pulse of sufficient duration at the

VP(HIGH) level to blow the addressed fuse.

Cycling the Supply. Powering-down, and then powering-up the

supply voltage. Cycling the supply is used to clear the program-

ming settings in Try mode.

Programming Guidelines

Programmable Linear Hall Ef fect Sensor ICs with Analog Output

Available in a Miniature Thin Profile Surface Mount Package

A1381, A1382,

A1383, and A1384

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Figure 1. Parameter selection pulse train. This shows the sequence for

selecting the register corresponding to key 1, indicated by a single VPM

pulse.

Parameter Selection

Each programmable parameter can be accessed through a specific

sisting of a VPH pulse, a series of VPM pulses, and a VPH pulse

(with no VCC supply interruptions) must be applied serially to

the VOUT pin. The number of VPM pulses is called the key, and

uniquely identifies each register. The pulse train used for selec-

tion of the first register, key 1, is shown in figure 1.

The A138x has three registers that select among the five pro-

grammable parameters:

Quiescent voltage output, VOUT(Q)

Sensitivity, Sens

Sensitivity temperature coefficient, TCSens

Polarity, POL

Overall device locking, LOCK

Bit Field Addressing

After a programmable parameter has been selected, a VPH pulse

transitions the programming logic into the bit field address-

ing state. Applying a series of VPM pulses to the VOUT pin of

the device, as shown in figure 2, increments the bit field of the

selected parameter.

When addressing the bit field, the number of VPM pulses is rep-

resented by a decimal number called a code. Addressing activates

the corresponding fuse locations in the given bit field by incre-

menting the binary value of an internal DAC. The value of the bit

field (and code) increments by one with the falling edge of each

VPM pulse, up to the maximum possible code (see the Program-

ming Logic table). As the value of the bit field code increases, the

value of the programmable parameter changes.

Measurements can be taken after each pulse to determine if the

desired result for the programmable parameter has been reached.

Cycling the supply voltage resets all the locations in the bit field

that have unblown fuses to their initial states.

Fuse Blowing

After the required code is found for a given parameter, its value

can be set permanently by blowing individual fuses in the appro-

priate register bit field. Blowing is accomplished by applying

a VPH pulse, called a blow pulse, of sufficient duration at the

VP(HIGH) level to permanently set an addressed bit by blowing a

fuse internal to the device. Due to power requirements, the fuse

for each bit in the bit field must be blown individually. To accom-

plish this, the code representing the desired parameter value must

be translated to a binary number. For example, as shown

V+

P(HIGH)

P(MID)

P(LOW)

Code 1

Code 2

Code 2n – 2

Code 2n – 1

V+

LOW

ACTIVE

P(HIGH)

P(MID)

P(LOW)

Figure 2. Bit field addressing pulse train. Addressing the bit field by

incrementing the code causes the programmable parameter value to

change. The number of bits available for a given programming code, n,

varies among parameters; for example, the bit field for VOUT(Q) has 6 bits

available, which allows 63 separate codes to be used.

Programming Procedures

Programmable Linear Hall Ef fect Sensor ICs with Analog Output

Available in a Miniature Thin Profile Surface Mount Package

A1381, A1382,

A1383, and A1384

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

in figure 3, decimal code 5 is equivalent to the binary number

101. Therefore bit 2 (code 4) must be addressed and blown, the

device power supply cycled, and then bit 0 (code 1) addressed

and blown. An appropriate sequence for blowing code 5 is shown

in figure 4. The order of blowing bits, however, is not important.

Blowing bit 0 first, and then bit 2 is acceptable.

Note: After blowing, the programming is not reversible, even

after cycling the supply power. Although a register bit field fuse

cannot be reset after it is blown, additional bits within the same

example, if bit 1 (binary 10) has been blown, it is still possible to

blow bit 0. The end result would be binary 11 (decimal code 3).

Locking the Device

After the desired code for each parameter is programmed, the

device can be locked to prevent further programming of any

parameters.

Additional Guidelines

The additional guidelines in this section should be followed to

ensure the proper behavior of these devices:

A 0.1 μF blowing capacitor, C• BLOW, must be mounted between

the VOUT pin and the GND pin during programming, to ensure

enough current is available to blow fuses.

The C• BLOW blowing capacitor must be replaced in the final

application with a suitable CL. (The maximum load capacitance

is 10 nF for proper operation.)

The power supply used for programming must be capable of •

delivering at least 26 V and 300 mA.

Be careful to observe the t• LOW delay time before powering

down the device after blowing each bit.

The following programming order is recommended:•

POL1.

TC2. SENS

Sens3.

V4. OUT(Q)

LOCK (only after all other parameters have been pro-5.

grammed and validated, because this prevents any further

programming of the device)

Figure 4. Example of programming pulses applied to the VOUT pin that

result in permanent parameter settings. In this example, the register cor-

responding to key 1 is selected and code 5 is addressed and blown.

V+

Selection

(Key 1)

= 0 V

Selection

(Key 1)

Addressing

P(HIGH)

P(MID)

P(LOW)

Programming of Code 5 in Key 1

(Code 4)

Addressing

(Code 1)

(Code 4 in

Key 1)

Blow

BLOW

(Code 1 in

Key 1)

Blow

= 0 V V

= 0 V

Figure 3. Example of code 5 broken into its binary components, which are

code 4 and code 1.

(Decimal Equivalent)

Code 5

Bit Field Selection

Address Code Format

Code in Binary

Fuse Blowing

Target Bits

Fuse Blowing

Address Code Format

(Binary)

1 0 1

Bit 2 Bit 0

Code 4 Code 1

(Decimal Equivalents)

Programmable Linear Hall Ef fect Sensor ICs with Analog Output

Available in a Miniature Thin Profile Surface Mount Package

A1381, A1382,

A1383, and A1384

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Try Mode

Try mode allows a single programmable parameter to be tested

without permanently setting its value. Multiple parameters cannot

be tested simultaneously in this mode. After powering the VCC

supply, select the desired parameter register and address its bit

field. When addressing the bit field, each VPM pulse increments

the value of the parameter register, up to the maximum possible

code (see Programming Logic table). The addressed parameter

value remains stored in the device even after the programming

drive voltage is removed from the VOUT pin, allowing the value

to be measured. Note that for accurate time measurements, the

blow capacitor, CBLOW, should be removed during output voltage

measurement.

It is not possible to decrement the value of the register without

resetting the parameter bit field. To reset the bit field, and thus the

value of the programmable parameter, cycle the supply (VCC) voltage.

Blow Mode

After the required value of the programmable parameter is found

using Try mode, its corresponding code should be blown to make

its value permanent. To do this, select the required parameter

described in the Fuse Blowing section). The supply must be

cycled between blowing each bit of a given code. After a bit is

blown, cycling the supply will not reset its value.

Lock Mode

To lock the device, address the LOCK bit and apply a blow pulse

with CBLOW in place. After locking the device, no future pro-

gramming of any parameter is possible.

Programming Modes

Programmable Linear Hall Ef fect Sensor ICs with Analog Output

Available in a Miniature Thin Profile Surface Mount Package

A1381, A1382,

A1383, and A1384

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Initial State After system power-up, the programming logic is

reset to a known state. This is referred to as the Initial state. All

the bit field locations that have intact fuses are set to logic 0.

While in the Initial state, any VPM pulses on the VOUT pin are

ignored. To enter the Parameter Selection state, apply one VPH

pulse on the VOUT pin.

Parameter Selection State This state allows the selection of the

parameter register containing the bit fields to be programmed. To

select a parameter register, increment through the keys by apply-

ing VPM pulses on the VOUT pin. Register keys select among the

following programming parameters:

1 pulse - Sens•

2 pulses - V• OUT(Q)

3 pulses - TC• SENS, POL, and LOCK

To enter the Bit Field Addressing state, apply one VPH pulse on

the VOUT pin.

Bit Field Addressing State This state allows the selection of the

individual bit fields to be programmed in the selected parameter

cycle device power or blow the fuses for the selected code. Note

that merely addressing the bit field does not permanently set

the value of the selected programming parameter; fuses must be

blown to do so.

Fuse Blowing State To blow an addressed bit field, apply a

VPH pulse on the VOUT pin. Power to the device should then be

cycled before additional programming is attempted. Note: Each

bit representing a decimal code must be blown individually (see

the Fuse Blowing section).

Programming State Machine

Power-Up

Initial

Parameter Selection

Bit Field Addressing

Fuse Blowing

VPM

VPM = VP(LOW) –VP(MID) –VP(LOW)

VPH = VP(LOW) –VP(HIGH) –VP(LOW)

VPM

VPM VPM

VPM VPM VPM

VPH VPH

VPH

TCSENS,

POL,

LOCK

VOUT(Q)

SENS

User Power-Down

Required

12n – 1

n = total

bits in

Programmable Linear Hall Ef fect Sensor ICs with Analog Output

Available in a Miniature Thin Profile Surface Mount Package

A1381, A1382,

A1383, and A1384

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Programming Logic Table

Programmable

Parameter

(Register Key)

Bit Field Address

Description

Binary Format

[MSB → LSB]

Decimal Equivalent

Code

Sens

(1)

000000 0 Initial value (Sensinit)

111111 63 Maximum value of sensitivity (Sens) in range

VOUT(Q)

(2)

000000 0 Initial value (VOUT(Q)init)

111111 63 Maximum value of quiescent voltage output

(VOUT(Q)) in range; B = 0 G

TCSENS , POL, LOCK

(3)

000000 0 Initial value of sensitivity temperature coefficient

range (TCSensinit)

000111 7 Maximum value of sensitivity temperature coef-

ficient (TCSens) in range

001000 8

POL bit, switches polarity (causes VOUT to

increase with a negative [north polarity] field

applied to the branded face of the device)

010000 16 LOCK bit, enables permanent locking of all pro-

gramming bit fields in the device

Programmable Linear Hall Ef fect Sensor ICs with Analog Output

Available in a Miniature Thin Profile Surface Mount Package

A1381, A1382,

A1383, and A1384

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Package LH, 3 Pin; (SOT-23W)

0.55 REF

Gauge Plane

Seating Plane

0.25 BSC

0.95 BSC

0.95

1.00

0.70 2.40

AActive Area Depth, 0.28 mm REF

Reference land pattern layout

All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary

to meet application process requirements and PCB layout tolerances

Branding scale and appearance at supplier discretion

PCB Layout Reference View

Standard Branding Reference View

Branded Face

N = Last two digits of device part number

T = Temperature code

NNT

2.90 +0.10

–0.20

8X 10° REF

0.180+0.020

–0.053

0.05 +0.10

–0.05

0.25 MIN

1.91 +0.19

–0.06

2.98 +0.12

–0.08

1.00 ±0.13

0.40 ±0.10

4°±4°

For Reference Only; not for tooling use (reference dwg. 802840)

Dimensions in millimeters

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

DHall element, not to scale

1.49

0.96

Programmable Linear Hall Ef fect Sensor ICs with Analog Output

Available in a Miniature Thin Profile Surface Mount Package

A1381, A1382,

A1383, and A1384

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Package UA, 3-Pin SIP

231

1.27 NOM

1.02

MAX

0.51

REF

45°

0.79 REF

2X10°

2.04

1.44

Gate and tie bar burr area

Dambar removal protrusion (6X)

Branding scale and appearance at supplier discretion

Hall element, not to scale

Active Area Depth, 0.50 mm REF

For Reference Only; not for tooling use (reference DWG-9013)

Dimensions in millimeters

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

Standard Branding Reference View

NNT

Mold Ejector

Pin Indent

Branded

Face

= Supplier emblem

N = Last two digits of device part number

T = Temperature code

4.09 +0.08

–0.05

0.41 +0.03

–0.06

3.02 +0.08

–0.05

0.43 +0.05

–0.07

14.99 ±0.25

1.52 ±0.05

Please note that there are changes to the existing UA package drawing pending.

Please contact the Allegro Marketing department for additional information.

Programmable Linear Hall Ef fect Sensor ICs with Analog Output

Available in a Miniature Thin Profile Surface Mount Package

A1381, A1382,

A1383, and A1384

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

For the latest version of this document, visit our website:

www.allegromicro.com

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-

mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the

information being relied upon is current.

Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the

failure of that life support device or system, or to affect the safety or effectiveness of that device or system.

The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;

nor for any in fringe ment of patents or other rights of third parties which may result from its use.

Revision History

Revision Revision Date Description of Revision

Rev. 8 January 30, 2012 Update product availability