DS1321 CSS DS1321 DALLAS Flexible Nonvolatile Controller with Lithium Battery Monitor ee SEMICONDUCTOR FEATURES Converts CMOS SRAM into nonvolatile memory Unconditionally write-protects SRAM when Vcc is out of tolerance Automatically switches to battery backup supply when Vcc power failure occurs Flexible memory organization Mode 0: 4 banks with 1 SRAM each Mode 1: 2 banks with 2 SRAMs each Mode 2: 1 bank with 4 SRAMs each Monitors voltage of a lithium cell and provides advanced warning of impending battery failure Signals lowbattery condition on active low Battery Warning output signal Resets processor when power failure occurs and holds processor in reset during system power-up Optional -5% or 10% power fail detection 16pin DIP, 16pin SOIC and 20-pin TSSOP pack- ages |ndustrial temperature range of 40C to +85C. PIN DESCRIPTION Vecl +5V Power Supply Input Veco SRAM Power Supply Output VBAT Backup Battery Input A,B Address Inputs CEH CEI4 Chip Enable Inputs CEOT - CEO4 Chip Enable Outputs TOL Voc Tolerance Select BW - Battery Warning Output (Open Drain) RST Reset Output (Open Drain) MODE Mode Input GND Ground NC No Connection PIN ASSIGNMENT Veco TU] 1 46 O Veer Vear CL] 2 15] RST ToL[] 3 1441 Bw cen CT] 4 13] CEot cel2[] 5 12 [1] CEO2 ACEB(L] 6 11 1] CEO3 BCE LJ 7 io L] CEO4 GND CL] 8 9(0 MODE DS1321 16-PIN DIP (300 MIL) Veco OF | 1 1610 Veo Vear OD | 2 15[10 RST ToL OH | 3 140 BW cen O1 | 4 1310 CEotT cele OF |5 1210 CEo2 ACEI O11] |6 1110 CEO3 B/CEI4 OL | 7 10M CEO4 GND OF | 8 9f MODE DS1321S 16-PIN SOIC (150 MIL) Veco [] 1 2011 Voor Vear LI 2 191] RST ToL F 3 is] BW cen CT] 4 17( CEOT cel2 O 5 16] CEO2 nc [] 6 15(J Nc ACEI [| 7 14[] CEOs BCE TJ 8 131] CEO4 nc [] 9 121] ne @nD [J 10 111] MODE DS1321E 20-PIN TSSOP 022598 1/12DS1321 DESCRIPTION The DS1321 Flexible Nonvolatile Controller with Lith- ium Battery Monitor is a CMOS circuit which solves the application problem of converting CMOS SRAMs into nonvolatile memory. Incoming power is monitored for an out-of-tolerance condition. When such a condition is detected, chip enable outputs are inhibited to accom- plish write protection and the battery is switched on to supply the SRAMs with uninterrupted power. Special circuitry uses a low-leakage CMOS process which affords precise voltage detection at extremely low bat- tery consumption. One DS1321 can support as many as four SRAMs arranged in any of three memory config- urations. In addition to batterybackup support, the DS1321 per- forms the important function of monitoring the remaining capacity of the lithium battery and providing a warning before the battery reaches end-of-life. Because the open-circuit voltage of a lithium backup battery remains relatively constant over the majority of its life, accurate battery monitoring requires loadedbattery voltage measurement. The DS1321 performs such measure- ment by periodically comparing the voltage of the bat- tery, as it supports an internal resistive load, with a care- fully selected reference voltage. If the battery voltage falls below the reference voltage under such conditions, the battery will soon reach end-of-life. As a result, the Battery Warning pin is activated to signal the need for battery replacement. MEMORY BACKUP The DS1321 performs all the circuit functions required to provide batterybackup for as many as four SRAMs. First, the device provides a switch to direct power from the battery or the system power supply (Vccj). When- ever Vccy is less than the Vcctp trip point and Vcc is less than the battery voltage Vpaq, the battery is switched in to provide backup power to the SRAM. This switch has voltage drop of less than 0.2 volts. Second, the DS1321 handles power failure detection and SRAM writeprotection. Veg, is constantly moni- tored, and when the supply goes out of tolerance, a pre- cision comparator detects power failure and inhibits the four chip enable outputs in order to writeprotect the SRAMs._ This is accomplished by holding CEO1 through CEO4 to within 0.2 volts of Veco when Vcc is outof tolerance. If any CElis active (low) atthe time that power failure is detected, the corresponding CEO signal is kept low until the CEI signal is brought high again. Once the CEI signal is brought high, the CEO signal is taken high and held high until after Voc) has returned to its nominal voltage level. If the CEI signal is not brought high by 1.5 ws after power failure is detected, the corre- sponding CEO is forced high at that time. This specific scheme for delaying write protection for up to 1.5 us guarantees that any memory access in progress when power failure occurs will complete properly. Power fail- ure detection occurs in the range of 4.75 to 4.5 volts (5% tolerance) when the TOL pin is wired to GND or in the range of 4.5 to 4.25 volts (10% tolerance) when TOL is connected to Veco. 022598 2/12DS1321 MEMORY CONFIGURATIONS The DS1321 can be configured via the MODE pin for three different arrangements of the four attached SRAMs. The state of the MODE pin is latched at Voc = VocTp on power up. See Figure 1 for details. MEMORY CONFIGURATIONS Figure 14 MODE = GND (4 BANKS WITH 1 SRAM EACH): AB DS1321 CEO1 BANK 1 00 CEI1 +C} QO CEO2 (> BANK 2 01 A 2-TO-4 DECODER CEO3 B > BANK 3 10 Q CEO4 BANK 4 1 MODE = Vcco (2 BANKS WITH 2 SRAM EACH): DS1321 CEI > CEl2 MODE FLOATING (1 BANK WITH 4 SRAMs): UPPER LOWER BYTE BYTE CEO4 CEOQ3 CEO2 CEO1 ' ' DS1321 ' ' CEI4 CEI3 CEI2 CEN 022598 3/12DS1321 BATTERY VOLTAGE MONITORING The DS1321 automatically performs periodic battery voltage monitoring at a factoryprogrammed time inter- val of 24 hours. Such monitoring begins within tpec after Voc) rises above Vcctp, and is suspended when power failure occurs. After each 24 hour period (tgtTcn) has elapsed, the DS1321 connects Vgarz to an internal 1MQ test resistor (Rint) for one second (tgtpy). During this one second, if Vat falls below the factoryprogrammed battery volt- age trip point (Vptp), the battery warning output BW is asserted. While BWis active, battery testing will be per- formed with period tprcw to detect battery removal and replacement. Once asserted, BW remains active until the battery is physically removed and replaced by a fresh cell. The battery is still retested after each Voc power-up, however, even if BW was active on power down. If the battery is found to be higher than Vptp dur- ing such testing, BW is deasserted and regular 24hour testing resumes. BW has an open-drain output driver. Battery replacement following BW activation is normally done with Voc) nominal so that SRAM data is not lost. During battery replacement, the minimum time duration between old battery detachment and new battery attachment (tppga) must be met or BW will not deacti- vate following attachment of the new battery. Should BW not deactivate for this reason, the new battery can be detached for tgppa and then reattached to clear BW. NOTE: The DS1321 cannot constantly monitor an attached battery because such monitoring would drasti- cally reduce the life of the battery. As a result, the DS1321 only tests the battery for one second out of every 24 hours and does not monitor the battery in any way between tests. If a good battery (one that has not been previously flagged with BW) is removed between battery tests, the DS1321 may not immediately sense the removal and may not activate BW until the next scheduled battery test. If a battery is then reattached to the DS1321, the battery may not be tested until the next scheduled test. NOTE: Battery monitoring is only a useful technique when testing can be done regularly over the entire life of a lithium battery. Because the DS1321 only performs battery monitoring when Vcc _ is nominal, systems which are powereddown for excessively long periods can completely drain their lithium cells without receiving any advanced warning. To prevent such an occurrence, systems using the DS1321 battery monitoring feature should be poweredup periodically (at least once every few months) in order to perform battery testing. Further- more, anytime BW is activated on the first battery test after a powerup, data integrity should be checked via checksum or other technique. POWER MONITORING The DS1321 automatically detects out-oftolerance power supply conditions and warns a processorbased system of impending power failure. When Vcc, falls below the trip point level defined by the TOL pin (Voctp), the Voc; comparator activates the reset signal RST. Reset occurs in the range of 4.75 to 4.5 volts (5% tolerance) when the TOL pin is connected to GND or in the range of 4.5 to 4.25 volts (10% tolerance) when TOL is connected to Voco. RST also serves as a power-on reset during power-up. After Voc) exceeds Vectp, RST will be held active for 200 ms nominal (tapy). This reset period is sufficiently long to prevent system operation during poweron tran- sients and to allow tpec to expire. RST has an open drain output driver. FRESHNESS SEAL MODE When the battery is first attached to the DS1321 without Voc power applied, the device does not immediately provide battery-backup power on Vcoco. Only after Voc exceeds Voctp and later falls below both Vectp and Vgat will the DS1321 leave Freshness Seal Mode and provide battery-backup power. This mode allows a battery to be attached during manufacturing but not used until after the system has been activated for the first time. As a result, no battery energy is drained dur- ing storage and shipping. 022598 4/12DS1321 FUNCTIONAL BLOCK DIAGRAM Figure 2 MODE 7 CEI J > [0 CEOT CEl2 FEDS CHIP ENABLE -) >_>__ CEO2 DECODE LOGIC AICEI3 ZEAS B/CEI4 AER J >>[>o asi RST DELAY TIMING CIRCUITRY | Veci = Vv cco + Vectp REF 3 5 ) >___4 TOL + VY ' ' REDUNDANT LOGIC 1 I 1 ' | Qo \ rn es i VeaT ; WW 1 ' CURRENT-LIMITING REDUNDANT ! BATTERY CHARGING/SHORTING ' RESISTOR SERIES FET ' PROTECTION CIRCUITRY Vere REF 5 1.2MQ BATTERY WARNING CONTROL CIRCUITRY 022598 5/12DS1321 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground 0.5V to +7.0V Operating Temperature 40C to +85C Storage Temperature 55C to +125C Soldering Temperature 260C for 10 seconds * This is astress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is notimplied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (-40C to +85C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Supply Voltage TOL=GND Vecl 4.75 5.0 5.5 Vv 1 Supply Voltage TOL=Vcoco Vecl 4.5 5.0 5.5 Vv 1 Battery Supply Voltage VBaT 2.0 3.0 6.0 Vv 1 Logic 1 Input Vin 2.0 Vec!+0.3 Vv 1,12 Logic 0 Input VIL 0.3 +0.8 Vv 1,12 DC ELECTRICAL CHARACTERISTICS (-40C to +85C; Voc) > Vectp) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Operating Current (TTL inputs) lect 1 1.5 mA 2 Operating Current (CMOS inputs) loce 100 150 HA 2,5 RAM Supply Voltage Veco Vecl-0.2 Vv 1 RAM Supply Current leco1 185 mA 3 (Veco 2 Vcc! -0.2V) Supply Current locoe 260 mA 4 (Veco 2 Vcc) -0.3V) Vec Trip Point (TOL=GND) VoctTp 4.50 4.62 4.75 Vv 1 Vec Trip Point (TOL=Vcco) VoctTp 4.25 4.37 4.50 Vv 1 Veat Trip Point VeTp 2.50 2.6 2.70 Vv 1 Output Current @ 2.4V lou -1 mA 7,10 Output Current @ 0.4V lo 4 mA 7,10 Input Leakage lit -1.0 +1.0 HA Output Leakage ILo -1.0 +1.0 pA Battery Monitoring Test Load RINT 0.8 1.2 1.5 MQ 022598 6/12DS1321 DC ELECTRICAL CHARACTERISTICS (40C _ to +85C; Veci < Vat; Voci < Voctp) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Battery Current IBAT 100 nA 2 Battery Backup Current locos 500 HA 6 Supply Voltage Veco VeatT0.2 1 CEO Output VoHL Vpat0.2 1,8 CAPACITANCE (ta=25C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Capacitance Cin 7 pF (CEI*, TOL, MODE) Output Capacitance Court 7 pF (CEO*, BW, RST) AC ELECTRICAL CHARACTERISTICS (-40C to +85C; Voc = Vectp) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES CEI to CEO Propagation Delay tpp 12 20 ns CE Pulse Width tcE 1.5 us 11 Voc Valid to End of Write tREC 125 ms 9 Protection Voc Valid to CEI Inactive tpu 2 ms Voc Valid to RST Inactive tReU 150 200 350 ms 10 Voc Valid to BW Valid tppu 1 s 10 AC ELECTRICAL CHARACTERISTICS (-40C to +85C; Vec! < Vectp) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Vcc Slew Rate te 150 ps Voc Fail Detect to RST Active tReD 15 us 10 Vcc Slew Rate tr 15 ps AC ELECTRICAL CHARACTERISTICS (-40C to +85C; Voc! = Vectp) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Battery Test to BW Active taw 1 s 10 Battery Test CycleNormal tBTCN 24 hr Battery Test Cycle-Warning tBTcw 5 s Battery Test Pulse Width tBTPW 1 s Battery Detach to Battery Attach tBDBA 7 s Battery Attach to BW Inactive tBaBW 1 s 10 022598 7/12DS1321 TIMING DIAGRAM: POWER UP \ \ CEI1 CEl4 DON'T CARE N tpu] ted | tpp Vear 0.2 CEO1 - CEO4 | tp r Vectp a VBaT tapu Veci > trPu < SLEWS UP WITH Voc Veco V BAT Vin 2 RST \ SLEWS UP Vv BW WITH Vec RE NOTE: If VBat > Vectp. Veco will begin to slew with Veco, when Vocl = Vectp. 022598 8/12DS1321 TIMING DIAGRAM: POWER DOWN toe cs CSSAION CEO Vi cel NS trpep VoctP VeaT Vcco SLEWS DOWN aN WITH Voc Vat RST X Vit SLEWS DOWN WITH Voc BW NOTE: If Veat > Vectp, Veco will slew down with Voc until Veco) = Voctp. 022598 9/12DS1321 TIMING DIAGRAM: BATTERY WARNING DETECTION Voctp V, cc tapu yy Dy Ve Ce Vaart __,, \ \ | _ JI \ VBTP tetcn >| t tatpw w__ BICW - BATTERY TEST L i ACTIVE ] a, Ye : Ye BW NOTE: tgw is measured from the expiration of the internal timer to the activation of the battery warning output BW. TIMING DIAGRAM: BATTERY REPLACEMENT cc BATTERY BATTERY \ DETACH vt BAT BTP FLOATING 'BaBw ke ' p84 022598 10/12DS1321 NOTES: 1. All voltages referenced to ground. . Measured with outputs open circuited. . lecor is the maximum average load which the DS1321 can supply to attached memories at Voco = Voc} 0.2V. 2 3 4. Ieco2 is the maximum average load which the DS1321 can supply to attached memories at Voco > Voc) 0.3V. 5. All inputs within 0.3V of ground or Voc), 6 . lecog is the maximum average load current which the DS1321 can supply to the memories in the battery backup mode at Veco > VBat 0.2V. 7. Measured with a load as shown in Figure 1. 8. Chip Enable Outputs CEO1 CEO4 can only sustain leakage current in the battery backup mode. 9. CEO1 through CEO4 will be held high for a time equal to tpg after Voc) crosses VocTp on powerup. 10. BW and RST are open drain outputs and, as such, cannot source current. External pull-up resistors should be connected to these pins for proper operation. Both BW and RST can sink 10 mA. 11. t maximum must be met to ensure data integrity on power down. 12. In battery backup mode, inputs must never be below ground or above Voco. DC TEST CONDITIONS AC TEST CONDITIONS Outputs Open Output Load: See below All voltages are referenced to ground Input Pulse Levels: 0 3.0V Timing Measurement Reference Levels Input: 1.5V Output: 1.5V Input pulse Rise and Fall Times: 5 ns OUTPUT LOAD Figure 3 +5 VOLTS 1.1KQ D.U.T. 30 pF* 6802 *INCLUDING SCOPE AND JIG CAPACITANCE 022598 11/12DS1321 DATA SHEET REVISION SUMMARY The following represent the key differences between 03/26/96 and 06/12/97 version of the DS1321 data sheet. Please review this summary carefully. 1. Changed Icco; from 200 to 185 mA max . Changed Iccoe from 350 to 260 mA max . Changed Vptp from 2.55 2.65V to 2.50 2.70V 2 3 4. Changed Rjy from 1.0 typ to 1.2 MQ and 1.4 max to 1.5 MQ 5. Changed tpp from 5 typ, 15 max to 12 typ, 20 max 6. Changed trpo units from ns to ps 7 . Changed block diagram to show U.L. compliance The following represent the key differences between 06/12/97 and 09/29/97 version of the DS1321 data sheet. Please review this summary carefully. 1. Changed AC test conditions The following represent the key differences between 09/29/97 and 12/12/97 version of the DS1321 data sheet. Please review this summary carefully. 1. Removed preliminary from title bar. 2. Specified which inputs and outputs are relevant for Cjy and Coyt specs. This is not a change, just a clarification. 022598 12/12