19-2887; Rev. 3; 11/92 General Description The MAX900-903 high-speed, low-power, single/dual/ quad voltage comparators feature differential analog inputs and TTL logic outputs with active internal pull-ups. Fast propagation delay (8ns typ at 5mV overdrive) makes the MAX900-903 ideal for fast A/D converters and sampling circuits, line receivers, V/F converters, and many other data-dis- crimination applications. All comparators can be powered from separate analog and digital power supplies or from a single combined supply voltage. The analog input common-mode range includes the negative rail, al- MA AAI/VI High-Speed, Low-Power Voltage Comparators Features @ 8ns Typ Propagation Delay @ 18mW/Comparator Power Consumption (Typ at +5V) @ Separate Analog and Digital Supplies Flexible Analog Supply: +5V to +10V or +5V input Range Includes Negative Supply Rail @ TTL Compatible Outputs @ TTL Compatible Latch Inputs (Except MAX901) Ordering information lowing ground sensing when powered from a single PART TEMP. RANGE PIN-PACKAGE supply. The MAX900-903 consume 18mW per com- MAX900ACPP 0C to +70C 20 Plastic DIP parator when powered from +5V. MAXS00BCPP O'Cto+70C 20 Plastic DIP The MAX900-903 are equipped with independent MAXS00ACWP 0C. to +70C 20 Wide SO TTL compatible latch inputs. The comparator output MAX900BCWP OC to 470C 30 Wide SO states are held when the latch inputs are driven low. - ~ The MAX901 provides the same performance as the MAXS00BC/D OC to +70C Dice MAX900, MAX902, and MAX903 with the exception MAX900AEPP -40C to +85C 20 Plastic DIP of the latches. MAXQ00BEPP -40C to +85C 20 Plastic DIP App fications MAXSO0AEWP -40C to +85C 20 Wide SO igh Speed A/D Converters MAX900BEWP -40C to +85C 20 Wide SO IgM oPee onver'e MAX900AMJP S5Cto+125C 20 CERDIP High-Speed V/F Converters MAX900BMUJP 55Cto+125C 20 CERDIP Line Receivers: Ordering Information continued at end of data sheet. Threshold Detectors *Cantact factory for dice specifications. Input Trigger Circuitry High-Speed Data Sampling PWM Circuits Pin Configurations TOP VIEW nae MAX907 AAAXLAA Nt ._ MAX903 IN-(A) [7 Ha] IN- (0) n-(A) 1] 4] vec** 7 Ine (A) [2 15] IN+(0) in+ (A) [2] 3] NC. veo" [1] fe] Yoo" GND [3 | 7X Vita veo" cnn [31 7 12] our@) ne(2}> [7] out outa) [4] Dia] out (0) carcuia) [4] 8 fia] Latcn @) n- [3] fe] GNO out (8) [5h e]12] 0uT(C) outa) [5 /\. Fig} voo"** vee" [4] rs] LATCH ve*[e] 4 3 + 14] Voo"*" NC. [6] 3 | IN+ (B) IN+ (8) [7] 10] i+ (C) Vee" 8] IN-(B) DIP/SO IN- (8) [8] 19] IN-(C) DIPISO DIP/SO = MADE Pin Contigurations continued on page 12 DIGITAL V+ MAAXLIA Maxim Integrated Products 1 For free samples & the latest literature: http:/;www.maxim-ic.com, or phone 1-800-998-8800 06/E06/1+06/006XVNMAX900/901/902/903 High-Speed, Low-Power Voltage Comparators ABSOLUTE MAXIMUM RATINGS (Note 1) Analog Supply Voltage (Vcc to VEE) .....-...0-..0000. +12V Digital Supply Voltage (Vpp to GND).................. +7V Differential Input Voltage .......... [VEE-0.2V J to [Voc+0.2V] Common-Mode Input Voltage ...... [VeE-0.2V ] to [Vcc+0.2V] Latch Input Voltage (MAX800/902/903 only) -0.2V to [Vpp+0.2V] Output Short-Circuit Duration toGND...... ede te tne eee eee enne nee Indefinite TOVDD . 002 ccc nce eee eee 1 min Internal Power Dissipation .....................06- 500mWw Derate above +100C 2 wee eee eee fOmw/"C Operating Temperature Ranges: MAX900-903_C_o 6... eee eee 0C to +70C MAX900-903_E eee -40C to +85C MAX900-S03_M_ 0 ww. eee eee eee -58C to +125C Junction Temperature (Tj)................. -65C to +160C Storage Temperature Range .............. -65C to +150C Lead Temperature (soldering, 10sec) .............. +300C Note 1: Absolute maximum ratings apply to both packaged parts and dice, unless otherwise noted. Stresses beyond those listed undar Absolute Maximum Ratings may cause permanent damage to tha device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions ELECTRICAL CHARACTERISTICS extended periods may affect device reliability. (Veco = +5V, Vee = -5V, Vop = +5V, LE1-LE4 = Logic High, Ta = +25C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MAXSOOA/901A MAXS00B/901B/202/903 UNITS MIN TYP MAX MIN TYP MAX Input Offset Voltage Vos ven ow 0.5 2.0 1.0 40 mv Input Bias Current Ip lina or HN- 3 6 4 10 pA Input Offset Current los ven oN; 50 250 100 500 nA Input Voltage Range Vom (Note 2) VeE-0.4 Vec-2.25| VeEE-0.1 Voc-2.25| V Rejoctenaio. CMRR Woo 1 +278, 50 150 75 250 | wv Power-Supply Rejection Ratio PSRR |} (Note 3) 50 150 100 250 pv Output High Voltage VOH eel 24 35 246 35 V Output Low Voltage Vor | jN>2oemnA 03 04 03 o4 | v Latch Input Voltage High VLH (Note 4) 1.4 2.0 1.4 2.0 V Latch Input Voltage Low ViL (Note 4) 0.8 1.4 0.8 1.4 Vv Latch Input Current High ILH (Note a 1 20 1 20 pA Latch Input Current Low he (Note ad 1 20 1 20 pA MA AXLAAH Low-Power Voltage Comparators ELECTRICAL CHARACTERISTICS (continued) (Vcc = +5V, Vee = -5V, Vop = +5V, LE1-LE4 = Logic High, Ta = +25C, unless otherwise noted.) nA| MAXoo2 MAX903 PARAMETER SYMBOL | CONDITIONS UNITS MIN TYP MAX |MIN TYP MAX] MIN TYP MAX Positive Analog Supply Current Icc (Note 8) 10 15 5 8 25 4 mA Negative Analog Supply Current lEE (Note 8) 7 12 3.5 6 2 3 mA Digital Supply Current IDD (Note 8) 4 6 2 3 1 1.5] mA we Voc = Vpp = +5V, Power Dissipation Po VEE = OV 70 = 105 35 55 18 28) mW TIMING CHARACTERISTICS (Voc = +5V, VEE = -5V, Vpp = +5V, LE1-LE4 = Logic High, Ta = +25C, unless otherwise noted.) MAXS900A/MAX901A MAX902 MAX903 PARAMETER SYMBOL| CONDITIONS |MAX900B/MAX901B UNITS MIN TYP MAX | MIN TYP MAX| MIN TYP MAX VoD = 5mvV, Input-to-Output High CL = 15pF, Response Time tod+ lo = 2mA 8 10 8 10 8 10 ns (Note 5) Vop = 5mvV, Input-to-Output Low - CL = 15pF, Response Time tba lo = 2mA 8 10 8 10 8 10 ns (Note 5) Difference in Response Atod (Notes 5, 8) 05 20 05 2.0 0.5 20 ns Time Between Outputs pi ' , , , Latch Disable to Output High Delay tpd+(D) | (Notes 4, 7) 10 10 10 ns Taber toOutput | 14-4) | (Notes 4, 7) 12 12 12 ns Minimum Setup Time ts (Notes 4, 7) 2 2 2 ns Minimum Hold Time th (Notes 4, 7) 1 1 1 ns Minimum Latch Disable Pulse Widih tpw(D) | (Notes 4, 7) 10 10 10 ns Note 2: The input common-mode voltage and input signal voltages should not be allowed to go negative by more than 0.2V below VEE The upper end of the common-mode voltage range is typically Vcc-2V, but either or both inputs can go to a maximum of Voc+0.2V without damage. Note 3: +4.75V<Vcoc<+10.5V for single-supply operation with VEE grounded. Specification does not apply to MAXS01. Guaranteed by design. Times are for 100mV step inputs (see propagation delay characteristics in Figures 2 and 3). Maximum difference in propagation delay between any of the fo See Timing Diagram (Figure 2). ur comparators in the MAX900/901/9 Owing to the difficult and critical nature of switching measurements involving the latch, these parameters cannot be tested in a production environment. Typical specifications listed are taken from measurements using a high-speed test-jig. lec tested for +4.75V<Vcoc<+10.5V with VEE grounded. IEE tested for -5.25V<VEE<-4.75V with Voc = +5V. +4.75V<Vpp<+5.25V with the worst-case condition of all four comparator outputs at logic low. 2/903. Tested for +4.75V<Vcc<+5.25V, and -5.25V<VeE<-4.75V with Vpp = +5V, although permissible analog power-supply range is IDD tested for MA AXLAA 06/206/1 06/006X VNMAX900/901/902/903 High-Speed, Low-Power Voltage Comparators ELECTRICAL CHARACTERISTICS (Voc = +5V, VEE = -5V, Vop = +5V, LE1-LE4 = Logic High; Ta = Full Operating Temperature, unless otherwise noted.) MAXSO00A/901A MAX900B/001 B/902/903 PARAMETER SYMBOL; CONDITIONS UNITS MIN TYP MAX MIN TYP MAX Input Offset Voltage Vos vee ON 1 3 2 6 mV Input Bias Current IB liN+ OF IIN- 4 10 6 15 pA | Vem = OV, nput Offset Current los Vo = 1.4V 100 500 200 800 nA Input Voltage Range Vom (Note 2) Vee-0.1 Vcc-2.25 | Vee-0.1 Voc-2.25 Vv 5V<Vom<+2.75V, Common-Mode ~ ' Rejection Ratio CMRR vont Vv 80 250 120 500 | uVN Power-Supply Rejection Ratio PSRR (Note 3) 100 250 150 500 pV Output High Voltage Vou | yiNz2omma' 24 36 24 35 v Output Low Voltage VoL Nek 03 04 03 04 V Latch Input Voltage High VLH (Note 8) 1.4 2.0 1.4 2.0 Vv Latch Input Voltage Low VEL (Note 8) 0.8 1.4 0.8 1.4 Vv Latch Input Current High ILH (hots a 2 20 1 20 pA Latch Input Current Low Ie thiote o 2 20 1 20 pA MAXS00A/MAXS01A MAX902 MAX903 PARAMETER SYMBOL | CONDITIONS | MAXS00B/MAxXe016 UNITS MIN TYP MAX |MIN TYP MAX| MIN TYP MAX Positive Analog Supply Current Icc (Note 8) 10 25 5 12 25 6 mA Negative Analog Supply Current IEE (Note 8) 7 20 3.5 10 2 5 mA Digital Supply Current IDD {Note 8) 4 10 2 5 1 25] mA Power Dissipation Po | yoo gp *8V) 70 105 35 55 18 28 | mw 4 MMAXIAAHigh-Speed, Low-Power Voltage Comparators TIMING CHARACTERISTICS (Voc = +5V, VEE = -5V, Vop = +5V, LE1-LE4 = Logic High, Ta = TMIN to TMAx, unless otherwise noted.) MAX900A/901A MAX900B/901B/902/903 PARAMETER SYMBOL; CONDITIONS UNITS MIN TYP MAX MIN TYP MAX Vopb = 5mvV Input-to-Output High CL = 15pF Response Time tpd+ lo =2mA 10 18 10 18 ns (Note 5) Vopb = 5mv Input-to-Output Low . CL = 15pF Response Time pa lo = 2mA 10 18 10 18 ns (Note 5) Difference in Response Time Between Outputs Atpd (Notes 5, 6) 1 3 1 3 ns Note 2: The input common-mode voltage or either input signal voltage should not be allowed to go negative by more than 0.2V below VEE. The upper end of the common-mode voltage range is typically Vcc-2.0V, but either or both inputs can go to a maximum of Vcc +0.2V without damage. Note 3: Tested for +4.75V<Vcoc<+5.25V, and -5.25V<VeE<-4.75V with Vpp = +5V, although permissible analog power-supply range is +4.75V<Voc<+10.5V for single-supply operation with Vee grounded. Note 4: Specification does not apply to MAX901 Note 5: Guaranteed by design. Times are for 100mV step inputs (see propagation delay characteristics in Figures 2 and 3). Note 6: Maximum difference in propagation delay between any of the four comparators in the MAX900/901/902/903. Note 7: See Timing Diagram (Figure 2). Owing to the difficult and critical nature of switching measurements involving the latch, these parameters cannot be tested in a production environment. Typical specifications listed are taken from measurements using a high-speed test-jig. Note 8: Icc tested for +4.75V<Vcc<+10.5V with VEE grounded. IEE tested for -5.25V<VEE<-4.75V with Vcc = +5V. lpp tested for +4.75V<Vpp<+5.25V with the worst-case condition of all four comparator outputs at logic low. Typical Operating Characteristics INPUT OFFSET VOLTAGE (mY) eo t - i BD INPUT OFFSET VOLTAGE INPUT BIAS CURRENT OUTPUT LOW VOLTAGE vs. TEMPERATURE vs. TEMPERATURE (VoL) vs. LOAD CURRENT z 40 = os w E35 g z . 5 0.4 c 5 sol. = 03 [ A= S5C 3 as 3 | @ 25 a = op Of\ Ta = +25C an, z A. a 20 ne Bo OA Ta = +128C z -40-20 0 20 40 60 80100120 ~40-20 0 20 40 60 80 100120 2. 4 6 6 10 TEMPERATURE (C) TEMPERATURE (C) LOAD CURRENT (mA) MAAXLAA 5 06/206/1 06/006X VNMAX900/90 1/902/903 Migh-Speed, Low-Power Voltage Comparators Typical Operating Characteristics (continued) Icc SUPPLY CURRENT INPUT OVERDRIVE vs. INPUT OVERDRIVE vs. (PER COMPARATOR) vs. Vcc SUPPLY VOLTAGE (Vpp = +5V) tpdt RESPONSE TIME tod- RESPONSE TIME WwW WwW g g < 3.0 Ta = +128C 5 4 5 4 E 9 2 _ 2.8 Le 3 >S 3 Zz 26 Ta = +25C zp 2 - ? = 2 5 5 1 5 24 oC! 3 2 22 w oO w o 5 g oO & 20 1090 _ a 18 QF 4 INPUT OVER oz: 0 g Ew bE 2 16 2 -100 2 100 z Z 4 5 6 7 8 9 10 o 2 4 6 8 10 12 14 o 2 4 6 8 10 12 14 Voc SUPPLY VOLTAGE (V) toa? RESPONSE TIME (ns) tpd- RESPONSE TIME (ns) RESPONSE TIME RESPONSE TIME vs. vs. TEMPERATURE LOAD CAPACITANCE (5mV (5mV OVERDRIVE) OVERDRIVE, Rioap = 2.4kQ) n ~ ea = = - = wi - wo wi Zz wn 3 z 2 3 a w tog- a rd ipd rd -40-20 0 20 40 60 80 100120 10 20 30 40 50 60 70 80 TEMPERATURE (C) LOAD CAPACITANCE (pF) 6 MA AXIAAHigh-Speed, Low-Power Voltage Comparators Pin Descriptions MAX3900 MAX901 PIN NAME FUNCTION PIN NAME FUNCTION 1,10, 11,20] IN-(4,B,C,D) | Negative Input 1,8,9,16 | IN-(A,B,c,D) | Negative Input TQ, 17, 5,U, (Channels A, B, C, D) ras co (Channels A, B, C, D) 2,9,12,19] IN+(A,B,C,D) | Positive Input 2,7,10,15| IN+(A,B,C,D) | Positive Input 9, Te, BM, (Channels A, B, C, D) es ou (Channels A, B, C, D) 3 GND Ground Terminal 3 GND Ground Terminal Latch Input Output 4,7, 14, 17 | LATCH (A,B, C,D) | (Channels A, B,C, D) 4,5, 12,13 | OUT(A,B,C,D) | (Channels A,B, C, D) Output Negative Analog Supply 5,6, 15,16 | OUT(A,B.C,D) | (Channels A, B,C, D) 6 VEE and Substrate 8 V Negative Analog Supply 11 VDD Positive Digital Supply cE and Substrate 14 Vcc Positive Analog Supply 13 Vpb Positive Digital Supply 18 Vcc Positive Analog Supply MAX902 MAX903 PIN NAME FUNCTION PIN NAME FUNCTION Negative Input 1 Vcc Positive Analog Supply 1,8 IN- (A, B) (Channels A, B) 2 IN+ Positive Input Positive Input 2,9 IN+ (A, B) (Channels A, B) 3 IN- Negative Input 3 GND Ground Terminal 4 VEE Negative Analog Supply and Substrate Latch Input 41 LATCH (A,B) | (Channels A. B) 5 LATCH Latch Input Output 6 GND Ground Terminal 5,12 OUT (A, B} (Channels A, B) 7 OUT Output 6, 13 N.C. No Connect 8 VDD Positive Digital Supply 7 Vee Negative Analog Supply and Substrate 10 Vob Positive Digital Supply 14 Voc Positive Analog Supply MA AXIAM 06/206/106/006X VWMAX900/901/902/803 Voltage Comparators Applications Information Circult Layout Because of the large gain-bandwidcth transfer function of the MAXS00-903, special precautions must be taken to realize their full high-speed capability. A printed circuit board with a good, low-inductance ground plane is man- datory. All decoupling capacitors (the small 100nF ce- ramic type is a good choice) should be mounted as close as possible to the power-supply pins. Separate decou- pling capacitors for analog Vcc and for digital Vpp are also recommended. Close attention should be paid to the bandwidth of the decoupling and terminating components. Short lead lengths on the inputs and outputs are essential to avoid unwanted parasitic feedback around the compa- rators. Solder the device directly to the printed circuit board instead of using a socket. input Slew-Rate Requirements As with all high-speed comparators, the high gain- bandwidth product of the MAX900-903 can create oscil- lation problems when the input traverses the linear region. For clean output switching without oscillation or steps in the output waveform, the input must meet minimum slew- rate requirements. Oscillation is largely a function of board layout and of coupled source impedance and stray input capacitance. Both poor layout and large source impedance will cause the part to oscillate and increase the minimum slew-rate requirement. In some applica- tions, it may be helpful to apply some positive feedback Nigh-Speed, Low-Power between the output and + input. This pushes the output through the transition region cleanly, but applies a hys- teresis in threshold seen at the input terminals. TTL Output and Latch inputs The comparator TTL output stages are optimized for driving low-power Schottky TTL with a fan-out of four. When the latch is connected to a logic high level or left floating, the comparator is transparent and immediately responds to changes at the input terminals. When the latch is connected to a TTL low level, the comparator output latches in the same state as at the instant that the latch command is applied, and will not respond to sub- sequent changes at the input. No latch is provided on the MAXS01. Power Supplies The MAX900-903 can be powered from separate analog and digital supplies or from a single +5V supply. The analog supply can range from +5V to +10V with VEE grounded for single-supply operation (Figures 1A and 1B) orfromasplitt5V supply (Figure 1C). The Vpp digital supply always requires +5V. In high-speed, mixed-signal applications where a com- * mon ground is shared, a noisy digital environment can adversely affect the analog input signal. When set up with separate supplies (Figure 1C), the MAX900-903 isolate analog and digital signals by providing a separate AGND(VEE) and DGND. Typical Power-Supply Alternatives +10V OUT +5V ~ | OUT OUT GND Figure 1A. Separate Analog Supply, Common Ground Figure 1B. Single +5V Supply, Common Ground Figure 1C. SplittSV Supply, Separate Ground MA AXIAALow-Power Voltage Definition of Terme Vos VIN Vop tpd+ tpd- tpd+ (D) MAAXIAN Input Offset Voltage: Voltage applied be- tween the two input terminals to obtain TTL logic threshold (+1.4V) at the output. Input Voltage Pulse Amplitude: Usually set to 100mV for comparator specifications. Input Voltage Overdrive: Usually set to 5mvV and in opposite polarity to VIN for com- parator specifications. Input to Output High Delay: The propagation delay measured from the time the input signal crosses the input offset voltage to the TTL logic threshold of an output low to high transistion. Input to Output Low Delay: The propagation delay measured from the time the input signal crosses the input offset voltage to the TTL logic threshold of an output high to low transition. Latch Disable to Output High Delay: The propagation delay measured from the latch signal crossing the TTL threshold in a low to high transition to the point cf the output cross- ing TTL threshold in a low to high transition. tpd- (D) Latch Disable to Output Low Delay: The tpw (D) propagation delay measured from the latch signal crossing the TTL threshold in a low to high transition to the point of the output crossing TTL threshold in a high to low tran- sition. Minimum Setup Time: The minimum time before the negative transition of the latch sig- nal that an input signal change must be pres- ent in order to be acquired and held at the outputs. Minimum Hold Time: The minimum time after the negative transition of the latch sig- nal that an input signal must remain un- changed in order to be acquired and held at the output. Minimum Latch Disable Piuse Width: The minimum time that the latch signal must re- main high in order to acquire and hold an input signal change. 06/Z0G/1 06/006EXVHMAX900/901/902/903 High-Speed, Low-Power Voltage Comparators ENABLE COMPARE COMPARE _ _ __ fey LATCH j LATCH sv ee DIFFERENTAL tow(D} INPUT VOLTAGE a Vos OUTPUT ov , Vns t +5mV COMPARATOR 1aVv INPUT "00m OUTPUT Sns/DIV Figure 2. MAX900/902/903 Timing Diagram Figure 3. tpa+ Response Time to 5mV Overdrive INPUT TQ 10X Vcc +5 Voo +5V ay SCOPE PROBE OUTPUT (10MQ, 14pF) _ = { 100nF} PRECISION 1k il 243k STEP > = GENERATOR ov 10k D.U.T. OUTPUT TO 10x INPUT 100mv y . 1 ents PROBE pe , OFFSET 10 PL mm) ADJUST _[roone | 10m [ome Vos = = = +5mV Vee -5V 5ns/DV Figure 4. tpa- Response Time to 5mV Overdrive 10 Figure 5. Response-Time Setup MA AXIAAHigh-Speed, Low-Power Voltage Comparators OUTPUT WwOlV INPUT 1OrviDIV ors/DIV OUTPUT v/DIV INPUT 10mv/DIV 5ns/DIV Figure 6. Response to SOMHz Sine Wave +1.25V VREF AAAXIMN Wy |_ UNDER MX7228 = \) vpact out ; LIMIT " VER OCTAL L > nen 8-BIT bas IN2"72 DAC | IN3 7" UNDER | oT" LIMIT Name ._ UNDER LIMIT MSB } Z D7 44 MAX901 8X8 1 | , DATA LATCH Zon UE, eae = | INS= > SL UNDER LIMIT m > Ne UNDER LIMIT oN OVER Inve t-- LIMIT VouT8 4 VDAC8 a |. OVER well LIMIT MAX901 Figure 8. Alarm Circuit Level-Monitors Eight Separate Inputs Figure 7. Response to 100MHz sine wave photo Typical Application Programmed, Variable-Alarm Limits By combining two quad analog comparators with an octal, 8-bit D/A converter (the MX7228), several alarm and limit-defect functions can be performed simulta- neously without external adjustments. The MX7228's internal latches allow the system processor to set the limit points for each comparator independently and update them at any time. Set the upper and lower thresholds for a single transducer by pairing the D/A converter and comparator sections. 11 MAXKISVI 06/Z206/106/006XUNMAX900/90 1/902/903 High-Speed, Low-Power Voltage Comparators _ Ordering Information (continued) Pin Configurations (continued) PART TEMP. RANGE PIN-PACKAGE MAX901ACPE 0C to +70C 16 Plastic DIP MAX901BCPE 0C to +70C 16 Plastic DIP MAX901ACSE OC to +70C 16 Narrow SO MAX301BCSE OC to +70C 16 Narrow SO MAX9801BC/D OC to +70C Dice* MAX901AEPE -40C to +85C 16 Plastic DIP MAX901BEPE -40C to +85C 16 Plastic DIP MAX901 AESE -40C to +85C 16 Narrow SO MAX901BESE -40C to +85C 16 Narrow SO MAX901AMJE -55C to +125C 16 CERDIP MAX901BMJE -55C to +125C 16 CERDIP MAX902CPD OC to +70C 14 Plastic DIP MAx902CSD 0C to +70C 14 Narrow SO MAx902C/D OC to +70C Dice* MAX902EPD -40C to +85C 14 Plastic DIP MAX902ESD -40C to +85C 14 Narrow SO MAX902MJD -55C to +125C 14 CERDIP MAX903CPA 0C to +70C 8 Plastic DIP MAX903CSA OC to +70C 8S0 MAX903C/D 0C to +70C Dice* MAX903EPA -40C to +85C 8 Plastic DIP MAX903ESA -40C to +85C 8SO0 MAX903MJA -55C to +125C 8 CERDIP * Contact factory for dice specifications. TOP VIEW et nea 0] IN-(0) IN (A) [2 | 19] IN+(D) Gnb [3 | . 7 [ral vec LATCH (A)[a | p [17] LATCH (0) OUT (A) LS | anexcian]16) OUT(O) our 6) [6 MAXSO0 [5] our\c) LATCH (B) a fs LATCH (C) ve*[a] A \ ZA A f13] Yoo In-6)[9H Lia] ins c) IN- (8) [ro Ha] IN- (C) DIP/SO - aNALOG V- AND SUBSTRATE "* ANALOG V+ *** DIGITAL V+ Chip Topography OUT = LATCH (0) (C) +tN(D) -IN(D) (1.73mm) -IN(A) -IN(B) +IN(A) +IN(B) GND {A) OUT ( ) LATCH (A) (B) 0.086 (2.18mm) Note: Substrate connected to VEE. MAX900/901/902/903 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 1991 Maxim Integrated Products Printed USA MAXIMA is a registered trademark of Maxim Integrated Products.