General-Purpose, −55°C to +125°C,
Wide Bandwidth, DC-Coupled VGA
Data Sheet
AD8336
Rev. F Document Feedback
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FEATURES
Low noise
Voltage noise: 3 nV/√Hz
Current noise: 3 pA/√Hz
Small-signal BW: 115 MHz
Large-signal BW: 2 V p-p = 80 MHz
Slew rate: 550 V/µs, 2 V p-p
Gain ranges (specified)
−14 dB to +46 dB
0 dB to 60 dB
Gain scaling: 50 dB/V
DC-coupled
Single-ended input and output
Supplies:
±
3 V to
±
12 V
Temperature range: −55°C to +125°C
Power
150 mW at
±
3 V, −55°C < T < +125°C
84 mW at ±3 V, PWRA = 3 V
APPLICATIONS
Industrial process controls
High performance AGC systems
I/Q signal processing
Video
Industrial and medical ultrasound
Radar receivers
GENERAL DESCRIPTION
The AD8336 is a low noise, single-ended, linear in dB, general-
purpose variable gain amplifier, usable over a large range of
supply voltages. It features an uncommitted preamplifier with a
usable gain range of 6 dB to 26 dB. The VGA gain range is 0 dB
to 60 dB, with absolute gain limits of −26 dB to +34 dB. When
the preamplifier gain is adjusted for 12 dB, the combined 3 dB
bandwidth of the preamplifier and VGA is 100 MHz, and the
amplifier is fully usable to 80 MHz. With ±5 V supplies, the
maximum output swing is 7 V p-p.
Because of the X-AMP® architecture, frequency response is
maintained across the entire gain range of the VGA. The differen-
tial gain control interface provides precise linear in dB gain scaling
of 50 dB/V over the temperature span of −55°C to +125°C and
is simple to interface with a variety of external sources.
The large supply voltage range makes the AD8336 suited for
industrial medical applications and video circuits. Dual-supply
operation enables bipolar input signals, such as those generated
by photodiodes or photomultiplier tubes.
The fully independent voltage feedback preamplifier allows both
inverting and noninverting gain topologies. The AD8336 can be
used within the specified gain range of −14 dB to +60 dB by
selecting a preamplifier gain between 6 dB and 26 dB and choosing
appropriate feedback resistors. For the nominal preamplifier gain of
4×, the overall gain range is −14 dB to +46 dB.
If required, quiescent power is limited to a safe level by
asserting the PWRA pin.
FUNCTIONAL BLOCK DIAGRAM
VOUT
VGAI
PRAO
GNEG
AD8336
VCOMVPOS GPOS
34dB
PREAMP
PWRA
ATTENUATOR
–60dB TO 0dB
GAI N CONT RO L
INTERFACE
INPP
INPN
+
–
BIAS
VNEG
4
5
2
13 3 11 12
1
10
98
06228-001
Figure 1.
AD8336 Data Sheet
Rev. F | Page 2 of 27
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Test Circuits ..................................................................................... 16
Theory of Operation ...................................................................... 20
Overview ...................................................................................... 20
Preamplifier ................................................................................. 20
VGA ............................................................................................. 20
Setting the Gain .......................................................................... 21
Noise ............................................................................................ 21
Offset Voltage .............................................................................. 21
Applications Information .............................................................. 22
Amplifier Configuration ........................................................... 22
Preamplifier ................................................................................. 22
Using the Power Adjust Feature ............................................... 23
Driving Capacitive Loads .......................................................... 23
Evaluation Board ............................................................................ 24
Optional Circuitry ...................................................................... 24
Board Layout Considerations ................................................... 24
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 27
REVISION HISTORY
11/2017—Rev. E to Rev. F
Changes to Figure 2 .......................................................................... 6
Updated Outline Dimensions ....................................................... 28
Changes to Ordering Guide .......................................................... 28
9/2016—Rev. D to Rev. E
Changes to Figure 47, Figure 48, and Figure 50 ......................... 14
Changes to Figure 51 ...................................................................... 15
5/2016—Rev. C to Rev. D
Changes to General Description Section and Figure 1 ............... 1
Changes to Figure 2 and Table 3 ..................................................... 6
Change to Overview Section ......................................................... 20
Updated Outline Dimensions ....................................................... 26
Changes to Ordering Guide .......................................................... 26
5/2011—Rev. B to Rev. C
Change to Figure 2 and Table 3 ...................................................... 6
Changes to OG ................................................................................ 26
4/2011—Rev. A to Rev. B
Change to Table 2 ............................................................................. 5
Changes to Figure 77 and Preamplifier Section ......................... 20
Changes to Evaluation Board Section, Optional Circuitry
Section, and Board Layout Considerations Section ................... 24
Added Table 6 .................................................................................. 24
Deleted Figure 83; Renumbered Figures Sequentially ............... 24
Changes to Figure 82, Figure 83, and Figure 84 ......................... 24
Changes to Figure 85, Figure 86, Figure 87, and Figure 88 ....... 25
Deleted Table 6 ................................................................................ 26
9/2008—Rev. 0 to Rev. A
Change to General Description Section ......................................... 1
Deleted Input Capacitance Parameter, Table 1 .............................. 3
Added Exposed Pad Notation to Figure 2 ...................................... 6
Changes to Figure 11 ......................................................................... 8
Changes to Figure 55 ...................................................................... 15
Change to Preamplifier Section .................................................... 20
Changes to Noise Section .............................................................. 21
Change to Circuit Configuration for Noninverting
Gain Section .................................................................................... 22
Changes to Table 5 .......................................................................... 22
Changes to Figure 89 and Table 6................................................. 26
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 27
10/2006—Revision 0: Initial Version
Data Sheet AD8336
Rev. F | Page 3 of 27
SPECIFICATIONS
VS = ±5 V, T = 25°C, gain range = −14 dB to +46 dB, preamplifier gain = 4×, f = 1 MHz, CL = 5 pF, RL = 500 Ω, PWRA = GND, unless
otherwise specified.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit1
PREAMPLIFIER
−3 dB Small-Signal Bandwidth VOUT = 10 mV p-p 150 MHz
−3 dB Large-Signal Bandwidth VOUT = 2 V p-p 85 MHz
Bias Current, Either Input 725 nA
Differential Offset Voltage ±600 μV
Input Resistance
900
kΩ
Input Capacitance 3 pF
PREAMPLIFIER + VGA
−3 dB Small-Signal Bandwidth VOUT = 10 mV p-p 115 MHz
VOUT = 10 mV p-p, PWRA = 5 V 40 MHz
VOUT = 10 mV p-p, preamplifier gain = 20× 20 MHz
VOUT = 10 mV p-p, preamplifier gain = −3× 125 MHz
−3 dB Large-Signal Bandwidth VOUT = 2 V p-p 80 MHz
OUT
30
MHz
VOUT = 2 V p-p, preamplifier gain = 20× 20 MHz
VOUT = 2 V p-p, preamplifier gain = −3× 100 MHz
Slew Rate VOUT = 2 V p-p 550 V/µs
Short-Circuit Preamplifier Input
Voltage Noise Spectral Density
±3 V ≤ VS ≤ ±12 V 3.0 nV/√Hz
Input Current Noise Spectral Density 3.0 pA/√Hz
Output-Referred Noise VGAIN = 0.7 V, preamplifier gain = 4× 600 nV/√Hz
VGAIN = −0.7 V, preamplifier gain = 4× 190 nV/√Hz
VGAIN = 0.7 V, preamplifier gain = 20× 2500 nV/√Hz
VGAIN = −0.7 V, preamplifier gain = 20× 200 nV/√Hz
GAIN
700
nV/√Hz
VGAIN = −0.7 V, −55°C ≤ T ≤ +125°C 250 nV/√Hz
DYNAMIC PERFORMANCE
Harmonic Distortion VGAIN = 0 V, VOUT = 1 V p-p
HD2 f = 1 MHz −58 dBc
HD3 f = 1 MHz −68 dBc
HD2 f = 10 MHz −60 dBc
HD3 f = 10 MHz −60 dBc
Input 1 dB Compression Point VGAIN = −0.7 V 11 dBm
VGAIN = +0.7 V −23 dBm
Two-Tone Intermodulation VGAIN = 0 V, VOUT = 1 V p-p, f1 = 0.95 MHz, f2 = 1.05 MHz −71 dBc
Distortion (IMD3) VGAIN = 0 V, VOUT = 1 V p-p, f1 = 9.95 MHz, f2 = 10.05 MHz −69 dBc
VGAIN = 0 V, VOUT = 2 V p-p, f1 = 0.95 MHz, f2 = 1.05 MHz −60 dBc
VGAIN = 0 V, VOUT = 2 V p-p, f1 = 9.95 MHz, f2 = 10.05 MHz −58 dBc
Output Third-Order Intercept
GAIN
OUT
34
dBm
VGAIN = 0 V, VOUT = 1 V p-p, f = 10 MHz 32 dBm
VGAIN = 0 V, VOUT = 2 V p-p, f = 1 MHz 34 dBm
VGAIN = 0 V, VOUT = 2 V p-p, f = 10 MHz 33 dBm
Overdrive Recovery VGAIN = 0.7 V, VIN = 100 mV p-p to 5 mV p-p 50 ns
Group Delay Variation 1 MHz < f < 10 MHz, full gain range ±1 ns
Preamplifier Gain = 20× 1 MHz < f < 10 MHz, full gain range ±3 ns
AD8336 Data Sheet
Rev. F | Page 4 of 27
Parameter Test Conditions/Comments Min Typ Max Unit1
ABSOLUTE GAIN ERROR2 −0.7 V < VGAIN < −0.6 V 0 1 to 5 6 dB
−0.6 V < VGAIN < −0.5 V 0 0.5 to 1.5 3 dB
−0.5 V < VGAIN < +0.5 V −1.25 ±0.2 +1.25 dB
−0.5 V < VGAIN < +0.5 V, ±3 V ≤ VS ≤ ±12 V ±0.5 +1.25 dB
GAIN
±0.5
dB
−0.5 V < VGAIN < +0.5 V, preamplifier gain = −3× ±0.5 dB
0.5 V < VGAIN < +0.6 V −4.0 −1.5 to −3.0 0 dB
0.6 V < VGAIN < +0.7 V −9.0 −1 to −5 0 dB
GAIN CONTROL INTERFACE
Gain Scaling Factor 48 49.9 52 dB/V
Intercept Preamplifier + VGA 16.4 dB
VGA only 4.5 dB
Gain Range 58 60 62 dB
Input Voltage (V
GAIN
) Range
−V
S
+V
S
V
Input Current 1 μA
Response Time 60 dB gain change 300 ns
OUTPUT PERFORMANCE
Output Impedance, DC to 10 MHz ±3 V ≤ VS ≤ ±12 V 2.5 Ω
Output Signal Swing RL ≥ 500 Ω (for |VS| ≤ ±5 V); RL ≥ 1 kΩ above that |VS| − 1.5 V
RL ≥ 1 kΩ (for |VS| = ±12 V) |VS| − 2.25 V
Output Current Linear operation − minimum discernable distortion 20 mA
Short-Circuit Current VS = ±3 V +123/−72 mA
VS = ±5 V +123/−72 mA
VS = ±12 V +72/−73 mA
Output Offset Voltage VGAIN = 0.7 V, gain = 200× −250 −125 +150 mV
±3 V ≤ VS ≤ ±12 V −200 mV
−55°C ≤ T ≤ +125°C −200 mV
PWRA PIN
Normal Power (Logic Low) VS = ±3 V 0.7 V
Low Power (Logic High)
S
1.5
V
Normal Power (Logic Low) VS = ±5 V 1.2 V
Low Power (Logic High) VS = ±5 V 2.0 V
Normal Power (Logic Low) VS = ±12 V 3.2 V
Low Power (Logic High) VS = ±12 V 4.0 V
POWER SUPPLY
Supply Voltage Operating Range ±3 ±12 V
Quiescent Current
VS = ±3 V 22 25 30
23 to 31
mA
PWRA = 3 V 10 14 18
VS = ±5 V 22 26 30
−55°C ≤ T ≤ +125°C 23 to 31 mA
PWRA = 5 V 10 14 18
V
S
= ±12 V
23
28
31
−55°C ≤ T ≤ +125°C 24 to 33 mA
PWRA = 5 V 16
Power Dissipation VS = ±3 V 150 mW
VS = ±5 V 260 mW
VS = ±12 V 672 mW
Power Supply Rejection Ratio (PSRR) VGAIN = 0.7 V, f = 1 MHz −40 dB
1 All dBm values are calculated with 50 Ω reference, unless otherwise noted.
2 Conformance to theoretical gain expression (see the Setting the Gain section).
Data Sheet AD8336
Rev. F | Page 5 of 27
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage (VPOS, VNEG) ±15 V
Input Voltage (INPP, INPN) VPOS, VNEG
Gain Voltage (GPOS, GNEG) VPOS, VNEG
PWRA 5 V, GND
VGAI VPOS + 0.6 V, VNEG − 0.6 V
Power Dissipation
V
S
≤ ±5 V
0.43 W
±5 V < VS ≤ ±12 V 1.12 W
Operating Temperature Range
±3 V < VS ≤ ±10 V −55°C to +125°C
±10 V < VS ≤ ±12 V −55°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering 60 sec) 300°C
Thermal Data1
θJA 58.2°C/W
θJB 35.9°C/W
θJC 9.2°C/W
ΨJT 1.1°C/W
ΨJB 34.5°C/W
1 4-layer JEDEC board, no airflow, exposed pad soldered to printed circuit board.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
AD8336 Data Sheet
Rev. F | Page 6 of 27
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. NC = NO CO NNE CT.
2. THE EX P OSE D P AD IS NO T CO NNE CTED I NTERNALLY .
FOR INCREASED RELIABILITY OF THE SOLDER
JOINTS AND M AX IMUM THERMAL CAPABIL ITY , I T IS
RECOMMENDE D THAT THE PADDLE BE S OLDE RE D
TO THE G ROUND PLANE.
VOUT
PWRA
VCOM
INPP
GNEG
VPOS
NC
NC
NC
GPOS
VNEG
VGAI
INPN
NC
NC
PRAO
1
2
3
4
11
12
10
9
5
6
7
8
15
16
14
13
06228-002
AD8336
TOP VIEW
(No t t o Scal e)
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1 VOUT Output Voltage.
2 PWRA Power Control. Normal power when grounded; power reduced by half if PWRA is pulled high.
3 VCOM Common-Mode Voltage. Normally GND when using a dual supply.
4 INPP Positive Input to Preamplifier.
5 INPN Negative Input to Preamplifier.
6 NC No Connect.
7 NC No Connect.
8 PRAO Preamplifier Output.
9 VGAI VGA Input.
10 VNEG Negative Supply.
11 GPOS Positive Gain Control Input.
12 GNEG Negative Gain Control Input.
13
VPOS
Positive Supply.
14 NC No Connect.
15 NC No Connect.
16 NC No Connect.
Not applicable EPAD The Exposed Pad is Not Connected Internally. For increased reliability of the solder joints and maximum
thermal capability, it is recommended that the paddle be soldered to the ground plane.
Data Sheet AD8336
Rev. F | Page 7 of 27
TYPICAL PERFORMANCE CHARACTERISTICS
VS = ±5 V, T = 25°C, gain range = −14 dB to +46 dB, preamplifier gain = 4×, f = 1 MHz, CL = 5 pF, RL = 500 Ω, PWRA = GND, unless
otherwise specified.
–20
40
10
0
30
50
–800
–10
V
GAIN
(mV)
–600 –400 –200 200 400 600 800
0
20
T = + 125°C
T = + 25°C
T = –55°C
GAIN (dB)
06228-003
Figure 3. Gain vs. VGAIN for Three Values of Temperature (T)
(See Figure 56)
–20
40
10
30
50
–10
0
20
GAIN (dB)
V
S
= ±12V
V
S
= ±5V
V
S
= ±3V
0–800 V
GAIN
(mV)
–600 –400 –200 200 400 600 800
06228-004
Figure 4. Gain vs. VGAIN for Three Values of Supply Voltage (VS)
(See Figure 56)
GAIN (dB)
–20
40
10
30
50
–10
0
20
60
70
PREAMP GAIN = 4×
PREAMP GAIN = 20×
0–800 V
GAIN
(mV)
–600 –400 –200 200 400 600 800
06228-005
Figure 5. Gain vs. VGAIN for Preamplifier Gains of 4× and 20×
(See Figure 56)
GAIN ERROR (dB)
–1.0
1.5
–1.5
1.0
2.0
0.5
0
–2.0
–0.5
T = + 125°C
T = + 25°C
T = –55°C
0–800 V
GAIN
(mV)
–600 –400 –200 200 400 600 800
06228-006
Figure 6. Gain Error vs. VGAIN for Three Values of Temperature (T)
(See Figure 56)
GAI N E RROR (dB)
–1.0
1.5
–1.5
1.0
2.0
0.5
0
–2.0
–0.5
V
S
= ±12V
V
S
= ±5V
V
S
= ±3V
0–800 V
GAIN
(mV)
–600 –400 –200 200 400 600 800
06228-007
Figure 7. Gain Error vs. VGAIN for Three Values of Supply Voltage (VS)
(See Figure 56)
GAI N E RROR (dB)
1.5
1.0
2.0
0.5
0
–2.0
–0.5
PR
EAMP G AIN = 20×
PREAMP GAIN = 4×
–1.0
–1.5
0–800 VGAIN (mV)
–600 –400 –200 200 400 600 800
06228-008
Figure 8. Gain Error vs. VGAIN for Preamplifier Gains of 4× and 20×
(See Figure 56)
AD8336 Data Sheet
Rev. F | Page 8 of 27
GAI N E RROR (dB)
0
PREAMP GAIN = 4×, f = 1MHz
PREAMP GAIN = 20×, f = 1MHz
PREAMP GAIN = 4×, f = 10MHz
PREAMP GAIN = 20×, f = 10MHz
0–800 V
GAIN
(mV)
–600 –400 –200 200 400 600 800
2.0
–2.0
–1.5
–1.0
–0.5
0.5
1.0
1.5
06228-009
Figure 9. Gain Error vs. VGAIN at 1 MHz and 10 MHz and
for Preamplifier Gains of 4× and 20× (See Figure 56)
GAI N E RROR (dB)
1.5
1.0
2.0
0.5
0
–2.0
–0.5
–1.0
–1.5
0–800 V
GAIN
(mV)
–600 –400 –200 200 400 600 800
PREAMP GAI N = –3× , f = 1M Hz
PREAMP GAI N = –3× , f = 10M Hz
PREAMP GAI N = –19× , f = 1M Hz
PREAMP GAI N = –19× , f = 10MHz
06228-010
Figure 10. Gain Error vs. VGAIN at 1 MHz and 10 MHz and
for Inverting Preamplifier Gains of −3× and −19× (See Figure 56)
GAI N ( dB)
–15
–15 –10 –5 0 5 10
0
–5
–10
15
35
50
45
40
COMMON-MODE VOLTAGE V
GAIN
(V)
V
S
= ±12V
V
S
= ±5V
V
S
= ±3V
06228-011
Figure 11. Gain vs. Common-Mode Voltage at VGAIN
% OF UNITS
GAI N E RROR (dB)
0
30
50
20
40
10
0.16
0.12
0.08
0.04
0
–0.12
–0.08
–0.04
60 UNIT S
VGAIN = –0.3V
VGAIN = + 0.3V
06228-012
Figure 12. Gain Error Histogram
% OF UNITS
GAIN SCALING (dB/V)
0
30
50
20
40
10
49.6 49.7 49.8 49.9 50.0 50.1 50.2
60 UNITS
–0.3V ≤ VGAIN ≤ 0.3V
06228-013
Figure 13. Gain Scaling Factor Histogram
OUTPUT OFFSET VOLTAGE (mV)
–60
–40
0
20
–20
–80
–140
–120
–100
–160
–200
–180
–220
T = + 125°C
T = + 85°C
T = + 25°C
T = –40°C
T = –55°C
VGAIN (V) 0.200.80.60.4–0.8 –0.6 –0.2–0.4
06228-014
Figure 14. Output Offset Voltage vs. VGAIN for
Various Values of Temperature (T)
Data Sheet AD8336
Rev. F | Page 9 of 27
OUTPUT OFFSET VOLTAGE (mV)
–60
–40
0
20
–20
VGAIN (V) 0.200.80.60.4
–80
–0.8
–140
–120
–100
–160
–200
–180
–0.6 –0.2–0.4
VS= ±12V
VS= ±5V
VS= ±3V
06228-015
Figure 15. Output Offset Voltage vs. VGAIN for
Three Values of Supply Voltage (VS)
OUTPUT OFFSET (mV)
0
30
20
10
SAMPLE SIZE = 60 UNITS
V
GAIN
= 0.7V
–200–240 –160 –120 –80 –40 040 80
–20–24 –16 –12 –8 –4 048
0
30
20
10
OUTPUT OFFSET (mV)
% OF UNITS
06228-016
SAMPLE SIZE = 60 UNITS
V
GAIN
= 0V
Figure 16. Output Offset Histogram
% OF UNITS
INTERCEPT (dB)
0
30
20
10
60 UNITS
16.45 16.5516.5016.4016.25 16.30 16.35
40
50
06228-017
Figure 17. Intercept Histogram
GAI N ( dB)
–10
0
10
20
40
30
50
100k
–20
FREQUENCY ( Hz ) 200M1M 100M10M
V
GAIN
= +0. 7V
+0.5V
+0.2V
0V
–0.2V
–0.5V
–30
–0.7V
06228-018
Figure 18. Frequency Response for Various Values of VGAIN
(See Figure 57)
GAI N ( dB)
–10
0
10
20
40
30
50
100k
–20
FREQUENCY ( Hz ) 200M1M 1
00M10M
V
GAIN
= +0.7V
+0.5V
+0.2V
0V
–0.2V
–0.5V
–30
–0.7V
LOW POWER MODE
06228-019
Figure 19. Frequency Response for Various Values of VGAIN, Low Power Mode
(See Figure 57)
GAI N ( dB)
–10
0
10
20
40
30
50
100k
70
FREQUENCY ( Hz )
1M 200M100M10M
V
GAIN
= +0. 7V
+0.5V
+0.2V
0V
60
PREAMP GAI N = 20×
–0.2V
–0.7V
–0.5V
06228-020
Figure 20. Frequency Response for Various Values of VGAIN
When the Preamplifier Gain is 20×
(See Figure 57)
AD8336 Data Sheet
Rev. F | Page 10 of 27
GAIN (dB)
–10
0
10
20
40
30
50
100k
–20
FREQUENCY ( Hz )
1M 200M100M10M
–30
PREAMP GAI N = –3×
V
GAIN
= +0. 7V
+0.5V
+0.2V
0V
–0.2V
–0.7V
–0.5V
06228-021
Figure 21. Frequency Response for Various Values of VGAIN
When the Preamplifier Gain is −3×
(See Figure 69 and Figure 57)
GAI N ( dB)
–10
0
10
20
15
5
25
100k FREQUENCY (Hz)
1M 200M100M10M
–5
V
GAIN
= 0V
C
L
= 47pF
C
L
= 22pF
C
L
= 10pF
C
L
= 0pF
06228-022
Figure 22. Frequency Response for Various Values of Load Capacitance (CL)
(See Figure 57)
GAI N ( dB)
–10
0
10
20
15
5
25
100k FREQUENCY ( Hz )
1M 500M100M10M
–5
30
V
S
= ±12V
V
S
= ±5V
V
S
= ±3V
GAI N = 20×
GAI N = 4×
06228-023
Figure 23. Preamplifier Frequency Response for Three Values of Supply
Voltage (VS) When the Preamplifier Gain is 4× or 20×
(See Figure 58)
GAI N ( dB)
–10
0
10
20
15
5
25
100k FREQUENCY ( Hz )
1M 500M100M10M
–5
30
GAI N = –3×
GAI N = –19×
VS = ±12V
VS = ±5V
VS = ±3V
06228-024
Figure 24. Preamplifier Frequency Response for Three Values of Supply
Voltage (VS) When the Inverting Gain Value is −3× or −19×
(See Figure 69)
GRO UP DE LAY ( ns)
0
10
20
15
5
FREQUENCY ( Hz )
1M 100M10M
PREAM P GAI N = 20×
PREAM P GAI N = 4×
06228-025
Figure 25. Group Delay vs. Frequency for Preamplifier Gains of 4× and 20×
(See Figure 59)
OUTPUT RESISTANCE (Ω)
0.1
1
100
1k
10
FREQUENCY ( Hz )
0.01 1M 500M100M10M
100k
06228-026
Figure 26. Output Resistance vs. Frequency of the Preamplifier
(See Figure 61)
Data Sheet AD8336
Rev. F | Page 11 of 27
OUTPUT RESISTANCE (Ω)
0.1
1
100
1k
10
FREQUENCY ( Hz )
1M 500M100M10M
0.01
100k
VS = ±12V
VS = ±5V
VS = ±3V
06228-027
Figure 27. Output Resistance vs. Frequency of the VGA
for Three Values of Supply Voltage (VS)
(See Figure 61)
OUTPUT-REFERRED NOISE (nV/
√Hz
)
0
100
–800 V
GAIN
(mV)
–600 –200–400 400 600200 800
0
1000
900
800
700
600
500
400
300
200 T = + 125°C
T = + 85°C
T = + 25°C
T = –40°C
T = –55°C
f = 5MHz
06228-028
Figure 28. Output-Referred Noise vs. VGAIN at Various Temperatures (T)
(See Figure 62)
0–800 VGAIN (mV)
–600 –200–400 400 600200 800
OUTPUT-REFERRED NOISE (nV/
√Hz
)
300
0
3000
2700
2400
2100
1800
1500
1200
900
600
f = 5MHz
PREAMP GAI N = 20×
T = + 125°C
T = + 85°C
T = + 25°C
T = –40°C
T = –55°C
06228-029
Figure 29. Output-Referred Noise vs. VGAIN at Various Temperatures (T)
When the Preamplifier Gain is 20×
(See Figure 62)
0–800 V
GAIN
(mV)
–600 –200–400 400 600200 800
INPUT-REFERRED NOISE (nV/√Hz)
1k
100
10
1
PREAMP G AIN = 4×
PREAMP G AIN = 20×
f = 5M Hz
06228-030
Figure 30. Input-Referred Noise vs. VGAIN for Preamplifier Gains of 4× and 20×
(See Figure 62)
INPUT-REFERRED NO I SE (n V/
√Hz
)
2
3
5
6
100k
4
FREQUENCY ( Hz )
1M 100M10M
0
1
VGAIN =
0.7V
VS = ±12V
VS = ±5V
VS = ±3V
06228-031
Figure 31. Short-Circuit Input-Referred Noise vs. Frequency at Maximum
Gain for Three Values of Supply Voltage (VS)
(See Figure 62)
2
3
5
6
100k
4
FREQUENCY ( Hz )
1M 100M10M
INPUT-REFERRED NO I SE (n V/
√Hz)
0
1
VGAIN = 0.7V
PREAMP GAI N = –3×
06228-032
Figure 32. Short-Circuit Input-Referred Noise vs. Frequency
at Maximum Inverting Gain
(See Figure 73)
AD8336 Data Sheet
Rev. F | Page 12 of 27
10k10
1
0.1 100 1k
SOURCE RESISTANCE (Ω)
10
INPUT-REFERRED NOISE (nV/√Hz)
INPUT-RE FERRE D NOIS E
100
V
GAIN = 0.7V
R
S
THERMAL NOISE ALONE
06228-033
Figure 33. Input-Referred Noise vs. Source Resistance
(See Figure 72)
NOISE FIGURE (dB)
40
0
20
50
–800 –600 –200–400 400 600200 800
30
0
10
60
SIMULATED
DATA
UNTERMINATED
70
V
GAIN
(mV)
f = 10M Hz
50Ω SOURCE
06228-034
Figure 34. Noise Figure vs. VGAIN
(See Figure 63)
HARMONIC DI S TO RTION (dBc)
–40
1.0k
–50
0
LOAD RESISTANCE (Ω)
200 1.6k400 1.4k600 1.2k800
–60
–65
–70 1.8k 2.0k 2.2k
–45
–55
HD3
HD2
VOUT = 2V p-p
VGAIN = 0V
f = 5M Hz
06228-035
Figure 35. Harmonic Distortion vs. Load Resistance
(See Figure 64)
HARMO NI C DISTO RTION (dBc)
–40
25
–50
0LO AD CAP ACIT ANCE ( pF )
54010 3515 3020
–60
HD3
–65
–70 45 50
HD2
–45
–55
V
OUT
= 2V p-p
V
GAIN
= 0V
f = 5MHz
06228-036
Figure 36. Harmonic Distortion vs. Load Capacitance
(See Figure 64)
HARMO NIC DISTORTION (dBc)
–30
400
–50
VGAIN (mV)
–600 800–400 600–200 2000
–60
–80
–70
–40
–20 OUTPUT SWING OF PREAMP
LIMITS VGAIN TO –400mV
HD2 AT 1MHz
HD2 AT 10MHz
HD3 AT 1MHz
HD3 AT 10MHz
VOUT = 1V p-p
06228-037
Figure 37. Second and Third Harmonic Distortion vs. VGAIN at 1 MHz and 10 MHz
(See Figure 64)
HARMO NI C DISTO RTION (dBc)
–30
–50
–60
–80
–70
–40
–20
400
VGAIN (mV)
–600 800–400 600–200 2000
OUTPUT SWING OF PREAMP LIMITS
VGAIN LEVEL S
VOUT = 0. 5V p-p
VOUT = 1V p-p
VOUT = 2V p-p
VOUT = 4V p-p
HD2
f = 5M Hz
06228-038
Figure 38. Second Harmonic Distortion vs. VGAIN
for Four Values of Output Voltage (VOUT)
(See Figure 64)
Data Sheet AD8336
Rev. F | Page 13 of 27
HARMO NI C DISTO RTION (dBc)
–30
–50
–60
–80
–70
–40
–20
V
OUT
= 0.5V p-p
V
OUT
= 1V p-p
V
OUT
= 2V p-p
V
OUT
= 4V p-p
OUTPUT SWING OF PREAMP LIMITS
MINIMUM US ABLE V
GAIN
LEVELS
HD3
f = 5MHz
400
V
GAIN
(mV)
–600 800–400 600–200 2000
06228-039
Figure 39. Third Harmonic Distortion vs. VGAIN
for Four Values of Output Voltage (VOUT)
(See Figure 64)
HARMO NI C DISTO RTION (dBc)
–60
–50
–20
–30
1M
–70
FREQUENCY ( Hz )
10M
–40
50M
HD2
HD3
V
OUT
= 2V p-p
V
GAIN
= 0V
06228-040
Figure 40. Harmonic Distortion vs. Frequency
(See Figure 64)
IMD3 (dBc)
–80
–60
–50
–20
–30
1M
–70
FREQUENCY ( Hz )
10M
–40
100M
0
–90
–10
VOUT = 1V p-p
VGAIN = 0V
TO NE S S E P ARATED BY 100kHz
06228-041
Figure 41. IMD3 vs. Frequency
(see Figure 76)
OUT P UT I P 3 ( dBm)
25
200
30
–800 V
GAIN
(mV)
–600 800–400 600–200 4000
20
0
10
40
5
15
35
1MHz 500mV
1MHz 1V
10MHz 500mV
10MHz 1V
V
OUT
= 1V p-p
V
GAIN
= 0V
COM POSIT E INPUT S S E P ARATED BY 100kHz
06228-042
Figure 42. Output-Referred IP3 (OIP3) vs. VGAIN
at Two Frequencies and Two Input Levels
(see Figure 76)
200–800 V
GAIN
(mV)
–600 800–400 600–200 4000
IP1dB (dBm)
0
–30
–10
10
30
20
–20
V
S
= ±5V
V
S
= ±3V
V
S
= ±12V INPUT LEVEL LIMITED
BY GAIN O F PRE AM P
06228-043
Figure 43. Input P1dB (IP1dB) vs. VGAIN at Three Power Supply Values (VS)
(see Figure 74 and Figure 75)
VOLTAGE (V)
300–100 TIME (ns)
100 2000
–1
2
0
1
3
–2
–3
V
IN
(V)
V
OUT
(V)
06228-044
Figure 44. Large-Signal Pulse Response of the Preamplifier
(See Figure 65)
AD8336 Data Sheet
Rev. F | Page 14 of 27
VOUT (mV)
–60
–20
20
0
40
–100
–40
–50 150100 25050 300200 350
VIN (mV)
–0.6
0
–0.2
0.2
0.4
–0.4
0
0.6
60
INPUT
OUT P UT W HE N P WRA = 0
OUT P UT W HE N P WRA = 1
VGAIN = 0.7V
TIME (ns)
06228-045
Figure 45. Noninverting Small-Signal Pulse Response for Both Power Levels
(See Figure 65)
V
GAIN
= 0.7V
PREAMP GAI N = –3×
INPUT
OUTPUT
V
OUT
(mV)
–60
–20
20
0
40
–100
–40
TIME (ns)
–50 150100 25050 300200 350
V
IN
(mV)
–0.6
0
–0.2
0.2
0.4
–0.4
0
0.6
60
06228-046
Figure 46. Inverting Gain Small-Signal Pulse Response
(See Figure 70)
–2.0
–1.0
0
2.0
1.5
–1.5–15
0
–20
20
10
15
–10
1.0
2.5
–2.5–25
25
5
–5 –0.5
0.5
INPUT
OUT P UT W HE N P WRA = 0
OUT P UT W HE N P WRA = 1
V
OUT
(V)
0–100 TI ME (n s)
–50 150100 25050 300200 350
V
GAIN
= 0.7V
06228-047
V
IN
(mV)
Figure 47. Large-Signal Pulse Response for Both Power Levels
(See Figure 65)
–15
0
–20
20
10
15
–10
–25
25
5
–5
–1.5
0
–2.0
2.0
1.0
1.5
–1.0
–2.5
2.5
0.5
–0.5
INPUT
OUTPUT
0–100 TIME (ns)
–50 150100 25050 300200 350
V
OUT
(V)
V
GAIN
= 0.7V
PREAM P GAI N = –3×
06228-048
V
IN
(mV)
Figure 48. Inverting Gain Large-Signal Pulse Response
(See Figure 70)
V
OUT
(V)
–2.0
–1.0
0
0
2.0
1.5
–100
–1.5
TIME (ns)
–50 20015010050 300250
V
IN
(mV)
–15
0
–20
20
10
15
–10
1.0
350
5
–5 –0.5
0.5
400
V
GAIN
= 0.7V
V
S
= ±3V
06228-049
INPUT
C
L
= 0pF
C
L
= 10pF
C
L
= 22pF
C
L
= 47pF
Figure 49. Large-Signal Pulse Response for Various Values of Load
Capacitance Using ±3 V Power Supplies
(See Figure 65)
V
GAIN
= 0.7V
V
S
= ±5V
*WITH 20Ω RESISTOR IN SERIES WITH OUTPUT.
0–100 TIME (ns)
–50 150100 25050 300200 350
V
OUT
(V)
–3
–1
1
2
–2
0
3
–30
–10
10
20
–20
0
30
06228-050
INPUT
C
L
= 0pF
C
L
= 10pF*
C
L
= 22pF*
C
L
= 47pF*
V
IN
(mV)
Figure 50. Large-Signal Pulse Response for Various Values of Load
Capacitance Using ±5 V Power Supplies
(See Figure 65)
Data Sheet AD8336
Rev. F | Page 15 of 27
VGAIN = 0.7V
VS = ±12V
VIN (mV)
0–100 TI ME (n s)
–50 150100 25050 300200 350
VOUT (V)
*WITH 20Ω RESISTOR IN SERIES WITH OUTPUT
INPUT
CL = 0pF
CL = 10pF *
CL = 22pF *
CL = 47pF *
06228-051
Figure 51. Large-Signal Pulse Response for Various Values of Load
Capacitance Using ±12 V Power Supplies
(See Figure 65)
06228-052
VOLTAGE (V)
2.5
2.0
1.5
TIME (µs)
01.51.0
0.5
–2.5
V
GAIN
V
OUT
–0.5
–0.5 0.5
–1.5
Figure 52. Gain Response
(See Figure 66)
INPUT VOLTAGE (V)
–6–9 TIME (µs)
–3 30 6
OUTPUT VOLTAGE (V)
–1
2
0
5
4
1
3
–2
–5
–4
–3
–0.1
0.2
0.5
0.4
0.1
0.3
–0.2
–0.5
–0.4
–0.3
VIN (V)
VOUT (V)
VGAIN = 0.7V
0
06228-053
Figure 53. VGA Overdrive Recovery
(See Figure 67)
–60
–50
–30
–20
100k
–40
FRE Q UE NCY ( Hz )
1M 5M
PSRR (dB)
–10
0
10 VPOS
PSRR
VNEG VGAIN = 0.7V
VGAIN = 0V
VGAIN = –0.7V
06228-054
Figure 54. PSRR vs. Frequency for Three Values of VGAIN
(See Figure 71)
QUI E S CE NT SUP P LY CURRENT (mA)
0–25
40
30
–65
10
TEMPERATURE (°C)
–45 15–5 35 55
20
75 95 115 135
LOW POWER
HIGH POWER
V
S
= ±12V
V
S
= ±5V
V
S
= ±3V
06228-055
Figure 55. IQ vs. Temperature for Three Values of Supply Voltage
and High and Low Power
(See Figure 68)
AD8336 Data Sheet
Rev. F | Page 16 of 27
TEST CIRCUITS
NETWORK AN
A
LYZE
R
50Ω
INOUT
453Ω
100Ω
301Ω
49.9Ω
50Ω
V
GAIN
AD8336
4
5
118
1
129
06228-056
+
–
PREAMP
Figure 56. Gain vs. VGAIN and Gain Error vs. VGAIN
NETWORK AN
A
LYZE
R
100Ω
301Ω
49.9Ω
50Ω
INOUT
453Ω
OPTIONAL
C
L
50Ω
115
1
128
AD8336
V
GAIN
06228-057
+
–
PREAMP
4
5
Figure 57. Frequency Response
NETWORK ANALYZER
100Ω
301Ω
49.9Ω
50Ω
INOUT
50Ω
453ΩNC
NC 453Ω
4
5
118
1
129
AD8336
06228-058
NC = NO CONNECT
+
–
PREAMP
Figure 58. Frequency Response of the Preamplifier
NETWORK ANALYZER
100Ω
301Ω
49.9Ω
50Ω
INOUT
50Ω
453Ω
4
5
118
1
129
AD8336
06228-059
+
–
PREAMP
Figure 59. Group Delay
100Ω
301Ω
453Ω50Ω
DMM
4
5
118
1
129
+
¯
AD8336
06228-060
+
–
PREAMP
Figure 60. Offset Voltage
NETWORK ANALYZER
0Ω
0Ω
100Ω
301Ω
49.9Ω
50Ω
IN
NC
NC
4
5
118
1
129
AD8336
06228-061
NC = NO CONNECT
CONFIGURE TO
MEASURE
Z-CONVERTED S22
+
–
PREAMP
Figure 61. Output Resistance vs. Frequency
Data Sheet AD8336
Rev. F | Page 17 of 27
100Ω
SPECTRUM ANALYZER
301Ω
IN
50Ω
5
118
1
129
4
AD8336
V
GAIN
06228-062
+
–
PREAMP
Figure 62. Input-Referred Noise and Output-Referred Noise
NOISE FIG URE METER
100Ω
1
301Ω
49.9Ω
(OR ∞)
INPUT
0Ω
0Ω
NOISE
SOURCE
DRIVE
NOISE
SOURCE
4
5
11
8
1
12
9
AD8336
V
GAIN
06228-063
+
–
PREAMP
Figure 63. Noise Figure vs. VGAIN
SPECTRUM ANALYZER
100Ω
301Ω
49.9Ω
INPUT
LOW-PASS
FILTER
C
L
50Ω
R
L
4
5
11
8
1
129
SIGNAL
GENERATOR
AD8336
V
GAIN
06228-064
+
–
PREAMP
Figure 64. Harmonic Distortion
OSCILLOSCOPE
301Ω
CH2
50Ω
OUT
50Ω
CH1
PULSE
GENERATOR
49.9Ω
20Ω 453Ω
0.7V
POWER
SPLITTER
100Ω
4
5
11
8
1
129
OPTIONAL
AD8336
06228-065
+
–
PREAMP
Figure 65. Pulse Response
OSCILLOSCOPE
100Ω
301Ω
CH2
50Ω
SQUARE
WAVE 50Ω
CH1
FUNCTION
GENERATOR
49.9Ω NC
NC = NO CONNECT
POWER
SPLITTER
DIFFERENTIAL
FET PROBE
4
5
8
1
12
9
11
453Ω
SINE
WAVE
PULSE
GENERATOR
AD8336
06228-066
+
–
PREAMP
Figure 66. Gain Response
OSCILLOSCOPE
100Ω
301Ω
CH2
50Ω
CH1
49.9Ω
POWER
SPLITTER 50Ω
453Ω NC
4
5
11
8
1
129
–20dB
ARBITRARY
WAVEFORM
GENERATOR
0.7V
AD8336
06228-067
NC = NO CONNECT
+
–
PREAMP
Figure 67. VGA Overdrive Recovery
AD8336 Data Sheet
Rev. F | Page 18 of 27
100Ω
301Ω
DMM
(+I)
DMM
(–I)
AD8336
4
5
11
8
1
12 10
13
9
06228-068
+
–
PREAMP
Figure 68. Supply Current
NETWO RK ANALYZER
100Ω
301Ω
100Ω
50Ω
INOUT
453Ω
50Ω
V
GAIN
AD8336
4
118
1
129
5
49.9Ω
06228-069
+
–
PREAMP
Figure 69. Frequency Response, Inverting Gain
OSCILLOSCOPE
100Ω
301Ω
CH2
50Ω
OUT
50Ω
CH1
PULSE
GENERATOR
100Ω
453Ω
0.7V
POWER
SPLITTER
AD8336
4
5
11
8
1
12
9
49.9Ω
06228-070
+
–
PREAMP
Figure 70. Pulse Response, Inverting Gain
V
GAIN
NET WORK ANALYZER
100Ω
301Ω
49.9Ω
50Ω
INOUT
BY
PASS
CAPACITORS
REMOVED FOR
MEASUREMENT
50Ω
DIFFERENTIAL
FET PROBE
BENCH
POWER SUPPLY
VPOS OR VNEG
POWER SUPPLIES
CONNECTED TO
NET WORK ANALYZER
BIAS P ORT
AD8336
11
8
1
12
9
06228-071
+
–
PREAMP
4
5
Figure 71. PSRR
SPECTRUM ANALYZER
100Ω
301Ω
0.7V
IN
50Ω
AD8336
4
5
118
1
12
9
06228-072
+
–
PREAMP
Figure 72. Input-Referred Noise vs. Source Resistance
SPECTRUM ANALYZER
100Ω
301Ω
0.7V
IN
50Ω
AD8336
4
5
11
8
1
12
9
06228-073
+
–
PREAMP
Figure 73. Short-Circuit Input-Referred Noise vs. Frequency
Data Sheet AD8336
Rev. F | Page 19 of 27
SIGNAL
GENERATOR
100Ω
301Ω
49.9Ω
50Ω
OUT
453Ω
22dB
AD8336
4
5
118
1
12
9
IN
50Ω
SPECTRUM
ANALYZER
OPTIONAL 20dB
ATTENUATOR
V
GAIN
06228-074
+
–
PREAMP
Figure 74. IP1dB vs. VGAIN
SIGNAL
GENERATOR
100Ω
301Ω
49.9Ω
50Ω
OUT
453Ω
AD8336 DUT
4
118
1
129
5
IN
50Ω
SPECTRUM
ANALYZER
–20dB
AD8336 AMPLIFIER
4
5
118
1
129
100Ω
301Ω
0Ω
0.7V V
GAIN
06228-075
+
–
PREAMP+
–
PREAMP
Figure 75. IP1dB vs. VGAIN, High Signal Level Inputs
SPECTRUM ANALYZER
100Ω
49.9Ω
INPUT
453Ω
50Ω
SIGNAL
GENERATOR
SIGNAL
GENERATOR
+22dB
+22dB –6dB
–6dB
COMBINER
–6dB
AD8336 DUT
4
118
1
129
5
301Ω
V
GAIN
06228-076
+
–
PREAMP
Figure 76. IMD and OIP3
AD8336 Data Sheet
Rev. F | Page 20 of 27
THEORY OF OPERATION
OVERVIEW
The AD8336 is the first VGA designed for operation over
exceptionally broad ranges of temperature and supply voltage.
The performance has been characterized from temperatures
extending from −55°C to +125°C, and supply voltages from ±3 V
to ±12 V. It is ideal for applications requiring dc coupling, large
output voltage swings, very large gain ranges, extreme temperature
variations, or a combination thereof.
The simplified block diagram is shown in Figure 77. The
AD8336 includes a voltage feedback preamplifier, an amplifier
with a fixed gain of 34 dB, a 60 dB attenuator, and various bias
and interface circuitry. The independent voltage feedback
operational amplifier can be used in noninverting and inverting
configurations and functions as a preamplifier to the variable gain
amplifier (VGA). If desired, the preamplifier output (PRAO)
and VGA input (VGAI) pins provide for connection of an
interstage filter to eliminate noise and offset. The bandwidth of
the AD8336 is dc to 100 MHz with a gain range of 60 dB (−14 dB
to +46 dB).
For applications that require large supply voltages, a reduction
in power is advantageous. The power reduction pin (PWRA)
permits the power and bandwidth to be reduced by about half
in such applications.
VOUT
VGAI
PRAO
GNEG VCOMVPOS GPOS
PWRA
–60dB TO 0dB
ATTENUATOR
AND GAIN
CONTROL
INT ERFACE
BIAS
VNEG
INPP
INPN
R
FB2
301Ω
4.48kΩ
+
_
*
34dB
12dB
91.43Ω
*OPTIO NAL DEPEAKING CAPACITO R. SEE TEXT .
06228-077
R
FB1
100Ω
1.28kΩ
+
–
PREAMP
Figure 77. Simplified Block Diagram
To maintain low noise, the output stages of both the preamplifier
and the VGA are capable of driving relatively small load resistances.
However, at the largest supply voltages, the signal current can
exceed safe operating limits for the amplifiers and, therefore,
the load current must not exceed 50 mA. With a ±12 V supply
and ±10 V output voltage at the preamplifier or VGA output,
load resistances as low as 200 Ω are acceptable.
For power supply voltages ≥ ±10 V, the maximum operating
temperature range is derated to +85°C because the power can
exceed safe limits (see the Absolute Maximum Ratings section).
Because harmonic distortion products can increase for various
combinations of low impedance loads and high output voltage
swings, it is recommended that the user determine load and
drive conditions empirically.
PREAMPLIFIER
The gain of the uncommitted voltage feedback preamplifier is set
with external resistors. The combined preamplifier and VGA gain
is specified in two ranges: −14 dB to +46 dB and 0 dB to 60 dB.
Since the VGA gain is fixed at 34 dB (50×), the preamplifier
gain is adjusted for gains of 12 dB (4×) and 26 dB (200×).
With low preamplifier gains between 2× and 4×, it can be desirable
to reduce the high frequency gain with a shunt capacitor across
RFB2 to ameliorate peaking in the frequency domain (see Figure 77).
To maintain stability, the gain of the preamplifier must be 6 dB
(2×) or greater.
Typical of voltage feedback amplifier configurations, the gain-
bandwidth product of the AD8336 is fixed (at 600); therefore,
the bandwidth decreases as the gain is increased beyond the
nominal gain value of 4×. For example, if the preamplifier gain
is increased to 20×, the bandwidth reduces by a factor of 5 to
about 20 MHz. The −3 dB bandwidth of the preamplifier with a
gain of 4× is about 150 MHz, and for the 20× gain is about 30 MHz.
The preamplifier gain diminishes for an amplifier configured
for inverting gain, using the same value of feedback resistors as for
a noninverting amplifier, but the bandwidth remains unchanged.
For example, if the noninverting gain is 4×, the inverting gain is
−3×, but the bandwidth stays the same as in the noninverting gain
of 4×. However, because the output-referred noise of the
preamplifier is the same in both cases, the input-referred noise
increases as the ratio of the two gain values increases. For the
previous example, the input-referred noise increases by a factor
of 4/3.
The output swing of the preamplifier is the same as for the VGA.
VGA
The architecture of the variable gain amplifier (VGA) section
of the AD8336 is based on the Analog Devices, Inc., X-AMP
(exponential amplifier), found in a wide variety of Analog Devices
variable gain amplifiers. This type of VGA combines a ladder
attenuator and interpolator, followed by a fixed-gain amplifier.
The gain control interface is fully differential, permitting positive
or negative gain slopes. Note that the common-mode voltage of
the gain control inputs increases with increasing supply.
The gain slope is 50 dB/V and the intercept is 16.4 dB when the
nominal preamplifier gain is 4× (12 dB). The intercept changes
with the preamplifier gain; for example, when the preamplifier
gain is set to 20× (26 dB), the intercept becomes 30.4 dB.
Pin VGAI is connected to the input of the ladder attenuator.
The ladder ratio is R/2R and the nominal resistance is 320 Ω. To
reduce preamplifier loading and large-signal dissipation, the
input resistance at Pin VGAI is 1.28 kΩ. Safe current density
and power dissipation levels are maintained even when large dc
signals are applied to the ladder.
Data Sheet AD8336
Rev. F | Page 21 of 27
The tap resistance of the resistors within the R/2R ladder is
640 Ω/3, or 213.3 Ω, and is the Johnson noise source of the
attenuator.
SETTING THE GAIN
The overall gain of the AD8336 is the sum (in decibels) or the
product (magnitude) of the preamplifier gain and the VGA gain.
The preamplifier gain is calculated as with any operational
amplifier, as seen in the Applications Information section. It is
most convenient to think of the device gain in exponential terms
(that is, in decibels) since the VGA responds linearly in decibels
with changes in control voltage VGAIN at the gain pins.
The gain equation for the VGA is
dB4.4
V
dB50
(V)(dB)
GAIN
VGainVGA
where VGAIN = VGPOS − VGNEG.
The gain and gain range of the VGA are both fixed at 34 dB and
60 dB, respectively; thus, the composite device gain is changed by
adjusting the preamplifier gain. For a preamplifier gain of 12 dB
(4×), the composite gain is −14 dB to +46 dB. erefore, the
calculation for the composite gain (in decibels) is
Composite Gain = GPRA + [VGAIN (V) × 49.9 dB/V] + 4.4 dB
For example, the midpoint gain when the preamplifier gain is
12 dB is
12 dB + [0 V × 49.9 dB/V] + 4.4 dB = 16.4 dB
Figure 3 is a plot of gain in decibels vs. VGAIN in millivolts, when
the preamplifier gain is 12 dB (4×). Note that the computed
result closely matches the plot of actual gain.
In Figure 3, the gain slope flattens at the limits of the VGAIN
input. The gain response is linear in dB over the center 80% of
the control range of the device. Figure 78 shows the ideal gain
characteristics for the VGA stage gain, the composite gain, and
the preamplifier gain.
GAIN (dB)
40
50
V
GAIN
(V)
30
10
0
20
–10
60
70
FOR PREAMP GAIN = 26dB
–30
–20
FOR PREAMP GAIN = 6dB
GAIN CHARACTERISTICS
COMPOSITE GAIN
VGA STAGE GAIN
USABLE GAIN RANGE OF
AD8336
FOR PREAMP GAIN = 12dB
0.5 0.70.30.1–0.1–0.3–0.5–0.7
06228-078
Figure 78. Ideal Gain Characteristics of the AD8336
NOISE
The noise of the AD8336 is dependent on the value of the VGA
gain. At maximum VGAIN, the dominant noise source is the
preamplifier, but it shifts to the VGA as VGAIN diminishes.
The input-referred noise at the highest VGA gain and a
preamplifier gain of 4×, with RFB1 = 100 Ω and RFB2 = 301 Ω, is
3 nV/Hz and is determined by the preamplifier and the gain
setting resistors. See Table 4 for the noise components for the
preamplifier.
Table 4. AD8336 Noise Components for Preamplifier Gain = 4×
Noise Component Noise Voltage (nV/√Hz)
Op Amp (Gain = 4×) 2.6
RFB1 = 100 Ω 0.96
RFB2 = 301 Ω 0.55
VGA 0.77
Using the values listed in Table 4, the total noise of the AD8336
is slightly less than 3 nV/Hz, referred to the input. Although
the input noise referred to the VGA is 3.1 nV/Hz, the input-
referred noise at the preamplifier is 0.77 nV/Hz when divided
by the preamplifier gain of 4×.
At other than maximum gain, the noise of the VGA is
determined from the output noise. The noise in the center of
the gain range is about 150 nV/Hz. Because the gain of the
fixed-gain amplifier that is part of the VGA is 50×, the VGA
input-referred noise is approximately 3 nV/Hz, the same value
as the preamplifier and VGA combined. This is expected since
the input-referred noise is the same at the input of the attenuator at
maximum gain. However, the noise referred to the VGAI pin (the
preamplifier output) increases by the amount of attenuation
through the ladder network. The noise at any point along the
ladder network is primarily composed of the ladder resistance
noise, the noise of the input devices, and the feedback resistor
network noise. The ladder network and the input devices are
the largest noise sources.
At minimum gain, the output noise increases slightly to about
180 nV/Hz because of the finite structure of the X-AMP.
OFFSET VOLTAGE
Extensive cancellation circuitry included in the variable gain
amplifier section minimizes locally generated offset voltages.
However, when operated at very large values of gain, dc voltage
errors at the output can still result from small dc input voltages.
When configured for the nominal gain range of −14 dB to +46 dB,
the maximum gain is 200× and an offset of only 100 μV at the
input generates 20 mV at the output.
The primary source for dc offset errors is the preamplifier;
ac coupling between the PRAO and VGAI pins is the simplest
solution. In applications where dc coupling is essential, a comp-
ensating current can be injected at the INPN input (Pin 5) to
cancel preamplifier offset. The direction of the compensating
current depends on the polarity of the offset voltage.
AD8336 Data Sheet
Rev. F | Page 22 of 27
APPLICATIONS INFORMATION
AMPLIFIER CONFIGURATION
The AD8336 amplifiers can be configured in various options. In
addition to the 60 dB gain range variable gain stage, an uncommit-
ted voltage gain amplifier is available to the user as a preamplifier.
The preamplifier connections are separate to enable noninverting
or inverting gain configurations or the use of interstage filtering.
The AD8336 can be used as a cascade connected VGA with pre-
amp input, as a standalone VGA, or as a standalone preamplifier.
This section describes some of the possible applications.
VOUT
V
GAI
2
13
PRAO
1
GNEG
AD8336
3
VCOMVPOS
9
GPOS
8
34dB
PWRA
ATTENUATOR
–60dB TO 0dB
12
GAIN CONTROL
INTERFACE
11
INPP 4
5
INPN
BIAS
10
VNEG
06228-079
+
–
PREAMP
Figure 79. Application Block Diagram
PREAMPLIFIER
While observing just a few constraints, the uncommitted voltage
feedback preamplifier of the AD8336 can be connected in a variety
of standard high frequency operational amplifier configurations.
The amplifier is optimized for a gain of 4× (12 dB) and has a gain
bandwidth product of 600 MHz. At a gain of 4×, the bandwidth
is 150 MHz. The preamplifier gain can be adjusted to a minimum
gain of 2×; however, there will be a small peak in the response at
high frequencies. At higher preamplifier gains, the bandwidth
diminishes proportionally in conformance to the classical voltage
gain amplifier GBW relationship.
While setting the overall gain of the AD8336, the user must
consider the input-referred offset voltage of the preamplifier.
Although the offset of the attenuator and postamplifier are
almost negligible, the preamplifier offset voltage, if uncorrected,
is increased by the combined gain of the preamplifier and post-
amplifier. Therefore, for a maximum gain of 60 dB, an input offset
voltage of only 200 μV results in an error of 200 mV at the output.
Circuit Configuration for Noninverting Gain
The noninverting configuration is shown in Figure 80. The
preamplifier gain is described by the classical operational
amplifier gain equation:
1
1
2
FB
FB
R
R
Gain
The practical gain limits for this amplifier are 6 dB to 26 dB.
The gain bandwidth product is about 600 MHz, so at 150 MHz,
the maximum achievable gain is 12 dB (4×). The minimum gain
is established internally by fixed loop compensation and is 6 dB
(2×). This amplifier is not designed for unity-gain operation.
Table 5 shows the gain and bandwidth for the noninverting gain
configuration.
PRAO
34dB
AD8336
PREAMPLIFIER
–60dB TO 0dB
INPP
4
5
INPN
9
GAIN = 12dB
R
FB1
100Ω
VGAI
13
VPOSVNEG
10
+5V
–5V
PWRA
2 3
VCOM
8
R
FB2
301Ω
VOUT
1
06228-080
Figure 80. Circuit Configuration for Noninverting Gain
The preamplifier output reliably sources and sinks currents up
to 50 mA. When using ±5 V power supplies, the suggested sum
of the output resistor values is 400 Ω total for the optimal trade-
off between distortion and noise. Much of the low gain value
device characterization was performed with resistor values of
301 Ω and 100 Ω, resulting in a preamplifier gain of 12 dB (4×).
With supply voltages between ±5 V and ±12 V, the sum of the
output resistance must be increased accordingly; a total
resistance of 1 kΩ is recommended. Larger resistance values,
subject to a trade-off in higher noise performance, can be used
if circuit power and load driving is an issue. When considering
the total power dissipation, remember that the input ladder
resistance of the VGA is part of the preamplifier load.
Table 5. Gain and Bandwidth for Noninverting Preamplifier
Configuration
Preamplifier Gain Preamplifier
BW (MHz)
Composite
Gain (dB)
Numerical dB
4× 12 150 −14 to +46
8× 18 60 −8 to +52
16× 24 30 −2 to +58
20× 26 25 0 to +60
Data Sheet AD8336
Rev. F | Page 23 of 27
Circuit Configuration for Inverting Gain
The preamplifier can also be used in an inverting configuration,
as shown in Figure 81.
PRAO
34dB
AD8336
PREAMPLIFIER
INPP
4
5
+
–
8
9
GAIN = 9.6dB INPN
R
FB1
100Ω
R
FB2
301Ω
13
VPOSVNEG
10
VOUT
1
+5V
–5V
PWRAVGAI
2 3
VCOM
–60dB TO 0dB
06228-081
Figure 81. Circuit Configuration for Inverting Gain
The considerations regarding total resistance vs. distortion, noise,
and power that were noted in the noninverting case also apply
in the inverting case, except that the amplifier can be operated
at unity inverting gain. The signal gain is reduced while the
noise gain is the same as for the noninverting configuration:
FB1
FB2
R
R
GainSignal
and
1
FB1
FB2
R
R
GainNoise
USING THE POWER ADJUST FEATURE
The AD8336 has the provision to operate at lower power with a
trade-off in bandwidth. The power reduction applies to the
preamplifier and the VGA sections, and the bandwidth is reduced
equally between them. Reducing the power is particularly useful
when operating with higher supply voltages and lower values of
output loading that otherwise stresses the output amplifiers. When
Pin PWRA is grounded, the amplifiers operate in their default
mode, and the combined 3 dB bandwidth is 80 MHz with the
preamplifier gain adjusted to 4×. When the voltage on Pin PWRA
is between 1.2 V and 5 V, the power is reduced by approximately
half and the 3 dB bandwidth reduces to approximately 35 MHz.
The voltage at Pin PWRA must not exceed 5 V.
DRIVING CAPACITIVE LOADS
The output stages of the AD8336 are stable with capacitive loads
up to 47 pF for a supply voltage of ±3 V and with capacitive loads
up to 10 pF for supply voltages up to ±8 V. For larger combined
values of load capacitance and/or supply voltage, a 20 Ω series
resistor is recommended for stability.
The influence of capacitance and supply voltage are shown in
Figure 50 and Figure 51, where representative combinations of
load capacitance and supply voltage requiring a 20 Ω resistor
are marked with an asterisk. No resistor is required for the ±3 V
plots in Figure 49, but a resistor is required for most of the ±12 V
plots in Figure 51.
AD8336 Data Sheet
Rev. F | Page 24 of 27
EVALUATION BOARD
An evaluation board, AD8336-EVALZ, is available online for
the AD8336. Figure 82 is a photo of the board.
The board is shipped from the factory configured for a non-
inverting preamplifier gain of 4×. To change the value of the
gain of the preamplifier or to change the gain polarity to inverting,
alter the component values or install components in the alternate
locations provided. All components are standard 0603 size, and
the board is compliant with RoHS requirements. Table 6 shows
the components to be removed and added to change the amplifier
configuration to inverting gain.
Table 6. Component Changes for Inverting Configuration
Remove Install
R4, R7 R5, R6
OPTIONAL CIRCUITRY
The AD8336 features differential inputs for the gain control,
permitting nonzero or floating gain control inputs. To avoid any
delay in making the board operational, the gain input circuit is
shipped with Pin GNEG connected to ground via a 0 Ω resistor
in the R17 location. The user can adjust the gain of the device
by driving the GPOS test loop with a power supply or voltage
reference. Optional resistor networks R15/R17 and R13/R14
provide fixed-gain bias voltages at Pin GNEG and Pin GPOS for
non-zero common-mode voltages. The gain control can also be
driven with an active input such as a ramp. Provision is made for
an optional SMA connector at PRVG for monitoring the
preamplifier output or for driving the VGA from an external
source. Remove the 0 Ω resistor at R9 to isolate the preamplifier
from an external generator. The capacitor at Location C1 limits
the bandwidth of the preamplifier.
BOARD LAYOUT CONSIDERATIONS
The evaluation board uses four layers, with power and ground
planes located between two conductor layers. This arrangement
is highly recommended for customers, and several views of the
board are provided as reference for board layout details. When
laying out a printed circuit board for the AD8336, remember to
provide a pad beneath the device to solder the exposed pad of
the matching device. The pad in the board must have at least
five vias to provide a thermal path for the chip scale package.
Unlike leaded devices, the thermal pad is the primary means
to remove heat dissipated within the device.
0
6228-083
Figure 82. AD8336 Evaluation Board
06228-084
Figure 83. Component Side Copper
0
6228-085
Figure 84. Secondary Side Copper
Data Sheet AD8336
Rev. F | Page 25 of 27
06228-086
Figure 85. Component Side Silkscreen
06228-087
Figure 86. Internal Ground Plane Copper
06228-088
Figure 87. Internal Power Plane Copper
AD8336 Data Sheet
Rev. F | Page 26 of 27
VIN
–V
S
112
11
10
94
3
2
VOUT
PWRA
VCOM
VPOS
GPOS
VNEG
PRAO
INPP
AD8336
VPOS
VOUTL
R2
49.9Ω
R8
301Ω
R7
100Ω
R4
0Ω
R9
0ΩPRVG
L2
120nH
R10
49.9Ω
R14
L1
120nH
R5
C4
10µF
35V
C2
10µF
25V
C5
0.1µF
C3
0.1µF
U1
16 131415
5 876
INPN NC NC
VGAI
R12
0Ω
R11
0Ω
GNEG
GND GND3GND2GND1
R13
R15
R17
0Ω
R6
R3
0Ω
C1
NC NC NC
GNEG
GPOS
+
+
VIN1
POWER
LOW
NORM
VOUT
VOUTD
R16
4.99kΩ
CR1
5.1V C8
0.1µF
VP
VP
C7
1nF
C6
1nF
R1
0Ω
06228-082
NC = NO CONNECT. DO NOT CO NNE CT TO T HIS PIN.
Figure 88. AD8336-EVALZ Schematic Shown as Shipped, Configured for a Noninverting Gain of 4×
Data Sheet AD8336
Rev. F | Page 27 of 27
OUTLINE DIMENSIONS
2.25
2.10 SQ
1.95
COMPLIANT
TO
JEDEC STANDARDS M O-220- V GGC
10-30-2017-C
1
0.65
BSC
PIN 1
INDICATOR
1.95 REF
0.75
0.60
0.50
TOP VIEW
12° M AX 0.80 M AX
0.65 TYP
COPLANARITY
0.08
1.00
0.85
0.80
0.35
0.30
0.25
0.05 M AX
0.02 NO M
0.20 REF
16
5
13
8
9
12
4
0.60 M AX
0.60 M AX
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
EXPOSED
PAD
0.20 M IN
BOTTOM VIEW
3.75 BSC
SQ
FOR PRO P E R CONNECTION O F
THE EXPOSED PAD, REFER TO
THE P IN CO NFI GURATIO N AND
FUNCTION DES CRIPT IO NS
SECTION OF THIS DATA SHEET.
SEATING
PLANE
Figure 89. 16-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.85 mm Package Height
(CP-16-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD8336ACPZ-R7
−40°C to +85°C
16-Lead Lead Frame Chip Scale Package [LFCSP]
CP-16-4
AD8336ACPZ-RL −40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-4
AD8336ACPZ-WP −40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-4
AD8336-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
©2006–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06228-0-11/17(F)