aire 67C401/13, 67C 402/23 Low Density First-In First-Out (FIFO) 64 x 4, 64 x 5 CMOS Memory (Cascadable) cl Advanced Micro Devices DISTINCTIVE CHARACTERISTICS Zero standby power High-speed 15 MHz shift-in/shift-out rates Very low active power consumption TTL-compatible Inputs and outputs Readily expandable in word width and depth RAN-based architecture for short fall-through delay Full CMOS cell for maximum nolse Immunity Asynchronous operation Output enable feature (67C4013/23) GENERAL DESCRIPTION The 67C40X/XX series devices are high-performance CMOS RAN-based First-In First-Out (FIFO) buffer memory products organized as 64 words by 4 or by 5, bits wide. These devices use Advanced Micro Devices latest CMOS process technology and meet the de- mands for high-speed, low-power operation. By utilizing anon-chip, dual-port RAM, avery short fail-through time is realized, thus improving overall system performance. By using both Read and Write pointers for addressing each memory location, the data can propagate to the outputs in much less time than in traditional register- based FIFOs. These FIFOs are easily integrated into many applications and perform particularly well for high- speed disc controllers, graphics, and communication network systems. The 550 uW standby power specifica- tion makes these devices ideal for ultra-low power and battery-powered systems. BLOCK DIAGRAM Input Shift Data Ready In In input Input Master eae, > Register Reset Write 64 x 4/5 Read Pointer 21 Dual Port Pointer Counter RAM Counter q Output Output Enable Regeter Control (6704013/23 only) Logic Shift Output Data Out Ready Out 10998D-1 PRODUCT SELECTOR GUIDE 67C401-10 67C401-15 67C4013-10 67C4013-15 67C402-10 67C402-15 Part Number 67C4023-10 67C4023-15 Shift-In/Shift-Out Rate Operating Frequency 10 MHz 15 MHz Maximum Power Supply Current 35 mA 45 mA Operating Range Com'l Com'l 2-142 Publication# 10898 Rev.D Amendment Issue Date: September 1992AMD cl CONNECTION DIAGRAMS DIP DIP 67C401/13 67C402/23 NC/OE 1] Veco NC/OE [J 1 ~~ 181] Vcc Input Ready 1} Shift Out Input Ready [] 2 17 1] Shift Out Shift In ] Output Ready Shit in 1] 3 16 1] Output Ready Do N Oo Do [4 15 1] Op Di U5 14JO1 Data Ds Hos Outputs Data [ H De 1 02 in< O26 13[]02 > Outputs Ds 1 Os Ds (]7 12 [os GND [] Master Reset ps Os 11 lo. GND 9 10 |] Master Reset 10998D-2 10998D-3 PLCC PLCC 5 5 5 9 5 | =< oO as Q gz29 3k 2z23 2% 1 3 2 #1 #20 19 e sFTin [| 4 Nc set in{] 4 18] ]OUT RDY Dolf 5 67C401/13 [out RDy Dol] 5 e7caoz23 17411 D,{] 6 64x4 16] Oo Df] 6 64x5 169] 0, FIFO FIFO De| lo, Doif 7 15 ] Oz nc[] 8 1] O Ds[] 8 141] 05 10 11 12 13 9 10 11 12 13 9 c & 9 10998D-4 a 2 c 9 10998D-5 6 o Note: 1. Pin 1 is marked for orientation for plastic packages. LOGIC SYMBOLS 67C401/402 67C4013/4023 4/5 465 4/5 45 >} Do-aa Oo-a4 > Do-ava Qo-a4 - >" Shift-In AA Shitt-in Input Ready -_> Input Ready -___> _ 4 Shift-Out 4F Shift-Out Output Ready - OE Output Ready -> MR MR 10998D-6 10998D-7 67C401/13, 67C402/23 2-143zt AMD ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: 870401 10 N C tL OPTIONAL PROCESSING Blank = Standard processing TEMPERATURE RANGE C = Commercial (0C to +70C) PACKAGE TYPE N = 16-Pin or 18-Pin Plastic DIP (PD 016 or PD 018) NL= 20-Pin Plastic Leaded Chip Carrier (PL 020) DEVICE NUMBER/DESCRIPTION SPEED OPTION -10 = 10 MHz Shift Rate -15 = 15 MHz Shift Rate Low Density First-In First-Out (FIFO) CMOS Memories (Cascadablie) 87C401 = 64x 4, Totem Pole Output 6704013. = 64x 4, Three-State Output 670402 = 64x 5, Totem Pole Output 67C4023. = 64x 5, Three-State Output Valid Combinations 67C401-10 67C401-15 67C4013-10 67C4013-15 670402-10 N, NL 67C402-15 67C4023-10 67C4023-15 Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consuit the lo- cal AMD sales office to confirm availability of specific valid combinations, to check on newly released combinations, and to obtain additional data on AMD's standard military grade products. 2-144 67C401/13, 67C402/23ABSOLUTE MAXIMUM RATINGS Supply Voltage Vcc ............. ~0.5 Vto +7.0V Input Voltage ................0, ~15Vto +7.0V Off-state Output Voltage ........ 0.5 to Vec +0.5V Storage Temperature .......... -65C to +150C Power Dissipation ...................00.. 1.0W Stresses above those listed under Absolute Maximum Rat- ings may cause permanent device failure. This is a stress rat- ing only; functional operation of the device at these limits or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of the device to absolute maximum ratings for extended periods may affect device reliability. AMD al OPERATING RANGES Commercial (C) Devices Ambient Temperature (Ta) Operating in Free Air............ 0C to +70C Supply Voltage (Vcc ) with Respect to Ground ..... +4.50 V to +5.50 V Operating ranges define those limits between which the func- tionality of the device is guaranteed. OPERATING CONDITIONS, Commercial Parameter 10 15 Symbol | Parameter Description Figure | Min. | Max.| Min. |Max. | Unit fin Shift in rate 1 10 15 |MHz tsin* Shift in HIGH time 1 16 16 ns tsn.* Shift in LOW time 1 30 30 ns tios Input data setup to SI (Shift In) 1 0 0 ns tiny Input data hold time from Si (Shift In) 1 40 40 ns trios Input data setup to IR (Input Ready) 3 0 0 ns tRIDH Input data hold time from IR (input Ready) 3 30 30 ns four Shift out rate 4 10 15 |MHz tson Shift out HIGH time 4 24 21 ns fsou* Shift out LOW time 4 30 30 ns tmRw Master Reset pulse 8 35 35 ns tmrs Master Reset to SI! 8 65 65 ns See AC test and high-speed application note. 67C401/13, 67C402/23 2-145G1 aw DC CHARACTERISTICS over COMMERCIAL operating range unless otherwise specified Parameter -10 -15 Symbol | Parameter Description Test Condition Min. Max. Min. Max. | Unit Vi" Low-level input voltage 0.8 0.8 v Vin* High-level input voitage 2 2 v lin Input Current Vec = Max., GND <Vin <Vcc -1 1 ~-1 1 pA loz Off-state output current Vcc = Max., GND <VouT <Vcc - 5 -5 5 pA lot = 20 0.1 0.1 Vec = Min. nA Vv VoL Low-level output voltage lot = 8 mA 0.4 0.4 . . loH = -20 pA Vec - 0.1 Veco - 0.1 Vou High-level output voltage Vec = Min. Vv loH = -4 mA 2.4 2.4 los** Output short-circuit current | Vcc = Max.| Vo #0 V -90 -20 ~90 -20 mA 100 100 Standby supply current ve = ce HA Ice Voc = Max. P= . lout = 0 ViH = Min., 35 45 mA Operating supply current Vit = Max. fin = fouT = Max. Vit and Vit are input conditions of output tests and are not themselves directly tested. Vit and Vin are absolute voltages with respect to device ground and include all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment. SWITCHING CHARACTERISTICS over COMMERCIAL operating range unless otherwise specified Parameter 10 15 Symbol | Parameter Description Figure | Min. |Max. | Min. |Max. | Unit taL: Shift in T fo Input Ready Low 1 60 55 | ns tran Shift in | to Input Ready HIGH 55 55 | ns ton: | Shift Out T to Output Ready LOW 55 47 | ns tory | Shift Out 1 to Output Ready HIGH 50 47 | ns toox Output Data Hold (previous word) 4 5 5 ns toos Output Data Shift (next word) 35 33 | ns ter Data throughput 3.6 100 90 | ns twror. |Master Reset 1 to Output Ready LOW 100 100 | ns twrirnH =| Master Reset 1 to Input 8 Ready HIGH 100 100 | ns tMRO Master Reset | to Outputs LOW 35 35 | ns tieH input Ready pulse HIGH 3 19 16 ns tory Output Ready pulse HIGH 6 16 16 ns torp Output Ready T to Data Valid 4 -3 -3 | ns tPHz* 25 25 teu Output Disable Delay 25 25 ns tezu A 30 30 tea Output Enable Delay 30 30 ns *See AC test and high-speed application note. **Enable/Disable delays refer to 67C4013/23 only. 2-146 67C401/13, 67C402/23AMD at CAPACITANCES* Parameter Symbol | Parameter Description Test Conditions Min. Max. Unit Cin input capacitance Ta = 25C, f = 1 MHz 10 Cout Output capacitance Veco =4.5V 7 pF * These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. _ 3V Duout VT Output Enable A ov tpz. s ane = __ Se S1 Closed 1.5V Sf Waveform 1 $2 Open Vr |4 VoL+0.5V VoL tP2H L tpHz >} i | Vou $1 Open Kv, Vou~ 0.5 V Waveform 2 S2Closed_ A ov 15V Si and S2 Vr=15 Closed 10998D-6 Figure A. Enable and Disable Notes: 1. Waveform 1 is for a data output with internal conditions such that the output is low except when disabled by the output control. 2. Waveform 2 is for a data output with internal conditions such that the output is high except when disabled by the output control. Icc VS. Frequency 50 d 40 + Vec = Max 30 + , lec mA 20+ jo+ Ta = 0C fin = fouT Vit = Max, ViH = Min 0 t t t 0 1 5 10 15 Frequency MHz 4 10998D-7 67C401/13, 67C402/23 2-147cl AMD a < AAA. vvv--0 R1 wore J Test Point > R2 L Standard AC Test Load AAA 10998D-8 Input Pulse Ampitude = 3 V Input Rise and Fall Time (10% 90%) = 2.5 ns Measurements made at 1.5 V All Diodes are 1N916 or 1N3064 Resistor Values lou R1 R2 8mA 6000 1200 0 Test Point cL > Vec L S1 ) Ss 5 pF R2 = { $2 10998D-9 Three-State Test Load FUNCTIONAL DESCRIPTION Data Input The FIFO consists of a dual-port RAM and two ring counters for read and write. After power-up, the Master Reset should be pulsed LOW, which internally rests both the read and write counters. When the Ready (IR) is HIGH, the FIFO is ready to accept DATA from the Dx inputs. Data then present at the inputs is written into the first location of the RAM when Shift-In (SI) is brought HIGH. ASI HIGH signal causes the IR to go LOW. When the SI is brought LOW and the FIFO is not full, IR will go HIGH, indicating that more room is available. The write pointer now points to the next location in the RAM. Ifthe memory is full, then the IR will remain LOW. Data Output Data is read from Ox outputs. Just after the first shift-in, the first data word is available at the outputs, which is in- dicated by the Output Ready (OR) going HIGH. When the OR is HIGH, data may be shifted out by bringing the Shift-Out (SO) HIGH. A HIGH signal at SO causes the read pointer to point to the next location in the RAM, and also the OR to go LOW. Valid data is maintained while the SO is HIGH. When the SO is brought LOW, the OR goes HIGH, indicating the presence of new valid data. If the FIFO is emptied, OR stays LOW, and Ox remains as before, (i.e., data does not change if the FIFO is empty). A dual-port RAM inside the chip provides the capability of simultaneous and asynchronous write (Shift-Ins) and reads (Shift-Outs). 2-148 67C401/13, 67C402/23AMD cl AC TEST AND HIGH-SPEED APPLICATION NOTES Since the FIFO is a very-high-speed device, care must be exercised in the design of the hardware and the tim- ing utilized within the design. Device grounding decou- pling is crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor supply decoupling and grounding. Advanced Micro Devices recommends a monolithic ceramic capacitor of 0.1 uF directly be- tween Vcc and GND with very short lead length. In addi- tion, care must be exercised in how the timing is set and how the parameters are measured. For example, since an AND gate function is associated with both the Shift- In-Input Ready combination, as well as the Shift-Out- Output Ready combination, timing measurements may be misleading; i.e., a rising edge of the Shift-In pulse is not recognized until Input Ready is HIGH. If Input Ready is not HIGH due to (a) too high a frequency, or (b) FIFO being full or affected by Master Reset, the Shift-In activ- ity will be ignored. This will affect the device froma func- tional standpoint, and will also cause the effective timing of Input Data Hold time (tox) and the next activity of Input Ready (tint) to be extended relative to Shift-In going HIGH. The same type of problem also relates to tinH, tor. and torn. For high-speed applications, proper grounding technique is essential. In order to diminish timing ambiguities between the Shift-In-Input-Ready or Shift-Out-Output-Ready pairs when operating at high frequencies, it is recommended that the tsi and tsou pulse widths be as short as possible within the specified limits. TAIN fA* tsiq tsiL Shift in Input Ready Po \ Of Input Data pa tIDH tips TAIN tIRH ee IRL (XXRRRRREK RRR 10998D-10 Figure 1. Input Timing Shift In DD Input Ready Input Data indicated by Input Ready HIGH. a FW =e XR Stable bas X XA AAA AARALA) vo 10998D-11 Input Ready HIGH indicates space is available and a Shift-In pulse may be applied. Input Data is loaded into the first available memory location. Input Ready goes LOW indicating this memory location is full. Shift-In going LOW allows Input Ready to sense the status of the next memory location. The next memory location is empty as If the FIFO is already full, then the Input Ready remains LOW. Note: Shift-In pulses applied while Input Ready is LOW will be ignored. Figure 2. The Mechanism of Shifting Data Into the FIFO 67C401/13, 67C402/23 2-149zt AMD Shift Out Xr Shift In J \ Input Ready XY tPT tIPH tRIDS | tRIDH XXXKKKKKKKKKKKKKKKKKK e Stable Data a Input Dat nputData X XXXXMAAAAAAAAAAY Stable Data 10998D-12 1. FIFO is initially full. 2. Shift-In is held HIGH. 3. Shift-Out pulse is applied. An empty location is detected by the internal pointers on the falling edge of SO. 4. As soon as Input Ready becomes HIGH, the Input Data is loaded into this location. Figure 3. Data Is shifted In whenever Shift-In and input Ready are Both HIGH TAouT 1AouT Shift Out KN tsoH *y*+ tsol > torH Output Ready G y \ tops torD i tORL Output Data A-Data B-Daia C-Data toDH 10998D-13 1. The diagram assumes that the FIFO contains at least threa words: A-Data (first input word), B-Data (second input word), and C-Data (third input word). 2. Output data changes on the falling edge of SO after a valid Shift-Out Sequence, i.e., OR and SO are both high together. Figure 4. Output Timing 2-150 67C401/13, 67C402/23AMD al nh AP Shift Out Output Ready Output Data AorB 10998D-14 Output Ready HIGH indicates that data is available and a Shift-Out pulse may be applied. Shift-Out goes HIGH causing B-Data (second input word) to advance to the output register. Output data remains as valid A-Data while Shift-Out is HIGH. Output Ready goes LOW. Shift-Out goes LOW causing Output Ready to go HIGH and new data (B) to appear at the data outputs. if the FIFO has only one word loaded (A-Data) then Output Ready stays LOW and the output data remains the same (A-Data). Figure 5. The Mechanism of Shifting Data Out of the FIFO Output Ready DY j BWM > Shift In Shift Out y tpT f# topH 10998D-15 FIFO initially empty. Shift-Out held HIGH. Shift-In pulse applied. A full location is detected by the internal pointers on the falling edge of Shift-in. As soon as Output Ready becomes HIGH, the word is shifted out. Figure 6. ter and tory Specification 67C401/13, 67C402/23 2-151zi AMD Shift Out \ g Output Ready () () () () () () () () Output Data A-Data x 10998D-16 1, The internal logic does not detect the presence of any words in the FIFO. 2. New data (A) arrives at the outputs. 3. Output Ready goes HIGH indicating arrival of the new data. 4. Since Shift-Out is held HIGH, Output Ready goes immediately LOW. 5. As soon as Shift-Out goes LOW, the Output Data is subject to change. Output Ready will go HIGH or remain LOW depend- ing on whether there are any additional words in the FIFO. Figure 7. Data is Shifted Out Whenever Shift Out and Output Ready are Both HIGH MASTER RESET h t iMAwW > Input Ready XD tMRIRH | Output Ready et tMRORL Ht {MRS Shift In Data Outputs NYYXY\ [* tMRO -| 10998D-17 1, FIFO is initially full. Figure 8. Master Reset Timing 2-152 67C401/13, 67C402/23AMD al NORMALIZED Icc vs FREQUENCY 100 O.8V<VIN<S2.0V 60 Normalized Icc (%) 40 0O.0V<SVNS5.5V 20 fin = fout (MHz) 10998D-18 Ta = 0C, Vec = 5.5 V, fin = fout 67C401/13, 67C402/23 2-153