SQ1912AEEH-T1_GE3 - VISHAY

SQ1912AEEH

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S15-1251 Rev. A, 01-Jun-15 1Document Number: 62983

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Automotive Dual N-Channel 20 V (D-S) 175 °C MOSFET

Marking Code: 8R

FEATURES

• TrenchFET® power MOSFET

• AEC-Q101 qualified

• 100 % Rg tested

• Typical ESD protection: 800 V

• Material categorization:

for definitions of compliance please see

www.vishay.com/doc?99912

Notes

a. Package limited.

b. Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 %.

c. When mounted on 1" square PCB (FR4 material).

PRODUCT SUMMARY

VDS (V) 20

RDS(on) (Ω) at VGS = 4.5 V 0.280

RDS(on) (Ω) at VGS = 2.5 V 0.360

RDS(on) (Ω) at VGS = 1.8 V 0.450

ID (A) 0.8

Configuration Dual

SOT-363

SC-70 Dual (6 leads)

Top View

3 k

ORDERING INFORMATION

Package SC-70

Lead (Pb)-free and Halogen-free SQ1912AEEH-T1-GE3

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT

Drain-Source Voltage VDS 20 V

Gate-Source Voltage VGS ± 12

Continuous Drain Current aTC = 25 °C ID

0.8

TC = 125 °C 0.8

Continuous Source Current (Diode Conduction) a IS0.8

Pulsed Drain Current bIDM 3

Maximum Power Dissipation bTC = 25 °C PD

1.5 W

TC = 125 °C 0.5

Operating Junction and Storage Temperature Range TJ, Tstg -55 to +175 °C

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL LIMIT UNIT

Junction-to-Ambient PCB Mount cRthJA 220 °C/W

Junction-to-Foot (Drain) RthJF 100

SQ1912AEEH

www.vishay.com Vishay Siliconix

S15-1251 Rev. A, 01-Jun-15 2Document Number: 62983

For technical questions, contact: automostechsupport@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

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Notes

a. Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 %.

b. Guaranteed by design, not subject to production testing.

c. Independent of operating temperature.

d. Gate is obscured by ESD network series resistance and cannot be tested directly.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation

of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device reliability.

SPECIFICATIONS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Static

Drain-Source Breakdown Voltage VDS VGS = 0, ID = 250 μA 20 - - V

Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 μA 0.45 0.6 1.5

Gate-Source Leakage IGSS VDS = 0 V, VGS = ± 4.5 V - - ± 1 μA

VDS = 0 V, VGS = ± 12 V - - ± 10 mA

Zero Gate Voltage Drain Current IDSS

VGS = 0 V VDS = 20 V - - 1

μA VGS = 0 V VDS = 20 V, TJ = 125 °C - - 50

VGS = 0 V VDS = 20 V, TJ = 175 °C - - 150

On-State Drain Current a I

D(on) V

GS = 4.5 V VDS ≥ 5 V 1.5 - - A

Drain-Source On-State Resistance a R

DS(on)

VGS = 4.5 V ID = 1.2 A - 0.200 0.280

VGS = 4.5 V ID = 1.2 A, TJ = 125 °C - - 0.423

VGS = 4.5 V ID = 1.2 A, TJ = 175°C - - 0.510

VGS = 2.5 V ID = 1 A - 0.261 0.360

VGS = 1.8 V ID = 0.2 A - 0.320 0.450

Forward Transconductance b gfs VDS = 10 V, ID = 1.2 A - 2.6 - S

Dynamic b

Input Capacitance Ciss

VGS = 0 V VDS = 10 V, f = 1 MHz

-27-

pF Output Capacitance Coss -19-

Reverse Transfer Capacitance Crss -7-

Total Gate Charge c Qg

VGS = 4.5 V VDS = 10 V, ID = 1.2 A

- 1 1.25

nC Gate-Source Charge c Qgs -0.14-

Gate-Drain Charge c Qgd -0.27-

Gate Resistance dRg f = 1 MHz 1.5 3 4.5 kΩ

Turn-On Delay Time c td(on)

VDD = 10 V, RL = 20 Ω

ID ≅ 0.5 A, VGEN = 4.5 V, Rg = 1 Ω

-6682

Rise Time c tr - 108 135

Turn-Off Delay Time c td(off) - 715 893

Fall Time c tf - 390 487

Source-Drain Diode Ratings and Characteristics b

Pulsed Current a ISM --3A

Forward Voltage VSD IF = 0.5 A, VGS = 0 - 0.8 1.2 V

SQ1912AEEH

www.vishay.com Vishay Siliconix

S15-1251 Rev. A, 01-Jun-15 3Document Number: 62983

For technical questions, contact: automostechsupport@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

Gate Current vs. Gate-Source Voltage

Output Characteristics

Transconductance

Gate Current vs. Gate-Source Voltage

Transfer Characteristics

On-Resistance vs. Drain Current

0.000

0.001

0.002

0.003

0.004

0.005

0 5 10 15 20 25

IGSS - Gate Current (mA)

VGS - Gate-to-Source Voltage (V)

TJ = 25 °C

0.0

0.4

0.8

1.2

1.6

2.0

0.0 0.2 0.4 0.6 0.8 1.0

ID- Drain Current (A)

VDS-Drain-to-Source Voltage (V)

VGS = 5 V thru 2 V

VGS = 1 V

VGS = 1.5 V

0.0 0.2 0.4 0.6 0.8 1.0

gfs-Transconductance (S)

ID- Drain Current (A)

TC= 125 °C

TC= - 55 °C

TC= 25 °C

100

10-2

10-4

10-6

10-8

10-10

0 4 8 12 16 20

IGSS - Gate Current (μA)

VGS - Gate-to-Source Voltage(V)

TJ = 150 °C

TJ = 25 °C

0.0

0.4

0.8

1.2

1.6

2.0

0.0 0.5 1.0 1.5 2.0 2.5

ID- Drain Current (A)

VGS -Gate-to-Source Voltage (V)

TC= - 55 °C

TC= 125 °C

TC= 25 °C

0.0

0.1

0.2

0.3

0.4

0.5

0.0 0.4 0.8 1.2 1.6 2.0

RDS(on) -On-Resistance (Ω)

ID- Drain Current (A)

VGS = 4.5 V

VGS = 2.5 V

VGS = 1.8 V

SQ1912AEEH

www.vishay.com Vishay Siliconix

S15-1251 Rev. A, 01-Jun-15 4Document Number: 62983

For technical questions, contact: automostechsupport@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

Capacitance

On-Resistance vs. Junction Temperature

On-Resistance vs. Gate-to-Source Voltage

Gate Charge

Source Drain Diode Forward Voltage

Threshold Voltage

0 5 10 15 20

C - Capacitance (pF)

VDS-Drain-to-Source Voltage (V)

Ciss

Coss

Crss

0.5

0.8

1.1

1.4

1.7

2.0

- 50 - 25 0 25 50 75 100 125 150 175

RDS(on) -On-Resistance (Normalized)

TJ- Junction Temperature (°C)

ID= 1.2 A

VGS = 4.5 V

VGS = 2.5 V

0.0

0.2

0.4

0.6

0.8

1.0

012345

RDS(on) -On-Resistance (Ω)

VGS -Gate-to-Source Voltage (V)

TJ= 150 °C

TJ= 25 °C

0.0 0.2 0.4 0.6 0.8 1.0

VGS -Gate-to-Source Voltage (V)

Qg-Total Gate Charge (nC)

ID= 1.2 A

0.001

0.01

0.1

0.00.20.40.60.81.01.2

IS-Source Current (A)

VSD-Source-to-Drain Voltage (V)

TJ= 25 °C

TJ= 150 °C

- 0.5

- 0.3

- 0.1

0.1

0.3

0.5

- 50 - 25 0 25 50 75 100 125 150 175

VGS(th) Variance (V)

TJ- Temperature (°C)

ID= 250 μA

ID= 5 mA

SQ1912AEEH

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S15-1251 Rev. A, 01-Jun-15 5Document Number: 62983

For technical questions, contact: automostechsupport@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted)

Drain Source Breakdown vs. Junction Temperature

Safe Operating Area

- 50 - 25 0 25 50 75 100 125 150 175

VDS-Drain-to-Source Voltage (V)

TJ- Junction Temperature (°C)

ID= 1 mA

0.01

0.1

100

0.01 0.1 1 10 100

ID- Drain Current (A)

VDS-Drain-to-Source Voltage (V)

* VGS > minimum VGS at which RDS(on) is specied

100 ms

Limited by RDS(on)*

IDM Limited

TC= 25 °C

Single Pulse

BVDSS Limited

10 ms

1 s, 10 s, DC

SQ1912AEEH

www.vishay.com Vishay Siliconix

S15-1251 Rev. A, 01-Jun-15 6Document Number: 62983

For technical questions, contact: automostechsupport@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

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THERMAL RATINGS (TA = 25 °C, unless otherwise noted)

Normalized Thermal Transient Impedance, Junction-to-Ambient

Normalized Thermal Transient Impedance, Junction-to-Foot

Note

• The characteristics shown in the two graphs

- Normalized Transient Thermal Impedance Junction-to-Ambient (25 °C)

- Normalized Transient Thermal Impedance Junction-to-Foot (25 °C)

are given for general guidelines only to enable the user to get a “ball park” indication of part capabilities. The data are extracted from single

pulse transient thermal impedance characteristics which are developed from empirical measurements. The latter is valid for the part

mounted on printed circuit board - FR4, size 1" x 1" x 0.062", double sided with 2 oz. copper, 100 % on both sides. The part capabilities

can widely vary depending on actual application parameters and operating conditions.

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon

Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and

reliability data, see www.vishay.com/ppg?62983.

10-3 10 -2 00601110-1

10-4 100

0.1

0.01

0.2

0.1

0.05

Single Pulse

Duty Cycle = 0.5

Square Wave Pulse Duration (s)

Normalized Effective Transient

Thermal Impedance

1. Duty Cycle, D =

2. Per Unit Base = RthJA = 220 °C/W

3. TJM - T A = PDMZthJA(t)

Notes:

4. Surface Mounted

PDM

0.02

10-3 10-2 01110-1

10-4

0.1

0.01

0.2

0.1

0.05

Single Pulse

Duty Cycle = 0.5

Square Wave Pulse Duration (s)

Normalized Effective Transient

Thermal Impedance

0.02

A2A

-A-

-B-

654

Package Information

Vishay Siliconix

Document Number: 71154

06-Jul-01 www.vishay.com

SCĆ70: 6ĆLEADS

MILLIMETERS INCHES

Dim Min Nom Max Min Nom Max

A0.90 – 1.10 0.035 – 0.043

A1– – 0.10 – – 0.004

A20.80 – 1.00 0.031 – 0.039

b0.15 – 0.30 0.006 – 0.012

c0.10 – 0.25 0.004 – 0.010

D1.80 2.00 2.20 0.071 0.079 0.087

E1.80 2.10 2.40 0.071 0.083 0.094

E11.15 1.25 1.35 0.045 0.049 0.053

e0.65BSC 0.026BSC

e11.20 1.30 1.40 0.047 0.051 0.055

L0.10 0.20 0.30 0.004 0.008 0.012

7_Nom 7_Nom

ECN: S-03946—Rev. B, 09-Jul-01

DWG: 5550

AN816

Vishay Siliconix

Document Number: 71405

12-Dec-03

www.vishay.com

Dual-Channel LITTLE FOOTR 6-Pin SC-70 MOSFET

Copper Leadframe Version

Recommended Pad Pattern and Thermal Performance

INTRODUCTION

The new dual 6-pin SC-70 package with a copper leadframe

enables improved on-resistance values and enhanced

thermal performance as compared to the existing 3-pin and

6-pin packages with Alloy 42 leadframes. These devices are

intended for small to medium load applications where a

miniaturized package is required. Devices in this package

come in a range of on-resistance values, in n-channel and

p-channel versions. This technical note discusses pin-outs,

package outlines, pad patterns, evaluation board layout, and

thermal performance for the dual-channel version.

PIN-OUT

Figure 1 shows the pin-out description and Pin 1 identification

for the dual-channel SC-70 device in the 6-pin configuration.

Both n-and p-channel devices are available in this package –

the drawing example below illustrates the p-channel device.

FIGURE 1.

SOT-363

SC-70 (6-LEADS)

Top View

For package dimensions see outline drawing SC-70 (6-Leads)

(http://www.vishay.com/doc?71154)

BASIC PAD PATTERNS

See Application Note 826, Recommended Minimum Pad

Patterns With Outline Drawing Access for Vishay Siliconix

MOSFETs, (http://www.vishay.com/doc?72286) for the SC-70

6-pin basic pad layout and dimensions. This pad pattern is

sufficient for the low-power applications for which this package

is intended. Increasing the drain pad pattern (Figure 2) yields

a reduction in thermal resistance and is a preferred footprint.

FIGURE 2. SC-70 (6 leads) Dual

48 (mil)

16 (mil)

654

321

61 (mil)

26 (mil)

8 (mil)

0.0 (mil)

23 (mil)

71 (mil)

96 (mil)

26 (mil)

87 (mil)

EVALUATION BOARD FOR THE DUAL-

CHANNEL SC70-6

The 6-pin SC-70 evaluation board (EVB) shown in Figure 3

measures 0.6 in. by 0.5 in. The copper pad traces are the same

as described in the previous section, Basic Pad Patterns. The

board allows for examination from the outer pins to the 6-pin

DIP connections, permitting test sockets to be used in

evaluation testing.

The thermal performance of the dual 6-pin SC-70 has been

measured on the EVB, comparing both the copper and Alloy

42 leadframes. This test was then repeated using the 1-inch2

PCB with dual-side copper coating.

A helpful way of displaying the thermal performance of the

6-pin SC-70 dual copper leadframe is to compare it to the

traditional Alloy 42 version.

AN816

Vishay Siliconix

www.vishay.com

Document Number: 71405

12-Dec-03

FIGURE 3.

Front of Board SC70-6 Back of Board SC70-6

SC70−6 DUAL vishay.com

THERMAL PERFORMANCE

Junction-to-Foot Thermal Resistance

(the Package Performance)

Thermal performance for the dual SC-70 6-pin package is

measured as junction-to-foot thermal resistance, in which the

“foot” is the drain lead of the device as it connects with the

body. The junction-to-foot thermal resistance for this device is

typically 80_C/W, with a maximum thermal resistance of

approximately 100_C/W. This data compares favorably with

another compact, dual-channel package – the dual TSOP-6 –

which features a typical thermal resistance of 75_C/W and a

maximum of 90_C/W.

Power Dissipation

The typical RθJA for the dual-channel 6-pin SC-70 with a

copper leadframe is 224_C/W steady-state, compared to

413_C/W for the Alloy 42 version. All figures are based on the

1-inch2 FR4 test board. The following example shows how the

thermal resistance impacts power dissipation for the dual 6-pin

SC-70 package at varying ambient temperatures.

Alloy 42 Leadframe

ALLOY 42 LEADFRAME

Room Ambient 25 _CElevated Ambient 60 _C

PD+TJ(max) *TA

RqJA

PD+150oC*25oC

413oCńW

PD+303 mW

PD+TJ(max) *TA

RqJA

PD+150oC*60oC

413oCńW

PD+218 mW

COOPER LEADFRAME

Room Ambient 25 _CElevated Ambient 60 _C

PD+TJ(max) *TA

RqJA

PD+150oC*25oC

224oCńW

PD+558 mW

PD+TJ(max) *TA

RqJA

PD+150oC*60oC

224oCńW

PD+402 mW

Although they are intended for low-power applications,

devices in the 6-pin SC-70 dual-channel configuration will

handle power dissipation in excess of 0.5 W.

TESTING

To further aid the comparison of copper and Alloy 42

leadframes, Figures 4 and 5 illustrate the dual-channel 6-pin

SC-70 thermal performance on two different board sizes and

pad patterns. The measured steady-state values of RθJA for

the dual 6-pin SC-70 with varying leadframes are as follows:

LITTLE FOOT 6-PIN SC-70

Alloy 42 Copper

1) Minimum recommended pad pattern on

the EVB board (see Figure 3). 518_C/W 344_C/W

2) Industry standard 1-inch2 PCB with

maximum copper both sides. 413_C/W 224_C/W

The results indicate that designers can reduce thermal

resistance (θJA) by 34% simply by using the copper leadframe

device as opposed to the Alloy 42 version. In this example, a

174_C/W reduction was achieved without an increase in board

area. If an increase in board size is feasible, a further 120_C/W

reduction can be obtained by utilizing a 1-inch2. PCB area.

The Dual copper leadframe versions have the following suffix:

Dual: Si19xxEDH

Compl.: Si15xxEDH

AN816

Vishay Siliconix

Document Number: 71405

12-Dec-03

www.vishay.com

Time (Secs)

FIGURE 4. Dual SC70-6 Thermal Performance on EVB

Thermal Resistance (C/W)

500

100

200

100 1000

300

1010-1

10-2

10-3

10-4

10-5

Alloy 42

400

Time (Secs)

FIGURE 5. Dual SC70-6 Comparison on 1-inch2 PCB

Thermal Resistance (C/W)

500

100

200

100 1000

300

1010-1

10-2

10-3

10-4

10-5

400

Copper

Alloy

Application Note 826

Vishay Siliconix

www.vishay.com Document Number: 72602

18 Revision: 21-Jan-08

APPLICATION NOTE

RECOMMENDED MINIMUM PADS FOR SC-70: 6-Lead

0.096

(2.438)

Recommended Minimum Pads

Dimensions in Inches/(mm)

0.067

(1.702)

0.026

(0.648)

0.045

(1.143)

0.016

(0.406)

0.026

(0.648)

0.010

(0.241)

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Revision: 01-Jan-2021 1Document Number: 91000

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