12-1
Semiconductor
Features
• Direct RESET
• TTL and CMOS Compatible Address and Enable
Inputs
• Maximum Power Supply Rating . . . . . . . . . . . . . . . .44V
• Break-Before-Make Switching
• Alternate Source
Applications
• Data Acquisition Systems
• Communication Systems
• Automatic Test Equipment
• Microprocessor Controlled Systemd
Description
The DG526, DG527, DG528, and DG529 are CMOS
Monolithic 16-Channel/Dual 4-Channel Analog Multiplexers.
Each device has on-chip address and control latches to sim-
plify design in microprocessor based applications. The DG526
uses 4 address lines to control its 16 channels; the DG527,
DG528 both use 3 address lines to control their 8 channels;
and the DG529 uses 2 address lines to control its 4 channels.
The enable pin is used to enable the address latches during
the WR pulse. It can be hard wired to the logic supply if one of
the channels will always be used (except during a reset) or it
can be tied to address decoding circuitry for memory mapped
operation. The RS pin is used to clear all latches regardless of
the state of any other latch or control line. The WR pin is used
to transfer the state of the address control lines to their
latches, except during a reset or when EN is lo w.
A channel in the ON state conducts signals equally well in
both directions. In the OFF state each channel blocks volt-
ages up to the supply rails. The address inputs, WR, RS and
the enable input are TTL and CMOS compatible over the full
specified operation temperature range.
Part Number Information
PART
NUMBER TEMP.
RANGE (oC) PACKAGE PKG. NO.
DG526AK -55 to 125 28 Ld CERDIP F28.6
DG526AK/883B -55 to 125 28 Ld CERDIP F28.6
DG526BK -25 to 85 28 Ld CERDIP F28.6
DG526BY -25 to 85 28 Ld SOIC M28.3
DG526CJ 0 to 70 28 Ld PDIP E28.6
DG526CK 0 to 70 28 Ld CERDIP F28.6
DG526CY 0 to 70 28 Ld SOIC M28.3
DG527AK -55 to 125 28 Ld CERDIP F28.6
DG527AK/883B -55 to 125 28 Ld CERDIP F28.6
DG527BK -25 to 85 28 Ld CERDIP F28.6
DG527BY -25 to 85 28 Ld SOIC M28.3
DG527CJ 0 to 70 28 Ld PDIP E28.6
DG527CK 0 to 70 28 Ld CERDIP F28.6
DG527CY 0 to 70 28 Ld SOIC M28.3
DG528AK -55 to 125 18 Ld CERDIP F18.3
DG528AK/883B -55 to 125 18 Ld CERDIP F18.3
DG528BK -25 to 85 18 Ld CERDIP F18.3
DG528BY -25 to 85 18 Ld SOIC M18.3
DG528CJ 0 to 70 18 Ld PDIP E18.3
DG528CK 0 to 70 18 Ld CERDIP F18.3
DG528CY 0 to 70 18 Ld SOIC M18.3
DG529AK -55 to 125 18 Ld CERDIP F18.3
DG529AK/883B -55 to 125 18 Ld CERDIP F18.3
DG529BK -25 to 85 18 Ld CERDIP F18.3
DG529BY -25 to 85 18 Ld SOIC M18.3
DG529CJ 0 to 70 18 Ld PDIP E18.3
DG529CK 0 to 70 18 Ld CERDIP F18.3
DG529CY 0 to 70 18 Ld SOIC M18.3
PART
NUMBER TEMP.
RANGE (oC) PACKAGE PKG. NO.
April 1999
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1999
DG526, DG527,
DG528, DG529
Analog CMOS
Latchable Multiplexers
File Number 3139.2
FOR A POSSIBLE SUBSTITUTE PRODUCT
call Central Applications 1-800-442-7747
or email: centapp@harris.com
OBSOLETE PRODUCT
12-2
Pinouts
DG526
(PDIP, CERDIP, SOIC)
TOP VIEW
DG527
(PDIP, CERDIP, SOIC)
TOP VIEW
DG528
(PDIP, CERDIP, SOIC)
TOP VIEW
DG529
(PDIP, CERDIP, SOIC)
TOP VIEW
V+
NC
RS
S16
S15
S14
S13
S12
S11
S10
S9
GND
WR
A3
D
S8
S7
S6
S5
S3
S1
EN
A0
A1
A2
V-
S4
S2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
V+
DB
RS
S8B
S7B
S6B
S5B
S4B
S3B
S2B
S1B
GND
WR
NC
DB
S8A
S7A
S6A
S5A
S3A
S1A
EN
A0
A1
A2
V-
S4A
S2A
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1RS
A2
GND
V+
S5
S6
S7
A1
S8
WR
A0
EN
V-
S1
S2
S4
S3
D10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1RS
GND
V+
S1B
S2B
S3B
A1
DB
WR
A0
EN
V-
S1A
S2A
S4A
S3A
DA
S4B
DG526, DG527, DG528, DG529
12-3
Functional Diagrams
DG526
16-CHANNEL SINGLE ENDED MULTIPLEXER DG527
DIFFERENTIAL 8-CHANNEL MULTIPLEXER
DG528
8-CHANNEL SINGLE ENDED MULTIPLEXER DG529
DUAL 4-CHANNEL MULTIPLEXER
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
WR RS
D
V+ V- GND
ENA3A2A1A0
DECODER LOGIC AND LATCHES
S1A
S2A
S3A
S4A
S5A
S6A
S7A
S8A
S1B
S2B
S3B
S4B
S5B
S6B
S7B
S8B
WR RS
DA
V+ V- GND
ENA2A1A0
DECODER LOGIC AND LATCHES
DB
S1
S2
S3
S4
S5
S6
S7
S8
WR
A2A1A0
DECODER LOGIC AND LATCHES
EN
RS
LATCHES
D
V+ V- GND
S1A
S2A
S3A
S4A
WR
A0
DECODER LOGIC
EN
RS
LATCHES
S1B
S2B
S3B
S4B
DB
A0
DECODER LOGIC AND LATCHES
DA
V+ V- GND
DG526, DG527, DG528, DG529
12-4
Schematic Diagrams
LOGIC INTERFACE AND LEVEL SHIFTER
DECODER AND SWITCH
TO
DECODER
LOGIC
TRIP
POINT
REF
-
V+
GND
AX, EN,
V-
RS, WR
+
SX
DX
DE-
CODER
AX‘
EN‘
RS‘
V-
V+
WR‘
V+
DG526, DG527, DG528, DG529
12-5
Absolute Maximum Ratings Thermal Information
V+ to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44V
V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-25V
VIN to Ground (Note 1). . . . . . . . . . . . . . . . . . . . (V- - 2V), (V+ + 2V)
VS or VD to V+ (Note 1) . . . . . . . . . . . . . . . . . . . . . . . .+2V, (V- - 2V)
VS or VD to V- (Note 1). . . . . . . . . . . . . . . . . . . . . . . . -2V, (V+ + 2V)
Current, Any Terminal Except S or D . . . . . . . . . . . . . . . . . . . .30mA
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . .20mA
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40mA
(Pulsed at 1ms, 10% Duty Cycle Max)
Operating Conditions
Operating Temperature
C Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC
B Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC
A Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)
18 Ld PDIP Package . . . . . . . . . . . . . . 90 N/A
18 Ld CERDIP Package . . . . . . . . . . . 75 22
18 Ld SOIC Package. . . . . . . . . . . . . . 95 N/A
28 Ld PDIP Package . . . . . . . . . . . . . . 60 N/A
28 Ld CERDIP Package . . . . . . . . . . . 55 18
28 Ld SOIC Package. . . . . . . . . . . . . . 70 N/A
Maximum Junction Temperature
Ceramic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range
C Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65oC to 125oC
A and B Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CA UTION: Stresses abo v e those listed in “Absolute Maximum Ratings” ma y cause permanent damage to the de vice. This is a stress only rating and oper ation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications (Note 3) V+ = +15V, V- = -15V, GND = 0V, WR = 0V, RS = 2.4V, EN = 2.4V, TA = 25oC,
Unless Otherwise Specified
PARAMETER (NOTE 6)
TEST CONDITIONS
A SUFFIX B AND C SUFFIX
UNITSMIN (NOTE 2)
TYP MAX MIN (NOTE 2)
TYP MAX
DYNAMIC
Switching Time
of Multiplexer,
tTRANSITION
DG526,
DG527 See Figure 3 (Note 7) - 0.65 1 - 0.65 - µs
DG528,
DG529 See Figure 3 - 0.6 1 - 0.6 - µs
Break-Before-
Make Interval,
tOPEN
DG526,
DG527 See Figure 4 - 0.2 - - 0.2 - µs
DG528,
DG529 - 0.2 - - 0.2 - µs
Enable and
Write Turn-ON
Time,
tON (EN, WR)
DG526,
DG527 See Figures 1, 6 (Note 7) - 0.7 1.5 - 0.7 - µs
DG528,
DG529 See Figures 5, 6 (Note 7) - 1 1.5 - 1 - µs
Enable and
Reset Turn
OFF Time,
tOFF (EN, RS)
DG526,
DG527 See Figures 2, 7 (Note 7) - 0.4 1 - 0.4 - µs
DG528,
DG529 See Figures 5, 6 (Note 7) - 0.4 1 - 0.4 - µs
Off Isolation,
OIRR DG526,
DG527 VEN = 0V, R = 1kΩ, CL = 15pF,
VS = 7VRMS, f = 500kHz (Note 4) -55--55-dB
DG528,
DG529 -68--68-dB
Logic Input
Capacitance,
CIN
DG526,
DG527 f = 1MHz - 6 - - 6 - pF
DG528,
DG529 - 2.5 - - 2.5 - pF
Source OFF
Capacitance,
CS(OFF)
DG526,
DG527 VS = 0V VEN = 0V,
f = 140kHz -10--10-pF
DG528,
DG529 -5--5-pF
DG526, DG527, DG528, DG529
12-6
Drain OFF
Capacitance,
CD(OFF)T
DG526 VD = 0V VEN = 0V,
f = 140kHz -65--65-pF
DG527 - 35 - - 35 - pF
DG528 - 25 - - 25 - pF
DG529 - 12 - - 12 - pF
Charge
Injection, Q DG526,
DG527 See Figure 8 - 6 - - 6 - pC
DG528,
DG529 -4--4-pC
INPUT
Address Input
Current, Input
Voltage High,
IAH
DG526,
DG527 VA = 2.4V -10 0.02 - -10 0.02 - µA
VA = 15V - 0.02 10 - 0.02 10 µA
DG528,
DG529 VA = 2.4V -10 -0.002 - -10 -0.002 - µA
VA = 15V - 0.006 10 - 0.006 10 µA
Address Input
Current, Input
Voltage Low,
IAL
DG526
DG527 VEN = 2.4V All VA = 0V,
RS = 0V,
WR = 0V
-10 0.01 - -10 0.01 - µA
VEN = 0V -10 0.01 - -10 0.01 - µA
DG528
DG529 VEN = 2.4V -10 -0.002 - -10 -0.002 - µA
VEN = 0V -10 -0.002 - -10 -0.002 - µA
SWITCH
Analog Signal Range,
VANALOG (Note 7) -15 - +15 -15 - +15 V
Drain Source ON
Resistance, rDS(ON) VD = ±10V, VAL = 0.8V, VAH = 2.4V,
IL = -200µA
Sequence Each Switch ON
- 270 400 - 270 450 Ω
Greatest Change in Drain
Source ON Resistance
Between Channels,
∆rDS(ON)
-10V ≤VS≤10V - 6 - - 6 - %
Source OFF
Leakage
Current,
IS(OFF)
DG526,
DG527 VEN = 0V VS = ±10V,
VD = +10V -1 0.02 1 - 0.02 - nA
DG528,
DG529 VS = ±10V,
VD = +10V -1 -0.005 1 -5 -0.005 5 nA
Drain OFF
Leakage
Current,
ID(OFF)
DG526 VEN = 0V VS = ±10V,
VD = +10V -10 0.2 10 - 0.2 - nA
DG527 VS = ±10V,
VD = +10V -5 0.2 5 - 0.2 - nA
DG528 VS = ±10V,
VD = +10V -10 -0.015 10 -20 0.015 20 nA
DG529 VS = ±10V,
VD = +10V -10 -0.008 10 -20 0.008 20 nA
Drain ON
Leakage
Current, ID(ON)
DG526 Sequence Each
Switch On
VAL = 0.8V and
VAH = 2.4V
(Note 5)
VD = VS(ALL) =
±10V -10 0.2 10 - 0.2 - nA
DG527 VD = VS(ALL) =
±10V -5 0.2 5 - 0.2 - nA
Electrical Specifications (Note 3) V+ = +15V, V- = -15V, GND = 0V, WR = 0V, RS = 2.4V, EN = 2.4V, TA = 25oC,
Unless Otherwise Specified (Continued)
PARAMETER (NOTE 6)
TEST CONDITIONS
A SUFFIX B AND C SUFFIX
UNITSMIN (NOTE 2)
TYP MAX MIN (NOTE 2)
TYP MAX
DrDS(ON)=rDS(ON)MAX - rDS(ON)MIN
rDS(ON)AVG.
DG526, DG527, DG528, DG529
12-7
Drain ON
Leakage
Current, ID(ON)
(Continued)
DG528 Sequence Each
Switch On
VAL = 0.8V and
VAH = 2.4V
(Note 5)
VD = VS(ALL) =
±10V -10 -0.03 10 -20 -0.03 20 nA
DG529 VD = VS(ALL) =
±10V -10 -0.015 10 -20 -0.015 20 nA
SUPPLY
Positive
Supply
Current, I+
DG526,
DG527 VEN = 0V All VA = 0V - 2.0 3.0 - 2.0 - mA
DG528,
DG529 - - 2.5 - - -2.5 mA
Positive
Supply
Current, I-
DG526,
DG527 VEN = 0V All VA = 0V -2.0 -1.2 - - -1.2 - mA
DG528,
DG529 -1.5 - - -1.5 - - mA
Electrical Specifications TA = Over Operating Temperature Range, V+ = +15V, V- = -15V, GND = 0V, WR = 0V,
RS = 2.4V, EN = 2.4V Unless Otherwise Specified
PARAMETER (NOTE 6)
TEST CONDITIONS
A SUFFIX B AND C SUFFIX
UNITSMIN (NOTE 2)
TYP MAX MIN (NOTE 2)
TYP MAX
INPUT
Address Input Current
Input Voltage High, IAH VA = 2.4V -30 - - -30 - - µA
VA = 15V - - 30 - - 30 µA
Address Input
Current, Input
Voltage Low,
IAL
DG526,
DG527 VA = 2.4V VA(ALL) =
0V,
RS = 0V,
WR = 0V
-10-----µA
VA = 0V -10 - - - - - µA
DG528,
DG529 -30 - - -30 - - µA
VA = 0V -30 - - -30 - - µA
SWITCH
Analog Signal Range,
VANALOG Note 7 -15 - +15 - - - %
Drain Source ON
Resistance, rDS(ON) VD = ±10V, VAL = 0.8V, VAH = 2.4V,
IS = -200µA, Sequence Each Switch ON - - 500 - - 500 Ω
Source Off Leakage
Current, IS(OFF) VEN = 0V VS = ±10V,
VD = +10V -50 - 50 - - - nA
Drain OFF
Leakage
Current,
ID(OFF)
DG526 VEN = 0V VS = ±10V,
VD = +10V -300 - 300 -300 - 300 nA
DG527 -200 - 200 -200 - 200 nA
DG528 VS = +10V,
VD = ±10V -200 - 200 -200 - 200 nA
DG529 -100 - 100 -100 - 100 nA
Drain ON
Leakage
Current, ID(ON)
DG526 Sequence Each Switch
On, VAL = 0.8V,
VAH = 2.4V (Note 5)
VD =
VS(ALL) =
±10V
-300 - 300 -300 - 300 nA
DG527 -200 - 200 -200 - 200 nA
DG528 -200 - 200 -200 - 200 nA
DG529 -100 - 100 -100 - 100 nA
Electrical Specifications (Note 3) V+ = +15V, V- = -15V, GND = 0V, WR = 0V, RS = 2.4V, EN = 2.4V, TA = 25oC,
Unless Otherwise Specified (Continued)
PARAMETER (NOTE 6)
TEST CONDITIONS
A SUFFIX B AND C SUFFIX
UNITSMIN (NOTE 2)
TYP MAX MIN (NOTE 2)
TYP MAX
DG526, DG527, DG528, DG529
12-8
Minimum Input Timing Requirements Over Full Temperature Range
PARAMETER MEASURED TERMINAL MIN UNITS
WRITE Pulse Width, tWW WR, See Figure 1 300 ns
A, EN Data Valid After WRITE (Stabilization Time), tDW A0, A1, (A2), EN, WR; See Figure 1 180 ns
A, EN Data Valid After WRITE (Hold Time), tWD A0, A1, (A2), EN, WR; See Figure 1 30 ns
RESET Pulse Width, tRS RS, (Note 6), VS = 5V, See Figure 2 500 ns
NOTES:
1. Signals on VS, VD or VIN e xceeding V+ or V- will be clamped by internal diodes. Limit diode forward current to maxim um current ratings .
2. Typical values are for design aid only, not guaranteed and not subject to production testing.
3. The algebraic convention whereby the most negative value is a minimum, and most positive value is a maximum, is used in this datasheet.
4. , where VS = input to OFF switch, and VD = output due to VS.
5. ID(ON) is leakage from driver into “ON” switch.
6. Period of Reset (RS) pulse must be at least 50µs during or after power ON.
7. Parameter not tested. Parameter guaranteed by design or characterization.
Test Circuits and Waveforms
FIGURE 1. WR TIMING WAVEFORMS FIGURE 2. RS TIMING WAVEFORMS
FIGURE 3A. tTRANSITION SWITCHING TIME TEST CIRCUIT
† Similar connections for DG526
FIGURE 3B. tTRANSITION SWITCHING TIME TEST CIRCUIT
† Similar connections for DG527
OFF Isolation 20 VS
VD
----------
=
3V
0
WR
A0, A1, (A2)3V
0
1.5V
tWW
tDW tWD
2.0V
0.8V
EN
3V
0
RS
VO
0V
SWITCH
OUTPUT
1.5V
tRS
tOFF(RS)
0.8VO
EN
RS
A0
S2 THRU S7
A1
A2
LOGIC
INPUT
50Ω
+2.4V
SWITCH
OUTPUT
35pF1MΩ
+15V
-15V
+10V
±10V
GND WR V-
DG528†S1
S8
D
V+
VD
EN
RS S2A THRU S4A,
A0
A1
LOGIC
INPUT
50Ω
+2.4V
SWITCH
OUTPUT
35pF1MΩ
+15V
-15V
+10V
±10V
GND WR V-
DG529†S1B
S4B
DB
V+
DA
S2B, AND S3B
VDB
DG526, DG527, DG528, DG529
12-9
FIGURE 3C. tTRANSITION SWITCHING TIME WAVEFORM
FIGURE 4A. tOPEN (BREAK-BEFORE-MAKE) SWITCHING TIME
WAVEFORM FIGURE 4B. tOPEN (BREAK-BEFORE-MAKE) SWITCHING TIME
TEST CIRCUIT
† Similar connections for DG526, DG527
FIGURE 5A. ENABLE tON AND tOFF SWITCHING TIME TEST
CIRCUIT
† Similar connections for DG526
FIGURE 5B. ENABLE tON AND tOFF SWITCHING TIME TEST
CIRCUIT
† Similar connections for DG527
Test Circuits and Waveforms
(Continued)
3V
50%
0
VS1
0.8VS1
0
0.8VS8
VS8
SWITCH
OUTPUT
VD
TRANSITION
S1 ON
S8 ON
TRANSITION
LOGIC INPUT
tr < 20ns
tf < 20ns
3V
50%
0
VS
80%
0V tOPEN
SWITCH
OUTPUT
VD
LOGIC INPUT
tr < 20ns
tf < 20ns
EN
RS
A0,A
1, (A2)
LOGIC
INPUT
50Ω
+2.4V
SWITCH
OUTPUT
35pF1kΩ
+15V
-15V
GND WR V-
DG528†
DB (D)
V+
ALL S AND DA
VD
DG529
+5V
EN
RS
A0
S2 THRU S7
A1
A2
EN 50Ω
+2.4V
SWITCH
OUTPUT
35pF1kΩ
+15V
-15V
GND WR V-
DG528†S1
D
V+
VD
-5V EN
RS
S1A THRU S4A,
A0
A1
EN 50Ω
+2.4V
SWITCH
OUTPUT
35pF1kΩ
+15V
-15V
GND WR V-
DG529†S1B
DB
V+
VDB
-5V
DA, S2B, S3B,
S4B
DG526, DG527, DG528, DG529
12-10
FIGURE 5C. ENABLE tON AND tOFF SWITCHING TIME WAVEFORMS
FIGURE 6A. WRITE tON SWITCHING TIME WAVEFORMS FIGURE 6B. WRITE tON SWITCHING TIME TEST CIRCUIT
† Similar connections for DG526, DG527
FIGURE 7A. RESET tOFF SWITCHING TIME WAVEFORMS FIGURE 7B. RESET tOFF SWITCHING TIME TEST CIRCUIT
† Similar connections for DG526, DG527
Test Circuits and Waveforms
(Continued)
3V
50%
0
0.1VO
0.9VO
SWITCH
OUTPUT
VD
EN
tr < 20ns
tf < 20ns
0
VO
VS
tON (EN) tOFF (EN)
tr < 20ns
tf < 20ns
3V
1.5V
0V
SWITCH
OUTPUT
VO
0V
tON (WR)
0.2VO
50%
Device must be reset prior to applying WR pulse.
EN
A0, A1, (A2)
REMAINING
RS
WR
LOGIC
INPUT
+2.4V
SWITCH
OUTPUT
35pF
1kΩ
+15V
-15V
GND V-
DG528 S1 OR
DB(D)
V+
SWITCHES
VO
DG529†S1B +5V
WR
RS
tr < 20ns
tf < 20ns
3V
1.5V
0V
SWITCH
OUTPUT
VO
tOFF (RS)
0.8VO
RS 50%
EN
RS
A0, A1, (A2)
+2.4V
SWITCH
OUTPUT
35pF1kΩ
+15V
-15V
GND WR V-
DG528
DB (D)
V+
VO
DG529†+5V
REMAINING
SWITCHES
RS
S1 OR
S1B
DG526, DG527, DG528, DG529
12-11
FIGURE 8A. CHARGE INJECTION WAVEFORMS FIGURE 8B. CHARGE INJECTION TEST CIRCUIT
† Similar connections for DG526, DG527
Test Circuits and Waveforms
(Continued)
3V
EN
0
VO∆VO
∆VO is the measured voltage error due to charge injection.
The error voltage in Coulombs is Q = CL x ∆VO.
EN
A0, A1, (A2)
CL = 1000pF
+15V
-15V
GND WR V-
DG528
D
V+
DG529†
RS
VO
+2.4V
Sx
Typical Performance Curves
FIGURE 9. rDS(ON) vs ANALOG SIGNAL V OL TA GE vs SUPPLY
VOLTAGE FIGURE 10. TYPICAL rDS(ON) VARIATION WITH TEMPERATURE
550
500
450
400
350
300
250
200
150
100
50
0
rDS (ON) (Ω)
-15
ANALOG SIGNAL VOLTAGE (V)
-13 -11 -9 -7 -5 -3 -1 0 +1 +3 +5 +7 +9 +11+13 +15
IO = -200µA
VEN = +5V
(A) V+ = +15V, V- = -15V
(B) V+ = +12V, V- = -12V
(C) V+ = +10V, V- = -10V
(D) V+ = +7.5V, V- = -7.5V
(A)
(B)
(C)
(D)
-55
TEMPERATURE (oC)
-25 25 45 70 100 125
400
360
320
280
240
200
160
120
80
40
0
rDS(ON) (Ω)
0
V+ = +15V V- = -15V
VEN = 2.4V
IO = -200µA+10V SIGNALS
+10V SIGNALS
DG526, DG527, DG528, DG529
12-12
Truth Tables
DG526
A3A2A1A0EN WR RS ON SWITCH
Latching XXXXX 1Maintains
Previous
Switch State
Reset XXXXXX0None
(Latches
Cleared)
Trans-
parent
Operation
XXXX001 None
0000101 1
0001101 2
0010101 3
0011101 4
0100101 5
0101101 6
0110101 7
0111101 8
1000101 9
1001101 10
1010101 11
1011101 12
1100101 13
1101101 14
1110101 15
1111101 16
Logic “0” = VAL, VENL ≤0.8V
DG528
A2A1A0EN WR RS ON SWITCH
XXXX 1Maintains Previous
Switch Condition
XXXXX0None (Latches Cleared)
X X X 0 0 1 None
000101 1
001101 2
010101 3
011101 4
100101 5
101101 6
110101 7
111101 8
DG527
A2A1A0EN WR RS ON SWITCH
Latching XXXX 1Maintains
Previous
Switch State
Reset XXXXX0None
(Latches
Cleared)
Trans-
parent
Operation
X X X 0 0 1 None
000101 1
001101 2
010101 3
011101 4
100101 5
101101 6
110101 7
111101 8
Logic “1” = VAH, VENH ≥2.4V
DG529
A1A0EN WR RS ON SWITCH
X X X 1 Maintains Previous Switch
Condition
XXXX0None (Latches Cleared)
X X 0 0 1 None
00101 1
01101 2
10101 3
11101 4
Logic “1”: VAH ≥2.4V
Logic “0”: VAL ≤0.8V
DG526, DG527, DG528, DG529
12-13
Die Characteristics
DIE DIMENSIONS:
3810µm x 2769µm
METALLIZATION:
Type: Al
Thickness: 10kű1kÅ
PASSIVATION:
Type: PSG Over Nitride
PSG Thickness: 7kű1.4kÅ
Nitride Thickness: 8kű1.2kÅ
WORST CASE CURRENT DENSITY:
9.1 x 104 A/cm2
Metallization Mask Layout
DG526
PIN 12
GND
PIN 13
WR
PIN 14
A3
PIN 15
A2
PIN 16
A1
PIN 17
A0
PIN18
EN
PIN 3
RS
PIN 2
NC
PIN 1
V+
PIN 28
D
PIN 27
V-
PIN 4
S16
PIN 5
S15
PIN 6
S14
PIN 7
S13
PIN 8
S12
PIN 9
S11
PIN 10
S10
PIN 11
S9
PIN 19
S1
PIN 20
S2
PIN 21
S3
PIN 22
S4
PIN 23
S5
PIN 24
S6
PIN 25
S7
PIN 26
S8
DG526, DG527, DG528, DG529
12-14
Die Characteristics
DIE DIMENSIONS:
3810µm x 2769µm
METALLIZATION:
Type: Al
Thickness: 10kű1kÅ
PASSIVATION:
Type: PSG Over Nitride
PSG Thickness: 7kű1.4kÅ
Nitride Thickness: 8kű1.2kÅ
WORST CASE CURRENT DENSITY:
9.1 x 104 A/cm2
Metallization Mask Layout
DG527
PIN 12
GND
PIN 13
WR
PIN 14
NC
PIN 15
A2
PIN 16
A1
PIN 17
A0
PIN18
EN
PIN 3
RS
PIN 2
DB
PIN 1
V+
PIN 28
DA
PIN 27
V-
PIN 11
S1B
PIN 10
S2B
PIN 9
S3B
PIN 8
S4B
PIN 7
S5B
PIN 6
S6B
PIN 5
S7B
PIN 4
S8B
PIN 19
S1A
PIN 20
S2A
PIN 21
S3A
PIN 22
S4A
PIN 23
S5A
PIN 24
S6A
PIN 25
S7A
PIN 26
S8A
DG526, DG527, DG528, DG529
12-15
Die Characteristics
DIE DIMENSIONS:
3100µm x 2083µm
METALLIZATION:
Type: Al
Thickness: 10kű1kÅ
PASSIVATION:
Type: PSG Over Nitride
PSG Thickness: 7kű1.4kÅ
Nitride Thickness: 8kű1.2kÅ
WORST CASE CURRENT DENSITY:
9.1 x 104 A/cm2
Metallization Mask Layout
DG528
PIN 2
A0
PIN 1
WR
PIN 18
RS
PIN 17
A1
PIN 16
A2
PIN 3
EN
PIN 7
S3
PIN 6
S2
PIN 5
S1
PIN 4
V-
PIN 11
S7
PIN 13
S5
PIN 14
V+
PIN 15
GND PIN 12
S6
PIN 8
S4
PIN 9
D
PIN 10
S8
DG526, DG527, DG528, DG529
12-16
Die Characteristics
DIE DIMENSIONS:
3100µm x 2083µm
METALLIZATION:
Type: Al
Thickness: 10kű1kÅ
PASSIVATION:
Type: PSG Over Nitride
PSG Thickness: 7kű1.4kÅ
Nitride Thickness: 8kű1.2kÅ
WORST CASE CURRENT DENSITY:
9.1 x 104 A/cm2
Metallization Mask Layout
DG529
PIN 7
S3A
PIN 6
S2A
PIN 5
S1A
PIN 4
V-
PIN 11
S4B
PIN 13
S2B
PIN 14
S1G
PIN 15
V+ PIN 12
S3B
PIN 2
A0
PIN 1
WR
PIN 18
RS
PIN 17
A1
PIN 16
GND
PIN 3
EN
PIN 8
S4A
PIN 9
DA
PIN 10
S8A
DG526, DG527, DG528, DG529
