IS62/65WV102416EALL
IS62/65WV102416EBLL
Integrated Silicon Solution, Inc.- www.issi.com 1
Rev. A1
2/22/2016
1Mx16 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
KEY FEATURES
High-speed access time: 45ns, 55ns
CMOS low power operation
– Operating (typical):
- 10.8mW (1.8V), 18mW (3.0V)
– CMOS Standby (typical):
- 48 µW (1.8V), 90 µW (3.0V)
TTL compatible interface levels
Single power supply
–1.65V—1.98V Vdd (62/65WV102416EALL)
– 2.2V--3.6V Vdd (62/65WV102416EBLL)
Data control for upper and lower bytes
Industrial and Automotive temperature support
DESCRIPTION
The IS62WV102416EALL/BLL and
IS65WV102416EALL/BLL are Low Power, 16M bit
static RAMs organized as 1024K words by 16bits. It is
fabricated using 's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields high-
performance and low power consumption devices.
When is HIGH (deselected) or when CS2 is low
(deselected) or when is low , CS2 is high and both
and are HIGH, the device assumes a standby
mode at which the power dissipation can be reduced
down with CMOS input levels.
Easy memory expansion is provided by using Chip
Enable and Output Enable inputs. The active LOW
Write Enable controls both writing and reading of
the memory. A data byte allows Upper Byte and
Lower Byte ( access.
The IS62WV102416EALL/BLL and
IS65WV102416EALL/BLL are packaged in the JEDEC
standard 48-pin BGA (6mm x 8mm).
BLOCK DIAGRAM
Copyright © 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
FEBRUARY 2016
IS62/65WV102416EALL
IS62/65WV102416EBLL
Integrated Silicon Solution, Inc.- www.issi.com 2
Rev. A1
2/22/2016
PIN CONFIGURATIONS
48-PIN BGA
1 2 3 4 5 6
AA0 A1 A2 CS2
BI/O8 A3 A4 I/O0
CI/O9 I/O10 A5 A6 I/O1 I/O2
DGND I/O11 A17 A7 I/O3 VDD
EVDD I/O12 NC A16 I/O4 GND
FI/O14 I/O13 A14 A15 I/O5 I/O6
GI/O15 A19 A12 A13 I/O7
HA18 A8 A9 A10 A11 NC
PIN DESCRIPTIONS – 2 CS OPTION
A0-A19
Address Inputs
I/O0-I/O15
Data Inputs/Outputs
, CS2
Chip Enable Inputs
Output Enable Input
Write Enable Input
Lower-byte Control (I/O0-I/O7)
Upper-byte Control (I/O8-I/O15)
NC
No Connection
VDD
Power
GND
Ground
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Rev. A1
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FUNCTION DESCRIPTION
SRAM is one of random access memories. Each byte or word has an address and can be accessed randomly. SRAM
has three different modes supported. Each function is described below with Truth Table.
STANDBY MODE
Device enters standby mode when deselected ( HIGH or CS2 LOW or both and are HIGH). The input and
output pins (I/O0-15) are placed in a high impedance state. The current consumption in this mode will be either ISB1 or
ISB2 depending on the input level. CMOS input in this mode will maximize saving power.
WRITE MODE
Write operation issues with Chip selected ( LOW and CS2 HIGH) and Write Enable ( ) input LOW. The input and
output pins(I/O0-15) are in data input mode. Output buffers are closed during this time even if is LOW. and
enables a byte write feature. By enabling LOW, data from I/O pins (I/O0 through I/O7) are written into the location
specified on the address pins. And with being LOW, data from I/O pins (I/O8 through I/O15) are written into the
location.
READ MODE
Read operation issues with Chip selected ( LOW and CS2 HIGH) and Write Enable ( ) input HIGH. When is
LOW, output buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted. and
enables a byte read feature. By enabling LOW, data from memory appears on I/O0-7. And with being LOW,
data from memory appears on I/O8-15.
In the READ mode, output buffers can be turned off by pulling HIGH. In this mode, internal device operates as
READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used.
TRUTH TABLE
Mode
CS2
I/O0-I/O7
I/O8-I/O15
VDD Current
Not Selected
H
X
X
X
X
High-Z
High-Z
ISB1,ISB2
X
L
X
X
X
High-Z
High-Z
X
X
X
X
H
High-Z
High-Z
Output Disabled
L
H
H
H
X
High-Z
High-Z
ICC
L
H
H
H
L
High-Z
High-Z
Read
L
H
H
L
H
DOUT
High-Z
ICC
L
H
H
L
L
High-Z
DOUT
L
H
H
L
L
DOUT
DOUT
Write
L
H
L
X
H
DIN
High-Z
ICC
L
H
L
X
L
High-Z
DIN
L
H
L
X
L
DIN
DIN
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Rev. A1
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ABSOLUTE MAXIMUM RATINGS
AND OPERATING RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
Vterm
Terminal Voltage with Respect to GND
–0.2 to +3.9(VDD+0.3V)
V
tBIAS
Temperature Under Bias
–55 to +125
C
VDD
VDD Related to GND
–0.2 to +3.9(VDD+0.3V)
V
tStg
Storage Temperature
–65 to +150
C
IOUT
DC Output Current (LOW)
20
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING RANGE
(1)
Range
Device Marking
Ambient Temperature
VDD(min)
VDD(typ)
VDD(max)
Commercial
IS62WV102416EALL
0C to +70C
1.65V
1.8V
1.98V
Industrial
IS62WV102416EALL
-40C to +85C
1.65V
1.8V
1.98V
Automotive
IS65WV102416EALL
-40C to +125C
1.65V
1.8V
1.98V
Commercial
IS62WV102416EBLL
0C to +70C
2.2V
3.3V
3.6V
Industrial
IS62WV102416EBLL
-40C to +85C
2.2V
3.3V
3.6V
Automotive
IS65WV102416EBLL
-40C to +125C
2.2V
3.3V
3.6V
Note:
1. Full device AC operation assumes a 100 µs ramp time from 0 to Vcc(min) and 200 µs wait time after Vcc stabilization.
PIN CAPACITANCE (1)
Parameter
Symbol
Test Condition
Max
Units
Input capacitance
CIN
TA = 25°C, f = 1 MHz, VDD = VDD(typ)
10
pF
DQ capacitance (IO0–IO15)
CI/O
10
pF
Note:
1. These parameters are guaranteed by design and tested by a sample basis only.
THERMAL CHARACTERISTICS (1)
Parameter
Symbol
Rating
Units
Thermal resistance from junction to ambient (airflow = 0m/s)
RθJA
43.05
°C/W
Thermal resistance from junction to case
RθJC
5.75
°C/W
Note:
1. These parameters are guaranteed by design and tested by a sample basis only.
IS62/65WV102416EALL
IS62/65WV102416EBLL
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Rev. A1
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ELECTRICAL CHARACTERISTICS
IS62(5)WV102416EALL
DC ELECTRICAL CHARACTERISTICS-I
(OVER THE OPERATING RANGE)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH Voltage
IOH = -0.1 mA
1.4
—
V
VOL
Output LOW Voltage
IOL = 0.1 mA
—
0.2
V
VIH
(1)
Input HIGH Voltage
1.4
VDD + 0.2
V
VIL
(1)
Input LOW Voltage
–0.2
0.4
V
ILI
Input Leakage
GND < VIN < VDD
–1
1
µA
ILO
Output Leakage
GND < VIN < VDD, Output Disabled
–1
1
µA
Notes:
1. VILL(min) = -1.0V AC (pulse width < 10ns). Not 100% tested.
VIHH (max) = VDD + 1.0V AC (pulse width < 10ns). Not 100% tested.
IS62(5)WV102416EBLL
DC ELECTRICAL CHARACTERISTICS-I
(OVER THE OPERATING RANGE)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH Voltage
2.2 ≤ VDD < 2.7, IOH = -0.1 mA
2.0
—
V
2.7 ≤ VDD ≤ 3.6, IOH = -1.0 mA
2.4
—
V
VOL
Output LOW Voltage
2.2 ≤ VDD < 2.7, IOL = 0.1 mA
—
0.4
V
2.7 ≤ VDD ≤ 3.6, IOL = 2.1 mA
—
0.4
V
VIH
(1)
Input HIGH Voltage
2.2 ≤ VDD < 2.7
1.8
VDD + 0.3
V
2.7 ≤ VDD ≤ 3.6
2.2
VDD + 0.3
V
VIL
(1)
Input LOW Voltage
2.2 ≤ VDD < 2.7
–0.3
0.6
V
2.7 ≤ VDD ≤ 3.6
–0.3
0.8
V
ILI
Input Leakage
GND < VIN < VDD
–1
1
µA
ILO
Output Leakage
GND < VIN < VDD, Output Disabled
–1
1
µA
Notes:
1. VILL(min) = -2.0V AC (pulse width < 10ns). Not 100% tested.
VIHH (max) = VDD + 2.0V AC (pulse width < 10ns). Not 100% tested.
IS62/65WV102416EALL
IS62/65WV102416EBLL
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Rev. A1
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IS62(5)WV102416EALL
DC ELECTRICAL CHARACTERISTICS-II FOR POWER
(OVER THE OPERATING RANGE)
Symbol
Parameter
Test Conditions
Grade
Typ.
Max.
Unit
ICC
VDD Dynamic
Operating
Supply Current
VDD=VDD(max), IOUT=0mA, f=fMAX
Com.
6
12
mA
Ind.
-
12
Auto.
-
12
ICC1
VDD Static
Operating
Supply Current
VDD=VDD(max), IOUT = 0mA, f=0Hz
Com.
3
6
mA
Ind.
-
6
Auto.
-
6
ISB1
CMOS Standby
Current (CMOS
Inputs)
VDD=VDD(max),
(1) 0V ≤ CS2 ≤ 0.2V
or
(2) ≥ VDD - 0.2V, CS2 ≥ VDD - 0.2V
or
(3) and ≥ VDD- 0.2V
≤ 0.2V, CS2 ≥ VDD - 0.2V
Com.
30
50
µA
Ind.
-
65
µA
Auto.
-
165
µA
Note:
Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VDD = VDD(typ), TA = 25C
IS62(5)WV102416EBLL
DC ELECTRICAL CHARACTERISTICS-II FOR POWER
(OVER THE OPERATING RANGE)
Symbol
Parameter
Test Conditions
Grade
Typ.
Max.
Unit
ICC
VDD Dynamic
Operating
Supply Current
VDD=VDD(max), IOUT=0mA, f=fMAX
Com.
6
12
mA
Ind.
-
12
Auto.
-
12
ICC1
VDD Static
Operating
Supply Current
VDD=VDD(max), IOUT = 0mA, f=0Hz
Com.
3
6
mA
Ind.
-
6
Auto.
-
6
ISB1
CMOS Standby
Current (CMOS
Inputs)
VDD=VDD(max),
(1) 0V ≤ CS2 ≤ 0.2V
or
(2) ≥ VDD - 0.2V, CS2 ≥ VDD - 0.2V
or
(3) and ≥ VDD- 0.2V
≤ 0.2V, CS2 ≥ VDD - 0.2V
Com.
30
50
µA
Ind.
-
65
µA
Auto.
-
165
µA
Note:
Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VDD = VDD(typ), TA = 25℃
IS62/65WV102416EALL
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Rev. A1
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AC CHARACTERISTICS
(6)
(OVER OPERATING RANGE)
READ CYCLE AC CHARACTERISTICS
Parameter
Symbol
45ns
55ns
unit
notes
Min
Max
Min
Max
Read Cycle Time
tRC
45
-
55
-
ns
1,5
Address Access Time
tAA
-
45
-
55
ns
1
Output Hold Time
tOHA
8
-
8
-
ns
1
, CS2 Access Time
tACS1/tACS2
-
45
-
55
ns
1
Access Time
tDOE
-
22
-
25
ns
1
to High-Z Output
tHZOE
-
18
-
18
ns
2
to Low-Z Output
tLZOE
5
-
5
-
ns
2
, CS2 to High-Z Output
tHZCS//tHZCS2
-
18
-
18
ns
2
, CS2 to Low-Z Output
tLZCS/tLZCS2
10
-
10
-
ns
2
, Access Time
tBA
-
45
-
55
ns
1
, to High-Z Output
tHZB
-
18
-
18
ns
2
, to Low-Z Output
tLZB
10
-
10
-
ns
2
WRITE CYCLE AC CHARACTERISTICS
Parameter
Symbol
45ns
55ns
unit
notes
Min
Max
Min
Max
Write Cycle Time
tWC
45
-
55
-
ns
1,3,5
,CS2 to Write End
tSCS1/tSCS2
35
-
40
-
ns
1,3
Address Setup Time to Write End
tAW
35
-
40
-
ns
1,3
Address Hold from Write End
tHA
0
-
0
-
ns
1,3
Address Setup Time
tSA
0
-
0
-
ns
1,3
, / Valid to End of Write
tPWB
35
-
40
-
ns
1,3
Pulse Width
tPWE
35
-
40
-
ns
1,3,4
Data Setup to Write End
tSD
28
-
28
-
ns
1,3
Data Hold from Write End
tHD
0
-
0
-
ns
1,3
LOW to High-Z Output
tHZWE
-
18
-
18
ns
2,3
HIGH to Low-Z Output
tLZWE
10
-
10
-
ns
2,3
Notes:
1. Tested with the load in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. tHZOE, tHZCS, tHZB, and tHZWE transitions are
measured when the output enters a high impedance state. Not 100% tested.
3. The internal write time is defined by the overlap of =LOW, CS2=HIGH, ( or )=LOW, and =LOW. All four conditions must be in valid
states to initiate a Write, but any condition can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
4. tPWE > tHZWE + tSD when OE is LOW.
5. Address inputs must meet VIH and VIL SPEC during this period. Any glitch or unknown inputs are not permitted. Unknown input with standby
mode is acceptable.
6. Data retention characteristics are defined later in DATA RETENTION CHARACTERISTICS.
IS62/65WV102416EALL
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AC TEST CONDITIONS (OVER THE OPERATING RANGE)
Parameter
Symbol
Conditions
Units
Input Rise Time
TR
1.0
V/ns
Input Fall Time
TF
1.0
V/ns
Output Timing Reference Level
VREF
½ VTM
V
Output Load Conditions
Refer to Figure 1 and 2
OUTPUT LOAD CONDITIONS FIGURES
Figure1 Figure2
Parameters
VDD=1.65~1.98V
VDD=2.2~2.7V
VDD=2.7~3.6V
R1
13500Ω
16667Ω
1103Ω
R2
10800Ω
15385Ω
1554Ω
VTM
VDD
VDD
VDD
30pF,
including
jig and
scope
R2
R1
VTM
OUTPUT
5pF,
including
jig and
scope
R2
R1
VTM
OUTPUT
IS62/65WV102416EALL
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TIMING DIAGRAM
READ CYCLE NO. 1(1,2) (ADDRESS CONTROLLED) ( = =VIL, CS2= =VIH)
READ CYCLE NO. 2(1,3) ( , CS2, , AND & CONTROLLED)
Notes:
1. is HIGH for Read Cycle.
2. The device is continuously selected. , , , or =VIL.CS2= =VIH.
3. Address is valid prior to or coincident with LOW transition.
tRC
ADDRESS
CS2
,
I/O0-15
tAA
tDOE
DATA VALID
LOW-Z
HIGH-Z
tLZB
tBA
tHZB
tHZCS1/
tHZCS2
tLZCS1/
tLZCS2
tACS1/tACS2
tLZOE
tHZOE
tOHA
tRC
ADDRESS
I/O0-15
tAA
tOHA
tOHA
DATA VALID
PREVIOUS DATA VALID
Low-Z
Low-Z
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WRITE CYCLE NO. 1 ( CONTROLLED, = HIGH OR LOW)
Notes:
1. tHZWE is based on the assumption when tSA=0nS after READ operation. Actual DOUT for tHZWE may not appear if goes high before
Write Cycle. tHZOE is the time DOUT goes to High-Z after goes high.
2. During this period the I/Os are in output state. Do not apply input signals.
WRITE CYCLE NO. 2 ( CONTROLLED: IS HIGH DURING WRITE CYCLE)
Notes:
1. tHZWE is based on the assumption when tSA=0nS after READ operation. Actual DOUT for tHZWE may not appear if goes high before
Write Cycle. tHZOE is the time DOUT goes to High-Z after goes high.
2. During this period the I/Os are in output state. Do not apply input signals.
tWC
ADDRESS
CS2
,
DOUT
tSCS1
tAW
tLZWE
tHZWE
tSA
tPWE
tPWB
tSCS2
DIN
tHA
tSD
tHD
DATA VALID
DATA UNDEFINED(2)
DATA UNDEFINED(1)
tWC
ADDRESS
CS2
DOUT
tSCS1
tAW
tLZWE
tHZWE
tSA
tPWE
tSCS2
DIN
tHA
tSD
tHD
DATA VALID
DATA UNDEFINED(2)
DATA UNDEFINED(1)
HIGH-Z
tPWB
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WRITE CYCLE NO. 3 ( CONTROLLED: IS LOW DURING WRITE CYCLE)
Notes:
1. If is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the previous
READ operation will drive IO BUS.
tWC
ADDRESS
CS2
DOUT
tSCS1
tAW
tLZWE
tHZWE
tSA
tPWE
tSCS2
DIN
tHA
tSD
tHD
DATA VALID
DATA UNDEFINED(1)
DATA UNDEFINED(1)
HIGH-Z
LOW
tPWB
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WRITE CYCLE NO. 4 ( & CONTROLLED)
Notes:
1. If is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the previous
READ operation will drive IO BUS.
2. Due to the restriction of note1, is recommended to be HIGH during write period.
3. Note stays LOW in this example. If toggles, tPWE and tHZWE must be considered.
tWC
tWC
CS2
LOW
HIGH
DATA UNDEFINED(1)
DATA
VALID
DATA
VALID
tHD
tSD
tHD
tLZWE
tHZWE
tPWB
tHA
tHA
tSA
ADDRESS
DOUT
DIN
tPWB
tSD
tSA
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DATA RETENTION CHARACTERISTICS
Symbol
Parameter
Test Condition
OPTION
Min.
Typ.(2)
Max.
Unit
VDR
VDD for Data
Retention
See Data Retention Waveform
IS62(5)WV102416EALL
1.5
-
V
IS62(5)WV102416EBLL
1.5
-
V
IDR
Data Retention
Current
VDD= VDR(min),
(1) 0V ≤ CS2 ≤ 0.2V, or
(2) ≥ VDD – 0.2V,
CS2 ≥ VDD - 0.2V
(3) and ≥ VDD -0.2V,
≤ 0.2V, CS2 ≥ VDD - 0.2V
Com.
-
-
50
uA
Ind.
-
-
65
Auto
-
-
165
tSDR
Data Retention
Setup Time
See Data Retention Waveform
0
-
-
ns
tRDR
Recovery Time
See Data Retention Waveform
tRC
-
-
ns
Note:
1. If >VDD–0.2V, all other inputs including CS2 and and must meet this condition.
2. Typical values are measured at VDD=VDR(min), TA = 25℃ and not 100% tested.
DATA RETENTION WAVEFORM ( CONTROLLED)
DATA RETENTION WAVEFORM (CS2 CONTROLLED)
DATA RETENTION MODE
tRDR
tSDR
VDD
GND
VDR
> VDD-0.2V
DATA RETENTION MODE
tRDR
tSDR
VDD
GND
VDR
CS2
CS2 < 0.2V
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ORDERING INFORMATION
1.65V~1.98V Industrial Range (-40C to +85C)
Speed (ns)
Order Part No
Package
55
IS62WV102416EALL-55BI
48-pin BGA
IS62WV102416EALL-55BLI
48-pin BGA, Lead-free
1.65V~1.98V Automotive (A3) Range (-40C to +125C)
Speed (ns)
Order Part No
Package
55
IS65WV102416EALL-55BA3
48-pin BGA
IS65WV102416EALL-55BLA3
48-pin BGA, Lead-free
2.2V~3.6V Industrial Range (-40C to +85C)
Speed (ns)
Order Part No
Package
45
IS62WV102416EBLL-45BI
48-pin BGA
IS62WV102416EBLL-45BLI
48-pin BGA, Lead-free
55
IS62WV102416EBLL-55BLI
48-pin BGA, Lead-free
2.2V~3.6V Automotive (A3) Range (-40C to +125C)
Speed (ns)
Order Part No
Package
55
IS65WV102416EBLL-55BA3
48-pin BGA
IS65WV102416EBLL-55BLA3
48-pin BGA, Lead-free
IS62/65WV102416EALL
IS62/65WV102416EBLL
Integrated Silicon Solution, Inc.- www.issi.com 15
Rev. A1
2/22/2016