DS33Z44DK Ethernet Transport Design Kit www.maxim-ic.com GENERAL DESCRIPTION FEATURES Demonstrates Key Functions of DS33Z44 Ethernet Transport Chipset Includes Two Resource Cards: One with DS21458 T1/E1 SCT and one with DS3174 T3/E3 SCT, Transformers, BNC and RJ48 Network Connectors, and Termination Provides Support for Hardware and Software Modes On-Board MMC2107 Processor and ChipView Software Provide Point-and-Click Access to the DS33Z44 Register Set All DS33Z44 Interface Pins are Easily Accessible for External Data Source/Sink LEDs for Loss-of-Signal, Queue Overflow, Ethernet Link, Tx/Rx, and Interrupt Status Easy-to-Read Silkscreen Labels Identify the Signals Associated with All Connectors, Jumpers, and LEDs The DS33Z44 design kit is an easy-to-use evaluation board for the DS33Z44 Ethernet transport-over-serial link device. The DS33Z44DK is intended to be used with a resource card for the serial link. The serial link resource cards are complete with transceivers, transformers, and network connections. Dallas' ChipView software is provided with the design kit, giving point-and-click access to configuration and status registers from a Windows(R)-based PC. On-board LEDs indicate receive loss-of-signal, queue overflow, Ethernet link, Tx/Rx, and interrupt status. Windows is a registered trademark of Microsoft Corp. ORDERING INFORMATION PART DS33Z44DK DESCRIPTION DS33Z44 demo card, T3/E3, T1/E1 transceiver resource card included DESIGN KIT CONTENTS * * * * 1 of 59 DS33Z44DK Main Board Quad-Port Serial Card with DS21458 T1/E1 SCT Quad-Port Serial Card with DS3174 T3/E3 SCT CD_ROM o ChipView Software and Manual o DS33Z44DK Data Sheet o Configuration Files REV: 110106 DS33Z44DK TABLE OF CONTENTS GENERAL DESCRIPTION ..........................................................................................................1 ORDERING INFORMATION .......................................................................................................1 DESIGN KIT CONTENTS............................................................................................................1 COMPONENT LIST .....................................................................................................................3 PC BOARD ERRATA ................................................................................................................10 FILE LOCATIONS .....................................................................................................................10 BASIC OPERATION..................................................................................................................11 POWERING UP THE DESIGN KIT ...............................................................................................................11 General ............................................................................................................................................................... 11 BASIC DS33Z44 INITIALIZATION (USED FOR ALL QUICK SETUPS) .............................................................11 Quick Setup #1 (Device Driver + CPLD Loopback) ........................................................................................... 11 Quick Setup #2 (DS3174 T3E3) ......................................................................................................................... 12 Quick Setup #3 (DS21458 T1E1) ....................................................................................................................... 12 CONFIGURATION SWITCHES AND JUMPERS......................................................................13 ADDRESS MAP (ALL CARDS) ................................................................................................15 DS33Z44 INFORMATION..........................................................................................................15 DS33Z44DK INFORMATION ....................................................................................................15 TECHNICAL SUPPORT ............................................................................................................15 DOCUMENT REVISION HISTORY ...........................................................................................15 SCHEMATICS ...........................................................................................................................16 LIST OF FIGURES Figure 1. System Floorplan.......................................................................................................................................... 8 Figure 2. DS3174 Resource Card Floorplan ............................................................................................................... 8 Figure 3. DS21458 Resource Card Floorplan ............................................................................................................. 9 LIST OF TABLES Table 1. Component List (Decoupling Caps Not Shown)............................................................................................ 3 Table 2. Main Board PC Board Configuration ........................................................................................................... 13 Table 3. DS3174 Serial Reference Card Jumper Settings........................................................................................ 14 Table 4. Overview of Daughter Card Address Map................................................................................................... 15 2 of 59 DS33Z44DK COMPONENT LIST Table 1 shows the component list for the DS33Z44 and DS33Z11/DS33Z41 design kits and resource cards. This BOM contains the part listing for five boards. These boards are the DS33Z11DK, DS33Z44DK, DS21458RC, DS3174RC, and DS2155-DS21348-DS3170RC. Each reference designator is only used once. For example, U18 only appears on the DS33Z11DK and is not used on any of the other boards. See Table 2. Table 1. Component List (Decoupling Caps Not Shown) DESIGNATION QTY DESCRIPTION SUPPLIER PART U18 1 ELITE 10/100 ETHERNET TRANSPORT OVER SERIAL LINK 14X14 CSBGA 169 PIN Dallas Semiconductor DS33Z11 U20 1 3.3V T1.E1.J1 QUAD TRANSCEIVER 0-70C 256P BGA Dallas Semiconductor DS21458 U22 1 QUAD 10/100 ETHERNET EXTENSION TO WAN 17X17 PBGA 256 PIN Dallas Semiconductor DS33Z44 U23 1 DS3/E3 SCT, 11X11 CSBGA, 100 PIN Dallas Semiconductor DS3170 U24 1 T1/E1/J1 XCVR 100P QFP 0-70C Dallas Semiconductor DS2156L U25 1 3.3V LIU Dallas Semiconductor DS21348 UB08 1 QUAD TRIPLE DUAL SINGLE ATM PACKET PHYS FOR DS3 E3 STS1 0-70C 400P BGA Dallas Semiconductor DS3184 U01, U09 2 SOIC 8PIN STEP-UP DC-DC CONVERTER 0.5A LIMIT Maxim MAX1675EUA U07, U11 2 8-Pin MAX/SOIC 1.8V or Adj Maxim MAX1792EUA18 U13, UB01 2 MICROPROCESSOR VOLTAGE MONITOR, 2.93V RESET, 4PIN SOT143 Maxim MAX811SEUS-T U21, UB07 2 Dual RS-232 transceivers with 3.3V/5V internal capacitors MAXIM NA U31, UB06, UB11 3 8-Pin MAX/SOIC 2.5V or Adj Maxim MAX1792EUA25 C11, C13, C16, C25, C27, C31- C35, C37, C41, C47, CB10, CB63, CB114, CB128, CB164, CB496 19 1206 CERAM 10uF 10V 20% Panasonic ECJ-3YB1A106M CB390, CB391, CB395, CB396 4 1206 CERAM 0.1uF 25V 10% Panasonic ECJ-3VB1E104K D01-D03, D05, DB03-DB05 DS01, DS07, DS10-DS12, DS17, DS20 DS02, DS03, DS09, DS14, DS15 7 SCHOTTKY DIODE, 1 AMP 40 VOLT International Rectifier 10BQ040 7 LED, AMBER, SMD Panasonic LN1451C 5 L_LED, GREEN, SMD Panasonic LN1351C 13 LED, RED, SMD Panasonic LN1251C 2 LED, GREEN, SMD Panasonic LN1351C 19 L_LED, RED, SMD Panasonic LN1251C 76 STANDARD GROUND CLIP KEYSTONE 4954 8 KIT, 4-40 HARDWARE, .50 NYLON STANDOFF AND NYLON HEX-NUT NA Lab Stock DS04-DS06, DS08, DS13, DS16, DS18, DS27, DS28, DS35, DS37, DS38, DS40 DS19, DS43 DS21-DS26, DS30, DS32- DS34, DS36, DS39, DS41, DS42, DS44-DS48 GND_TP01-GND_TP07, GND_TP09--GND_TP44, GND_TP46-GND_TP68, GND_TPB01-GND_TPB10 H1-H8, H17-H19 3 of 59 DS33Z44DK DESIGNATION QTY DESCRIPTION SUPPLIER PART H9-H16 16 KIT, 4-40 HARDWARE, 1.12 NYLON STANDOFF AND NYLON HEX-NUT (1.12 STANDOFF PN = 4807K-ND) NA Lab Stock J01-J05 5 CONNECTOR, FASTJACK SINGLE, 8 PIN Halo Electronics HFJ11-2450E J06, J41 2 100 MIL 2*7 POS JUMPER NA Lab Stock J07-J12 6 RECEPTACLE, SMD, 140 PIN, .8MM, 2 ROW VERTICAL AMP 5-179010-6 J13-J22 10 L_TERMINAL STRIP, 10 PIN, DUAL ROW, VERT DO NOT POPLUATE NA Lab Stock J23, J29, J32, J38, J39, J43, J44, J47, JB07 9 L_TERMINAL STRIP, SHROUDED, 10 PIN, DUAL ROW, VERT 3M Electronics 2510-6002UB J24, J30, J31, J33 4 100 MIL 2 POS JUMPER NA Lab Stock J25, J26, J45, J46 4 TERMINAL STRIP, 10 PIN, DUAL ROW, VERT NA Lab Stock J27, J42 2 CONN 50 PIN, 2 ROW, POSTS VERT, MOTHERBOARD FOOTPRINT SAMTEC TSW-125-07-T-D J28, J36 2 L_CONN, DB9 RA, LONG CASE AMP 747459-1 J48, J54, JB01 3 SOCKET, BANANA PLUG, HORIZONTAL, BLACK Mouser Electronics 164-6218 J49-J52 4 CONNECTOR BNC 75 OHM VERTICAL 5PIN Cambridge CP-BNCPC-004 J53, JB02, JB08 3 SOCKET, BANANA PLUG, HORIZONTAL, RED Mouser Electronics 164-6219 J55, JB11 2 L_RJ48 8 PIN SINGLE PORT CONNECTOR MOLEX 15-43-8588 J56-J59, J61, J63 6 CONNECTOR BNC 75 OHM RA 5PIN Trompetor UCBJR220 J60, J62, J64, J65 4 CONNECTOR BNC RA 5PIN Trompetor UCBJR220 JB05, JB06, JB09, JB10, JB13, JB14 6 PLUG, SMD, 140 PIN, .8MM, 2 ROW VERTICAL AMP 179031-6 JB12 1 RA RJ45 8PIN 4PORT JACK MOL 43223-8140 JP01-JP19 19 100 MIL 3 POS JUMPER NA NA L01, L03-L08, LB01, LB02 9 FERRITE 3A 100 OHM AT 100 MHZ 1206 SMD Steward HI1206N101R-00 L02, L09 2 INDUCTOR 22.0uH 2PIN SMT 20% Coiltronics UP1B-220 L10 1 XFMR 1-2CT XMIT, 1-1CT RCV, 40P WIDE SOIC Pulse T1068 10 RES 0603 54.9 Ohm 1/16W 1% Panasonic ERJ-3EKF54R9V 10 RES 0603 49.9 Ohm 1/16W 1% Panasonic ERJ-3EKF49R9V R05, R06, R08, R09, R11 5 RES 0603 10.0K Ohm 1/16W 1% - Must be 1% tolerance Panasonic ERJ-3EKF1002V R07, R12, R16, R79, R160, R244, R248, R250, R251, R254, R255, RB126, RB143, RB147, RB150, RB157 16 RES 0603 1.0K Ohm 1/16W 5% Panasonic ERJ-3GEYJ102V R10, R107 2 RES 1206 5.6 Ohm 1/8W 5% Panasonic ERJ8GEYJ5R6V R132, R137, R142, R144, R156, RB194, RB208, RB227 8 L_RES 0603 0 Ohm 1/16W 1% AVX CJ10-000F R01, R02, RB10, RB11, RB18, RB19, RB22, RB23, RB26, RB27 R03, R04, RB12, RB13, RB20, RB21, RB24, RB25, RB28, RB29 4 of 59 DS33Z44DK DESIGNATION QTY R13-R15, R18-R20, R22, R23, R29, R30, RB01, RB03, RB07, RB09, RB15-RB17, RB30- RB32, RB34-RB38, RB41, RB44, RB47, RB48, RB50- RB52, B55, RB60, RB62, RB72, RB73, RB75, RB80, RB82 40 RES 0603 5.1K Ohm 1/16W 5% Panasonic ERJ-3GEYJ512V 104 RES 0603 30 Ohm 1/16W Panasonic ERJ-3GEYJ300V 8 L_RES 0805 0.0 Ohm 1/10W 5% Panasonic ERJ6GEY0R00V 10 RES 0603 332 Ohm 1/16W 1% Panasonic ERJ-3EKF3320V 16 RES 1206 0 Ohm 1/8W 5% Panasonic 2 RES 0805 51.1 Ohm 1/10W 1% Panasonic ERJ8GEYJ0R00V ERJ-6ENF51R1V R24, R114, R197, RB14, RB33, RB40, RB42, RB43, RB49, RB53, RB54, RB57-RB59, RB71, RB77, RB78, RB152- RB156, RB221, RB234, RB251, RB284, RB304, RB331, RB332, RB342, RB344, RB350, RB354, RB360 34 L_RES 0603 330 Ohm 1/16W 5% Panasonic ERJ-3GEYJ331V R242, R243, RB144, RB166, RB355-RB358, RB368-RB371 12 RES 0603 51 Ohm 1/16W 5% Panasonic ERJ-3GEYJ510V 13 RES 0603 330 Ohm 1/16W 5% Panasonic ERJ-3GEYJ331V 152 RES 0402 30 Ohm 1/16W 5% Panasonic ERJ-2GEJ300X 2 RES 0603 1.0M Ohm 1/16W 5% Panasonic R77, RB159 2 L_RES 1206 0 Ohm 1/8W 5% Panasonic ERJ-3GEYJ105V ERJ8GEYJ0R00V R80, R81, R84, R87, R89, R91- R93, R95, R108, R110, R118, R127, R152, R153, R196, R209, R214, R229-R236, RB200, RB237, RB238, RB263, RB264, RB286, RB287, RB300, RB301, RB333, RB364 37 RES 0603 10K Ohm 1/16W 5% Panasonic R17, R21, R25-R28, R31, R55, R57-R59, R71, R74-R76, R83, R96-R102, R105, R106, R109, R111, R112, R115-R117, R120, R122-R126, R128, R133, R134, R140, R141, RB61, RB96, RB97, RB99, RB100, RB102-RB110, RB112, RB114-RB119, RB121, RB123-RB125, RB127, RB128, RB130, RB131, RB133, RB135-RB138, RB145, RB148, RB149, RB160, RB161, RB164, RB165, RB167-RB171, RB173-RB181, RB184, RB187, RB311, RB320, RB335, RB339, RB359 R171, R172, R174, R175, R190, R191, R240, R241 R198-R200, R210-R213, RB306, RB325, RB326 R201-R208, RB321-RB324, RB327-RB330 R239, RB349 R32, R70, R78, R161, R176, R194, R195, R237, R238, RB129, RB134, RB146, RB193 R33-R54, R60-R69, R72, R73, R131, R136, R143, R147, R150, R154, R158, R163, R166, R169, R173, R178- R189, R215-R228, RB89- RB95, RB101, RB188-RB191, RB196-RB199, RB202-RB205, RB210-RB213, RB216-RB219, RB223-RB226, RB230-RB233, RB239-RB242, RB244-RB249, RB252-RB260, RB265-RB268, RB270-RB282, RB289-RB297 R56, R90 DESCRIPTION 5 of 59 SUPPLIER PART ERJ-3GEYJ103V DS33Z44DK DESIGNATION QTY DESCRIPTION SUPPLIER PART R85, R88, R94, R104, R113, RB02, RB04-RB06, RB08, RB39, RB45, RB46, RB56, RB63-RB70, RB76, RB83, RB98, RB183, RB185, RB192, RB209, RB228, RB302, RB303, RB305, RB338, RB340, RB341, RB346-RB348, RB351-RB353, RB361-RB363, RB365-RB367 48 RES 0603 2.0K Ohm 1/16W 5% Panasonic ERJ-3GEYJ202V R86, R103, R119, R121, R129, R130, R135, R138, R139, R145, R146, R149, R151, R157, R162, R164, R167, R168, R170, R177, R192, R193, R245-R247, R249, R252, R253, R256, R257, RB74, RB79, RB132, RB139-RB141, RB151, RB162, RB163, RB172, RB182, RB186, RB206, RB207, RB214, RB215, RB220, RB222, RB229, RB235, RB236, RB243, RB250, RB261, RB262, RB269, RB308-RB310, RB343, RB345 61 L_RES 0603 10K Ohm 1/16W 5% Panasonic ERJ-3GEYJ103V RB201, RB285 2 RES 0805 330 Ohm 1/10W 5% Panasonic ERJ-6GEYJ331V RB283 1 RES 0603 10K Ohm 1/10W 5% - SEE SPECIAL INSTRUCTIONS Panasonic 603_ERJ3GEYJ103V RB298, RB299, RB312-RB319, RB336, RB337 12 RES 0805 61.9 Ohm 1/10W 1% Panasonic ERJ-6ENF61R9V RB81, RB84-RB88, RB111, RB113, RB120, RB122 10 RES 0603 DO NOT POPULATE NA NA SW01-SW05, SW08-SW21, SW24-SW26, SW29-SW31, SW33-SW44 37 L_SWITCH, SP3T SLIDE, 4PIN TH Tyco 3-1437575-3 SW06, SW22 2 L_SWITH 8POS 16PIN DIP LOW PROFILE AMP 435668-7 SW07, SW23 2 SWITCH MOM 4PIN SINGLE POLE Panasonic EVQPAE04M SW27, SW28, SW32 3 L_DIPSWITCH, 10 POS AMP 435668-9 T01, T03 2 XFMR 16P SMT Pulse TX1099 T02, TB01 2 XFMR, OCTAL T3/E3, 1 TO 2, SMT 32 PIN Pulse T3049 TP01-TP78, TPB01, TPB02 80 TESTPOINT, 1 PLATED HOLE, DO NOT STUFF NA NA U02-U06 5 IC, DsPHYTER11-SINGLE 10/100 ETHERNET TRANSCEIVER, 65 PIN LLP National Semiconductor DP83847ALQA5 6A U08, U12, U29 3 1MBit Flash based config mem Avnet XCF01SV020C U10 1 XILINX SPARTAN xc200 2.5V FPGA,256 PIN BGA Xilinx XC2S2005FG256C U14, U26, U30, UB05 4 CYPRESS SRAM, LAB STOCK NA NA U15, U19 2 mmc2107 processor Motorola MMC2107 U16, U27 2 XILINX SPARTAN 2.5V FPGA,256 PIN BGA Xilinx XC2S505FG256C U17, U28, U32 3 10 pin res pack, 10K ohm NA NA UB02, UB03, UB04 3 100 PIN CPLD XILINX XC95144XL10TQ100C UB09, UB10 2 SYNCHRONOUS DRAM, 1MEGX32X4 BANKS, TSOP 86 PIN Micron MT48LC4M32B2 TG-7 6 of 59 DS33Z44DK DESIGNATION QTY DESCRIPTION UX01-UX12, UXB02-UXB04, UXB06-UXB08 18 HIGH SPEED BUFFER Fairchild NC7SZ86 UXB01, UXB05 2 HIGH SPEED INVERTER Fairchild NC7SZ86 X01, X02 2 XTAL LOW PROFILE 8.0MHZ ECL EC1-8.000M Y01, Y09 2 OSCILLATOR, CRYSTAL CLOCK, 3.3V - 25.000 MHZ, Low Jitter required for PHY SaRonix NTH089AA325.000 Y02, Y13 2 SPI SERIAL EEPROM 16K 8 PIN DIP 2.7V NEEDS SOCKET Atmel AT25160A-10PI2.7 Y03 1 OSCILLATOR, CRYSTAL CLOCK, 3.3V - 2.048 MHZ SaRonix NTH039A32.0480 Y05, Y06 2 OSCILLATOR, CRYSTAL CLOCK, 3.3V - 100.000 MHZ SaRonix NTH089A3100.0000 Y07 1 OSCILLATOR, CRYSTAL CLOCK, 3.3V - 44.736 MHZ SaRonix NTH089AA344.736 Y08 1 OSCILLATOR, CRYSTAL CLOCK, 5.0V - 44.736 MHZ SaRonix NTH089AA44.736 YB02 1 L_OSCILLATOR, CRYSTAL CLOCK, 3.3V - 2.048 MHZ SaRonix NTH039A32.0480 7 of 59 SUPPLIER PART DS33Z44DK Figure 1. System Floorplan DS33Z44 MAINBOARD LEDS AND TESTPOINTS DS21458 RESOURCE CARD (DETAIL PROVIDED BELOW) SERIAL INTERFACE 2 X 140 PIN CONNECTORS SDRAM ETHERNET PHYs, MAGNETIC, LEDS, AND JUMPERS DS33Z44 HARDWARE MODE SWITCHES FOR DS33Z44 DS3184 RESOURCE CARD (DETAIL PROVIDED BELOW) MICROPROCESSOR AND SERIAL PORT (57600-8-N-1) TEST POINTS + JUMPERS DS3174 PORT 3 LAN PORT 3 CPLD (MUX) DS3174 PORT 1 LAN PORT 4 JUMPERS DS3174 CPLD (MUX) OSC QUAD-PORT T3/E3 TRANSCEIVER LOOPBACK JUMPER 8 of 59 DS3174 PORT 2 LAN PORT 2 JTAG 140 PIN CONNECTORS (2 TOP, 2 BOTTOM) Figure 2. DS3174 Resource Card Floorplan DS3174 PORT 4 LAN PORT 1 BNC Tx Rx DS33Z44DK The DS3174 quad T3/E3 PC board floorplan is shown in Figure 2. Jumpers JP16, JP17, JP18, and JP19 are 3-pin jumpers used to tri-state/enable T3/E3 ports. With the board oriented as shown in Figure 2, the top 2 pins of each jumper would be connected to enable T3/E3 traffic. A 2-pin jumper, JP24, has been added to allow loopback. When installed, the board is in loopback at the CPLD; all traffic sent by the DS33Z44 is then sent back to the Z44. Traffic sent by the DS3174 is ignored in CPLD loopback mode. The quad T3/E3 board is intended to be connected to the DS33Z11 or DS33Z44 motherboards. The quad T3/E3 board can be used with the quad T1/E1 board. When used in this manner, the quad T1/E1 board is stacked underneath the quad T3/E3 board. Jumpers on the T3/E3 board are then used to tri-state or enable individual ports on either board. Figure 3 shows the DS21458 quad T1/E1 PC board floorplan. The current configuration is to populate oscillators for MCLK1 with a 2.048MHz oscillator. Testpoints for port 3 and port 4 are provided on the WAN card, and testpoints for ports 1 and 2 are provided on the motherboard. The quad T1/E1 board can be used with the quad T3/E3 board. When used in this manner, the quad T1/E1 board is stacked underneath the quad T3/E3 board. Jumpers on the T3/E3 board are then used to tri-state or enable individual ports on either board. PORT 2 OSC MCLK1, 2 FPGA DS21458 QUAD-PORT T1/E1 TRANSCEIVER INT LED QUAD TRANSFORMER PORT 4 RLOS LEDS 9 of 59 PORT 1 PORT 3 QUAD-PORT RJ45 TEST POINTS JTAG 140 PIN CONNECTORS Figure 3. DS21458 Resource Card Floorplan DS33Z44DK PC BOARD ERRATA * * * Silk screen for the serial resource card has VCC and ground indicators pointing the wrong direction for configuration switches SW27, SW28, and SW32. This should be corrected with an adhesive label. Signal descriptions for JTAG connector are incorrect on the Quad T1E1 card. This should be corrected with an adhesive label. In the PCB layout the transformer TX primary is on the wrong side (creating a 2:1 winding instead of a 1:2). This has been corrected in the schematic, the PCB / assembly has been modified to correct this. FILE LOCATIONS This design kit relies upon several supporting files, which are provided on the CD and are available as a zip file from the Maxim website at www.maxim-ic.com/DS33Z44DK. All locations are given relative to the top directory of the CD/zip file. * DS33Z44 register definition files and configuration files: o .\cfg_demo_gui\DS33Z44_cfg_demo_gui\DS33Z44.def o .\DS33Z44_cfg_demo_gui\SU_LI_PORT4.def (def files for port 3, 2, 1 not shown) o .\DS33Z44_cfg_demo_gui\basic_config.mfg * DS21458 register definition files and configuration files: o .\DS33Z44_cfg_demo_gui\Qt1e1_DS21458\DS21458RC.def o .\DS33Z44_cfg_demo_gui\Qt1e1_DS21458\DS21458RC_FPGA.def o .\DS33Z44_cfg_demo_gui\Qt1e1_DS21458\e1_gapclk_crc4_hdb3_nocas.ini o .\DS33Z44_cfg_demo_gui\Qt1e1_DS21458\gapclk_DS21458_T1_ESF_LBO0.ini * DS3174 register definition files and configuration files: o .\DS33Z44_cfg_demo_gui\Qt3e3_DS3184\ds3184_evbrd_reduced.def o ..... 14 other low level def files .... o .\DS33Z44_cfg_demo_gui\Qt3e3_DS3184\84_t3_sct_needscoaxlb.mfg 10 of 59 DS33Z44DK BASIC OPERATION Powering Up the Design Kit * * * Attach resource card to main board. Connect PCB 3.3V and GND banana plugs to power supply. At power-up the system should draw approximately 1A. Set switches for software mode as described in Table 2 (short description follows). * Top left bank: All low, except for MODEC0, which is high. * Top right bank: A2, A1, A0 in mid position, SCANTRI low * Bottom Bank: All high (AFCS, FULLDS, H1OS) General * Upon power-up, the processor FPGA Status LEDs (DS19 green) will be lit. Interrupt LEDs (DS42 red) will not be lit. DS33Z44 Queue overflow LEDs (DS45, DS46, DS47, DS48 red) will not be lit. PHY LINK LED (DS02, DS03, DS14 green) should be lit if the Ethernet is connected. Following are several basic system initializations. Basic DS33Z44 Initialization (Used for All Quick Setups) This section covers four basic methods for configuring the Z44. Any one of these initializations can be used with the following Quick Setup examples: 1. Upon power-up, the on-board device driver provides a basic configuration for the DS33Z44 and attached serial cards. This enables traffic to pass from the Ethernet port to the serial port. Consult the device driver documentation for further details. Device driver behavior is dependant upon jumper settings, which are detailed in Table 2. 2. Register-Based Configuration. Launch ChipView.exe and select Register View. When prompted for a definition file, pick the file named DS33Z44.def. After the definition file loads, go to the File menu and select FileMemory Config FileLoad .MFG file. When prompted, select the file named 4Portsbasic_config.mfg. 3. Hardware Mode. Set switches as described in the section for powering up the design kit, then change the following: HWMODE3.3V, A03.3VV, A13.3V, A20V. This sets the part for LSB first, scrambling off, HDLC encapsulated. At this point traffic will pass from the Ethernet port to the serial port. In this mode broadcast frames are not passed (i.e., ping). 4. EEPROM mode is available with the DK, but is beyond the scope of this manual. Quick Setup #1 (Device Driver + CPLD Loopback) * * * * * On the serial resource card install jumper 24. Jumpers JP16-JP19 should be set high. This places the card in CPLD loopback and enables all four ports as described in Table 3. Complete the hardware configuration and one of the basic DS33Z44 configurations as described in the previous section. Using a patch cable, connect the Ethernet connector to an ordinary PC, or network test equipment. This should cause the link LED to turn on. At this point any packets sent to the DS33Z44 are echoed back. Incoming packets (i.e., ping) should cause the RX LED to blink, after which the TX LED should also blink. To interact with the device driver select from the drop down menu: * ToolsPluginsLoad Plugins. When asked if DLLs have already registered select yes * Select ToolsPluginsDS33Z44/11/41 Device Driver Demo * A new form called `Zchip Configuration' pops up. * Preload basic configuration for the GUI by selecting FileLoad Settings (in the `Zchip Configuration' form). Select the file named `basic_Config.eset' 11 of 59 DS33Z44DK Quick Setup #2 (DS3174 T3E3) * * * * * * On the DS3174 serial resource card install jumper J24. Jumpers JP16-JP19 should be set high. This places the card in DS3174 mode and enables all four ports as described in Table 3. Complete the hardware configuration and one of the basic DS33Z44 configurations as previously described. Using a patch cable, connect the Ethernet connector to an ordinary PC, or network test equipment. This should cause the link LED to turn on. Launch ChipView.exe (or use existing session if it is already open) and select Register View. When prompted for a definition file, pick the file name ds3184_evbrd_reduced.def. After the definition file loads, go to the File menu and select FileMemory Config FileLoad .MFG file. When prompted, select the file named 84_t3_sct_needscoaxlb.mfg. Place a loopback connector at the DS3174 network side. At this point, any packets sent to the DS33Z44 are echoed back. Incoming packets (i.e., ping) should cause the RX LED to blink, after which the TX LED should also blink. Quick Setup #3 (DS21458 T1E1) * * * * * Complete the hardware configuration and one of the basic DS33Z44 configurations as previously described. Using a patch cable, connect the Ethernet connector to an ordinary PC, or network test equipment. This should cause the link LED to turn on. Launch ChipView.exe (or use existing session if it is already open) and select Register View. When prompted for a definition file, pick the file named DS21458.def. After the definition file loads, go to the File menu and select FileReg Ini FileLoad Ini File. When prompted, pick the file named e1_gapclk_crc4_hdb3_nocas.ini. Place a loopback connector at the DS21458 network side; RLOS LED should go out. At this point any packets sent to the DS33Z44 are echoed back. Incoming packets (i.e. ping) should cause the RX LED to blink, after which the TX LED should also blink. 12 of 59 DS33Z44DK CONFIGURATION SWITCHES AND JUMPERS The DS33Z44DK has several configuration switches, banana plugs, oscillators, and jumpers. Table 2 provides a description of these signals, given in order of appearance on the PC board (going from left to right, top to bottom). Table 2. Main Board PC Board Configuration SILKSCREEN REFERENCE FUNCTION BASIC SETTING SW MODE HW MODE DESCRIPTION This jumper is not for use with the DS33Z44 design kit. Pin J25.10 has been removed to prevent accidental installation. When installed the device driver will configure the DS33Z44 and the Transceiver during power-up. When installed the driver will respond to interrupts. System Ground. Always connected to power supply. System VDD. Always connected to power supply. Debug connector for processor J25.9 + J25.10 Reserved Not Installed -- J25.7 + J25.8 Enable device driver User decision -- J25.5 + J25.6 Enable callbacks User decision -- Power supply ground -- -- Power supply VDD -- -- BDM DS33Z44 mode pin; DTE/DCE selection -- -- Low Low Low for DTE DS33Z44 mode pin Low Low High for RMII, low for MII DS33Z44 mode pin Low Low SPI EEPROM hardware mode configuration switch DS33Z44 mode pin High Low Software mode selected DS33Z44 mode pin Low Low Software mode selected DS33Z44 mode pin Low Low Hardware/software mode (software mode selected) DS33Z44 mode pin Low Low Set low for normal operation DS33Z44 mode pin Low Low Set low for normal operation ....testpoints.... DS33Z44 testpoints -- -- Z-RESET (button) DS33Z44 reset -- -- A2, A1, A0 (3pos switches) DS33Z44/SPI pins Mid position Mid position SDRAM CLOCK DS33Z44 SDRAM clock Installed Installed MII CLOCK PHY MII clock Installed Installed spi_cs, spi_ck, spi_miso, spi_mosi -- -- -- SPI signals (for EEPROM memory) ....testpoints..... DS33Z44 testpoints -- -- DS33Z44 serial port testpoints AFCS (1 per port) DS33Z44 mode pin HW mode only High GROUND (banana plug) VDD 3.3V (banana plug) OnCe DCEDTES (3pos switch) RMIIMII (3pos switch) CKPHA (3pos switch) MODEC0 (3pos switch) MODEC1 (3pos switch) HWMODE (3pos switch) SCANMO (3pos switch) SCANTRI (3pos switch) 13 of 59 Processor bus, JTAG and LAN side testpoints for Zchip System reset Address pin/EEPROM config switch. Set to mid position to allow connection to processor. 100MHz oscillator to drive SDRAM clock 25MHz oscillator to drive SDRAM clock Set high to enable auto flow control. DS33Z44DK SILKSCREEN REFERENCE FULLDS (1 per port) FUNCTION BASIC SETTING SW MODE HW MODE DESCRIPTION DS33Z44 mode pin HW mode only High Set high to enable full duplex. H10S (1 per port) DS33Z44 mode pin HW mode only High Set high to confg for 100Mb. GROUND/VDD (banana plug) Power supply ground/3.3V -- -- VDD 3.3V (banana plug) Power supply VDD -- -- Redundant connection to system power. Use plugs at either top or bottom of board. Redundant connection to system power. Use plugs at either top or bottom of board. Table 3. DS3174 Serial Reference Card Jumper Settings JUMPER SETTINGS MODE JP16 Port 4 tri-state (at CPLD) JP17 Port 2 tri-state (at CPLD) JP18 Port 3 tri-state (at CPLD) JP19 Port 1 tri-state (at CPLD) J243 CPLD loopback COMMENT When the middle pin of this 3 position jumper is set to VCC, the CPLD passes traffic from the DS3174 to the DS33Z44. When the pin is set low, the CPLD tri-states this port. When the middle pin of this 3 position jumper is set to VCC, the CPLD passes traffic from the DS3174 to the DS33Z44. When the pin is set low, the CPLD tri-states this port. When the middle pin of this 3 position jumper is set to VCC, the CPLD passes traffic from the DS3174 to the DS33Z44. When the pin is set low, the CPLD tri-states this port. When the middle pin of this 3 position jumper is set to VCC, the CPLD passes traffic from the DS3174 to the DS33Z44. When the pin is set low, the CPLD tri-states this port. CPLD loopback makes the following connections: Zrser Ztser, Ztden 3.3V, Zrden 3.3V, Ztclki OscY03, Zrclki OscY03 14 of 59 DS33Z44DK ADDRESS MAP (ALL CARDS) Motorola resource card address space begins at 0x81000000. All offsets given below are relative to the beginning of the daughter card address space (shown previously). Table 4. Overview of Daughter Card Address Map OFFSET DEVICE 0X0000 to 0X0087 FPGA 0X1000 to 0X1FFF DS33Z44 DS33Z44. Uses CS_X1. 0X2000 to 0X2FFF DS21458 T1E1 DS21458 resource card. Uses CS_X2. 0X4000 to 0X4010 FPGA 0X3000 to 0X3FFF DS3174 DESCRIPTION Processor board identification FPGA on DS21458 resource card. Used to facilitate IBO mode. Default configuration of FPGA is compatible with non-IBO mode functionality. The FPGA settings do not require modification for use with the DS33Z44. T3E3 resource card. Uses CS_X3. Registers in the DS33Z44, DS21458, and DS3174 can be easily modified using the ChipView host-based userinterface software with the definition files previously mentioned. DS33Z44 INFORMATION For more information about the DS33Z44, consult the DS33Z44 data sheet available on our website at www.maxim-ic.com/DS33Z44. DS33Z44DK INFORMATION For more information about the DS33Z44DK, including software downloads, consult the DS33Z44DK data sheet available on the our website at www.maxim-ic.com/DS33Z44DK. TECHNICAL SUPPORT For additional technical support, go to www.maxim-ic.com/support. DOCUMENT REVISION HISTORY REVISION DATE 032305 DESCRIPTION 051105 Initial DS33Z44DK data sheet release. Updated Basic DS33Z44 Initialization section; added step to Quick Setup #1. Added new PC board errata. 110106 Updated schematics. 042205 15 of 59 DS33Z44DK SCHEMATICS The DS33Z44DK schematics are featured in the following pages. As this is a hierarchal schematic some explanation is in order. The main board is composed of six hierarchal blocks: the processor block, the DS33Z44 block, and four Ethernet blocks inside the DS33Z44 block, which is a nested hierarchy block. Each serial card (DS21458 and DS3174) consists of a single hierarchy block, which connects to a 140-pin AV bus that snaps into the mainboard. All signals inside a hierarchy block are local, with exception for VCC and ground. In-port and out-port connectors are used to allow signals inside a hierarchy block to become accessible as pins on the hierarchy blocks symbol. From here, blocks are wired together as if they were ordinary components. The system diagram is shown again below, with schematic page numbers given for each functional block. This system contained other hierarchy blocks that are not shown (primarily a single-port serial card and the DS33Z11 mainboard). Due to this, page numbers will not be continuous and some gaps in numbering will be seen when referring to the total page count. However, page numbers inside any given hierarchy block will be continuous. DS33Z44 MAINBOARD TOP LEVEL DS21458 RESOURCE CARD PHY SYMBOLS ON PAGES 26-27 PORT 3 ETHERNET PHY SCHEMATIC PAGES 36-37 PORT 2 ETHERNET PHY SCHEMATIC PAGES 32-33 DS33Z44 BLOCK PAGE 20 SYMBOL SCHEMATIC PAGES 22-29 SERIAL INTERFACE 2 X 140 PIN CONNECTORS PORT 1 ETHERNET PHY SCHEMATIC PAGES 30-31 SCHEMATIC PAGES 46-55 P BLOCK PAGE 21 SYMBOL DS3184 RESOURCE CARD SCHEMATIC PAGES 56-63 SCHEMATIC PAGES 38-44 16 of 59 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2006 Maxim Integrated Products The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation. A B C D Z44_RCLK<1> Z44_RDEN<1> GND GND GND V3_3 GND GND Z44_RDEN<2> Z44_RSER<2> GND GND 20C5<> 20A8<> 20A1 20C8<> 20A8<> 20B8<> 20C5<> 20A5<> 20B5<> XA<15..0> 20C8<> 20B5<> 8 20A1> V3_3 20A1 OSC2_NU OSC4_NU 11 7 9 4 2 GND GND GND GND 21A6> TDI_NU 21A6> TMS_NU 20A5<> 20A1> V3_3 20B8<> 0 GND 20A3<> FPGAGCLK1_NU GND 20B5<> 20A8<> 20A5<> 20A1> V3_3 20A1 20C8<> 20C5<> 20B8<> GND GND GND 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 JB14 6 5 PLUG 4 22D5v 22B1v 22A1v 21B7< 7 25C3v 20D1> 25D3v 20D1> BLOCK NAME: _z44top_dn. 6 GND GND GND 20A8<> GND GND GND V3_3 GND GND GND V3_3 GND GND GND CS_X2 V3_3 CS_X3 WR_X GND GND PARENT BLOCK: \_ztopdn_\ 5 21C4> 20A5<> 20A1> 21C4> 21B4> 6 2 4 OSC1_NU GND 20A8<> 20A5<> 20A1> V3_3 Z44_RCLK<4> Z44_RDEN<4> Z44_RSER<4> Z44_RCLK<3> Z44_RDEN<3> Z44_RSER<3> XD<7..0> 20B5<> MOTHERBOARD CONNECTORS FOR WAN R.C. 20A1 20C8<> 20C5<> 20B8<> 20B5<> 20A3 21B4> 20A1 20C8<> 20C5<> 20B8<> 25B3v 20D1> 20C5<> 20B8<> 20B5<> 20A8<> 20A5<> 20A1> 25B3v 20D1> 25B3v 20D1> 20C5<> 20B8<> 20B5<> 20A8<> 20A5<> 20A1> 25D3v 20D1> 20D1> 25B6v XA<15..0> OSC3_NU GND GND 10 6 8 3 5 1 TDO_NU 21A5> TCK_NU 21A5> 20A1 20C8<> 20A1 20C8<> Z44_TCLK<2> 20D1> 25B6v 20A2> 20B3<> 20C6<> 20D1> 25B5v Z44_TDEN<2> Z44_TSER<2> SIG_RETURN GND 20C5<> 20B8<> 20B5<> 20A8<> 20A5<> 20A1> V3_3 20D1> 25D6v 20A1 20C8<> Z44_TCLK<1> 21C4> CS_X5 GND 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 JB10 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND P1 CONNECTOR (PLUG) 20C5<> 20B8<> 20B5<> 20A8<> 20A5<> 20A1> V3_3 20A2> 20B3<> 20C6<> 20D1> 25C6v 20D1> 25C5v Z44_TDEN<1> SIG_RETURN Z44_TSER<1> 20A1 20C8<> INT2 20C8<> 21C7< 22B7v RESET_B 21C4> 20C3< 22B6v INT3 21C7< INT4 21C7< GND 20A8 21B4> GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND P2 CONNECTOR (PLUG) GND 20D1> Z44_RCLK<2> 25B7v 20B5<> 20A8<> 20A5<> 20A1> V3_3 20A1 20C8<> 20C5<> 20B8<> 20D1> 25B7v 20D1> 25B7v PLUG 7 RW_X 5 7 1 3 0 21B4> XD<7..0> FPGAGCLK1_NU 20A8<> GND 3 SIG_RETURN 20B3<> ENGINEER: STEVE SCULLY 2 20C6<> MODEC0 MODEC1 HWMODE RCLKI<4..1> TCLKI<4..1> RDEN<4..1> TDEN<4..1> DS33Z11/41/44DK01A0 20A2> 20C6<> 20D1> 25B2v 20D1> 25B2v TITLE: Z44_TCLK<4> SIG_RETURN 20D1> 25D2v 20D1> 25B2v Z44_TDEN<4> Z44_TSER<4> Z44_TCLK<3> INT RSER<4..1> TSER<4..1> HIERARCHICAL BLOCK _z44andlan_dn 2 PAGES 22-29 20D1> 25C2v 20D1> 25D2v Z44_TDEN<3> Z44_TSER<3> 22B6v 21C4> 20C7<> WR CS_X1 CS WR_DUT RESET_B RESET_B 22B6v 21C4> 22B6v 21B7< ALE CS_X4 21C4> 22B5v 3 A_DUT<9..0> ADDR<9..0> D_DUT<7..0> 21B7< DAT<7..0> 22B6v 21B7< RD_DUT RD DS33Z44 TOP LEVEL 20B5<> 20A8<> 20A5<> 20A1> V3_3 20A1 20C8<> 20C5<> 20B8<> 20D1> 25D7v 20D1> 25C7v INT5 INT2 Z44_RSER<1> Z44INT 20D1> 25C7v 21C7< 20D1> 8 CR-20 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I8@\_ZTOP_LIB\.\_Z44TOP_DN\(SCH_1):PAGE1 BIS1_DUT GND V3_3 21B7< 22B6v 21B7< 22B6v 1 09/16/2004 PAGE: 1/2(BLOCK) 20/71(TOTAL) DATE: V3_3 25D7v 25B7v 20C8<> 20B5<> 20B8<> 25B3v 25D3v 25C5v 25B2v 20B3<> 20C6<> 25B5v 25D2v 21B7< 22B6v BIS0_DUT BTS_DUT Z44INT 20C8< Z44_RSER<4..1> Z44_TSER<4..1> Z44_RDEN<4..1> Z44_TDEN<4..1> Z44_RCLK<4..1> Z44_TCLK<4..1> 1 A B C D A B C 8 BIS1_DUT BTS_DUT BTS_DUT 7 42C3v 20C1> 42C3v 20C1> BIS0_DUT A_DUT<11..0> BIS1_DUT D_DUT<7..0> A_DUT<11..0> 42C3v 20C1> BIS0_DUT 42D5v 20D3< 42A6v 42A5v 20D3< WR_DUT PAGES 38-44 6 RW_X RESET_B CS_X5 CS_X4 CS_X3 CS_X2 CS_X1 I1 5 5 4 38A5v XD<7..0> 4 20A5<> 42B3v 20A3<> 42B3v 20C7<> 20C3< 20C5<> 42A4v 20C3<> 42A4v 20A5<> 42A4v 20A5<> 42B3v 20D3< 42B3v XA<15..0> RW_X WR_X RESET_B CS_X1 CS_X2 CS_X3 CS_X4 CS_X5 20A8<> 44A7v 20A8<> 44A7v 20A7<> 44A7v 20A7<> 44A7v XD<7..0> WR XA<15..0> _motprocrescard_dn HIERARCHICAL BLOCK D_DUT<7..0> WR_DUT 39D4v 20C8<> 42C3v 20D3< INT5 INT5 38B7v 20C7<> RD_DUT INT4 INT4 RD_DUT INT3 INT3 38B7v 20C7<> 42C3v 20D3< INT2 INT2 38B7v 20C8<> 20C7<> 6 TMS_NU TMS_NU 7 TDI_NU TDI_NU D 8 CR-21 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I8@\_ZTOP_LIB\.\_Z44TOP_DN\(SCH_1):PAGE2 TCK_NU TDO_NU TCK_NU TDO_NU 20A3 20A5 42B3v 20A6 20A8 42C7v 3 2 1 ENGINEER: 3 09/16/2004 PAGE: 2/2(BLOCK) 21/71(TOTAL) STEVE SCULLY DATE: 1 TITLE: DS33Z11/41/44DK01A0 2 A B C D A B C SD_CLKI SD_RAS SD_CAS SD_WE SD_CS SD_CLKO SD_DQM0 SD_DQM1 SD_DQM2 SD_DQM3 SD_BA0 SD_BA1 T11 N11 P8 R147 RB217 R158 N7 R7 R163 RB282 8 V3_3 1 330 RB332 DS42 RED 2 1 2 7 P15 RB219 T15 T7 M7 RB239 RB226 T8 R9 RB246 R166 R8 NC7SZ86_U UXB07 4 BUFFER SWE* SCAS* SRAS* SYSCLKI SDCLKO SDCS* SDMASK<3> SDMASK<2> SDMASK<1> SDMASK<0> SBA<1> SBA<0> MDIO TPB01 F10 RB230 RB161 MDIO MDC TP34 F11 UNMARKED RESISTORS ARE 30 OHM 24C4< 24C4< 24C4< 28D5< 24C3< 24C4< 24C4< 24C4< 24C4< 24C4< 24B4< 24B4< 1 R99 U22 DS33Z44_U1 JTAG MICRO PORT/SPI MASTER PORT INT* 22A6<> 1 20D2^ MDC CS* IN 20D3^ 27B3> 26B6> 26B3> 27B6> 27B3> 26B6> 26B3> 27B6> SPI_CS* INT 22C2< REF_CLKO RD*/DS* 20D3^ IN B15 WR*/RW* IN 20D3^ RB181 RST* REF_CLKO 22A5<> JTMS HWMODE REF_CLK MODEC<0> C15 22A5<> JTDI 6 22A7> 20D2^ 28D4< 20C2^ OUT 28D2< 20C2^ 1 22A5<> JTDO MODEC<1> OUT OUT OUT 28D4< 20C2^ 1 22A5<> JTCLK DCEDTES 28D2< TPB02 MII/RMII SDRAM CONTROL 22A5<> F7 JTMS E4 JTDI E5 JTDO D4 JTCLK E6 JTRST JTRST RMIIMIIS 28C4< REF_CLK 28B4< 28A4< 28C4< 5 22D6< JTRST JTDO JTDI 22D6<> 9 7 3 5 JTMS 22D6< 22D6< 1 JTCLK 22D6< 7 C6 D<7> 10 8 6 4 2 10 8 6 4 2 4 IO TDO_NU TDI_NU TMS_NU TCK_NU 20D3^ DAT<7..0> IN 20D3^ 22B1< ADDR<9..0> 22A2<> 22B2<> 22B2<> CONN_10P 9 7 5 3 1 J32 6 C5 1 D<6> 22C2< D<2>/SPICK 22C2> D<1>/MISO 5 22C2< D<0>/MOSI B7 A5 A<9> D<5> B4 A<8> D<4> A4 A<7> 3 0 C3 A<6> 4 9 B3 A<5> B6 8 A3 A<4> B5 7 C2 A<3> D<3> 6 B2 A<2> 2 5 A2 A<1> ZMOSI A6 ZMISO A7 ZSPISCK 3 4 B1 ZADDR0 ZADDR1 ZADDR2 A1 4 A<0> 5 V3_3 3 SCK CS* 6 1 3 ENGINEER: STEVE SCULLY 2 Y02 2.7V GND HOLD* WP* VCC ZADDR2 ZADDR1 ZADDR0 SP3T SW18 SP3T SW08 SP3T SW04 IN 2 1 0 V3_3 1 09/16/2004 PAGE: 1/8(BLOCK) 22/71(TOTAL) DATE: 4 4 4 4 7 3 8 1 V3_3 AT25160A_U SO SI 2 5 TITLE: DS33Z11/41/44DK01A0 22C4< 22C4< 22D4< ZMOSI 22C4<> ZMISO 22B4<> ZSPISCK 22A6> ZSPICS 22C4<> 2 RB79 6 SCAN ENABLE RMIIMIIS DCEDTES MODEC1 MODEC0 HWMODE RESET_B WR RD ZSPICS CS INT 28B4< 10K RB74 20D3^ 22C4< D 7 10K 8 ADDR<9..0> CR-22 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I8@\_ZTOP_LIB\.\_Z44TOP_DN\(SCH_1):PAGE1_I2@\_ZTOP_LIB\.\_Z44ANDLAN_DN\(SCH_1):PAGE1 SCAN MODE D3 D1 E13 E1 E2 D8 D5 D6 D7 A15 C4 CKPHA E7 E8 F6 CKPHA SCANMOD SCANEN A B C D A 8 B A J48 V3_3 B A J53 CONN_BANANA_2P 1 2 RED CONN_BANANA_2P 1 2 BLACK SDA<11> NC1 NC2 NC3 NC4 N9 N10 M8 N8 P9 P10 T9 F3 F8 F9 G1 RB205 RB224 RB231 RB232 RB225 RB266 TP51 TP52 TP50 TP49 R154 5 6 7 8 9 10 11 7 SDA<10> M9 RB216 4 VSS0 VSS1 VSS2 VSS3 J3 J4 J5 J6 SDA<9> SDA<8> SDA<7> SDA<6> SDA<5> SDA<4> SDA<3> 3.3VDD5 2 VSS6 SD_A<11..0> P11 RB223 3 3.3VDD6 VSS7 SDA<2> 3.3VDD7 2 VSS8 B 24A3> R11 RB190 2 3.3VDD8 2 VSS9 SDA<1> T10 RB196 1 3.3VDD9 2 VSS10 C VSS13 3.3VDD4 2 VSS5 SDA<0> VSS14 R10 3.3VDD12 2 3.3VDD10 2 3.3VDD11 CB381 10UF C89 10UF C88 10UF C101 10UF CB417 10UF CB408 VSS11 2 1.8VDD3 I182 NA DS33Z44 29B6< 23D4< 29A4<> SDRAM CONTROL PWR/GND U22 DS33Z44_U1 2 VSS15 R150 2 VSS16 0 2 VSS17 3.3VDD0 VSS18 3.3VDD1 2 G3 1.8VDD1 VSS19 G4 2 VSS20 3.3VDD2 1.8VDD4 2 VSS21 G5 1.8VDD2 V3_3 1.8VDD5 2 VSS22 3.3VDD3 3.3VDD13 V1_8ZCHIP V1_8ZCHIP 2 VSS23 G6 29B6< 23B4< 29A4<> 1.8VDD6 V3_3 6 5 UNMARKED RESISTORS ARE 30 OHMS 4 2 1 3.3VDD15 4 2 SDATA<30> RB210 1 1.8VDD7 G7 G8 G9 G10 H3 H4 H5 H6 H7 H8 H9 H10 3.3VDD14 2 1.8VDD9 5 RB211 VSS12 2 1.8VDD10 2 SDATA<29> 1 1 1.8VDD0 2 1.8VDD11 2 SDATA<28> RB191 6 2 D 7 SDATA<31> RB218 31 8 CR-23 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I8@\_ZTOP_LIB\.\_Z44TOP_DN\(SCH_1):PAGE1_I2@\_ZTOP_LIB\.\_Z44ANDLAN_DN\(SCH_1):PAGE2 RB212 VSS24 K5 J7 J8 J9 J10 K3 K4 L10 M10 K6 K7 K8 K9 K10 L3 L4 L5 L6 L7 L8 L9 SDATA<27> M11 M12 L12 M13 N13 29 28 27 VSS4 1.8VDD8 CB26 1 470UF CB289 1 0.1UF C184 1 0.1UF CB240 1 0.1UF CB47 1 0.1UF CB312 1 0.1UF CB315 1 0.1UF CB298 1 0.1UF CB323 1 0.1UF CB423 1 0.1UF CB301 1 0.1UF CB421 1 0.1UF CB469 10UF CB335 10UF CB446 10UF CB402 10UF CB492 2 1.8VDD12 C1 D2 E3 F4 M4 A14 P2 N3 L13 M14 K12 E14 F13 G12 1.8VDD13 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 RB249 RB267 R173 RB280 RB268 RB265 R169 RB281 RB248 RB241 RB213 RB242 RB247 RB233 RB240 RB279 RB197 R143 RB189 RB198 RB202 R4 P5 T4 R5 T5 T6 R6 P7 N6 P6 M6 M3 M5 N4 N5 P4 R12 N12 P12 T13 T12 T14 SDATA<1> SDATA<2> SDATA<3> SDATA<4> SDATA<5> SDATA<6> SDATA<7> SDATA<8> SDATA<9> SDATA<10> SDATA<11> SDATA<12> SDATA<13> SDATA<14> SDATA<15> SDATA<16> SDATA<17> SDATA<18> SDATA<19> SDATA<20> SDATA<21> 3 SDATA<0> 26 SD_DQ<31..0> 2 3 ENGINEER: STEVE SCULLY 2 TITLE: DS33Z11/41/44DK01A0 24D7 UNMARKED RESISTORS ARE 30 OHM 25 RB203 SDATA<24> N15 P14 SDATA<23> P13 24 RB204 R14 SDATA<26> 23 RB188 R13 SDATA<22> SDATA<25> 22 R131 RB199 21 R136 10UF CB361 10UF CB495 10UF CB202 10UF CB115 10UF 10UF C90 10UF CB400 1 0.1UF CB162 1 0.1UF C102 1 0.1UF CB386 1 0.1UF CB177 1 0.1UF CB227 1 0.1UF CB246 1 0.1UF CB178 1 0.1UF CB256 1 0.1UF CB255 1 0.1UF CB247 1 0.1UF CB387 1 0.1UF CB211 1 470UF 1 09/16/2004 PAGE: 2/8(BLOCK) 23/71(TOTAL) DATE: 1 A B C D A B 8 7 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 DQ<29> DQ<28> DQ<27> DQ<26> DQ<25> DQ<24> DQ<23> DQ<22> DQ<21> DQ<20> DQ<19> DQ<18> DQ<17> DQ<16> DQ<15> DQ<14> DQ<13> DQ<12> DQ<11> DQ<10> DQ<9> DQ<8> DQ<7> DQ<6> 1 0 MT48LC4M32B2_TSOP_U UB09 6 5 A<11> A<10> A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> BA<1> BA<0> DQM<3> DQM<2> DQM<1> DQM<0> RAS* CAS* WE* CS* CKE CLK V3_3 SYNCHRONOUS DRAM MT48LC4M32B2 - 1 MEG X 32 X 4 BANKS DQ<1> DQ<30> DQ<5> VDD4 VSS4 5 VSS2 DQ<4> VDD3 VSS3 DQ<3> VDDQ8 VSSQ8 3 VDDQ7 VSSQ7 DQ<2> VDDQ6 VSSQ6 4 5 7 8 10 11 13 74 76 77 79 80 82 83 85 31 33 34 36 37 39 40 42 45 47 48 50 51 53 VSSQ5 2 VSSQ4 SD_DQ<31..0> VSSQ3 C 23A2 VDD2 5 VDDQ5 6 VDDQ4 4 2 DQ<0> DQ<31> 54 56 30 31 VSSQ2 D 7 VDD1 VSS1 86 72 58 44 8 VDDQ3 43 29 15 1 CR-24 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I8@\_ZTOP_LIB\.\_Z44TOP_DN\(SCH_1):PAGE1_I2@\_ZTOP_LIB\.\_Z44ANDLAN_DN\(SCH_1):PAGE3 VDDQ2 81 75 55 49 41 35 9 3 VDDQ1 VSSQ1 84 78 52 46 38 32 12 6 4 4 25 0 26 1 27 2 60 3 61 4 62 5 63 6 64 7 65 8 66 9 24 10 21 11 22C8< 22C8< 22C8< 22C8< 22C8< SD_A<11..0> 22 SD_BA0 23 SD_BA1 SD_DQM0 SD_DQM1 SD_DQM2 SD_DQM3 16 71 28 59 22B8< 22C8< SD_CS 22C8< SD_WE 22B8< SD_CAS 22B8< SD_RAS 22B8< 68 67 20 17 18 19 SD_CLKO 3 2 1 ENGINEER: STEVE SCULLY 09/16/2004 PAGE: 3/8(BLOCK) 24/71(TOTAL) 1 DATE: 2 TITLE: DS33Z11/41/44DK01A0 23C8 V3_3 FROM Z11 SYSCLKO 3 A B C D A B C D COL_DET<1> FULLDS<1> PORT2 PIN L2 29D2< 26C5> RCLKI<1> TP57 RSER<1> TP59 RDEN<1> TP58 RXD0<1> 26D5> 26D5> RXD1<1> 26D5> RXD2<1> 26D5> RXD3<1> 26C5> RXDV<1> 26C5> RX_CRS<1> 26C5> RX_ERR<1> PORT1 PIN G2 RXDV RX_CRS/CRS_DV RX_ERR D10 D12 E12 PORT1 PORT2 PORT3 PORT4 8 TSER TCLKI COL_DET FULLDS P16 J15 7 PORT1 PORT2 PORT3 PORT4 J16 L11 C8 L16 M16 TP61 TP60 TP62 TP64 TP65 6 5 4 5 H10S<2> AFCS<2> 29B2< 29A2< TCLKI<2> IN 20D2^ RB339 30 TSER<2> OUT 20D2^ TDEN<2> IO 20D2^ RB164 TXD0<2> 26D5< RB165 30 TXD1<2> 26D5< 30 RB180 TXD2<2> 26D5< 30 RB121 TXD3<2> 26D5< 30 RB179 TX_EN<2> 26C5< 30 TX_CLK<2> 26D5< RX_CLK<2> 26D2> QOVF<2> 29D8<> TCLKI<1> IN 20D2^ RB335 30 TSER<1> OUT 20D2^ TDEN<1> IO 20D2^ R105 TXD0<1> 26D8< R122 30 TXD1<1> 26D8< R96 30 TXD2<1> 26D8< R115 30 TXD3<1> 26D8< 30 R98 TX_EN<1> 26C8< 30 TX_CLK<1> 26D8< RX_CLK<1> 26D5> QOVF<1> 29D8<> H10S<1> 29C2< AFCS<1> 29D2< 4 29B4< 27C2> 27C2> 27C2> 27C2> 27D2> 27D2> 27D2> 27D2> 20D2^ IN 20D2^ IN 20D2^ IN COL_DET<3> FULLDS<3> RCLKI<3> RSER<3> RDEN<3> RXD0<3> RXD1<3> RXD2<3> RXD3<3> RXDV<3> RX_CRS<3> RX_ERR<3> COL_DET<4> FULLDS<4> RCLKI<4> RSER<4> RDEN<4> RXD0<4> RXD1<4> RXD2<4> RXD3<4> RXDV<4> RX_CRS<4> RX_ERR<4> PORT4 PIN T3 29D4< 27C5> 27C5> 27C5> 27C5> 27D5> 27D5> 27D5> 27D5> 20D2^ IN 20D2^ IN 20D2^ IN PORT3 PIN N2 N1 P1 N2 A12 F16 D14 F14 D15 C14 B14 C13 B13 T1 T2 T3 H12 H11 G11 M15 K11 J12 J13 J14 G15 REV01A0 SCHEMATIC SYMBOL (AND PCB) FOR Z44 HAD ERRORS TXD/RXD PINS FOR PHY CONNECTION WERE INCORRECT CORRECT PINOUT SHOWN AT BOTTOM OF PAGE RXD0--RXD3 B11,C11,D11,E11 RXD0--RXD3 K13,K14,H15,K16 RXD0--RXD3 G15,J14,J13,J12 RXD0--RXD3 B13,C13,B14,C14 AFCS H10S QOVF RX_CLK RX_ERR TX_EN RXDV TX_CLK N14 TXD3 RXD3 RX_CRS/CRS_DV L15 TXD2 RXD2 L14 R16 TXD1 RXD1 R15 K2 J2 J1 TXD0 TDEN/TBSYNC PORT C10 B10 C7 A11 A9 E10 E9 D9 C9 B9 F5 F2 F1 TP63 6 RXD0 RDEN/RBSYNC RSER RCLKI TXD0--TXD3 B9, C9, D9, E9 TXD0--TXD3 R15,R16,L15,N14 TXD0--TXD3 F15,G14,H13,H14 TXD0--TXD3 B16,C16,D16,E16 COL_DET<2> 29B2< FULLDS<2> 26C2> 20D2^ IN AFCS H10S QOVF RX_CLK TX_CLK TX_EN TXD3 TXD2 TXD1 TXD0 TDEN/TBSYNC TSER TCLKI DS33Z44_U1 U22 FULLDS RXD3 E11 A10 RXD2 D11 COL_DET RXD1 D13 RXD0 RDEN/RBSYNC H2 C11 RSER PORT B11 RCLKI DS33Z44_U1 U22 H1 7 G2 RCLKI<2> TP54 L2 RSER<2> TP56 K1 20D2^ IN RDEN<2> TP55 L1 20D2^ IN K13 26D2> RXD0<2> K14 26D2> RXD1<2> RXD2<2> H15 26D2> K16 26D2> RXD3<2> K15 26C2> RXDV<2> RX_CRS<2> N16 26C2> T16 26C2> RX_ERR<2> 20D2^ IN 20D2^ IN 20D2^ IN 8 CR-25 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I8@\_ZTOP_LIB\.\_Z44TOP_DN\(SCH_1):PAGE1_I2@\_ZTOP_LIB\.\_Z44ANDLAN_DN\(SCH_1):PAGE4 RCLKI 30 30 30 30 30 30 30 20D2^ IO 20D2^ OUT 20D2^ IN 20D2^ 29A4< 29A4< 29C8<> TXD0<4> 27D4< TXD1<4> 27D4< TXD2<4> 27D4< TXD3<4> 27D4< TX_EN<4> 27C4< TX_CLK<4> 27D4< RX_CLK<4> 27D2> TSER<4> 29C4< 29C4< 29C8<> TXD0<3> 27D8< TXD1<3> 27D8< TXD2<3> 27D8< TXD3<3> 27D8< TX_EN<3> 27C8< TX_CLK<3> 27D8< RX_CLK<3> 27D5> IO 20D2^ 3 STEVE SCULLY 2 1 ENGINEER: QOVF<4> H10S<4> AFCS<4> R124 RB168 RB167 RB171 R126 TDEN<4> RB320 TCLKI<4> QOVF<3> H10S<3> AFCS<3> RB170 30 30 RB187 30 RB169 30 R123 R97 TSER<3>OUT IN 20D2^ 09/16/2004 PAGE: 4/8(BLOCK) 25/71(TOTAL) C12 B12 A8 A13 A16 G13 E16 D16 C16 30 TDEN<3> RB311 TCLKI<3> 1 DATE: AFCS H10S QOVF RX_CLK TX_CLK TX_EN TXD3 TXD2 TXD1 TXD0 B16 R3 R2 R1 J11 F12 B8 H16 G16 E15 H14 H13 G14 F15 P3 M2 M1 2 TITLE: DS33Z11/41/44DK01A0 FULLDS COL_DET RX_ERR TSER TCLKI TDEN/TBSYNC PORT RX_CRS/CRS_DV RXDV RXD3 RXD2 RXD1 RXD0 RDEN/RBSYNC RSER AFCS H10S QOVF RX_CLK TX_CLK TX_EN TXD3 TXD2 TXD1 TXD0 DS33Z44_U1 U22 FULLDS COL_DET RX_ERR TSER TCLKI TDEN/TBSYNC PORT RX_CRS/CRS_DV RXDV RXD3 RXD2 RXD1 RXD0 RDEN/RBSYNC RSER RCLKI DS33Z44_U1 U22 3 A B C D A B C LED_COL_A1<1> 8 30C5v 26C8< 1 1 RED DS13 2 RB71 330 R23 5.1K AMBER R13 5.1K DS07 RB49 2 330 GREEN R19 5.1K DS09 RB58 2 330 LED_TX_A3<1> 1 LED_RX_A4<1> 30C5v 26C8< 30C5v 26C8< 5.1K RB80 5.1K LED_DPLX_A0<1> RB75 LED_RX_ADD4 LED_TX_ADD3 LED_GDLINK_A2<1> 30C5v 26C8< 30C5v 26C8< LED_RX_A4<1> LED_TX_A3<1> 7 LED_GDLINK_ADD2 LED_COL_ADD1 LED_GDLINK_A2<1> _mii_wan_dn PAGES 30-31 LED_COL_A1<1> TX_EN TX_CLK TXD3 TXD2 TXD1 TXD0 LED_DPLX_ADD0 TX_CLK<1> TX_EN<1> TXD0<1> TXD1<1> TXD2<1> TXD3<1> LED_DPLX_A0<1> 30A5v 25C5< 30A5v 25C5<> 30A5v 25C5< 30A5v 25C5< 30A5v 25C5< 30A5v 25C5< V3_3 RXDV RX_ERR RX_CRS RX_CLK RXD3 RXD2 RXD1 RXD0 6 COL_DET 6 26B3> 27B3> 27B6> 22C8< MDIO MDC D HIERARCHICAL BLOCK IN RESET_B RESET_B 30A7v 30A7v 25C8< 30A7v 30A7v 25C8< 25C8< 25C8< 26B4< 5 32C5v 26C5< 32C5v 26C5< 4 1 RB15 5.1K RB14 330 GREEN RB42 330 RED DS05 2 R14 5.1K AMBER DS01 2 LED_RX_A4<2> 1 LED_TX_A3<2> 1 R18 5.1K R22 5.1K RB34 5.1K DS02 RB33 2 330 LED_GDLINK_A2<2> 32C5v 26C5< LED_COL_A1<2> 32C5v 26C5< 32C5v 26C5< LED_RX_ADD4 LED_TX_ADD3 LED_GDLINK_ADD2 LED_DPLX_A0<2> LED_RX_A4<2> 32C5v 26A4<> 32C5v 30C5v LED_TX_A3<2> 32C5v 26A4<> 28A4< 30C7v 26B3> 27B3> 27B6> 22C8< 32C5v 30C5v LED_GDLINK_A2<2> LED_COL_ADD1 32C5v 26A4<> _mii_wan_dn PAGES 32-33 LED_COL_A1<2> TX_EN TX_CLK TXD3 TXD2 TXD1 TXD0 3 HIERARCHICAL BLOCK LED_DPLX_ADD0 TX_CLK<2> TX_EN<2> TXD0<2> TXD1<2> TXD2<2> TXD3<2> 4 LED_DPLX_A0<2> 32A5v 25A5< 32A5v 25A5<> 32A5v 25A5< 32A5v 25A5< 32A5v 25A5< 32A5v 25B5< 32C5v 26B4< RX_CLK<1> 25C5<> 30A7v RX_CRS<1> 25C8< 30A7v RX_ERR<1> 25C8< 30A7v RXDV<1> 25C8< 30A7v COL_DET<1> 25C8< 32C5v 30A7v RXD0<1> RXD1<1> RXD2<1> RXD3<1> 5 V3_3 RESET_B 7 RXDV RX_ERR RX_CRS RX_CLK RXD3 RXD2 RXD1 RXD0 COL_DET V3_3 26B6> 27B3> 27B6> 22C8< 3 32A7v 30C7v 32C7v L01 STEVE SCULLY 1 2 1 1 32C5v 30C5v 09/16/2004 CHASSIS 1 PAGE: 5/8(BLOCK) 26/71(TOTAL) DATE: CHASSIS GND FOR PHY LB02 100O100MZH 2 2 100O100MZH 28A4< 32C7v 26B6> 27B3> 27B6> 22C8< 32C5v 30C5v TITLE: DS33Z11/41/44DK01A0 ENGINEER: 32A7v 25A8< 32A7v 32A7v 25A8< 25A8< 25B8< RX_CLK<2> 25A5<> 32A7v RX_CRS<2> 25A8< 32A7v RX_ERR<2> 25A8< 32A7v RXDV<2> 25A8< 32A7v COL_DET<2> 25A8< 32A7v RXD0<2> RXD1<2> RXD2<2> RXD3<2> 2 27C3> 27C7> 20C3^ 22A6< 26B7< MDIO MDC 8 MII_CLK<2> CR-26 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I8@\_ZTOP_LIB\.\_Z44TOP_DN\(SCH_1):PAGE1_I2@\_ZTOP_LIB\.\_Z44ANDLAN_DN\(SCH_1):PAGE5 MII_CLK<1> MDC MDIO 1 MII_CLK CB03 10UF CB01 10UF CB02 10UF RESET_B 0.1UF MDC MDIO 2 C04 MII_CLK A B C D 27B8< 36C5v 27B8< 36C5v LED_COL_A1<3> LED_DPLX_A0<3> 8 36C5v 27C8< 36C5v 27C8< 1 AMBER RED RB36 5.1K DS04 RB43 2 330 LED_RX_A4<3> 1 GREEN RB32 5.1K DS03 RB40 2 330 RB62 5.1K DS12 RB77 2 330 1 LED_TX_A3<3> 36C5v 27C8< 5.1K RB82 5.1K RB51 LED_RX_ADD4 LED_TX_ADD3 LED_GDLINK_A2<3> 36C5v 27C8< 36C5v 27C8< LED_RX_A4<3> LED_TX_A3<3> 7 LED_GDLINK_ADD2 LED_COL_ADD1 LED_GDLINK_A2<3> _mii_wan_dn PAGES 36-37 LED_COL_A1<3> TX_EN TX_CLK TXD3 TXD2 TXD1 TXD0 LED_DPLX_ADD0 TX_CLK<3> TX_EN<3> TXD0<3> TXD1<3> TXD2<3> TXD3<3> LED_DPLX_A0<3> 36A5v 25C1< 36A5v 25C1<> 36A5v 25C1< 36A5v 25C1< 36A5v 25C1< 36A5v 25C1< V3_3 V3_3 RESET_B A B C D HIERARCHICAL BLOCK 7 MDIO MDC 8 COL_DET RXDV RX_ERR RX_CRS RX_CLK RXD3 RXD2 RXD1 RXD0 6 6 26B3> 26B6> 27B3> 22C8< 36A7v 36A7v 25C4< 36A7v 36A7v 25C4< 25C4< 25C4< 5 LED_COL_A1<4> LED_DPLX_A0<4> GREEN 1 34C5v 27C5< 4 1 RB53 330 RED DS08 2 R15 5.1K AMBER RB73 5.1K R24 330 R20 5.1K DS10 RB59 2 330 DS14 LED_TX_A3<4> LED_RX_A4<4> 34C5v 27C5< 34C5v 27C5< R30 5.1K R29 5.1K LED_RX_ADD4 LED_TX_ADD3 LED_GDLINK_ADD2 LED_GDLINK_A2<4> 34C5v 27C5< 34C5v 27C5< 34C5v 36C5v LED_RX_A4<4> LED_TX_A3<4> 34C5v 27A4<> 34C5v 27A4<> LED_GDLINK_A2<4> LED_COL_ADD1 LED_COL_A1<4> 34C5v 27A4<> _mii_wan_dn PAGES 34-35 34C5v 27B4< TX_EN TX_CLK TXD3 TXD2 TXD1 TXD0 LED_DPLX_ADD0 TX_CLK<4> TX_EN<4> TXD0<4> TXD1<4> TXD2<4> TXD3<4> 3 HIERARCHICAL BLOCK LED_DPLX_A0<4> 34A5v 25A1< 34A5v 25A1<> 34A5v 25A1< 34A5v 25A1< 34A5v 25B1< 34A5v 25B1< 4 34C5v 27B4< 28A4< 36C7v 26B3> 26B6> 27B3> 22C8< 34C5v 36C5v RX_CLK<3> 25C1<> 36A7v RX_CRS<3> 25C4< 36A7v RX_ERR<3> 25C4< 36A7v RXDV<3> 25C4< 36A7v COL_DET<3> 25C4< 36A7v RXD0<3> RXD1<3> RXD2<3> RXD3<3> 5 CR-27 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I8@\_ZTOP_LIB\.\_Z44TOP_DN\(SCH_1):PAGE1_I2@\_ZTOP_LIB\.\_Z44ANDLAN_DN\(SCH_1):PAGE6 MDC MDIO 2 RESET_B V3_3 RESET_B 1 MII_CLK RXDV RX_ERR RX_CRS RX_CLK RXD3 RXD2 RXD1 RXD0 COL_DET 3 ENGINEER: 34A7v 36C7v 34C7v STEVE SCULLY 2 09/16/2004 34C5v 36C5v 1 1 PAGE: 6/8(BLOCK) 27/71(TOTAL) DATE: 28A4< 34C7v 26B3> 26B6> 27B6> 22C8< 34C5v 36C5v TITLE: DS33Z11/41/44DK01A0 26B3> 26B6> 27B6> 22C8< 34A7v 25A4< 34A7v 34A7v 25A4< 25B4< 25B4< RX_CLK<4> 25A1<> 34A7v RX_CRS<4> 25A4< 34A7v RX_ERR<4> 25A4< 34A7v RXDV<4> 25A4< 34A7v COL_DET<4> 25A4< 34A7v RXD0<4> RXD1<4> RXD2<4> RXD3<4> 2 26B3> 27C7> 20C3^ 22A6< 26B7< MII_CLK<4> RESET_B MII_CLK<3> MDC MDIO MDIO MDC MII_CLK A B C D A B C D V3_3 8 8 GND V3_3 4 1 GND 1 OSC Y05 7 OUT VCC 5 8 30 OSC100MHZ R112 V3_3 100.000MHZ_3.3V 7 1 6 UXB03 4 BUFFER NC7SZ86_U 6 R111 30 4 1 22B8< 5 GND 1 OSC OUT VCC 5 8 30 R116 30 30 R100 30 RB61 30 R17 4 22D8<> 27B2> MII_CLK<4> REF_CLK 27B6> 26B2> MII_CLK<3> MII_CLK<2> 2 2 26B6> RB08 2 2.0K MII_CLK<1> CKPHA 1 RB83 2 2.0K SCANEN 1 2 RMIIMIIS 1 RB76 2 2.0K 2 RB39 2 2.0K SCANMOD 1 2 2 RB02 2 2.0K 1 RB98 2 2.0K MODEC1 1 22A5< R25 4 HWMODE 22A5< 22A5< 22A6< 20C2^ 22A6> 20C2^ 22A6> 25.000MHZ_3.3V Y01 V3_3 SD_CLKI 5 CR-28 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I8@\_ZTOP_LIB\.\_Z44TOP_DN\(SCH_1):PAGE1_I2@\_ZTOP_LIB\.\_Z44ANDLAN_DN\(SCH_1):PAGE7 SP3T SW03 SP3T SW20 SP3T SW19 SP3T SW05 SP3T SW01 SP3T SW21 V3_3 22A6< 20C2^ 22A6> 3 ENGINEER: 1 RB56 2 2.0K RB06 2 2.0K 2 2 SP3T SW09 SP3T SW02 STEVE SCULLY 2 1 V3_3 1 3 DCEDTESTRI 4 1 3 MODEC0TRI 4 1 09/16/2004 PAGE: 7/8(BLOCK) 28/71(TOTAL) DATE: SIGNAME_TRI DOES NOT CONNECT ANYWHERE (HELPS PCB NETLIST) DCEDTES 1 MODEC0 2 TITLE: DS33Z11/41/44DK01A0 1 3 CKPHATRI 4 1 3 SCANENTRI 4 1 3 SCANMODTRI 4 1 3 RMIIMIISTRI 4 1 3 MODEC1TRI 4 1 3 HWMODETRI 4 3 A B C D A B C QOVF<3> QOVF<4> 25A1> 8 4 3 2 1 V3_3 V3_3 TP76 TP73 2 CB411 1 QOVF<2> 25C1> 0.1UF 2 C213 1 1 2 RB360 DS48 1 2 330 330 RB354 DS47 RB350 DS46 1 2 330 SHDN RST IN IN 7 GND SET OUT OUT U11 MAX1792 0.1UF 2 CB279 1 25A5> 0.1UF 2 CB241 1 TP68 0.1UF QOVF<1> 8 2 CB254 1 5 6 7 RED RED RED 0.1UF 2 CB228 1 25C5> 0.1UF 2 CB15 1 RED 23D4< 23B4< 29A4<> 0.1UF 2 CB231 1 RB344 DS45 1 2 330 0.1UF TP67 10UF 6 6 2 CB261 1 1UF 7 0.1UF 2 CB380 1 8 V1_8ZCHIP 0.1UF D 2 CB468 1 2 C214 1 1UF C64 0.1UF 2 CB185 1 1UF CB13 1 2 0.1UF 2 CB358 1 1 2 1 1UF CB184 0.1UF 1UF 0.1UF 2 CB248 1 CB133 2 1 C51 0.1UF 2 CB439 1 2 C80 0.1UF 2 CB366 1 2 1 0.1UF 2 CB368 1 2 1 2 1UF CB176 1 0.1UF 2 CB367 1 5 H10S<3> AFCS<3> 1 1 AFCS<4> H10S<4> 4 2.0K RB361 2.0K RB362 2.0K 2 2 2 2 2 2 2.0K RB352 2.0K RB351 2.0K RB353 RB363 23B4< 23D4< 29B6< 25A1< 4 FULLDS<3> FULLDS<4> 1 25C1< 25C1< 25C4< 25A1< 25A4< V1_8ZCHIP 5 CR-29 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I8@\_ZTOP_LIB\.\_Z44TOP_DN\(SCH_1):PAGE1_I2@\_ZTOP_LIB\.\_Z44ANDLAN_DN\(SCH_1):PAGE8 1UF SP3T SW39 SP3T SW41 SP3T 1 3 4 V3_3 1 3 4 25A5< H10S<2> AFCS<2> 1 1 3 ENGINEER: STEVE SCULLY 2 1 2.0K RB346 2.0K RB347 2.0K 2 2 2 2 2 2 2.0K RB340 2.0K RB338 2.0K RB341 RB348 H10S<1> FULLDS<2> 1 25C5< AFCS<1> 1 TITLE: DS33Z11/41/44DK01A0 H10STRI<4> 1 3 AFCSTRI<4> 4 25A5< 2 FULLDS<1> 1 25B5< 25C8< 25A8< H10STRI<3> 1 3 AFCSTRI<3> 4 1 3 FULLDSTRI<3> 4 V3_3 1 3 FULLDSTRI<4> 4 SP3T SW36 SP3T SW37 SP3T SW40 2 2 2 SW38 3 SP3T SW33 SP3T SW34 SP3T 1 3 4 V3_3 1 09/16/2004 PAGE: 8/8(BLOCK) 29/71(TOTAL) DATE: H10STRI<2> 1 3 AFCSTRI<2> 4 1 3 4 D A B C H10STRI<1> 1 3 AFCSTRI<1> 4 1 3 FULLDSTRI<1> 4 V3_3 1 3 FULLDSTRI<2> 4 SP3T SW29 SP3T SW31 SP3T SW35 2 2 2 2 2 2 SW30 1 A B C 2 CB104 1 0.1UF 10UF 1 2 C41 V3_3 OUT RESERVED3 8 RXD2 RXD3 9 7 5 3 10 8 6 4 10 8 6 4 2 CONN_10P 9 7 5 3 1 2 RESERVED11 47 1 RESERVED10 44 RXD0 RXD1 X2 48 J16 RESET* 46 RESET_B X1 RBIAS 49 3 MII_CLK RBIAS RESERVED5 RESERVED14 RESERVED4 RESERVED13 RX_CLK RXDV RX_CRS COL_DET RX_ERR OUT OUT 26C8^ IN 31C8< 31C6<> 26C6^ OUT 26C6^ 31B5< OUT 26C6^ 31C5< OUT 26D8^ OUT 31C4< CONTROL 17 16 15 AN_EN AN_1 AN_0 TX_EN TX_CLK 9 7 5 3 10 8 6 4 10 8 6 4 2 CONN_10P 9 7 5 3 1 2 18 LED_SPEED 1 19 LED_RX/PHYAD4 J15 20 LED_TX/PHYAD3 TXD1 TXD0 TXD3 TXD2 RB37 5.1K RB30 5.1K RB09 5.1K TP02 AN0 6 5 2 JP01 AN_EN V3_3 2 JP07 IN 26D8^ 31C8< 4 26D8^ 31C8< IN 26D8^ 31C8< IN 4 3 JP12 V3_3 LEDS NEED TO BE ATTACHED OUTSIDE OF MODULE DUE TO STRAP ADAPTING OPTION OF DP83847 IN 26D8^ 31C8< 2 IO AN1 ON Z44 CARD ALL 4 PORTS MUST BE PLACED WITH EQUAL SPACING AND A COMMON CENTER LINE 7 IO IO IO LED_TX_ADD3 IO LED_RX_ADD4 21 LED_GDLINK_ADD2 LED_COL_ADD1 22 LED_COL/PHYAD1 LED_GDLNK/PHYAD2 LED_DPLX_ADD0 23 26C6^ LED_DPLX/PHYAD0 MDC IN MDIO IO 30 24 25 R101 MDIO MDC PLACEMENT NOTE: TESTPOINTS (SHOWN ABOVE) MUST BE PLACED THE SAME FOR EACH PORT TO ALLOW USE OF A DIFFERENT PHY CARD IF DESIRED. PLACEMENT SHOULD ALLOW 0.2 BETWEEN CONNECTORS. 31B8< 26D6^ OUT 31B8< 26D6^ OUT 31B8< 26D6^ 31B8< 26D6^ OUT 26C7^ IN 26C6^ IN R06 10.0K U02 DP83847_U1 RESERVED6 RESERVED15 C1 RESERVED7 RESERVED16 42 VDD/IO_VDD1 4 5 8 9 12 13 34 RESERVED12 VDD/IO_VDD2 28 56 14 AN_V3_3 GND2 COMPONETS FOR C1 AND RBIAS MUST BE PLACED CLOSE TO PIN 2 RESERVED2 C1PIN 1 RESERVED1 GND3 RESERVED8 RESERVED17 VDD1 57 59 63 VDD2 GND4 VDD/ANA_VDD GND1 V3_3 1 D 3 1 RESERVED9 RESERVED18 50 51 52 53 54 55 61 3 1 VDD3 GND5 58 60 62 64 65 3 1 5 V3_3 2 2 CB10 1 3 ENGINEER: STEVE SCULLY 2 TITLE: DS33Z11/41/44DK01A0 2 6 2 L08 1 100O100MZH 10UF 7 2 1 8 2 1 AN_V3_3 1 CR-30 : @\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page5_i54@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page1 CB221 1 0.1UF CB284 1 0.1UF CB291 1 0.1UF C18 1 0.1UF 2 CB72 1 0.1UF 2 CB40 1 0.1UF CB292 10UF CB87 10UF 2 1 1 30/71(TOTAL) 09/16/2004 PAGE: 1/2(BLOCK) DATE: C25 2 10UF 2 CB81 0.1UF CB73 2 0.1UF A B C D A B C D 8 RD_P RD_N RXD0 RXD1 RXD2 RXD3 8 TXD<3> 41 R106 30 30 RB112 30 RB125 30 RD+ RD- 7 6 7 RXD<3> RXD<2> 27 26 RXD<1> 29 RXD<0> TXD<2> 40 30 TXD<1> 39 RB100 TXD<0> 38 TXD0 TXD1 TXD2 TXD3 TX_EN 37 TX_ER TX_EN 35 TD- TD+ COL CRS/LED_CFG* TX_CLK RX_CLK RX_DV RX_ER/PAUSE_EN* PORT DP83847_U1 U02 7 11 10 43 45 36 32 31 33 6 TD_P TD_N RB135 30 30 RB127 RXDV RX_ERR 6 RX_CRS COL_DET RB1392 10K 5 5 1 UX054 RB84 RB113 DNP UX104 NC7SZ86_U BUFFER DNP 1 NC7SZ86_U BUFFER RB119 RB105 30 30 4 RX_CLK TX_CLK 4 CR-31 : @\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page5_i54@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page2 P5 P6 5 6 TD_N CHASSIS 8 SH2 J7,8 J4,5 J6 J3 J2 J1 SH1 1 CONN_HFJ11_2450_U P8 P3 3 TD_P P2 4 P1 RD_N 2 1 P4 RD_P J01 SYM_1 3 2 1 ENGINEER: STEVE SCULLY 09/16/2004 PAGE: 2/2(BLOCK) 31/71(TOTAL) CHASSIS 10 CHASSIS 9 DATE: RESISTORS FOR TD+-/RD+SHOULD BE PLACED CLOSE TO PHY CAPS FOR XFRM CENTER TAP SHOULD BE PLACED CLOSE TO XFRM RB25 49.9 RB24 49.9 RB23 54.9 RB22 54.9 .1UF CB32 2 TITLE: DS33Z11/41/44DK01A0 V3_3 .1UF CB60 3 CB299 .1UF A B C D A B C 2 CB103 1 0.1UF 10UF 1 2 C37 V3_3 OUT RESERVED3 8 RXD2 RXD3 9 7 5 3 10 8 6 4 10 8 6 4 2 CONN_10P 9 7 5 3 1 2 RESERVED11 47 1 RESERVED10 44 RXD0 RXD1 X2 48 J20 RESET* 46 RESET_B X1 RBIAS 49 3 MII_CLK RBIAS RESERVED5 RESERVED14 RESERVED4 RESERVED13 RX_CLK RXDV RX_CRS COL_DET RX_ERR OUT OUT 26C4^ IN 33C8< 33C6<> 26C2^ OUT 26C2^ 33B5< OUT 26C2^ 33C5< OUT 26D4^ OUT 33C4< CONTROL 17 16 15 AN_EN AN_1 AN_0 TX_EN TX_CLK 9 7 5 3 10 8 6 4 10 8 6 4 2 CONN_10P 9 7 5 3 1 2 18 LED_SPEED 1 19 LED_RX/PHYAD4 J19 20 LED_TX/PHYAD3 TXD1 TXD0 TXD3 TXD2 RB38 5.1K RB31 5.1K RB16 5.1K TP04 AN0 6 5 2 JP03 AN_EN V3_3 2 JP06 IN 26D4^ 33C8< 4 26D4^ 33C8< IN 26D4^ 33C8< IN 4 3 JP11 V3_3 LEDS NEED TO BE ATTACHED OUTSIDE OF MODULE DUE TO STRAP ADAPTING OPTION OF DP83847 IN 26D4^ 33C8< 2 IO AN1 ON Z44 CARD ALL 4 PORTS MUST BE PLACED WITH EQUAL SPACING AND A COMMON CENTER LINE 7 IO IO IO LED_TX_ADD3 IO LED_RX_ADD4 21 LED_GDLINK_ADD2 LED_COL_ADD1 22 LED_COL/PHYAD1 LED_GDLNK/PHYAD2 LED_DPLX_ADD0 23 26C3^ LED_DPLX/PHYAD0 MDC IN MDIO IO 30 24 25 R117 MDIO MDC PLACEMENT NOTE: TESTPOINTS (SHOWN ABOVE) MUST BE PLACED THE SAME FOR EACH PORT TO ALLOW USE OF A DIFFERENT PHY CARD IF DESIRED. PLACEMENT SHOULD ALLOW 0.2 BETWEEN CONNECTORS. 33B8< 26D2^ OUT 33B8< 26D2^ OUT 33B8< 26D2^ 33B8< 26D2^ OUT 26C3^ IN 26C3^ IN R05 10.0K U05 DP83847_U1 RESERVED6 RESERVED15 C1 RESERVED7 RESERVED16 42 VDD/IO_VDD1 4 5 8 9 12 13 34 RESERVED12 VDD/IO_VDD2 28 56 14 AN_V3_3 GND2 COMPONETS FOR C1 AND RBIAS MUST BE PLACED CLOSE TO PIN 2 RESERVED2 C1PIN 1 RESERVED1 GND3 RESERVED8 RESERVED17 VDD1 57 59 63 VDD2 GND4 VDD/ANA_VDD GND1 V3_3 1 D 3 1 RESERVED9 RESERVED18 50 51 52 53 54 55 61 3 1 VDD3 GND5 58 60 62 64 65 3 1 5 V3_3 2 2 CB496 1 3 ENGINEER: STEVE SCULLY 2 TITLE: DS33Z11/41/44DK01A0 2 6 2 L06 1 100O100MZH 10UF 7 2 1 8 2 1 AN_V3_3 1 CR-32 : @\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page5_i91@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page1 CB209 1 0.1UF CB91 1 0.1UF CB88 1 0.1UF C209 1 0.1UF 2 CB473 1 0.1UF 2 CB476 1 0.1UF CB174 10UF CB125 10UF 2 1 1 32/71(TOTAL) 09/16/2004 PAGE: 1/2(BLOCK) DATE: C13 2 10UF 2 CB46 0.1UF CB57 2 0.1UF A B C D A B C D 8 RD_P RD_N RXD0 RXD1 RXD2 RXD3 8 TXD<3> 41 R27 30 30 RB108 30 RB116 30 RD+ RD- 7 6 7 RXD<3> RXD<2> 27 26 RXD<1> 29 RXD<0> TXD<2> 40 30 TXD<1> 39 RB97 TXD<0> 38 TXD0 TXD1 TXD2 TXD3 TX_EN 37 TX_ER TX_EN 35 TD- TD+ COL CRS/LED_CFG* TX_CLK RX_CLK RX_DV RX_ER/PAUSE_EN* PORT DP83847_U1 U05 7 11 10 43 45 36 32 31 33 6 30 30 TD_P TD_N R21 RB131 RXDV RX_ERR 6 RX_CRS COL_DET RB1322 10K 5 5 1 UX074 RB85 RB122 DNP UX024 NC7SZ86_U BUFFER DNP 1 NC7SZ86_U BUFFER R28 RB103 30 30 4 RX_CLK TX_CLK 4 CR-33 : @\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page5_i91@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page2 P5 P6 5 6 TD_N CHASSIS 8 SH2 J7,8 J4,5 J6 J3 J2 J1 SH1 1 CONN_HFJ11_2450_U P8 P3 3 TD_P P2 4 P1 RD_N 2 1 P4 RD_P J05 SYM_1 3 2 1 ENGINEER: STEVE SCULLY 09/16/2004 PAGE: 2/2(BLOCK) 33/71(TOTAL) CHASSIS 10 CHASSIS 9 DATE: RESISTORS FOR TD+-/RD+SHOULD BE PLACED CLOSE TO PHY CAPS FOR XFRM CENTER TAP SHOULD BE PLACED CLOSE TO XFRM RB29 49.9 RB28 49.9 RB27 54.9 RB26 54.9 .1UF CB25 2 TITLE: DS33Z11/41/44DK01A0 V3_3 .1UF C05 3 CB282 .1UF A B C D A B C 2 CB101 1 0.1UF 10UF 1 2 C35 V3_3 OUT RESERVED3 8 RXD2 RXD3 9 7 5 3 10 8 6 4 10 8 6 4 2 CONN_10P 9 7 5 3 1 2 RESERVED11 47 1 RESERVED10 44 RXD0 RXD1 X2 48 J22 RESET* 46 RESET_B X1 RBIAS 49 3 MII_CLK RBIAS RESERVED5 RESERVED14 RESERVED4 RESERVED13 RX_CLK RXDV RX_CRS COL_DET RX_ERR OUT OUT 27C4^ IN 35C8< 35C6<> 27C2^ OUT 27C2^ 35B5< OUT 27C2^ 35C5< OUT 27D4^ OUT 35C4< CONTROL 17 16 15 AN_EN AN_1 AN_0 TX_EN TX_CLK 9 7 5 3 10 8 6 4 10 8 6 4 2 CONN_10P 9 7 5 3 1 2 18 LED_SPEED 1 19 LED_RX/PHYAD4 J21 20 LED_TX/PHYAD3 TXD1 TXD0 TXD3 TXD2 RB41 5.1K RB35 5.1K RB17 5.1K TP01 AN0 6 5 2 JP04 AN_EN V3_3 2 JP08 IN 27D4^ 35C8< 4 27D4^ 35C8< IN 27D4^ 35C8< IN 4 3 JP13 V3_3 LEDS NEED TO BE ATTACHED OUTSIDE OF MODULE DUE TO STRAP ADAPTING OPTION OF DP83847 IN 27D4^ 35C8< 2 IO AN1 ON Z44 CARD ALL 4 PORTS MUST BE PLACED WITH EQUAL SPACING AND A COMMON CENTER LINE 7 IO IO IO LED_TX_ADD3 IO LED_RX_ADD4 21 LED_GDLINK_ADD2 LED_COL_ADD1 22 LED_COL/PHYAD1 LED_GDLNK/PHYAD2 LED_DPLX_ADD0 23 27C3^ LED_DPLX/PHYAD0 MDC IN MDIO IO 30 24 25 R102 MDIO MDC PLACEMENT NOTE: TESTPOINTS (SHOWN ABOVE) MUST BE PLACED THE SAME FOR EACH PORT TO ALLOW USE OF A DIFFERENT PHY CARD IF DESIRED. PLACEMENT SHOULD ALLOW 0.2 BETWEEN CONNECTORS. 35B8< 27D2^ OUT 35B8< 27D2^ OUT 35B8< 27D2^ 35B8< 27D2^ OUT 27C3^ IN 27C3^ IN R09 10.0K U06 DP83847_U1 RESERVED6 RESERVED15 C1 RESERVED7 RESERVED16 42 VDD/IO_VDD1 4 5 8 9 12 13 34 RESERVED12 VDD/IO_VDD2 28 56 14 AN_V3_3 GND2 COMPONETS FOR C1 AND RBIAS MUST BE PLACED CLOSE TO PIN 2 RESERVED2 C1PIN 1 RESERVED1 GND3 RESERVED8 RESERVED17 VDD1 57 59 63 VDD2 GND4 VDD/ANA_VDD GND1 V3_3 1 D 3 1 RESERVED9 RESERVED18 50 51 52 53 54 55 61 3 1 VDD3 GND5 58 60 62 64 65 3 1 5 V3_3 2 2 CB128 1 3 ENGINEER: STEVE SCULLY 2 TITLE: DS33Z11/41/44DK01A0 2 6 2 L05 1 100O100MZH 10UF 7 2 1 8 2 1 AN_V3_3 1 CR-34 : @\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page6_i1@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page1 CB167 1 0.1UF CB71 1 0.1UF CB74 1 0.1UF CB474 1 0.1UF 2 CB196 1 0.1UF 2 CB283 1 0.1UF CB357 10UF CB64 10UF 2 1 1 34/71(TOTAL) 09/16/2004 PAGE: 1/2(BLOCK) DATE: C11 2 10UF 2 CB38 0.1UF CB51 2 0.1UF A B C D A B C D 8 RD_P RD_N RXD0 RXD1 RXD2 RXD3 8 TXD<3> 41 RB138 30 30 R125 30 RB137 30 RD+ RD- 7 6 7 RXD<3> RXD<2> 27 26 RXD<1> 29 RXD<0> TXD<2> 40 30 TXD<1> 39 RB128 TXD<0> 38 TXD0 TXD1 TXD2 TXD3 TX_EN 37 TX_ER TX_EN 35 TD- TD+ COL CRS/LED_CFG* TX_CLK RX_CLK RX_DV RX_ER/PAUSE_EN* PORT DP83847_U1 U06 7 11 10 43 45 36 32 31 33 6 TD_P TD_N RB133 30 30 RB123 RXDV RX_ERR 6 RX_CRS COL_DET RB1402 10K 5 5 1 UX084 RB86 RB120 DNP UX094 NC7SZ86_U BUFFER DNP 1 NC7SZ86_U BUFFER RB115 RB104 30 30 4 RX_CLK TX_CLK 4 CR-35 : @\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page6_i1@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page2 P5 P6 5 6 TD_N CHASSIS 8 SH2 J7,8 J4,5 J6 J3 J2 J1 SH1 1 CONN_HFJ11_2450_U P8 P3 3 TD_P P2 4 P1 RD_N 2 1 P4 RD_P J03 SYM_1 3 2 1 ENGINEER: STEVE SCULLY 09/16/2004 PAGE: 2/2(BLOCK) 35/71(TOTAL) CHASSIS 10 CHASSIS 9 DATE: RESISTORS FOR TD+-/RD+SHOULD BE PLACED CLOSE TO PHY CAPS FOR XFRM CENTER TAP SHOULD BE PLACED CLOSE TO XFRM RB21 49.9 RB20 49.9 RB18 54.9 RB19 54.9 .1UF CB29 2 TITLE: DS33Z11/41/44DK01A0 V3_3 .1UF CB34 3 C106 .1UF A B C D A B C 1 2 C28 0.1UF V3_3 OUT RESERVED3 8 RXD2 RXD3 9 7 5 3 10 8 6 4 10 8 6 4 2 CONN_10P 9 7 5 3 1 2 RESERVED11 47 1 RESERVED10 44 RXD0 RXD1 X2 48 J18 RESET* 46 RESET_B X1 RBIAS 49 3 MII_CLK RBIAS RESERVED5 RESERVED14 RESERVED4 RESERVED13 RX_CLK RXDV RX_CRS COL_DET RX_ERR OUT OUT 27C8^ IN 37C8< 37C6<> 27C6^ OUT 27C6^ 37B5< OUT 27C6^ 37C5< OUT 27D8^ OUT 37C4< CONTROL U03 DP83847_U1 17 16 15 AN_EN AN_1 AN_0 TX_EN TX_CLK 9 7 5 3 10 8 6 4 10 8 6 4 2 CONN_10P 9 7 5 3 1 2 18 LED_SPEED 1 19 LED_RX/PHYAD4 J17 20 LED_TX/PHYAD3 TXD1 TXD0 TXD3 TXD2 RB01 5.1K RB03 5.1K RB50 5.1K TP05 AN0 6 5 2 JP02 AN_EN V3_3 2 JP05 IN 27D8^ 37C8< 4 27D8^ 37C8< IN 27D8^ 37C8< IN 4 3 JP10 V3_3 LEDS NEED TO BE ATTACHED OUTSIDE OF MODULE DUE TO STRAP ADAPTING OPTION OF DP83847 IN 27D8^ 37C8< 2 IO AN1 ON Z44 CARD ALL 4 PORTS MUST BE PLACED WITH EQUAL SPACING AND A COMMON CENTER LINE 7 IO IO IO LED_TX_ADD3 IO LED_RX_ADD4 21 LED_GDLINK_ADD2 LED_COL_ADD1 22 LED_COL/PHYAD1 LED_GDLNK/PHYAD2 LED_DPLX_ADD0 23 27C6^ LED_DPLX/PHYAD0 MDC IN MDIO IO 30 24 25 R26 MDIO MDC PLACEMENT NOTE: TESTPOINTS (SHOWN ABOVE) MUST BE PLACED THE SAME FOR EACH PORT TO ALLOW USE OF A DIFFERENT PHY CARD IF DESIRED. PLACEMENT SHOULD ALLOW 0.2 BETWEEN CONNECTORS. 37B8< 27D6^ OUT 37B8< 27D6^ OUT 37B8< 27D6^ 37B8< 27D6^ OUT 27C7^ IN 27C6^ IN R11 10.0K C1 RESERVED6 RESERVED15 42 RESERVED7 RESERVED16 C34 1 10UF 2 VDD/IO_VDD1 4 5 8 9 12 13 34 RESERVED12 VDD/IO_VDD2 28 56 14 AN_V3_3 GND2 COMPONETS FOR C1 AND RBIAS MUST BE PLACED CLOSE TO PIN 2 RESERVED2 C1PIN 1 RESERVED1 GND3 RESERVED8 RESERVED17 VDD1 57 59 63 VDD2 GND4 VDD/ANA_VDD GND1 V3_3 1 D 3 1 RESERVED9 RESERVED18 50 51 52 53 54 55 61 3 1 VDD3 GND5 58 60 62 64 65 3 1 5 V3_3 2 2 CB164 1 3 ENGINEER: STEVE SCULLY 2 TITLE: DS33Z11/41/44DK01A0 2 6 2 L07 1 100O100MZH 10UF 7 2 1 8 2 1 AN_V3_3 1 CR-36 : @\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page6_i34@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page1 CB325 1 0.1UF CB326 1 0.1UF C17 1 0.1UF C24 1 0.1UF 2 C29 1 0.1UF 2 CB76 1 0.1UF CB20 10UF CB470 10UF 2 1 1 36/71(TOTAL) 09/16/2004 PAGE: 1/2(BLOCK) DATE: C31 2 10UF 2 CB83 0.1UF CB77 2 0.1UF A B C D A B C D 8 RD_P RD_N RXD0 RXD1 RXD2 RXD3 8 TXD<3> 41 RB130 30 30 RB107 30 RB114 30 RD+ RD- 7 6 7 RXD<3> RXD<2> 27 26 RXD<1> 29 RXD<0> TXD<2> 40 30 TXD<1> 39 RB96 TXD<0> 38 TXD0 TXD1 TXD2 TXD3 TX_EN 37 TX_ER TX_EN 35 TD- TD+ COL CRS/LED_CFG* TX_CLK RX_CLK RX_DV RX_ER/PAUSE_EN* PORT DP83847_U1 U03 7 11 10 43 45 36 32 31 33 6 TD_P TD_N RB136 30 30 RB124 RXDV RX_ERR 6 RX_CRS COL_DET RB1412 10K 5 5 1 UX064 RB81 RB111 DNP UX014 NC7SZ86_U BUFFER DNP 1 NC7SZ86_U BUFFER RB117 RB99 30 30 4 RX_CLK TX_CLK 4 CR-37 : @\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page6_i34@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page2 P5 P6 5 6 TD_N CHASSIS 8 SH2 J7,8 J4,5 J6 J3 J2 J1 SH1 1 CONN_HFJ11_2450_U P8 P3 3 TD_P P2 4 P1 RD_N 2 1 P4 RD_P J02 SYM_1 3 2 1 ENGINEER: STEVE SCULLY 09/16/2004 PAGE: 2/2(BLOCK) 37/71(TOTAL) CHASSIS 10 CHASSIS 9 DATE: RESISTORS FOR TD+-/RD+SHOULD BE PLACED CLOSE TO PHY CAPS FOR XFRM CENTER TAP SHOULD BE PLACED CLOSE TO XFRM RB13 49.9 RB12 49.9 RB11 54.9 RB10 54.9 .1UF C09 2 TITLE: DS33Z11/41/44DK01A0 V3_3 .1UF CB33 3 C112 .1UF A B C D A B 61 58 57 56 55 54 8 EB1* INT3* EB2* INT4 EB3* INT5* INT6* INT7* RXD1 TXD1 RXD2 TXD2 TEST ICOC10 ICOC11 ICOC12 ICOC13 ICOC20 ICOC21 ICOC22 PQA3 XTAL MMC2107 CONTROL EB0* INT2* 53 PQB3 INT1* ICOC23 PQB2 INT0* 52 I68 GND TEST 63 SCI2_OUT 66 68 SCI2_IN SCI1_OUT 69 70 SCI1_IN ICOC23 ICOC22 ICOC21 ICOC20 ICOC13 ICOC12 ICOC11 ICOC10 PQB1 YC0 C PQA1 EXTAL 7 TC2 TC1 CS3 67 78 94 143 1 3 GND MR* 5 2 4 RESET_B V3_3 4 17 20 21 20 19 18 25 27 30 31 34 35 16 15 14 13 12 11 22 16 21 17 15 12 10 7 5 4 3 2 22 23 24 25 26 27 28 29 1 30 PARENT BLOCK: \_z44top_dn\ RESET* VCC UB01 MAX811_U SOT143 2.93V MAX811SEUS-T I70 ONCE_DE_B SS CS0 118 RESET_B 128 CPUCLK_OUT 120 PROC_RESET_OUT SCK 93 86 85 83 81 CS2 CS1 CSE1 CSE0 62 60 BLOCK NAME: _motprocrescard_dn. 3 2 6 4 1 SW07 I64 SS* DE* SCK RSTOUT* CLKOUT RESET* CS0* CS1* CS2* CS3* TC1 TC2 CSE0 CSE1 144 31 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 VRL MMC2107 PORT VDD6 VSS7 VDD7 VSS8 VRH VRH D3 VSTBY D4 TA TEA TEA* D5 TA* D6 RW OE RCON SHS* D7 OE* D8 D9 RW D10 U19 1 2 RB159 VDDSYN 2 VSS6 I51 TQFP NA MMC2107 3 FLASH_VPP VPP D2 PQB0 MOSI VDDA D1 U19 4 VSSA PQA4 MISO VDDH VDDSYN VSSF I69 PQA0 TCLK 1 VDD5 TQFP NA MMC2107 TDI TRST* 0.0 C87 2 .1UF VDD4 VSS5 D 5 VDD3 VSS4 88 TIM_16H_8L 96 EB3 EB2 98 100 EB1 101 EB0 104 PQB3 105 PQB2 PQB1 106 107 PQB0 PQA4 108 109 PQA3 110 PQA1 111 PQA0 133 ONCE_TDI 135 2107_TDO TDO TMS VDDF D0 PD<31..0> A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 V3_3 10 9 8 7 6 5 4 11 13 14 23 24 26 28 0 11 6 1 12 139 50 13 137 49 14 136 3 15 134 2 16 132 47 17 131 29 19 18 20 119 122 21 117 121 22 116 2 1 ENGINEER: 3 09/16/2004 PAGE: 1/7(BLOCK) 38/71(TOTAL) STEVE SCULLY DATE: 1 TITLE: DS33Z11/41/44DK01A0 MMC2107 PROCESSOR RESOURCE CARD 10 9 8 7 6 5 4 3 2 1 0 89 84 82 79 75 72 71 80 90 91 124 125 130 142 138 USER_LED1 USER_LED2 INT3 INT4 RUN_KIT_USR TIM_STATUS INT2 YCO MOSI MISO XTAL OSC_MCU ONCE_TCLK ONCE_TRST_B ONCE_TMS VDD8 VSSSYN 6 VSS3 7 VDD2 59 95 97 99 102 92 113 112 87 115 74 103 123 141 129 77 65 45 33 19 9 VDD1 VSS2 8 VSS1 36 37 38 39 40 41 42 43 46 48 51 114 73 126 140 127 76 64 44 32 18 8 CR-38 : @\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page2_i1@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page1 PA<22..0> A B C D A B C D 2 25 3 26 4 28 27 31 15 14 13 12 11 10 9 A8 A9 A10 A11 A12 A13 A14 A15 A16 8 PA<17..1> 5 16 I54 UB05 CY62128V CY62128V NA V3_3 BOOT INTERN/EXTERN INTERNAL FLASH ENABLE XTAL W/ PLL FULL DRIVE MASTER MODE 17 8 PD<18> PD<19> PD<28> PD<22> PD<23> PD<21> PD<16> PD<17> PD<26> 7 CY62128V VCC A7 7 IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 1 1 31 30 29 28 27 26 25 24 21 18 15 17 14 20 13 2 19 10K 10K RB237 2 10K 10K R127 R92 10K 10K RB263 10K RB301 RB238 10K RB300 10K R93 RB264 1 1 1 1 1 2 1 5 2 2 2 2 2 1 2 6 PD<31..24> V3_3 2 10K 1 5 9 9 31 27 28 10 26 11 25 12 4 V3_3 I18 V3_3 A8 A9 A10 A11 A12 A13 A14 A15 A16 U14 CY62128V CY62128V NA PA<17..1> 10 11 12 13 14 15 16 17 WHEN SET FOR BOOT INTERNAL D18 HAS A 10K LOAD TO GND BOOT EXT D18 HAS A 10.5K LOAD TO V3V RCON R153 RESET CONFIGURATION 6 CY62128V 1.0K 4 IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 BTS_OBSXI BIS1OBSXI BIS0OBSXI V5_0 19 18 17 16 15 20 17 13 RESET AND CHIP CONFIGURATION PD<23..16> 30 1 2 3 STEVE SCULLY 2 1 A B C D AMBER V3_3 ENGINEER: 20 RB118 I65 DS17 09/16/2004 PAGE: 2/7(BLOCK) 39/71(TOTAL) 21 14 21 FLASH_VPP 1 DATE: 22 18 10 9 7 8 11 6 14 V3_3 0L_SMT0805_10PCT 13 ECJ-2VB1C104K 15 12 SWITCH 8 POS 16 5 4 3 2 1 SW22 I69 2 TITLE: DS33Z11/41/44DK01A0 23 19 INT3 INT4 USERFPGA2 INT5 3 1.0K CR-39 : @\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page2_i1@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page2 N_C A6 2 R250 1.0K 1 VCC A7 EB0 OE WE* A5 N_C A6 OE* A4 2 2 RB126 1 R251 1.0K 1 1 RB1572 1.0K 2 2 R244 1 WE* A5 CE2 A3 1 A4 CS0 A2 1.0K RB150 2 EB1 OE OE* A3 CE1* A1 1.0KRB147 CE2 A2 32 1 29 24 30 22 16 GND A0 6 7 8 9 10 11 12 23 8 7 6 5 4 3 2 1 A1 2 CB149 1 1 RB143 2 1 1.0K CS0 CE1* 32 1 29 24 30 22 16 GND A0 8 7 6 5 4 3 2 23 8 7 6 5 4 3 2 1 .1UF A B 8 PRT1_IN PRT1_OUT SCI1_IN PRT1_OUT PRT1_IN SCI1_OUT 10 9 8 7 6 5 4 3 2 1 E D C B A I35 J H G F J36 V3_3 9 8 7 6 FORCEOFF* VCC R1IN T1OUT R1OUT FORCEON T1IN T2IN INVALID* R2OUT 7 V+1 V+2 C1+ C1- C2+ C2- V- GND T2OUT R2IN 11 12 13 14 15 16 17 18 19 20 6 C43 1 2 10K 1 CONN_DB9P 5 4 3 2 1 10K V5_0 ONCETDI PIN 1UF 2 UB07 MAX3233E 10K MAX3233E MAX3233E V3_3 NA I31 2 2 1 1 C47 5 1UF 10UF C39 TDI ONCETDO PIN 1UF C91 4 ...FPGA+FLASH... JTAG CONFIGURATION MMC2107 2 2 10UF CB114 1 XTAL C118 2 1 2 R78 1 2 1 C RB200 330 1UF PLACE PADS FOR CAP BUT DO NOT POPULATE C83 8.0MHZ 2 1 1 68UF I13 2 C36 1 2 1 1UF OSC_MCU 5 6 7 8 U09 V3_3 RESET_B ONCE_TDI 2107_TDO ONCE_TCLK REF LBO* LBI 4 3 2 1 I11 R107 5.6 SMT1206_5PCT ERJ-8GEYJ5R6V SHDN GND LX FB MAX1675 OUT 1UF I47 CB35 L09 2 22.0UH C84 3 13 11 10 3 ENGINEER: STEVE SCULLY 2 VDDSYN 1 1 2 1 09/16/2004 PAGE: 3/7(BLOCK) 40/71(TOTAL) DATE: ALIGN KEY ONCE_TMS 12 ONCE_DE_B 14 ONCE_TRST_B 8 7 6 9 4 2 3 V3_3 CON14P I1 J41 CON14P CON14P NA 5 1 V3_3 2 TITLE: DS33Z11/41/44DK01A0 1UF X02 2 1 2 1 1 2 4 CB262 R91 1 CB148 2 1UF 1 .1UF CB466 5 1UF 2 2 1 10K 2 1 6 CB484 R10810K 1 7 1UF D 1 RB287 2 1 RB286 2 2 1 8 CB199 R118 10K 2 1.0M CR-40 : @\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page2_i1@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page3 1UF R90 1 1 2 C104 68UF A B C D A B C 9 7 10 8 6 10 8 8 IO1_0 IO3_0 IO4_0 IO5_0 IO6_0 IO7_0\VREF L12 B7 K12 J14 M13 B6 B4 4 3 2 1 IO9_0 IO10_0 IO11_0 IO12_0 IO13_0 IO14_0 IO15_0 IO16_0 IO17_0 IO18_0 IO19_0 IO20_0 A9 D12 B10 E13 A3 G15 B11 A5 A4 A6 B3 30 29 28 27 26 25 24 23 22 21 20 PD<31..16> 7 X_INIT IO8_0 E14 31 IO2_0\VREF GCK3 B8 5 SPARE_B<5..0> G13 1 2 3 4 6 4 CONN_10P 9 7 5 4 3 19 18 3 IO3_1 IO4_3\VREF 5 17 16 5 IO5_1 IO6_3 2 IO6_1 IO7_3\D6 2 IO7_1 IO8_3\D5 1 IO8_1 IO9_3 1 BANK 3 XC2S50_BGA U16 BANK 1 IO16_1 IO17_3 J25 IO17_1 IO18_3 D 6 IO18_1 IO19_3 7 5 IO19_1 IO20_3 8 6 5 R16 F15 E16 P16 IO5_2 IO6_2\D2 IO7_2\D1 IO8_2 15 14 13 12 11 10 9 8 7 6 C15 A10 A11 C12 F16 E15 A13 C16 D16 B12 C8 D9 IO13_2\(DOUT,BUSY) IO14_2 IO15_2 IO16_2 IO17_2 IO18_2 IO19_2 IO20_2 IO21_2 IO22_2 IO23_2 IO24_2 4 16 D14 D7 PA<16..0> 3 GREEN 2 1 1 2 1 RED RED 1 DS37 1 2 DS40 2 DS27 RED 2 RED RED RED 3 STEVE SCULLY 2 1 ENGINEER: 330 R195 330 R194 1 09/16/2004 PAGE: 4/7(BLOCK) 41/71(TOTAL) 1 330 RB193 1 DATE: V3_3 2 2 2 TITLE: DS33Z11/41/44DK01A0 USER_LED2 USER_LED1 TIM_INTERUPT_IND CFG_DIN PROC_RESET_OUT TIM_INTERUPT 4 IO12_2\(DIN,D0) IO11_2 IO10_2\VREF H13 IO4_2 L13 G16 IO3_2\D3 F13 H15 IO2_2\VREF IO9_2 H16 IO2_1\IRDY CR-41 : @\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page2_i1@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page4 IO9_1\VREF IO10_3\VREF GCK2 IO1_3\INIT* IO10_1 IO11_3\D4 IO1_1\CS* IO2_3\D7 IO11_1 IO12_3 IO2_1\WRITE* IO3_3 IO12_1 IO13_3\TRDY IO4_1\VREF IO5_3 IO13_1 IO14_3 IO20_1 BANK 2 IO21_3 IO14_1 IO15_3 IO21_1 IO22_3 IO15_1 IO16_3 IO22_1 IO23_3 N15 N14 C6 L14 C7 C10 N16 M16 K14 K16 J16 K15 J15 T15 G12 M14 M15 E11 A12 B16 D11 G14 D10 0 1 2 3 4 5 1 RB146 2 DS19 330 C9 OE B13 RW C13 CS0 D6 CS1 C11 CS2 A14 EB0 F14 EB1 A7 TA B5 TEA B9 D8 A8 E7 H14 J13 E6 F12 SCI2_IN E10 SCI2_OUT D5 L16 C5 K13 L15 BANK 0 A B C D A B C 8 5 7 9 6 10 8 6 10 8 6 3 1 2 7 XA<11..0> CONN_10P 9 7 5 IO6_4 IO7_4 IO8_4 T7 R5 M2 T12 9 8 7 IO10_4 IO11_4 IO12_4 IO13_4 IO14_4 IO15_4 IO16_4 IO17_4 IO18_4 IO19_4 IO20_4 IO21_4 IO22_4 T6 M1 T5 N2 P1 T3 T2 R10 T13 N12 B1 N10 L2 6 5 4 3 2 1 0 IO9_4\VREF IO5_4 R6 IO3_4\VREF P9 10 IO2_4 R9 11 IO1_4 H4 IO4_4 GCK0 N8 T10 10 GCK1 IO3_7\VREF 7 IO1_5 IO4_7 8 IO2_5\VREF IO5_7 4 IO3_5 IO6_7 4 IO4_5 IO7_7 3 IO5_5 IO8_7 5 I46 U16 BANK 5 BANK 7 XC2S50_BGA IO6_5 IO9_7\VREF 4 IO7_5 IO10_7 2 IO8_5\VREF IO11_7 2 IO9_5 IO12_7\IRDY 1 IO10_5 IO13_7 3 IO11_5 IO14_7 1 IO12_5 IO15_7 10 IO13_5 IO16_7 9 D_DUT<7..0> IO14_5 IO17_7 D SPARE_A<10..1> IO15_5 IO18_7 I34 CONN_THRU-HOLE NA NA J26 5 IO16_5 IO19_7 6 IO17_5 IO20_7 7 IO1_7 9 8 7 6 5 4 3 2 1 6 USERFPGA2 INT5 A_DUT<11..0> 5 11 10 9 8 7 6 5 4 3 2 1 0 8 IO2_7 4 7 6 5 4 3 2 1 0 IO19_5 R8 E4 T4 T11 P12 T14 F2 P13 P8 N11 R13CPUCLK_OUT N5 M6 P11 F1 N9 C2 L3 R7 M4 IO18_5 IO21_7 BANK 6 IO22_7 RW_X CS_X1 WR CS_X2 H1 J1 J3 P6 M11 K1 M3 P5 N1 R1 L1 N6 IO2_6 IO3_6 IO4_6\VREF IO5_6 IO6_6 IO7_6 IO8_6 IO9_6 IO10_6\VREF IO11_6 IO12_6 IO13_6 4 5 4 3 2 1 0 G4 H2 K3 P7 T8 IO18_6 IO19_6 IO20_6 IO21_6 IO22_6 IO23_6 XD<7..0> BUS MODE DETECTION (DUT AT CS_X2) 2 2 1 ENGINEER: 3 09/16/2004 PAGE: 5/7(BLOCK) 42/71(TOTAL) STEVE SCULLY DATE: 1 TITLE: DS33Z11/41/44DK01A0 WE ALSO FUNCTIONS AS ALT_WR_RW RW ALSO FUNCTIONS AS ALT_RD_DS 6 F5 IO16_6 G5 F4 IO15_6 IO17_6 7 L4 G2 IO14_6 BIS0_DUT BIS1_DUT RD_DUT BTS_DUT WR_DUT J2 ALE_DUT 3 IO1_6\TRDY T9 P10 C1 R11 D1 E1 K4 G3 H3 M10 K2 G1 A2 E3 D2 F3 E2 J4 R12 K5 L5 M7 N7 IO23_7 CR-42 : @\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page2_i1@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page5 BANK 4 CS_X3 CS_X4 CS_X5 CS_X6 ALE A B C D A B C D 8 8 RESET_B V3_3 A_DUT<11..0> SCK MISO MOSI SS 13 15 17 19 21 23 2 3 4 5 6 7 7 11 1 49 47 45 43 41 39 37 35 33 31 29 27 25 9 7 5 3 1 0 7 5V2 5V1 USER17 ALE RD WR AD0 AD1 3.3V1 3.3V2 AD2 AD3 AD4 AD5 AD6 AD7 CS2 CS3 CS4 CS5 CS6 CS1 INT2 INT3 INT4 INT5 A8 USER16 USER15 USER14 USER13 USER12 USER11 USER10 USER9 USER8 USER7 USER6 USER5 USER4 USER3 USER2 USER1 GND4 A9 A10 GND2 GND3 A11 GND1 1 50 48 46 WR_DUT ALE_DUT 6 INT4 INT3 INT2 INT5 D_DUT<7..0> CS_X1 CS_X6 CS_X5 CS_X4 CS_X3 CS_X2 A_DUT<11..0> RD_DUT 0 42 44 2 3 38 40 4 36 5 6 32 34 7 8 30 28 26 24 22 20 18 16 14 12 10 8 9 10 4 6 11 2 J27 CONN_50P_T1E1 MBVER 6 5 5 V3_3 4 4 10K 10K CR-43 : @\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page2_i1@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page6 2 R249 1 2 R246 1 2 10K R245 1 2 10K R247 1 IN IN IN IN IN IN IN IN IN IN WR_DUT RD_DUT CS_X1 CS_X2 CS_X3 WR RW_X TDO_NU TCK_NU TDI_NU TMS_NU CS_X4 CS_X5 XA<15..0> INT5 INT4 INT3 INT2 38A4> 3 2 1 ENGINEER: STEVE SCULLY 09/16/2004 PAGE: 6/7(BLOCK) 43/71(TOTAL) 42A4<> 43B6<> 21C5^ 42A4<> 43B6<> 21C5^ 42B3<> 43B6<> 21C5^ 42B3<> 43B6<> 21C5^ 42A4<> 43B6<> 21C5^ 42B3<> 21B5^ 42B3<> 21B5^ 42C3<> 43A6<> 21B5^ 42C3<> 43A6<> 21B7^ 21B7^ 42A6 43B7 43C6 DATE: OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT IO IO 44A6<> 21B6^ 44A6<> 21B6^ 44A6<> 21B6^ 38B5<> 40C3<> 21C5^ 43A7< 44B1< OUT 44A6<> 21B6^ 42C3<> 21B7^ 42C3<> 21B7^ 42C3<> 21B7^ OUT 39C3<> 42A6<> 43C6<> 21C7^ 38A7<> 39C3<> 43C6<> 21C7^ 38A7<> 39D3<> 43C6<> 21C7^ 38A7<> 43C6<> 21C7^ 1 TITLE: DS33Z11/41/44DK01A0 XD<7..0> D_DUT<7..0> 2 RESET_B BTS_DUT BIS0_DUT BIS1_DUT A_DUT<11..0> 42B7 21B5^ 3 A B C D A B 8 DONE 10K 10 9 8 7 6 5 4 3 2 GND DNC6 CEO* DNC5 DNC4 DNC3 TDO VCCINT VCCO VCCJ JTD_FLASH_TDO 9 7 6 5 10 TDI_NU 6 10 7 TDO_NU TMS_NU 8 TCK_NU 4 6 V3_3 JTD_FLASH_TDO 2 11 12 13 14 15 16 17 18 19 CONN_10P 9 8 4 3 7 2 1 J43 V3_3 XILINX_XCF01S CE* DNC2 OE/RST* CF* TCK TMS TDI CLK DNC1 ONCE_TCLK 1 XI_TMS 3 JTD_SPART_TDI 5 CCLK JTD_SPART2FLASH XI_TMS ONCE_TCLK XRST RB364 V2_5XI 1 2X_INIT D0 10K 20 VCCO5 VCCO6 VCCO7 VCCO8 VCCO9 VCCO10 VCCO11 VCCO12 VCCO13 VCCO14 VCCO15 VCCO16 H11 H12 J11 J12 L9 M9 L8 M8 J5 J6 H5 H6 VCCO3 E9 VCCO4 VCCO2 F8 F9 VCCO1 E8 GND2 1 GND1 2 CB270 1 GND3 1UF CB195 GND4 2 CB100 1 GND6 CFG_DIN 2 GND7 C V3_3 GND8 V3_3 1 GND9 2 1 GND5 2 1UF CB295 1 1 1UF CB457 2 1 GND10 4 3 2 IN IN SHDN RST GND14 1UF CB316 VCCINT2 1 1UF CB3721 .1UF CB3522 .1UF CB375 2 .1UF GND11 VCCINT3 5 6 7 8 VCCINT10 VCCINT9 CONTROL V3_3 XC2S50_BGA U16 GND SET OUT OUT MAX1792 GND16 1 VCCINT4 1 1 GND17 2 GND12 VCCINT6 2 GND18 VCCINT1 .1UF 2 CB3531 GND13 VCCINT7 GND19 1UF VCCINT5 UB11 1 GND20 CB3782 .1UF CB4092 .1UF CB373 1 .1UF GND15 VCCINT8 CB78 2 .1UF GND21 V3_3 GND24 1 CB157 2 GND22 VCCINT12 C3 C14 D4 D13 E5 E12 M5 M12 N4 N13 P3 P14 3 V2_5XI 2 GND34 4 GND25 VCCINT11 GND23 5 GND27 1 10UF CB171 2 GND26 U12 6 1UF GND29 1 1UF CB187 2 GND28 7 GND30 1 CB489 2 GND31 D 1 R89 2 1UF GND32 8 GND35 GND33 CR-44 : @\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page2_i1@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page7 A15 C4 B14 P15 D15 R14 TDI TCK TDO PROGRAM* CCLK DONE 5 4 1 P4 NC1 3 STEVE SCULLY 2 1 ENGINEER: R4 NC2 V3_3 09/16/2004 PAGE: 7/7(BLOCK) 44/71(TOTAL) R3 M2 CCLK DONE RESET_B 2 DATE: P2 M1 330 R238 TITLE: DS33Z11/41/44DK01A0 N3 M0 XI_TMS 1 JTD_SPART_TDI ONCE_TCLK JTD_SPART2FLASH XRST D3 TMS GND36 A1 A16 B2 B15 F6 F7 F10 F11 G6 G7 G8 G9 G10 G11 H7 H8 H9 H10 J7 J8 J9 J10 K6 K7 K8 K9 K10 K11 L6 L7 L10 L11 R2 R15 T1 T16 A B C D A B OUT 5 8 1/10(BLOCK) GND M8 A10 C9 CS RD WR 54C7<> IN 55A3<> 7 54C7<> IN 55A4< IN V3_3 RESET_AH 1 DVSS23 DVSS22 DVSS21 DVSS13 DVSS12 DVSS11 WR* RD* CS* TSTRST TEST2 TEST1 RPOSI RNEGI RCLKI MCLK2 MCLK1 LIUC 6 V3_3 V3_3 V3_3 R114 2 330 1 RED 2 DS25 I38 BLOCK NAME: _quadte1wan_dn. N4 N5 N6 D11 D12 D13 D9 H4 J12 H9 H10 G8 J14 J13 K15 MCLK 55A2<> 46A1<> IN 46D7< 51D7< LIUC INT* WAN_INTH5 55D5> 46A4<> OUT JTDI JTCLK JTMS JTDO JTRST K14 XI_TMS J15 52C1< 52C8<> 52A7<> ONCE_TCLK K16 52C1< 52C8<> 52A7<> JTD_FLASH_TDO C10 52C6<> K13 52A7<> JTDO458 53B6<> 2 DVSS31 MCLK2FPGA DVSS32 46C7< 2 MCLK DVDD11 2 DVSS33 30 RB184 30 DVDD12 DVSS41 RB160 DVDD21 2 DVSS43 C 4 DVDD13 2 DVSS42 D DVDD22 C42 10UF C48 10UF CB236 10UF CB126 10UF CB154 10UF C103 1 RVSS11 V3_3 2 RVSS12 8 DVDD23 RVSS13 VCC DVDD31 2 1 OSC DVDD32 RVSS21 CONTROL DS21458_U U20 RVDD1 1 3 BUFFER 4UX11 1 WAN_INT 4 46C7> 55D5> PARENT BLOCK: \_wan4z44_dn\ 5 I37 NC7SZ86_U NA NC7SZ86 V3_3 ESIBS<1> ESIBS<0> ESIBRD MUX BTS AD<7> AD<6> AD<5> AD<4> AD<3> AD<2> AD<1> AD<0> A<9> A<8> A<7>/ALE_AS A<6> A<5> A<4> A<3> A<2> A<1> A<0> DS21458 WAN INTERFACE BLOCK DVDD33 1 CB179 1 0.1UF CB144 1 0.1UF CB161 1 0.1UF CB160 1 0.1UF CB156 1 0.1UF CB120 2 0.1UF CB204 1 0.1UF CB138 1 0.1UF CB205 2 0.1UF RVSS22 RVDD2 YB02 4 RVDD4 RVSS43 I73 5 TVDD11 2.048MHZ_3.3V 6 TVDD12 TVSS11 7 NC1 8 CR-46 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE1 DVDD41 10UF CB151 10UF CB340 10UF CB112 10UF RVSS23 TVDD21 TVSS21 DVDD42 RVSS31 TVDD22 TVSS22 DVDD43 RVSS32 TVDD31 TVSS31 H1 J16 A9 T8 RVSS33 TVDD32 TVSS32 P4 P5 P6 C11 C12 C13 D3 E3 F3 L14 M14 N14 D4 E4 F4 L13 M13 N13 TVSS41 RVDD3 RVSS41 RVSS42 TVDD41 R6 T6 A11 B11 F1 F2 L15 L16 TVSS12 N1 J1 M1 E16 H16 D16 A5 A8 A4 T12 T13 T9 NC2 TVDD42 1 CB155 2 0.1UF 1 CB127 2 0.1UF 2 CB200 1 0.1UF 2 CB220 1 0.1UF TVSS42 R5 T5 A12 B12 E1 E2 M15 M16 NC3 B10 R8 H8 J8 J9 P8 D10 N8 P7 M7 R7 G1 G3 H2 E10 H3 G4 N7 B9 T7 G2 H6 J11 52B1< 55D6<> RESET_B 1 3 ENGINEER: STEVE SCULLY 2 I41 4 54C3 55A2 55A4 46B7< 1 INVERTER 09/16/2004 1 46/71(TOTAL) PAGE: DATE: NA NC7SZ86 NC7SZ86_U UXB05 RESET_AH IO IN 54C7 55A5 55A7 DAT<7..0> BTS 51C7< MUX 51B7< ESIBRD 51C7< ESIBR0 51C7< ESIBR1 51C7< 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 ADDR<9..0> 2 TITLE: DS33Z11/41/44DK01A0 K9 P3 E9 A B C D A B C D 51A6<> 53D7< 53D5<> 53B7<> IN RPOSO J6 TLCLK TSYNC TSSYNC TSYSCLK RLCLK RSYNC RMSYNC RSYSCLK 7 RLOS/LOTC RFSYNC BPCLK TCHCLK RCHCLK RSIGF TCHBLK TSIG RSIG RCHBLK TSER RSER TPOSI TPOSO TNEGI TNEGO RNEGO J4 K2 K3 RGAPCLK1 L2 M2 RSYNC1 K6 M3 RSYSCLK1 J3 L3 K4 RLOS1 K5 RSER1 TCLKO RCLKO TCLKI TCLK TTIPB TTIPA TRINGB TRINGA RCLK PORT TLINK K8 R1 RCLK1 RTIP RRING RLINK K1 RTIP1 49C8< 6 49D8< 5 49A5< RRING2 F16 PORT2_RRING = PIN F16 3 53D4<> 53A2<> TSSYNC1 53D5<> TSYSCLK1 53D7< BPCLK1 53C6<> TSYNC1 IO IN 53B2<> IN 53B2<> 49D8< TGAPCLK1 TSER1 TCLK1 TTIP1 4 51A6<> 53D7< RTIP2 H12 C15 H11 F10 C14 G16 H14 G15 G10 RGAPCLK2G11 F15 RSYNC2 E14 G13 RSYSCLK2H15 F14 G14 RLOS2 E15 RSER2 RCLK2 53D5<> 53B7<> IN 53C2< 53A7<> OUT 53B7<> OUT 49A5< TSSYNC TSYSCLK RMSYNC RSYSCLK 53D4<> IO 53A2<> IN 53B2<> IN 53A2<> 3 2 1 ENGINEER: STEVE SCULLY 09/16/2004 PAGE: 2/10(BLOCK) 47/71(TOTAL) TSSYNC2 53D4<> TSYSCLK2 53D7< TSYNC2 TGAPCLK2 TSER2 49B5< 49C5< TCLK2 TTIP2 TRING2 1 DATE: A13 B13 A14 B14 G12 A15 F12 F11 B15 E12 A16 F13 G9 E11 E13 D15 C16 B16 D14 J10 H13 2 TITLE: DS33Z11/41/44DK01A0 RLOS/LOTC RFSYNC BPCLK TSYNC RSYNC RSIGF TLCLK TCHCLK RCHCLK RLCLK TCHBLK TSIG RSIG RCHBLK TSER RSER TPOSI TPOSO TNEGI TNEGO RNEGO RPOSO TLINK RLINK TCLKI TCLKO RCLKO TTIPB TTIPA TRINGB TRINGA TCLK PORT RCLK RTIP RRING DS21458_U 4 DS21458_U TRING1 5 U20 R4 T4 R3 T3 L5 T2 L6 K7 T1 M5 R2 L4 M6 L7 N2 J7 P1 N3 M4 H7 J5 6 U20 P2 J2 L1 RRING1 49C8< 53C2< 53A7<> OUT 8 7 PORT1_RRING = PIN L1 53B7<> OUT 8 CR-47 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE2 A B C D A B C D 8 7 51A6<> 53D7< 53D4<> 53B7<> IN TCLKO RCLKO TNEGO RNEGO RPOSO F9 TLCLK TSYNC TSSYNC TSYSCLK RLCLK RSYNC RMSYNC RSYSCLK RLOS/LOTC RFSYNC 6 BPCLK TCHCLK RCHCLK RSIGF TCHBLK TSIG RSIG RCHBLK TSER RSER TPOSI TPOSO TNEGI TLINK TCLKI TCLK TTIPB TTIPA TRINGB RCLK PORT TRINGA RLINK 7 RRING RTIP TRING3 50D8< 53D4<> 53A2<> TSSYNC3 53D4<> TSYSCLK3 53C7< TSYNC3 53A2<> IN 53B2<> IN 50D8< TGAPCLK3 IO TSER3 TCLK3 TTIP3 5 4 53B7<> RSER4 RCLK4 RTIP4 N10 T15 P10 K12 P14 T10 P9 R10 R11 RGAPCLK4 M9 IN R12 53D4<> RSYNC4 N12 M10 RSYSCLK4 R9 53D7< N11 P11 P12 51A6<> RLOS4 53C2< 53A7<> OUT 53B7<> OUT 50A5< 50A5< RRING4 T11 TSSYNC4 53D4<> TSYSCLK4 53C7< 53A2<> IN 53B2<> IN 53A2<> IO 53D4<> TGAPCLK4 TSER4 TSYNC4 50B5< 50C5< TCLK4 TTIP4 TRING4 3 STEVE SCULLY 2 1 ENGINEER: N15 N16 P15 P16 L9 R16 L11 L12 T16 M12 R15 L10 K10 K11 R13 P13 T14 R14 M11 L8 N9 09/16/2004 PAGE: 3/10(BLOCK) 48/71(TOTAL) BPCLK TSYSCLK TSSYNC TSYNC TLCLK TCHCLK TCHBLK TSIG TSER TPOSI TPOSO TNEGI TNEGO TLINK TCLKI TCLKO TCLK TTIPB TTIPA TRINGB TRINGA 1 DATE: PORT 2 TITLE: DS33Z11/41/44DK01A0 RLOS/LOTC RFSYNC RSIGF RSYSCLK RMSYNC RSYNC RLCLK RCHCLK RCHBLK RSIG RSER RPOSO RNEGO RLINK RCLKO RCLK RTIP RRING PORT4_RRING = PIN T11 3 DS21458_U D1 D2 C1 C2 F6 B2 F7 G7 A1 E5 B1 D5 G6 F5 C5 B4 C4 B3 A3 D8 E8 4 DS21458_U C3 F8 C8 B7 C7 RGAPCLK3D7 B6 RSYNC3 B5 E6 RSYSCLK3 B8 E7 C6 RLOS3 D6 RSER3 RCLK3 50C8< 53B7<> OUT A7 RTIP3 50C8< G5 A2 A6 RRING3 5 U20 6 U20 PORT3_RRING = PIN A6 53C2< 53A7<> OUT 8 CR-48 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE3 A B C D A B C 2 32 31 RB3272 0 1 L10 RCV 35 34 33 8 9 10 I14 L10 XMIT 7 I11 6 RB3282 0 1 1 1UF C176 7 C2 C4 C6 C8 1 3 5 7 RJ45 2 4 6 8 C1 C3 C5 C7 JB12 I13 RJ45_4PORT 6 8 7 6 THE PCB LAYOUT INCORRECTLY USES PINS 38-40, 33-35, 28-30 AND 23-25 AS THE TX PRIMARY. THIS HAS BEEN CORRECTED IN THE SCHEMATIC, THE PCB / ASSEMBLY HAS BEEN MODIFIED TO ACCOMMODATE THIS. RRING1 RTIP1 TRING1 1 R207 2 0 R208 2 0 1 2 1 CB395 2 D 1 1 2 0.1UF TTIP1 8 5 5 47C4< 47C4< 47C2> 47C2> RRING2 RTIP2 TRING2 1 TTIP2 1 R203 2 0 R204 2 0 4 2 4 22 21 RB3212 0 1 L10 RCV 25 24 23 18 19 20 I26 L10 XMIT 17I2 16 RB3222 0 1 1 1UF C173 1 2 1 CB390 2 CR-49 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE4 1 2 RB317 61.9 RB313 61.9 0.1UF RB316 61.9 RB312 61.9 3 1 3 5 7 RJ45 2 4 6 8 A1 A3 A5 A7 JB12 3 ENGINEER: STEVE SCULLY 2 TITLE: DS33Z11/41/44DK01A0 A2 A4 A6 A8 I25 RJ45_4PORT 2 1 09/16/2004 PAGE: 4/10(BLOCK) 49/71(TOTAL) DATE: 1 A B C D A B C D 2 37 36 RB3292 0 1 L10 RCV 40 39 38 3 4 5 I25 L10 XMIT 2 I24 1 RB3302 0 1 1 1UF C175 7 D2 D4 D6 D8 1 3 5 7 RJ45 2 4 6 8 D1 D3 D5 D7 JB12 I19 RJ45_4PORT 6 8 7 6 THE PCB LAYOUT INCORRECTLY USES PINS 38-40, 33-35, 28-30 AND 23-25 AS THE TX PRIMARY. THIS HAS BEEN CORRECTED IN THE SCHEMATIC, THE PCB / ASSEMBLY HAS BEEN MODIFIED TO ACCOMMODATE THIS. RRING3 RTIP3 R201 2 0 R202 2 0 1 2 1 CB396 2 TRING3 1 1 1 2 0.1UF TTIP3 8 5 5 RTIP4 RRING4 48C4< TRING4 1 TTIP4 48C4< 48C1> 48C1> 1 R205 2 0 R206 2 0 4 2 4 27 26 RB3232 0 1 L10 RCV 30 29 28 13 14 I915 L10 XMIT 12I7 11 RB3242 0 1 1 1UF C174 1 2 1 CB391 2 CR-50 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE5 1 2 RB319 61.9 RB315 61.9 0.1UF RB318 61.9 RB314 61.9 3 1 3 5 7 RJ45 2 4 6 8 B1 B3 B5 B7 JB12 3 ENGINEER: STEVE SCULLY 2 TITLE: DS33Z11/41/44DK01A0 B2 B4 B6 B8 I8 RJ45_4PORT 2 1 09/16/2004 PAGE: 5/10(BLOCK) 50/71(TOTAL) DATE: 1 A B C D A B C D 8 8 7 46A2< 46A2< 46A2<> 46A2<> 46A2<> 46C7< RB2512 330 RB2842 330 1 RB2342 330 1 1 RB2212 330 1 MUX 1 2 2 DS34 2 DS33 2 1 1 1 1 DS30 RB3032 2.0K RB2282 2.0K RB1832 2.0K RB1922 2.0K RB2092 2.0K RB1852 2.0K DS32 1 BTS 1 ESIBR0 1 1 ESIBRD ESIBR1 1 LIUC ALL UNMARKED BIAS RESISTORS ARE 10K 7 NOTMUX MOT V3_3 6 RLOS4 RLOS3 RLOS2 RLOS1 6 48A4> 48A8> 47A4> 47A8> 5 5 CR-51 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE6 4 4 3 2 1 ENGINEER: 3 09/16/2004 PAGE: 6/10(BLOCK) 51/71(TOTAL) STEVE SCULLY DATE: 1 TITLE: DS33Z11/41/44DK01A0 2 A B C D A B C 0.1UF 2 C135 1 0.1UF 0.1UF 2 C85 1 7 9 TDI_NU TCK_NU TMS_NU 8 3 5 TDO_NU 1 10 8 6 4 2 VCCO VCCINT TDO DNC3 DNC4 DNC5 CEO* DNC6 GND DNC1 CLK TDI TMS TCK CF* OE/RST* DNC2 CE* JTDO458 V3_3 XILINX_XCF01S VCCJ D0 46C7> 20 19 18 17 16 15 14 13 12 11 6 7 JTD_SPART_TDI 52C1< 8 ONCE_TCLK 52C8<> 46C7< 10 XI_TMS 52C8<> 46C7< 4 2 CONN_10P 9 7 5 3 1 JB07 1 2 CCLK 3 52B1<> JTD_SPART2FLASH 4 5 46C7< 52A7<> XI_TMS 52C1< ONCE_TCLK 6 46C7< 52A7<> 52C1< 7 52B1< XRST R84 V2_5XI 2 1X_INIT 8 10K 9 10 52B1<> DONE CFG_DIN 2 CB245 1 53B2<> 52C1< 52C1< JTD_FLASH_TDO 6 46C7< VCCO5 VCCO6 VCCO7 VCCO8 VCCO9 VCCO10 VCCO11 VCCO12 VCCO13 VCCO14 VCCO15 VCCO16 H11 H12 J11 J12 L9 M9 L8 M8 J5 J6 H5 H6 VCCO3 E9 VCCO4 VCCO2 F8 F9 VCCO1 E8 GND1 2 C77 1 GND2 2 CB257 1 GND4 V3_3 GND6 1UF C188 GND3 C22 0.1UF 2 GND7 V3_3 GND8 0.1UF 2 CB190 1 2 0.1UF 2 CB150 1 1 2 CB168 1 2 1UF C23 1 0.1UF 2 CB134 1 1 GND9 U08 GND10 2 1 GND5 1 1UF CB65 2 0.1UF 2 C108 1 1 SHDN RST VCCINT2 GND14 0.1UF 1UF CB66 IN U10 GND SET OUT OUT 8 7 6 5 VCCINT9 CONTROL V3_3 XC2S50_BGA GND16 1UF CB2751 .1UF CB1352 .1UF CB216 2 .1UF GND11 IN 1 2 VCCINT4 MAX1792 GND17 1 VCCINT6 2 GND18 VCCINT1 .1UF GND13 VCCINT7 GND19 1 2 3 4 1 VCCINT3 1 VCCINT8 GND20 1UF VCCINT5 UB06 2 GND22 CB2782 .1UF CB3382 .1UF CB269 1 .1UF GND15 VCCINT10 C114 1 GND23 V3_3 2 GND24 D 2 GND25 V3_3 2 GND26 C192 2 .1UF GND21 2 VCCINT11 2 1 10UF C86 VCCINT12 C3 C14 D4 D13 E5 E12 M5 M12 N4 N13 P3 P14 2 CB3371 GND12 3 V2_5XI 2 GND28 4 1UF GND29 52B8< 1 5 GND30 1 1UF CB230 CB62 1 0.1UF C123 1 0.1UF C142 1 0.1UF C125 1 0.1UF GND27 6 1UF GND32 CB274 2 GND31 7 2 GND34 8 GND35 GND33 CR-52 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE7 C4 B14 P15 TCK TDO PROGRAM* 5 4 1 P4 NC1 3 STEVE SCULLY 2 1 ENGINEER: R4 NC2 V3_3 52B8<> 52C8<> 09/16/2004 PAGE: 7/10(BLOCK) 52/71(TOTAL) R3 M2 CCLK DONE DATE: P2 M1 330 RESET_B 2 RB129 TITLE: DS33Z11/41/44DK01A0 N3 R14 DONE M0 D15 CCLK XI_TMS 1 JTD_SPART_TDI ONCE_TCLK JTD_SPART2FLASH XRST A15 TDI 52B8<> D3 TMS GND36 A1 A16 B2 B15 F6 F7 F10 F11 G6 G7 G8 G9 G10 G11 H7 H8 H9 H10 J7 J8 J9 J10 K6 K7 K8 K9 K10 K11 L6 L7 L10 L11 R2 R15 T1 T16 A B C D A B C 8 48B1< 7 53C2< 48B4> 53C2< 48B8> 53C2< 47B4> 53C2< 47B8> 48C4> 48C8> 47C4> 47C8> 48B4< 48B8< 47B4< 47B8< TSYSCLK4 TSYSCLK3 MCLK2FPGA BPCLK1 RGAPCLK1 RGAPCLK2 RGAPCLK3 RGAPCLK4 RCLK1 RCLK2 RCLK3 RCLK4 RSER1 RSER2 RSER3 RSER4 46D7< 47B6> TSYSCLK 6 IO11_0 IO12_0 IO13_0 IO14_0 IO15_0 IO16_0 IO17_0 IO18_0 IO19_0 IO20_0 C8 D7 E7 B5 D6 A4 E6 D5 C5 IO7_0\VREF B4 A6 IO6_0 C6 IO10_0 IO5_0 A5 D8 IO4_0 B6 IO9_0 IO3_0 C7 IO8_0 IO2_0\VREF B7 B3 IO1_0 A7 A3 GCK3 B8 IO3_1 IO4_3\VREF 48B5< IO4_1\VREF IO5_3 TSYSCLK2 IO5_1 IO6_3 47B2< 47B8<> IO6_1 IO7_3\D6 TSYSCLK1 47B6< IO7_1 IO8_3\D5 47B6< IO8_1 IO9_3 RSYSCLK4 IO1_1\CS* IO2_3\D7 GCK2 IO1_3\INIT* IO2_1\WRITE* IO3_3 48B5< 48B8<> U10 BANK 1 BANK 3 XC2S50_BGA IO9_1\VREF IO10_3\VREF 48B4< 47B4<> IO10_1 IO11_3\D4 48B8< 47B2< IO11_1 IO12_3 RSYSCLK 48B4<> IO14_1 IO15_3 RSYSCLK3 IO16_1 IO17_3 RSYSCLK2 47B6<> IO17_1 IO18_3 47B4< 47B2<> IO18_1 IO19_3 RSYSCLK1 48B5<> IO19_1 IO20_3 47B8< 48B1< IO15_1 IO16_3 X_INIT 5 4 H13 G13 F15 E16 SPARE_TP1 TP32 IO4_2 IO5_2 IO6_2\D2 IO7_2\D1 48B5< 48B1< 47C5< 47C1< 48C5< 48C1< 47B5<> 47B1<> 48B5<> 48B1<> J13TSER3 G14TSER4 G15 TCLK1 G12 TCLK2 F16 TCLK3 F12 TCLK4 E15 TGAPCLK1 E14 TGAPCLK2 C16 TGAPCLK3 B16 TGAPCLK4 IO15_2 IO16_2 IO17_2 IO18_2 IO19_2 IO20_2 IO21_2 IO22_2 IO23_2 IO24_2 3 ENGINEER: STEVE SCULLY 2 1 RSER2 RSER3 RSER4 RSER1 TSER PULLDNS USED IN IBO MODE (IMPLEMENTS IMUX) TITLE: DS33Z11/41/44DK01A0 47B1< 52C8<> H14TSER2 C15 IO13_2\(DOUT,BUSY) CFG_DIN 47B5< IO14_2 D14 IO12_2\(DIN,D0) 53A7<> 48B4> 53A7<> 48B8> SPARE_TP2 TP30 E13TSER1 F13 IO10_2\VREF IO11_2 D16 IO9_2 F14 G16 IO3_2\D3 53A7<> 47B4> H15 IO2_2\VREF IO8_2 2 53A7<> 47B8> H16 IO2_1\IRDY 3 2.0K 4 R88 5 2.0K 6 R113 7 1 09/16/2004 PAGE: 8/10(BLOCK) 53/71(TOTAL) DATE: 2.0K D 8 R104 CR-53 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE8 2.0K 48B1<> IO20_1 BANK 2 IO21_3 IO12_1 IO13_3\TRDY IO21_1 IO22_3 1 1 IO13_1 IO14_3 IO22_1 IO23_3 N15 N14 M13 L14 P16 L13 N16 M16 K14 K16 J16 K15 J15 T15 R16 M14 M15 L12 L16 K13 L15 K12 J14 52B8<> R94 C9 B13 C13 A14 C11 E11 B11 RSYNC1 A11 TSSYNC1 C10 B9 D9 RSYNC2 A8 TSSYNC2 C12 RSYNC3 D12 TSSYNC3 B12 RSYNC4 A13 TSSYNC4 D11 A12 TSYNC1 B10 TSYNC2 D10 TSYNC3 A10 TSYNC4 E10 A9 BANK 0 A B C D A B T3ENH_T1ENLPRT4 T3ENH_T1ENLPRT3 T3ENH_T1ENLPRT2 T3ENH_T1ENLPRT1 Z44_TDEN<2> Z44_RDEN<2> Z44_TCLK<2> Z44_RCLK<2> Z44_TSER<2> Z44_RSER<2> Z44_TDEN<1> Z44_RDEN<1> Z44_TCLK<1> Z44_RCLK<1> Z44_TSER<1> Z44_RSER<1> 46B7< 55A2<> IO3_4\VREF P9 WR RD R48 R47 IO7_4 IO8_4 IO9_4\VREF IO10_4 IO11_4 IO12_4 IO13_4 IO14_4 IO15_4 IO16_4 IO17_4 IO18_4 IO19_4 IO20_4 IO21_4 IO22_4 N11 T12 R13 P13 T9 M10 R10 P10 R12 P11 T13 N12 P12 N10 T14 IO6_4 IO5_4 N2 M11 R11 IO4_4 IO2_4 R9 CS_X4 K5 IO1_4 IO5_5 IO8_7 IO4_5 IO7_7 GCK1 IO3_7\VREF 8 7 6 U10 BANK 5 BANK 7 XC2S50_BGA 5 PORTS ARE ENABLED BY DEFAULT ON T1 BRD, AND ARE DISABLED USING JUMPERS ON T3 BRD 55B2<> 54A5<> 55C2<> 54A5<> 55C6<> 54A5<> 55D6<> 54A6<> 55C8<> 55C6<> 55C8<> 55C6<> 55C8<> 55C6<> 55D8<> 55D6<> 55C8<> 55C6<> 55C8<> 55C6<> Z41RSYNC 55C6<> 46B7< 55A3<> Z41TSYNC 55C6<> 55D2<> 0 1 GCK0 IO6_5 IO9_7\VREF N9 IO7_5 IO10_7 C 2.0K IO8_5\VREF IO11_7 ADDR<9..0> RB04 IO9_5 IO12_7\IRDY 55A7 55A5 46C2< RB05 IO10_5 IO13_7 N8 IO1_5 IO4_7 54A8< 2.0K IO11_5 IO14_7 2 IO1_7 5 4 IO16_5 IO19_7 IO15_5 IO18_7 IO14_5 IO17_7 D IO2_7 IO12_5 IO15_7 6 IO17_5 IO20_7 7 IO18_5 IO21_7 8 CR-54 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE9 IO2_5\VREF IO5_7 54A8< 30 30 30 30 30 30 30 30 30 30 2.0K IO3_5 IO6_7 54A8< 2.0K BANK 6 IO22_7 IO13_5 IO16_7 IO19_5 R8 L5 T4 N6 R5 P6 R6 M7 P8 M4 N5 M3 J4 M6 K2 N7 T6 P7 R7 K3 54A8< R73 R46 R52 R72 R45 R54 R53 R49 R51 R50 RB45 4 3 2 1 0 J3 L1 L2 K4 L3 L4 IO4_6\VREF IO5_6 IO6_6 IO7_6 IO8_6 IO9_6 IO23_6 IO22_6 IO21_6 IO20_6 IO19_6 IO18_6 IO17_6 IO16_6 IO15_6 IO14_6 IO13_6 IO12_6 IO11_6 T2 T3 M1 P1 M2 P5 K1 T8 T10 T5 T7 R1 T11 Z44_TSER<3> RB101 30 OBS_RDEN<3> R44 30 R42 OBS_RCLK<3> OBS_TCLK<3> RB94 30 30 30 R39 OBS_RCLK<4> 30 RB93 OBS_TCLK<4> 30 RB92 OBS_RDEN<4> 30 R40 OBS_TDEN<4> 30 Z44_TSER<4> Z44_RCLK<4> Z44_TCLK<4> Z44_RDEN<4> Z44_TDEN<4> Z44_RSER<4> Z44_RCLK<3> Z44_TCLK<3> Z44_RDEN<3> Z44_TDEN<3> Z44_RSER<3> 2 3 ENGINEER: STEVE SCULLY 2 TITLE: DS33Z11/41/44DK01A0 TP13 TP25 TP12 TP24 TP14 R41 TP26 OBS_RSER<4> 30 TP28 OBS_TDEN<3> TP16 TP15 TP27 TP17 DAT<7..0> R43 OBS_RSER<3> 4 J1 IO3_6 TP29 5 H1 IO2_6 N1 7 55A4 55A2 46B1<> 6 J2 3 IO1_6\TRDY IO10_6\VREF IO23_7 C2 B1 C1 T3ENH_T1ENLPRT1E4 55D6<> T3ENH_T1ENLPRT2D1 55C6<> T3ENH_T1ENLPRT3E1 55C2<> T3ENH_T1ENLPRT4F2 55B2<> G3 H3 G4 G5 G1 A2 E3 D2 F3 E2 F1 F4 F5 G2 H2 H4 1 1 1 1 1 1 1 1 1 1 1 1 30 30 RB46 BANK 4 55B1<> 55B4<> 55B1<> 55B4<> 1 09/16/2004 PAGE: 9/10(BLOCK) 54/71(TOTAL) DATE: 55B1<> 55B4<> 55C1<> 55C4<> 55B1<> 55B4<> 55C1<> 55C4<> 1 A B C D A B C D V3_3 GND V3_3 Z44_RCLK<2> 54B8< 8 GND GND V3_3 GND GND GND V3_3 GND GND GND V3_3 GND GND GND V3_3 GND GND GND V3_3 GND GND 7 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 J12 46A4<> 46C7> 54B8< GND GND GND GND GND GND GND ADDR<9..0> 55A2 54C3 46B1<> 6 5 WAN R.C. CONNECTOR TO MOTHERBOARD OSC3_NU GND GND 6 8 3 5 1 4 CS_X5 CS 6 GND GND GND V3_3 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 GND GND GND RD 5 7 1 3 0 55A4 3 2 1 ENGINEER: STEVE SCULLY 09/16/2004 PAGE: 10/10(BLOCK) 55/71(TOTAL) SIG_RETURN DATE: I27 1 TITLE: DS33Z11/41/44DK01A0 54C7<> 46B7< GND 55A1> 55C6<> 54B1< 54A1< DAT<7..0> Z44_TCLK<4> SIG_RETURN Z44_TDEN<4> Z44_TSER<4> 54B1< 54A5<> 54A8< 54B1<> Z44_TCLK<3> 54B1< 54A5<> 54A8< 54B1<> Z44_TDEN<3> Z44_TSER<3> T3ENH_T1ENLPRT3 ALE CS_X4 54C7<> T3ENH_T1ENLPRT4 54C3 46B1<> GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 2 NOTE 3184 IS ON CS3 WHILE 21455 IS ON CS2/CS4 CS_X2 V3_3 CS_X3 WR I29 GND GND V3_3 GND GND GND V3_3 GND GND GND V3_3 GND GND GND V3_3 GND GND J09 RECEPTACLE GND OSC1_NU Z44_RCLK<4> Z44_RDEN<4> Z44_RSER<4> Z44_RCLK<3> Z44_RDEN<3> 2 4 3 P1 CONNECTOR (RECEPTICAL) Z44_RSER<3> 46B7< 54C7<> 46B7< DAT<7..0> 54B1< 54B1< 54B1< 54B1< 54B1< GND 46C2< 54C7 55A7 4 54B1< 54B8< 54B8< 55A1> 55B2<> 55C6<> 54B8<> 54A5<> 54A8< Z44_TCLK<2> TDO_NU 52A8<> TCK_NU 52A8<> 5 55A1> 55B2<> 55C6<> 54B8< 54C7< 54C7< Z44_TDEN<2> Z44_TSER<2> SIG_RETURN T3ENH_T1ENLPRT2 Z41RSYNC Z41TSYNC Z44_TCLK<1> Z44_TDEN<1> SIG_RETURN Z44_TSER<1> 54A6<> 54A8< 54B8<> INT2 55D7<> RESET_B 46A2<> 52B1< WAN_INT T3ENH_T1ENLPRT1 INT3 I28 6 GND GND GND GND GND GND GND GND P2 CONNECTOR (RECEPTICAL) RECEPTACLE 7 GND 46C2< 54C7 55A5 V3_3 OSC2_NU OSC4_NU 7 9 4 0 2 52A8<> TDI_NU 52A8<> TMS_NU Z44_RDEN<2> 54B8< Z44_RCLK<1> 54B8< Z44_RSER<2> Z44_RDEN<1> 54B8< 54A8< Z44_RSER<1> INT5 55D6<> INT2 54B8< ADDR<9..0> 8 CR-55 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE10 A B C D A B C D 10K V3_3 10 8 6 4 2 8 V3_3 F3 F4 J3 G4 E4 CS RD WR RED T3_INT CLKA CLKB 62B7<> 63B7<> 62B6<> 63B6<> TDI_NU TDO_NU RADR<0> RADR<1> RADR<2> RADR<3> RADR<4> R20 R19 R18 T20 T19 7 DS41 L17 L16 K18 J19 L18 L19 K2 L4 K1 L1 L2 RSOX REOP RVAL RERR RMOD<0> RMOD<1> RDY* INT* CLKA CLKB CLKC CS* RD* WR* MODE WIDTH TEST* HIZ* RST* TMOD<0> TMOD<1> TSCLK TPRTY TEN TSOX TEOP TSX TERR JTCLK JTMS JTDI JTDO JTRST* 62B7<> 63B7<> TMS_NU TCK_NU 62B6<> 63B6<> B17 B18 A17 A19 W16 V15 Y16 Y17 CLKB J20 RB331 330 63D5> 62D5> 56A6<> OUT 60B1< 60B1< 56C7< 56B4< 4 6 8 10 CONN_10P 9 7 5 3 JTCLK 61D2< 60D2< 56D8<> 61C2< 60C2< 56D8<> JTMS JTDI 56D8<> 60C2< JTDO84 56D8<> JTRST RB308 61C2< 56C7< 3 JTDI 5 JTDOCPLD 7 JTRST 9 1 7 L3 63A5< 62A5< IN K3 63A3> 62A3> IN V3_3 K4 62A4<> IN 63A4<> B1 0.0 R144 L5 RB227 0.0 M3 0.0 R156 2 R3 10K V3_3 RB283 B16 RESET_B GND 62D6<> IN 63D6<> JTCLK RB309 10K JTMS 10K RB250 V3_3 60B1< 56B4< 56B8<> 56C7< 60D2< 56C7< 61D2< 60C2< 56C7< 61C2< J39 NC7SZ86_U 6 5 6 TP66 4 3 V3_3 CONTROL DS3184 UB08 K17 D20 E19 D19 K16 K20 K19 F19 F18 E20 G18 M20 RPRTY* RDXA1/RPXA RDXA<2> RDXA<3> RDXA<4> REN* RSCLK T3_INT CLKB 4 IN 56B8<> 56C7< 60B1< V3_3 3 2 STEVE SCULLY 2 DS33Z11/41/44DK01A0 ENGINEER: TITLE: VALUE NOT SHOWN FOR 10K RES V3_3 R151 IO V3_3 62A6 62A7 63A6 63A7 62A3 62A5 63A3 63A5 0.0 DAT<7..0> PARENT BLOCK: \_wan4z44_dn\ 5 56B8> 62D5> 63D5> D<0> D<1> D<2> D<3> D<4> D<5> D<6> D<7> D<8> D<9> D<10> D<11> D<12> D<13> D<14> D<15> TDXA<1>/TPXA TDXA<2> TDXA<3> TDXA<4> TSPA 0 1 2 3 4 5 6 7 P1 U1 P2 T2 U2 W2 N3 P3 T3 U3 V3 N4 P4 R4 T4 J5 R142 RB222 R146 RB186 R135 RB229 RB206 R121 0 1 2 3 4 5 6 7 8 9 10 H1 E1 H2 G2 E2 D2 H3 G3 E3 D3 C3 N2 A<0>/BSWAP A<1> A<2> A<3> A<4> A<5> A<6> A<7> A<8> A<9> A<10> ALE ADDR<10..0> DS3184 WAN INTERFACE BLOCK BLOCK NAME: _quadte3wan_dn. 4UX12 1 8 CR-56 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I2@\_ZTOP_LIB\.\_QUADTE3WAN_DN\(SCH_1):PAGE1 H8 H7 H6 G8 G7 G6 F8 F7 F6 A2 R8 R7 R6 P8 P7 P6 N8 N7 N6 W1 R15 R14 R13 P15 P14 P13 N15 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19 VDD20 VDD21 VDD22 VDD23 VDD24 VDD25 VDD26 VDD27 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 K10 K9 K8 J10 J9 J8 M7 M6 L7 L6 K7 K6 J7 J6 A1 N10 N9 M10 M9 M8 L10 L9 L8 R12 R11 R10 R9 P12 P11 P10 P9 Y1 N12 N11 M13 1 09/16/2004 PAGE: 1/8(BLOCK) 56/71(TOTAL) DATE: 1 A B C D A B C D 59B8< 57A4< 57A4< 59B8< 8 57A4< 61B4> 60B4> IN 57C8< 57C5< 59D8< 59D4< 59B4< 57C8< 57C5< 59B4< 57C8< 57C5< 59D8< 59D4< 7 1 TE3_TSER<4..1> TE3_TSER<4..1> TOH TOHEN TCLKI TSOFI TPDENI RPDAT TSER RPDENI D8 E5 B4 B7 C5 C9 E6 D6 TOH TOHEN U11 T14 7 TCLKI TSOFI TPDENI RPDAT TSER RPDENI RLCLK RPOS RNEG RXP RXN Y14 U12 U13 Y10 4 V13 W13 TLCLK TPOS TNEG TXP TXN TOHCLK TOHSOF ROH ROHCLK ROHSOF TCLKO TSOFO TPDENO TPDAT RSER RCLKO RSOFO PORT TLCLK TPOS TNEG TXP TXN TOHCLK TOHSOF ROH ROHCLK ROHSOF TCLKO TSOFO TPDENO TPDAT RSER RCLKO RSOFO DS3184 UB08 RLCLK RPOS RNEG RXP RXN PORT DS3184 UB08 B8 A3 B3 F2 F1 Y12 W15 Y15 4 W5 4 Y5 PORT4=PINY12 1 1 TE3_RXP<4..1> TE3_RXN<4..1> PORT1=PINB8 TE3_RXP<4..1> TE3_RXN<4..1> 57A8< 57A4< 61B4> 60B4> IN 57C5< 59B4< 57C5< 57A8< 57A4< 57A4< 59D8< 59D4< 59B8< 57A8< 57C5< 59B4< 59B8< 59D4< 59D8< 8 6 4 4 4 4 4 4 4 A8 C4 D4 J2 J1 C8 C7 D10 D5 B2 D7 A7 A9 B9 E9 D9 E8 V11 V14 W14 W6 Y6 T11 T12 T10 T13 U14 Y13 V12 W10 V10 W11 Y11 W12 6 1 1 1 1 1 1 1 TE3_RXP<4..1> TE3_RXN<4..1> 2 2 5 4 61C4> 60B4> IN TE3_TSER<4..1> 57C2> 57C2> 57C5> 60B3> 61B3> 2 61B4> 57C5> 57A1> 57A1> 59C8< 57C5> 59A4< 57C5> 59A4< 59C8< TE3_RSER<4..1> OUT TE3_RCLK<4..1> TE3_RGAPCLK<4..1>OUT OUT 59C4< 57C2> 57C2> 59C4< PORT2=PINW8 W4 W7 V5 V9 T6 U6 U8 T5 W8 Y3 W3 R2 R1 TCLKI TSOFI TPDENI RPDAT TSER RPDENI TOH TOHEN 57A1> 57C2> 57C5> 60B4> 61B4> 57A1> 57C2> 57C5> 60A3> 60B3> 61A3> 61B3> 59A8< 57A2> 57A2> 59A8< TE3_TSER<4..1> 57A1> 57A5> 57C2> 60B3> 61B3> IN A14 D12 D13 A10 3 C13 B13 D11 E14 TLCLK TPOS TNEG TXP TXN TOHCLK TOHSOF ROH ROHCLK ROHSOF TCLKO TSOFO TPDENO TPDAT RSER RCLKO RSOFO 3 C11 C14 B14 B6 A6 E11 E12 E10 E13 D14 A13 C12 B10 C10 B11 A11 B12 TCLKI TSOFI TPDENI RPDAT TSER RPDENI TOH TOHEN RLCLK RPOS RNEG RXP RXN TE3_RSER<4..1> OUT TE3_RCLK<4..1> TE3_RGAPCLK<4..1>OUT OUT 61B4> 61C4> 57A5> 57C2> 57C5> 60B4> 57A5> 57C2> 57C5> 60B4> 61B4> 57A5> 57C2> 57C5> 60B3> 61B3> 57A5> 57C2> 57C5> 60B4> 61B4> 57A5> 57C2> 57C5> 60A3> 60B3> 61A3> 61B3> 57A5> 57C2> 57C5> 59A4< 59A8< 59C4< 59C8< 57A5> 57C2> 57C5> 59A4< 59A8< 59C4< 59C8< TE3_TCLK<4..1> TE3_TGAPCLK<4..1>OUT OUT TE3_TXP<4..1> TE3_TXN<4..1> 3 STEVE SCULLY 2 1 ENGINEER: 2 2 2 2 2 2 2 57A1> 57A5> 57C5> 60B4> 61B4> 57A1> 57A5> 57C5> 60B4> 61B4> 61C4> 57A1> 57A5> 57C5> 60B3> 61B3> 09/16/2004 PAGE: 2/8(BLOCK) 57/71(TOTAL) Y8 V4 U4 M2 M1 V8 V7 U10 U5 Y2 U7 Y7 Y9 W9 T9 U9 T8 TE3_RSER<4..1> OUT TE3_RCLK<4..1> TE3_RGAPCLK<4..1>OUT OUT 57A1> 57A5> 57C5> 60B4> 61B4> 57A1> 57A5> 57C5> 60A3> 60B3> 61A3> 61B3> 57A2> 57A5> 57C5> 59A4< 59A8< 59C4< 59C8< 57A2> 57A5> 57C5> 59A4< 59A8< 59C4< 59C8< TE3_TCLK<4..1> TE3_TGAPCLK<4..1>OUT OUT TE3_TXP<4..1> TE3_TXN<4..1> 1 DATE: TLCLK TPOS TNEG TXP TXN TOHCLK TOHSOF ROH ROHCLK ROHSOF TCLKO TSOFO TPDENO TPDAT RSER RCLKO RSOFO 3 3 3 3 3 3 3 2 TITLE: DS33Z11/41/44DK01A0 PORT DS3184 UB08 PORT DS3184 UB08 RLCLK RPOS RNEG RXP RXN TE3_TCLK<4..1> TE3_TGAPCLK<4..1>OUT OUT TE3_TXP<4..1> TE3_TXN<4..1> TE3_RSER<4..1> OUT TE3_RCLK<4..1> OUT TE3_RGAPCLK<4..1>OUT TE3_RXP<4..1> TE3_RXN<4..1> A12 B15 A15 3 B5 3 A5 PORT3=PINA12 4 57A1> 57A5> 57C2> 60B4> 61B4> 57A1> 57A5> 57C2> 60A3> 60B3> 61A3> 61B3> 59D4< 59B8< 57A8< 57A4< 59B4< 57C8< 59D8< TE3_TCLK<4..1> TE3_TGAPCLK<4..1>OUT OUT TE3_TXP<4..1> TE3_TXN<4..1> 5 CR-57 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I2@\_ZTOP_LIB\.\_QUADTE3WAN_DN\(SCH_1):PAGE2 A B C D 8 7 TDATA<0> TDATA<1> TDATA<2> TDATA<3> TDATA<4> TDATA<5> TDATA<6> TDATA<7> TDATA<8> TDATA<9> TDATA<10> TDATA<11> TDATA<12> TDATA<13> TDATA<14> TDATA<15> TDATA<16> TDATA<17> TDATA<18> TDATA<19> TDATA<20> TDATA<21> TDATA<22> TDATA<23> TDATA<24> TDATA<25> TDATA<26> TDATA<27> TDATA<28> TDATA<29> TDATA<30> TDATA<31> U20 T18 V20 U19 V19 V18 U18 W20 C20 B19 W19 W18 V17 Y18 W17 V16 R17 T16 T17 C17 C18 C16 D16 E16 F20 C19 D17 D18 U17 U16 T15 U15 5 V3_3 4 AVDDR1 AVDDR2 AVDDR3 AVDDR4 VDD28 VDD29 VDD30 VDD31 VDD32 VDD33 VDD34 VDD35 VDD36 VDD37 VDD38 VDD39 VDD40 DATA & I/O PORT DS3184 UB08 5 4 F5 G5 R5 P5 C1 C2 V1 V2 L20 M19 M18 N20 N19 N18 P20 P19 P18 P17 N17 M17 R16 P16 N16 M16 H20 G20 H19 G19 E18 J18 H18 J17 H17 G17 F17 E17 J16 H16 G16 F16 GPIO1 58B2<> GPIO2 58B2<> GPIO3 58A2<> GPIO4 58A2<> 1 1 1 RB153 DS21 1 2 330 RB155 DS22 1 2 330 RB154 DS23 1 2 330 RB152 DS24 2 1 330 3 STEVE SCULLY 2 1 ENGINEER: TP40 TP39 1 09/16/2004 PAGE: 3/8(BLOCK) 58/71(TOTAL) GPIO4 GPIO3 TP38 TP37 1 DATE: 58B3<> 58B3<> GPIO2 GPIO1 58B3<> 58B3<> 2 TITLE: DS33Z11/41/44DK01A0 NC PINS UNUSED???? GPIO<1> GPIO<2> GPIO<3> GPIO<4> GPIO<5> GPIO<6> GPIO<7> GPIO<8> RDATA<0> RDATA<1> RDATA<2> RDATA<3> RDATA<4> RDATA<5> RDATA<6> RDATA<7> RDATA<8> RDATA<9> RDATA<10> RDATA<11> RDATA<12> RDATA<13> RDATA<14> RDATA<15> RDATA<16> RDATA<17> RDATA<18> RDATA<19> RDATA<20> RDATA<21> RDATA<22> RDATA<23> RDATA<24> RDATA<25> RDATA<26> RDATA<27> RDATA<28> RDATA<29> RDATA<30> RDATA<31> 3 RED 6 TADR<0> TADR<1> TADR<2> TADR<3> TADR<4> A18 A16 E15 D15 C15 6 RED A B C 7 AVDDT1 AVDDT2 AVDDT3 AVDDT4 N14 N13 Y19 H15 H14 H13 G15 G14 G13 F15 F14 F13 B20 D1 T1 A4 Y4 J4 N1 E7 T7 G1 N5 C6 V6 K5 AVDDC M4 D 8 H5 AVDDJ1 AVDDJ2 AVDDJ3 AVDDJ4 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 M12 M11 L13 L12 L11 M15 M14 L15 L14 K15 K14 J15 J14 Y20 K13 K12 K11 J13 J12 J11 H12 H11 G12 G11 G10 G9 F12 F11 F10 F9 A20 H10 H9 H4 NC<0> NC<1> NC<2> NC<3> 2 0.0 2 M5 0.0 2 0.0 2 0.0 CR-58 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I2@\_ZTOP_LIB\.\_QUADTE3WAN_DN\(SCH_1):PAGE3 RED 1RB208 1R137 1RB194 1R132 RED A B C D A B C D TE3_RXN<4..1> TE3_TXP<4..1> TE3_TXN<4..1> 59D8< 59B4< 57C5< 57A4< 57A8< 57C8< 59D4< 59C8< 59A4< 57C2> 57A2> 57A5> 57C5> 59C4< 59C8< 59A4< 57C2> 57A2> 57A5> 57C5> 59C4< 8 TE3_RXP<4..1> TE3_TXN<4..1> TE3_TXP<4..1> 1 1 59D8< 59B4< 57C5< 57A4< 57A8< 57C8< 59D4< 59C4< 59A4< 57C2> 57A2> 57A5> 57C5> 59A8< 59C4< 59A4< 57C2> 57A2> 57A5> 57C5> 59A8< TE3_RXN<4..1> TE3_RXP<4..1> 8 1 1 2 2 2 2 1 6 27 8 25 RREF1 23 24 12 21 7 2:1 1 10 75 OHM RA J57 1 J51 75 OHM RA 1 J58 CONN_BNC_5P 6 75 OHM VERT CONN_BNC_5P RREF2 TREF2 TB019 2:1 TB0111 J50 CONN_BNC_5P 1 6 75 OHM VERT CONN_BNC_5P TREF1 22 2:1 TB017 26 2:1 TB015 7 28 R211 2 332 5 59C8< 59C4< 59A8< 57C5> 57C2> 57A5> 57A2> 59C8< 59C4< 59A8< 57C5> 57C2> 57A5> 57A2> 59D8< 59D4< 59B8< 57C8< 57C5< 57A8< 57A4< 4 TE3_TXN<4..1> TE3_TXP<4..1> TE3_RXN<4..1> TE3_RXP<4..1> 3 TE3_TXN<4..1> 59C8< 59A8< 59A4< 57C5> 57C2> 57A5> 57A2> 59D8< 59D4< 59B8< 57C8< 57C5< 57A8< 57A4< 3 TE3_TXP<4..1> 3 TE3_RXN<4..1> 59D8< 59B8< 59B4< 57C8< 57C5< 57A8< 57A4< 59C8< 59A8< 59A4< 57C5> 57C2> 57A5> 57A2> 3 TE3_RXP<4..1> 4 59D8< 59B8< 59B4< 57C8< 57C5< 57A8< 57A4< 5 CR-59 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I2@\_ZTOP_LIB\.\_QUADTE3WAN_DN\(SCH_1):PAGE4 1 R198 2 332 1 RB3562 51 1 RB3712 51 RB3582 51 1 R212 2 332 1 R199 2 332 1 2 3 4 5 2 3 4 5 4 4 4 4 4 29 2 31 14 16 18 17 J49 75 OHM RA 1 J56 75 OHM VERT RREF4 1 J52 CONN_BNC_5P TREF4 1 J59 CONN_BNC_5P 75 OHM RA 2 1 ENGINEER: 3 09/16/2004 PAGE: 4/8(BLOCK) 59/71(TOTAL) STEVE SCULLY DATE: 1 TITLE: DS33Z11/41/44DK01A0 2:1 TB0115 2:1 19 TREF3 TB0113 1 2 75 OHM VERT CONN_BNC_5P CONN_BNC_5P RREF3 20 2:1 TB011 32 2:1 TB013 3 30 R210 2 332 1 RB3062 332 1 1 RB3572 51 1 R213 2 332 1 R200 2 332 1 RB3552 51 RB3702 51 1 2 3 4 5 2 3 4 5 2 3 4 5 2 3 4 5 2 3 4 5 2 3 4 5 RB3682 51 1 RB3692 51 1 A B C D JP19 JMP_3 A B JP17 JMP_3 V3_3 60B1< 61B7<> 8 T3ENH_T1ENLPRT2 60C8<> 62C6<> IO55 IO56 IO57 IO58 IO59 IO60 IO61 IO62 IO63 IO64 IO65 IO66 IO67 IO68 IO69 UB04 XILINX_CPLD XILINX_XC9572XL Z44 CONNECTIONS 7 IO15 62C6<> 63C6<> 62C8<> 63C8<> 30 IO2 IO53 IO1 IO54 R64 IO70 62C8<> 63C8<> R61 IO3 IO52 IO71 IO4 IO51 IO72 62C6<> 63C6<> 30 R60 62D6<> 63D6<> IO12 6 PORTS ARE ENABLED BY DEFAULT ON T1 BRD AND ARE DISABLED USING JUMPERS ON T3 BRD 63C6<> 63D6<> OSC_A T3ENH_T1ENLPRT1 60C8<> 62D6<> 63D6<> 62D6<> 60A8<> 1 99 96 95 94 93 92 91 90 89 85 86 87 82 81 79 78 77 62C8<> 63C8<> 30 R63 IO5 IO50 T3ENH_T1ENLPRT2 T3ENH_T1ENLPRT1 R69 62C6<> 63C6<> 30 62C8<> 63C8<> R66 Z44_RSER<2> Z44_TSER<2> Z44_RCLK<2> Z44_TCLK<2> Z44_RDEN<2> Z44_TDEN<2> 30 R62 IO6 IO49 63C6<> 62C6<> 60A8<> 6 IO7 IO48 C 7 IO8 IO47 8 30 D 3 IO9 IO46 5 5 IO36 IO35 IO34 IO33 IO32 IO31 IO30 IO29 IO28 IO27 IO26 IO25 IO24 IO23 IO22 IO21 GCK3 IO20 IO19 14 27 15 17 30 60 72 70 64 68 74 40 65 54 55 63 58 56 4 4 4 4 4 4 2 2 2 2 2 2 1 V3_3 26 38 51 88 5 57 98 V3_3 1 3.3V3 3.3V2 3.3V1 2.5V_3.3V4 2.5V_3.3V3 2.5V_3.3V2 2.5V_3.3V1 2 5 8 30 RB149 30 RB148 30 RB145 CLKA CLKB OSC_A 56B8< 56B8<> 56B4< 56C7< 60B7<> 61B7<> 3 STEVE SCULLY 2 1 ENGINEER: OUT VCC V3_3 09/16/2004 PAGE: 5/8(BLOCK) 60/71(TOTAL) GND OSC Y08 44.736MHZ_5.0V 48 JTCLK 56D8<> 56C7< 61D2< 45 JTDO84 56C7<> 83 JTDT_NEXTCPLD61C2< JTMS 47 56D8<> 56C7< 61C2< 1 DATE: 61B3> 4 1 NC<8-0> TMS TDO TDI TCK 2 TITLE: DS33Z11/41/44DK01A0 57A5> 57C2> 57C5> 60B4> 61B4> TE3_RCLK<4..1> 57A1> 61C4> TE3_RSER<4..1> 57A1> 57A5> 57C2> 57C5> 60B4> 61B4> TE3_RGAPCLK<4..1> 57A1> 57A5> 57C2> 57C5> 60B3> 61B3> TE3_TCLK<4..1> 57A1> 57A5> 57C2> 57C5> 60B4> 61B4> TE3_TSER<4..1> 60B4> 61B4> 57A4< 57A8< 57C5< 57C8< TE3_TGAPCLK<4..1> 57A1> 57A5> 57C2> 57C5> 60B3> 61A3> 4 UB03 XILINX_CPLD XILINX_XC9572XL 3 J24 57A5> 57C2> 57C5> 60B4> 61B4> TE3_RCLK<4..1> 57A1> 61C4> TE3_RSER<4..1> 57A1> 57A5> 57C2> 57C5> 60B4> 61B4> 57A5> 57C2> 57C5> 60B3> TE3_RGAPCLK<4..1> 57A1> 61B3> TE3_TCLK<4..1> 57A1> 57A5> 57C2> 57C5> 60B4> 61B4> TE3_TSER<4..1> 60B4> 61B4> 57A4< 57A8< 57C5< 57C8< 57A5> 57C2> 57C5> 60A3> TE3_TGAPCLK<4..1> 57A1> 61A3> 61B3> SPARE_TP1 TP31 61C3<> LOOPBACK_CTRL 4 GND6 CR-60 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I2@\_ZTOP_LIB\.\_QUADTE3WAN_DN\(SCH_1):PAGE5 3 IO10 IO45 GND5 62D8<> 63D8<> 30 IO11 IO44 GND4 62C6<> 63C6<> 30 R65 IO42 GND3 62C8<> 63C8<> 30 R68 IO13 IO14 IO41 GND2 62C6<> 63C6<> 30 IO40 GND7 Z44_RSER<1> Z44_TSER<1> Z44_RCLK<1> Z44_TCLK<1> Z44_RDEN<1> Z44_TDEN<1> IO43 R85 R67 IO39 IO16 GCK1 IO17 IO38 GND8 29 25 28 18 20 10 11 97 13 3 8 9 12 4 6 22 23 GCK2 IO18 IO37 76 53 52 71 50 49 67 66 42 41 39 61 37 59 36 35 33 32 2.0K JMP_2 GND1 100 84 75 69 62 44 31 21 A B C D JP18 JMP_3 A B JP16 JMP_3 V3_3 60B1< 8 T3ENH_T1ENLPRT4 61C8<> 62B2<> 7 63B2<> 63C2<> OSC_A 60B7<> T3ENH_T1ENLPRT3 61C8<> 62C2<> 63C2<> 62C2<> 61A8<> 25 28 96 87 94 93 92 91 90 89 85 86 9 82 81 79 78 77 IO55 IO56 IO57 IO58 IO59 IO60 IO61 IO62 IO63 IO64 IO65 IO66 IO67 IO68 IO69 1 30 1 1 1 1 1 Z44 CONNECTIONS IO15 IO3 IO52 UB03 XILINX_CPLD XILINX_XC9572XL IO4 IO51 IO70 IO5 IO50 IO71 1 IO6 IO49 IO72 1 IO7 IO48 T3ENH_T1ENLPRT4 T3ENH_T1ENLPRT3 1 IO8 IO47 63B2<> 62B2<> 61A8<> 30 1 5 6 5 IO36 IO35 IO34 IO33 IO32 IO31 IO30 IO29 IO28 IO27 IO26 IO25 IO24 IO23 IO22 IO21 GCK3 IO20 IO19 20 27 16 29 30 61 33 39 60 42 74 40 54 72 71 50 70 36 3 3 3 3 3 3 1 1 1 1 1 1 1 IO2 IO53 IO1 IO54 60C4<> 26 38 51 88 5 57 98 3.3V3 3.3V2 3.3V1 2.5V_3.3V4 2.5V_3.3V3 2.5V_3.3V2 NC<8-0> TMS TDO TDI TCK 3 2 1 ENGINEER: STEVE SCULLY 09/16/2004 PAGE: 6/8(BLOCK) 61/71(TOTAL) 1 DATE: 61B3> 61A3> JTCLK 56D8<> 56C7< 60D2< 48 45 JTDT_NEXTCPLD60C2< 83 JTDOCPLD 56D8<> JTMS 56D8<> 56C7< 60C2< 47 2 TITLE: DS33Z11/41/44DK01A0 TE3_RCLK<4..1> 57A1> 57A5> 57C2> 57C5> 60B4> 61C4> TE3_RSER<4..1> 57A1> 57A5> 57C2> 57C5> 60B4> 61B4> TE3_RGAPCLK<4..1> 57A1> 57A5> 57C2> 57C5> 60B3> 61B3> TE3_TCLK<4..1> 57A1> 57A5> 57C2> 57C5> 60B4> 61B4> TE3_TSER<4..1> 60B4> 61B4> 57A4< 57A8< 57C5< 57C8< TE3_TGAPCLK<4..1> 57A1> 57A5> 57C2> 57C5> 60A3> 60B3> 4 UB04 XILINX_CPLD XILINX_XC9572XL 2.5V_3.3V1 V3_3 3 TE3_RCLK<4..1> 57A1> 57A5> 57C2> 57C5> 60B4> 61B4> TE3_RSER<4..1> 57A1> 57A5> 57C2> 57C5> 60B4> 61B4> TE3_RGAPCLK<4..1> 57A1> 57A5> 57C2> 57C5> 60B3> 61B3> TE3_TCLK<4..1> 57A1> 57A5> 57C2> 57C5> 60B4> 61B4> TE3_TSER<4..1> 60B4> 61B4> 57A4< 57A8< 57C5< 57C8< TE3_TGAPCLK<4..1> 57A1> 57A5> 57C2> 57C5> 60A3> 60B3> I79 TINYTESTPOINT NA NA SPARE_TP3 TP33 LOOPBACK_CTRL 4 GND6 63B2<> R35 Z44_RSER<4> 30 Z44_TSER<4> 62B2<> RB91 Z44_RCLK<4> R33 30 Z44_TCLK<4> RB95 30 Z44_RDEN<4> Z44_TDEN<4> 1 IO16 IO39 1 6 IO9 IO46 C 7 IO10 IO45 GND5 8 IO11 IO44 GND4 63C2<> IO12 IO43 GND3 D 3 IO13 IO14 IO42 GND2 CR-61 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I2@\_ZTOP_LIB\.\_QUADTE3WAN_DN\(SCH_1):PAGE6 3 30 R34 TP20 TP08 TP18 TP06 TP19 TP07 30 R36 Z44_RSER<3> 30 Z44_TSER<3> 62C2<> RB90 Z44_RCLK<3> R38 30 Z44_TCLK<3> RB89 30 Z44_RDEN<3> Z44_TDEN<3> IO41 GND7 R37 TP21 TP09 TP23 TP11 TP22 TP10 IO40 GCK1 IO17 IO38 GND8 8 18 17 13 14 10 99 12 15 4 6 95 97 1 3 22 23 GCK2 IO18 IO37 76 53 52 49 41 68 67 66 65 64 63 37 35 59 58 56 55 32 GND1 100 84 75 69 62 44 31 21 A B C D A B C D GND V3_3 VDD 8 7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 J10 GND GND 63D6<> T3_INT Z44_TCLK<2> 6 5 GND GND GND 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 J07 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 63A3<> RW 5 7 1 3 0 4 SIG_RETURN 62B3<> 62C6<> 62C8<> 63A1> 63B3<> 63C6<> 63C8<> 3 STEVE SCULLY 2 1 ENGINEER: I35 09/16/2004 PAGE: 7/8(BLOCK) 62/71(TOTAL) GND DATE: 63A3> 56B8< 62A1> 62C6<> 62C8<> 63A1> 63B3<> 63C6<> 63C8<> 63B2<> 61D6< 63B2<> 61D6< 1 TITLE: DS33Z11/41/44DK01A0 RD DAT<7..0> FPGAGCLK1_NU 62B7<> Z44_TCLK<4> SIG_RETURN Z44_TDEN<4> Z44_TSER<4> 63C2<> 61D5< 63C2<> 61D5< 61A8<> 61C8<> 63B2<> 61D7<> 63B2<> Z44_TCLK<3> T3ENH_T1ENLPRT4 2 61A8<> 61C8<> 63C2<> 61D6<> 63C2<> Z44_TDEN<3> Z44_TSER<3> T3ENH_T1ENLPRT3 ALE 63D3<> CS_X4 63D3<> NOTE 3184 IS ON CS3 WHILE 21455 IS ON CS2/CS4 63A4<> CS_X2 V3_3 CS_X3 WR 6 2 4 GND GND V3_3 GND GND GND V3_3 GND GND GND V3_3 GND GND GND V3_3 GND GND V3_3 63A4<> OSC1_NU Z44_RCLK<4> Z44_RDEN<4> Z44_RSER<4> Z44_RCLK<3> Z44_RDEN<3> RECEPTACLE 3 P1 CONNECTOR (RECEPTICAL) GND 4 Z44_RSER<3> DAT<7..0> 61D6< 63B5<> 61D6< 63B5<> 61D7< 63B5<> 61D5< 63C5<> 61D5< 63C5<> 61D6< 63C5<> 63A5< 56B7< 63A4<> CS 56B8< 63A4<> 63A5 63A3 62A3 56C3<> 63C6<> 60D6< 63C6<> 60D6< ADDR<10..0> OSC3_NU 63A6<> GND GND 10 6 8 3 5 1 TDO_NU 56D6<> 63B6<> TCK_NU 56D7<> 63B6<> 63D4<> CS_X5 62A1> 62B3<> 62C8<> 63A1> 63B3<> 63C6<> 63C8<> 60D7<> 63C6<> Z44_TDEN<2> Z44_TSER<2> SIG_RETURN 63C6<> 60D5< 63C6<> 60D5< 60A8<> 60C8<> 63C6<> Z44_TCLK<1> T3ENH_T1ENLPRT2 56A6<> 56B8> 63D5> 60A8<> 60C8<> 63D6<> 60D6<> 63D6<> Z44_TDEN<1> Z44_TSER<1> T3ENH_T1ENLPRT1 INT2 62D7<> 63D6<> 63D7<> RESET_B 63D6<> 56B8< I36 5 WAN R.C. CONNECTOR TO MOTHERBOARD GND GND GND GND GND GND GND GND 6 63D6<> INT3 INT4 GND GND GND GND GND GND P2 CONNECTOR (RECEPTICAL) RECEPTACLE 7 71 GND 72 63D7<> INT5 73 63D7<> 63D6<> 62D6<> INT2 74 GND 75 76 77 V3_3 78 60D6< 63D8<> Z44_RSER<1> 79 SIG_RETURN 80 63B3<> 63A1> 62C6<> 62B3<> 62A1> 63C8<> 63C6<> GND 81 60D5< 63C8<> Z44_RDEN<1> 82 83 GND 84 60D5< 63C8<> Z44_RCLK<1> 85 86 GND 87 88 89 V3_3 90 91 92 GND 93 60D7< 63C8<> Z44_RSER<2> 94 95 GND 96 60D6< 63C8<> Z44_RDEN<2> 97 98 GND 99 60D6< 63C8<> Z44_RCLK<2> 100 101 V3_3 102 103 104 GND 105 106 107 GND 108 109 110 GND 111 112 113 V3_3 114 115 116 GND 117 118 119 GND 120 62B3<> FPGAGCLK1_NU 121 122 GND 123 63B7<> 56D6<> TDI_NU 124 63B7<> 56D6<> TMS_NU 125 V3_3 126 0 127 2 128 GND 129 4 130 62A6 63A6 63A7 131 56D4< GND 132 ADDR<10..0>7 133 9 134 GND 135 136 137 V3_3 138 63A7<> OSC2_NU 139 63A7<> OSC4_NU 140 V3_3 8 CR-62 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I2@\_ZTOP_LIB\.\_QUADTE3WAN_DN\(SCH_1):PAGE7 A B C D A B C D 63A1> 62C8<> V3_3 GND V3_3 8 PLUG I25 7 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 JB06 5 4 6 5 WAN R.C. CONNECTOR TO MOTHERBOARD PLUG I8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 4 2 3 STEVE SCULLY 2 1 ENGINEER: 62A1> 62B3<> 62C6<> 62C8<> 63B3<> 63C6<> 63C8<> 09/16/2004 PAGE: 8/8(BLOCK) 63/71(TOTAL) SIG_RETURN DATE: I7 62C8<> 63A1> 63C6<> 63C8<> 1 TITLE: DS33Z11/41/44DK01A0 GND 1 ALE 62D3<> 2 CS_X4 62D3<> 3 4 GND 5 6 7 GND 8 9 10GND 11 12 13 14 15 16 GND 17 18 19 GND 20 21 22 GND 23 24 25 T3ENH_T1ENLPRT3 26 61A8<> 61C8<> 62C2<> 27 Z44_TSER<3> 61D6<> 62C2<> 28 GND 29 Z44_TDEN<3> 62C2<> 61D5< 30 31 GND 32 33 Z44_TCLK<3> 62C2<> 61D5< 34 GND 35 36 37 38 39 40GND T3ENH_T1ENLPRT4 41 61A8<> 61C8<> 62B2<> 42 Z44_TSER<4> 61D7<> 62B2<> 43GND 44 45 Z44_TDEN<4> 62B2<> 61D6< 46GND SIG_RETURN 47 62A1> 62B3<> 62C6<> 48 Z44_TCLK<4> 62B2<> 61D6< 49 50 51 52 GND 53 54 55GND 56 57 58 GND 59 60 0 61 62 1 63 3 GND 64 DAT<7..0> 65 5 66 7 67 GND 68 I6 62A3<> RW RD 62A3> 56B8< 69 70GND 3 NOTE 3184 IS ON CS3 WHILE 21455 IS ON CS2/CS4 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 JB05 P1 CONNECTOR (PLUG) PLUG STYLE CONNECTORS GO ON BOTTOM OF T3E3 WAN CARD DS21458 CONNECTS TO MOTHERBOARD BY STACKING ONTO T3E3 BRD 6 71 1 I14 GND 72 T3_INT 56A6<> 56B8> 62D5> 62D6<> INT3 2 73 62D4<> CS_X5 INT4 3 62D6<> 74 4 GND GND 75 INT2 62D6<> 62D7<> 63D7<> 5 76 RESET_B 62D6<> 56B8< 6 77 7 GND V3_3 78 T3ENH_T1ENLPRT1 60A8<> 60C8<> 62D6<> 8 79 9 Z44_TSER<1> 60D6<> 62D6<> 80 10GND GND 81 11 82 12 Z44_TDEN<1> 62C6<> 60D5< 83 13 GND 84 14 85 15 Z44_TCLK<1> 62C6<> 60D5< 86 16GND GND 87 17 88 18 89 19GND V3_3 90 20 T3ENH_T1ENLPRT2 91 21 60A8<> 60C8<> 62C6<> 92 22 GND GND 93 SIG_RETURN 23 62A1> 62B3<> 62C6<> 62C8<> 63A1> 63B3<> 63C8<> 94 24 Z44_TSER<2> 60D7<> 62C6<> 95 25 GND 96 26 Z44_RSER<3> 97 61D6< 62C5<> Z44_TDEN<2> 62C6<> 60D6< 27 98 28 GND GND 99 29 100 61D5< 62C5<> Z44_RDEN<3> Z44_TCLK<2> 62C6<> 60D6< 30 101 31 GND V3_3102 32 Z44_RCLK<3> 103 61D5< 62C5<> 33 104 34GND GND 105 35 106 36 107 37 GND 108 38 109 39 110 40GND GND111 41 112 61D7< 62B5<> Z44_RSER<4> 42 113 43GND V3_3114 44 115 61D6< 62B5<> Z44_RDEN<4> 45 116 46GND GND 117 47 Z44_RCLK<4> 118 61D6< 62B5<> 48 119 49 GND 120 50 121 51 122 52GND GND 123 TDO_NU 56D6<> 62B6<> 53 124 TCK_NU 56D7<> 62B6<> 54 125 55GND V3_3 126 56 127 57 1 128 58 GND GND 129 59 3 OSC1_NU 130 62A4<> 60 5 131 61 GND132 62 6 133 2 63 8 134 4 ADDR<10..0> 64 GND GND135 63A3 62A5 62A3 56C3<> DAT<7..0> 65 10 136 6 66 137 62A4<> CS_X2 GND 67 V3_3 138 I13 68 CS_X3 139 62A5< 56B7< 62A4<> CS OSC3_NU 62A6<> 69 WR 140 56B8< 62A4<> GND 70 P2 CONNECTOR (PLUG) 7 71 GND72 73 62D7<> INT5 74 63D6<> 62D7<> 62D6<> INT2 GND75 76 77 V3_3 78 79 60D6< 62D8<> Z44_RSER<1> SIG_RETURN 80 62C6<> 62B3<> 62A1> 63C6<> 63B3<> GND 81 82 60D5< 62C8<> Z44_RDEN<1> 83 GND 84 Z44_RCLK<1> 85 60D5< 62C8<> 86 GND 87 88 89 V3_3 90 91 92 GND 93 94 60D7< 62C8<> Z44_RSER<2> 95 GND 96 Z44_RDEN<2> 97 60D6< 62C8<> 98 GND 99 100 60D6< 62C8<> Z44_RCLK<2> 101 V3_3102 103 104 GND105 106 107 GND 108 109 110 GND 111 112 113 V3_3114 115 116 GND117 118 119 GND 120 121 122 GND 123 TDI_NU 124 62B7<> 56D6<> 125 62B7<> 56D6<> TMS_NU V3_3 126 127 0 128 2 GND 129 130 4 131 62A6 62A7 GND 132 63A6 ADDR<10..0>7 56D4< 133 134 9 GND 135 136 137 V3_3 138 OSC2_NU 139 62A7<> OSC4_NU 140 62A7<> I17 I15 8 CR-63 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I2@\_ZTOP_LIB\.\_QUADTE3WAN_DN\(SCH_1):PAGE8 A B C D