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GENERAL DESCRIPTION
The DS33Z44 design kit is an easy-to-use evaluation
board for the DS33Z44 Ethernet transport-over-serial
link device. The DS33Z44DK is intended to be used
with a resource card for the serial link. The serial link
resource cards are complete with transceivers,
transformers, and network connections. Dallas’
ChipView software is provided with the design kit,
giving point-and-click access to configuration and
status registers from a Windows®-based PC.
On-board LEDs indicate receive loss-of-signal, queue
overflow, Ethernet link, Tx/Rx, and interrupt status.
Windows is a registered trademark of Microsoft Corp.
ORDERING INFORMATION
PART DESCRIPTION
DS33Z44DK DS33Z44 demo card, T3/E3, T1/E1
transceiver resource card incl uded
FEATURES
Demonstrates Key Functions of DS33Z44
Ethernet Transport Chipset
Includes Two Resource Cards: One with
DS21458 T1/E1 SCT and one with DS3174
T3/E3 SCT, Transformers, BNC and RJ48
Network Connectors, and Termination
Provides Support for Hardware and Software
Modes
On-Board MMC2107 Processor and ChipView
Software Provide Point-and-Click Access to
the DS33Z44 Register Set
All DS33Z44 Interface Pins are Easily
Accessible for External Data Source/Sink
LEDs for Loss-of-Signal, Queue Overflow,
Ethernet Link, Tx/Rx, and Interrupt Status
Easy-to-Read Silkscreen Labels Identify the
Signals Associated with All Connectors,
Jumpers, and LEDs
DESIGN KIT CONTENTS
• DS33Z44DK Main Board
• Quad-Port Serial Card with DS21458 T1/E1 SCT
• Quad-Port Serial Card with DS317 4 T3/E3 SCT
• CD_ROM
o ChipView Software and Ma nual
o DS33Z44DK Data Sheet
o Configuration Files
www.maxim-ic.com
DS33Z44DK
Ethernet Transport Design Kit
DS33Z44DK
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TABLE OF CONTENTS
GENERAL DESCRIPTION..........................................................................................................1
ORDERING INFORMATION .......................................................................................................1
DESIGN KIT CONTENTS............................................................................................................1
COMPONENT LIST.....................................................................................................................3
PC BOARD ERRATA................................................................................................................10
FILE LOCATIONS.....................................................................................................................10
BASIC OPERATION..................................................................................................................11
POWERING UP THE DESIGN KIT ...............................................................................................................11
General............................................................................................................................................................... 11
BASIC DS33Z44 INITIALIZATION (USED FOR ALL QUICK SETUPS) .............................................................11
Quick Setup #1 (Device Driver + CPLD Loopback) ........................................................................................... 11
Quick Setup #2 (DS3174 T3E3)......................................................................................................................... 12
Quick Setup #3 (DS21458 T1E1)....................................................................................................................... 12
CONFIGURATION SWITCHES AND JUMPERS......................................................................13
ADDRESS MAP (ALL CARDS) ................................................................................................15
DS33Z44 INFORMATION..........................................................................................................15
DS33Z44DK INFORMATION ....................................................................................................15
TECHNICAL SUPPORT............................................................................................................15
DOCUMENT REVISION HISTORY ...........................................................................................15
SCHEMATICS ...........................................................................................................................16
LIST OF FIGURES
Figure 1. System Floorplan.......................................................................................................................................... 8
Figure 2. DS3174 Resource Card Floorplan ............................................................................................................... 8
Figure 3. DS21458 Resource Card Floorplan ............................................................................................................. 9
LIST OF TABLES
Table 1. Component List (Decoupling Caps Not Shown)............................................................................................ 3
Table 2. Main Board PC Board Configuration ........................................................................................................... 13
Table 3. DS3174 Serial Reference Card Jumper Settings........................................................................................ 14
Table 4. Overview of Daughter Card Address Map................................................................................................... 15
DS33Z44DK
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COMPONEN T LIST
Table 1 shows the component list for the DS33Z44 and DS33Z11/DS33Z41 design kits and resource cards. This
BOM contains the part listing for five boards. These boards are the DS33Z11DK, DS33Z44DK, DS21458RC,
DS3174RC, and DS2155-DS21348-DS3170RC. Each reference designator is only used once. For example, U18
only appears on the DS33Z11DK and is not used on any of the other boards. See Table 2.
Table 1. Component List (Decoupling Caps Not Shown)
DESIGNATION QTY DESCRIPTION SUPPLIER PART
U18 1
ELITE 10/100 ETHERNET TRANSPORT OVER
SERIAL LINK 14X14 CSBGA 169 PIN Dallas Semiconductor DS33Z11
U20 1
3.3V T1.E1.J1 QUAD TRANSCEIVER 0-70C 256P
BGA Dallas Semiconductor DS21458
U22 1
QUAD 10/100 ETHERNET EXTENSION TO WAN
17X17 PBGA 256 PIN Dallas Semiconductor DS33Z44
U23 1 DS3/E3 SCT, 11X11 CSBGA, 100 PIN Dallas Semiconductor DS3170
U24 1 T1/E1/J1 XCVR 100P QFP 0-70C Dallas Semiconductor DS2156L
U25 1 3.3V LIU Dallas Semiconductor DS21348
UB08 1
QUAD TRIPLE DUAL SINGLE ATM PACKET PHYS
FOR DS3 E3 STS1 0-70C 400P BGA Dallas Semiconductor DS3184
U01, U09 2 SOIC 8PIN STEP-UP DC-DC CONVERTER 0.5A
LIMIT Maxim MAX1675EUA
U07, U11 2 8-Pin μMAX/SOIC 1.8V or Adj Maxim MAX1792EUA18
U13, UB01 2 MICROPROCESSOR VOLTAGE MONITOR, 2.93V
RESET, 4PIN SOT143 Maxim MAX811SEUS-T
U21, UB07 2 Dual RS-232 transceivers with 3.3V/5V internal
capacitors MAXIM NA
U31, UB06, UB11 3 8-Pin μMAX/SOIC 2.5V or Adj Maxim MAX1792EUA25
C11, C13, C16, C25, C27, C31–
C35, C37, C41, C47, CB10,
CB63, CB114, CB128, CB164,
CB496
19 1206 CERAM 10uF 10V 20% Panasonic ECJ-3YB1A106M
CB390, CB391, CB395, CB396 4 1206 CERAM 0.1uF 25V 10% Panasonic ECJ-3VB1E104K
D01–D03, D05, DB03–DB05 7 SCHOTTKY DIODE, 1 AMP 40 VOLT International Rectifier 10BQ040
DS01, DS07, DS10–DS12,
DS17, DS20 7 LED, AMBER, SMD Panasonic LN1451C
DS02, DS03, DS09, DS14,
DS15 5 L_LED, GREEN, SMD Panasonic LN1351C
DS04–DS06, DS08, DS13,
DS16, DS18, DS27, DS28,
DS35, DS37, DS38, DS40
13 LED, RED, SMD Panasonic LN1251C
DS19, DS43 2 LED, GREEN, SMD Panasonic LN1351C
DS21–DS26, DS30, DS32–
DS34, DS36, DS39, DS41,
DS42, DS44–DS48
19 L_LED, RED, SMD Panasonic LN1251C
GND_TP01–GND_TP07,
GND_TP09-–GND_TP44,
GND_TP46–GND_TP68,
GND_TPB01–GND_TPB10
76 STANDARD GROUND CLIP KEYSTONE 4954
H1–H8, H17–H19 8 KIT, 4-40 HARDWARE, .50 NYLON STANDOFF AND
NYLON HEX-NUT NA Lab Stock
DS33Z44DK
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DESIGNATION QTY DESCRIPTION SUPPLIER PART
H9–H16 16
KIT, 4-40 HARDWARE, 1.12 NYLON STANDOFF
AND NYLON HEX-NUT (1.12 STANDOFF PN =
4807K-ND)
NA Lab Stock
J01–J05 5 CONNECTOR, FASTJACK SINGLE, 8 PIN Halo Electronics HFJ11-2450E
J06, J41 2 100 MIL 2*7 POS JUMPER NA Lab Stock
J07–J12 6
RECEPTACLE, SMD, 140 PIN, .8MM, 2 ROW
VERTICAL AMP 5-179010-6
J13–J22 10
L_TERMINAL STRIP, 10 PIN, DUAL ROW, VERT DO
NOT POPLUATE NA Lab Stock
J23, J29, J32, J38, J39, J43,
J44, J47, JB07 9 L_TERMINAL STRIP, SHROUDED, 10 PIN, DUAL
ROW, VERT 3M Electronics 2510-6002UB
J24, J30, J31, J33 4 100 MIL 2 POS JUMPER NA Lab Stock
J25, J26, J45, J46 4 TERMINAL STRIP, 10 PIN, DUAL ROW, VERT NA Lab Stock
J27, J42 2 CONN 50 PIN, 2 ROW, POSTS VERT,
MOTHERBOARD FOOTPRINT SAMTEC TSW-125-07-T-D
J28, J36 2 L_CONN, DB9 RA, LONG CASE AMP 747459-1
J48, J54, JB01 3 SOCKET, BANANA PLUG, HORIZONTAL, BLACK Mouser Electronics 164-6218
J49–J52 4 CONNECTOR BNC 75 OHM VERTICAL 5PIN Cambridge CP-BNCPC-004
J53, JB02, JB08 3 SOCKET, BANANA PLUG, HORIZONTAL, RED Mouser Electronics 164-6219
J55, JB11 2 L_RJ48 8 PIN SINGLE PORT CONNECTOR MOLEX 15-43-8588
J56–J59, J61, J63 6 CONNECTOR BNC 75 OHM RA 5PIN Trompetor UCBJR220
J60, J62, J64, J65 4 CONNECTOR BNC RA 5PIN Trompetor UCBJR220
JB05, JB06, JB09, JB10, JB13,
JB14 6 PLUG, SMD, 140 PIN, .8MM, 2 ROW VERTICAL AMP 179031-6
JB12 1 RA RJ45 8PIN 4PORT JACK MOL 43223-8140
JP01–JP19 19 100 MIL 3 POS JUMPER NA NA
L01, L03–L08, LB01, LB02 9 FERRITE 3A 100 OHM AT 100 MHZ 1206 SMD Steward HI1206N101R-00
L02, L09 2 INDUCTOR 22.0uH 2PIN SMT 20% Coiltronics UP1B-220
L10 1 XFMR 1-2CT XMIT, 1-1CT RCV, 40P WIDE SOIC Pulse T1068
R01, R02, RB10, RB11, RB18,
RB19, RB22, RB23, RB26,
RB27
10 RES 0603 54.9 Ohm 1/16W 1% Panasonic ERJ-3EKF54R9V
R03, R04, RB12, RB13, RB20,
RB21, RB24, RB25, RB28,
RB29
10 RES 0603 49.9 Ohm 1/16W 1% Panasonic ERJ-3EKF49R9V
R05, R06, R08, R09, R11 5 RES 0603 10.0K Ohm 1/16W 1% - Must be 1%
tolerance Panasonic ERJ-3EKF1002V
R07, R12, R16, R79, R160,
R244, R248, R250, R251,
R254, R255, RB126, RB143,
RB147, RB150, RB157
16 RES 0603 1.0K Ohm 1/16W 5% Panasonic ERJ-3GEYJ102V
R10, R107 2 RES 1206 5.6 Ohm 1/8W 5% Panasonic ERJ-
8GEYJ5R6V
R132, R137, R142, R144,
R156, RB194, RB208, RB227 8 L_RES 0603 0 Ohm 1/16W 1% AVX CJ10-000F
DS33Z44DK
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DESIGNATION QTY DESCRIPTION SUPPLIER PART
R13–R15, R18–R20, R22, R23,
R29, R30, RB01, RB03, RB07,
RB09, RB15–RB17, RB30–
RB32, RB34–RB38, RB41,
RB44, RB47, RB48, RB50–
RB52, B55, RB60, RB62, RB72,
RB73, RB75, RB80, RB82
40 RES 0603 5.1K Ohm 1/16W 5% Panasonic ERJ-3GEYJ512V
R17, R21, R25–R28, R31, R55,
R57–R59, R71, R74–R76, R83,
R96–R102, R105, R106, R109,
R111, R112, R115–R117,
R120, R122–R126, R128,
R133, R134, R140, R141,
RB61, RB96, RB97, RB99,
RB100, RB102–RB110, RB112,
RB114–RB119, RB121,
RB123–RB125, RB127, RB128,
RB130, RB131, RB133,
RB135–RB138, RB145, RB148,
RB149, RB160, RB161, RB164,
RB165, RB167–RB171,
RB173–RB181, RB184, RB187,
RB311, RB320, RB335, RB339,
RB359
104 RES 0603 30 Ohm 1/16W Panasonic ERJ-3GEYJ300V
R171, R172, R174, R175,
R190, R191, R240, R241 8 L_RES 0805 0.0 Ohm 1/10W 5% Panasonic ERJ-
6GEY0R00V
R198–R200, R210–R213,
RB306, RB325, RB326 10 RES 0603 332 Ohm 1/16W 1% Panasonic ERJ-3EKF3320V
R201–R208, RB321–RB324,
RB327–RB330 16 RES 1206 0 Ohm 1/8W 5% Panasonic ERJ-
8GEYJ0R00V
R239, RB349 2 RES 0805 51.1 Ohm 1/10W 1% Panasonic ERJ-6ENF51R1V
R24, R114, R197, RB14, RB33,
RB40, RB42, RB43, RB49,
RB53, RB54, RB57–RB59,
RB71, RB77, RB78, RB152–
RB156, RB221, RB234, RB251,
RB284, RB304, RB331, RB332,
RB342, RB344, RB350, RB354,
RB360
34 L_RES 0603 330 Ohm 1/16W 5% Panasonic ERJ-3GEYJ331V
R242, R243, RB144, RB166,
RB355–RB358, RB368–RB371 12 RES 0603 51 Ohm 1/16W 5% Panasonic ERJ-3GEYJ510V
R32, R70, R78, R161, R176,
R194, R195, R237, R238,
RB129, RB134, RB146, RB193
13 RES 0603 330 Ohm 1/16W 5% Panasonic ERJ-3GEYJ331V
R33–R54, R60–R69, R72, R73,
R131, R136, R143, R147,
R150, R154, R158, R163,
R166, R169, R173, R178–
R189, R215–R228, RB89–
RB95, RB101, RB188–RB191,
RB196–RB199, RB202–RB205,
RB210–RB213, RB216–RB219,
RB223–RB226, RB230–RB233,
RB239–RB242, RB244–RB249,
RB252–RB260, RB265–RB268,
RB270-RB282, RB289–RB297
152 RES 0402 30 Ohm 1/16W 5% Panasonic ERJ-2GEJ300X
R56, R90 2 RES 0603 1.0M Ohm 1/16W 5% Panasonic ERJ-3GEYJ105V
R77, RB159 2 L_RES 1206 0 Ohm 1/8W 5% Panasonic ERJ-
8GEYJ0R00V
R80, R81, R84, R87, R89, R91–
R93, R95, R108, R110, R118,
R127, R152, R153, R196,
R209, R214, R229–R236,
RB200, RB237, RB238, RB263,
RB264, RB286, RB287, RB300,
RB301, RB333, RB364
37 RES 0603 10K Ohm 1/16W 5% Panasonic ERJ-3GEYJ103V
DS33Z44DK
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DESIGNATION QTY DESCRIPTION SUPPLIER PART
R85, R88, R94, R104, R113,
RB02, RB04–RB06, RB08,
RB39, RB45, RB46, RB56,
RB63–RB70, RB76, RB83,
RB98, RB183, RB185, RB192,
RB209, RB228, RB302, RB303,
RB305, RB338, RB340, RB341,
RB346–RB348, RB351–RB353,
RB361–RB363, RB365–RB367
48 RES 0603 2.0K Ohm 1/16W 5% Panasonic ERJ-3GEYJ202V
R86, R103, R119, R121, R129,
R130, R135, R138, R139,
R145, R146, R149, R151,
R157, R162, R164, R167,
R168, R170, R177, R192,
R193, R245-R247, R249, R252,
R253, R256, R257, RB74,
RB79, RB132, RB139-RB141,
RB151, RB162, RB163, RB172,
RB182, RB186, RB206, RB207,
RB214, RB215, RB220, RB222,
RB229, RB235, RB236, RB243,
RB250, RB261, RB262, RB269,
RB308–RB310, RB343, RB345
61 L_RES 0603 10K Ohm 1/16W 5% Panasonic ERJ-3GEYJ103V
RB201, RB285 2 RES 0805 330 Ohm 1/10W 5% Panasonic ERJ-6GEYJ331V
RB283 1
RES 0603 10K Ohm 1/10W 5% - SEE SPECIAL
INSTRUCTIONS Panasonic 603_ERJ-
3GEYJ103V
RB298, RB299, RB312–RB319,
RB336, RB337 12 RES 0805 61.9 Ohm 1/10W 1% Panasonic ERJ-6ENF61R9V
RB81, RB84–RB88, RB111,
RB113, RB120, RB122 10 RES 0603 DO NOT POPULATE NA NA
SW01–SW05, SW08–SW21,
SW24–SW26, SW29–SW31,
SW33–SW44
37 L_SWITCH, SP3T SLIDE, 4PIN TH Tyco 3-1437575-3
SW06, SW22 2 L_SWITH 8POS 16PIN DIP LOW PROFILE AMP 435668-7
SW07, SW23 2 SWITCH MOM 4PIN SINGLE POLE Panasonic EVQPAE04M
SW27, SW28, SW32 3 L_DIPSWITCH, 10 POS AMP 435668-9
T01, T03 2 XFMR 16P SMT Pulse TX1099
T02, TB01 2 XFMR, OCTAL T3/E3, 1 TO 2, SMT 32 PIN Pulse T3049
TP01–TP78, TPB01, TPB02 80 TESTPOINT, 1 PLATED HOLE, DO NOT STUFF NA NA
U02–U06 5
IC, DsPHYTER11-SINGLE 10/100 ETHERNET
TRANSCEIVER, 65 PIN LLP
National
Semiconductor
DP83847ALQA5
6A
U08, U12, U29 3 1MBit Flash based config mem Avnet XCF01SV020C
U10 1 XILINX SPARTAN xc200 2.5V FPGA,256 PIN BGA Xilinx XC2S200-
5FG256C
U14, U26, U30, UB05 4 CYPRESS SRAM, LAB STOCK NA NA
U15, U19 2 mmc2107 processor Motorola MMC2107
U16, U27 2 XILINX SPARTAN 2.5V FPGA,256 PIN BGA Xilinx XC2S50-
5FG256C
U17, U28, U32 3 10 pin res pack, 10K ohm NA NA
UB02, UB03, UB04 3 100 PIN CPLD XILINX XC95144XL-
10TQ100C
UB09, UB10 2 SYNCHRONOUS DRAM, 1MEGX32X4 BANKS,
TSOP 86 PIN Micron MT48LC4M32B2
TG-7
DS33Z44DK
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DESIGNATION QTY DESCRIPTION SUPPLIER PART
UX01–UX12, UXB02–UXB04,
UXB06–UXB08 18 HIGH SPEED BUFFER Fairchild NC7SZ86
UXB01, UXB05 2 HIGH SPEED INVERTER Fairchild NC7SZ86
X01, X02 2 XTAL LOW PROFILE 8.0MHZ ECL EC1-8.000M
Y01, Y09 2 OSCILLATOR, CRYSTAL CLOCK, 3.3V - 25.000
MHZ, Low Jitter required for PHY SaRonix NTH089AA3-
25.000
Y02, Y13 2 SPI SERIAL EEPROM 16K 8 PIN DIP 2.7V NEEDS
SOCKET Atmel AT25160A-10PI-
2.7
Y03 1 OSCILLATOR, CRYSTAL CLOCK, 3.3V - 2.048 MHZ SaRonix NTH039A3-
2.0480
Y05, Y06 2 OSCILLATOR, CRYSTAL CLOCK, 3.3V - 100.000
MHZ SaRonix NTH089A3-
100.0000
Y07 1 OSCILLATOR, CRYSTAL CLOCK, 3.3V - 44.736 MHZ SaRonix NTH089AA3-
44.736
Y08 1 OSCILLATOR, CRYSTAL CLOCK, 5.0V - 44.736 MHZ SaRonix NTH089AA-
44.736
YB02 1
L_OSCILLATOR, CRYSTAL CLOCK, 3.3V - 2.048
MHZ SaRonix NTH039A3-
2.0480
DS33Z44DK
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Figure 1. System Floorplan
Figure 2. DS3174 Resource Card Floorplan
DS33Z44 MAINBOARD
DS33Z44
SDRAM
ETHERNET PHYs,
MAGNETIC,
LEDS, AND
JUMPERS
MICROPROCESSOR
AND SERIAL PORT
(57600-8-N-1)
HARDWARE
MODE SWITCHES
FOR DS33Z44
SERIAL INTERFACE
2 X 140 PIN CONNECTORS
LEDS AND TESTPOINTS DS21458 RESOURCE CARD
(DETAIL PROVIDED BELOW)
DS3184 RESOURCE CARD
(DETAIL PROVIDED BELOW)
BNC Tx Rx
DS3174 PORT 3
LAN PORT 3
DS3174 PORT 1
LAN PORT 4
DS3174 PORT 2
LAN PORT 2
DS3174 PORT 4
LAN PORT 1
DS3174
QUAD-PORT
T3/E3
TRANSCEIVER
CPLD
(MUX)
CPLD
(MUX)
140 PIN CONNECTORS (2 TOP, 2 BOTTOM)
TEST POINTS
+ JUMPERS
JUMPERS
LOOPBACK
JUMPER
OSC
JTAG
DS33Z44DK
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The DS3174 quad T3/E3 PC board floorplan is shown in Figure 2. Jumpers JP16, JP17, JP18, and JP19 are 3-pin
jumpers used to tri-state/enable T3/E3 ports. With the board oriented as shown in Figure 2, the top 2 pins of each
jumper would be connected to enable T3/E3 traffic.
A 2-pin jumper, JP24, has been added to allow loopback. When installed, the board is in loopback at the CPLD; all
traffic sent by the DS33Z44 is then sent back to the Z44. Traffic sent by the DS3174 is ignored in CPLD loopback
mode.
The quad T3/E3 board is intended to be connected to the DS33Z11 or DS33Z44 motherboards. The quad T3/E3
board can be used with the quad T1/E1 board. When used in this manner, the quad T1/E1 board is stacked
underneath the quad T3/E3 board. Jumpers on the T3/E3 board are then used to tri-state or enable individual ports
on either board.
Figure 3 shows the DS21458 quad T1/E1 PC board floorplan. The current configuration is to populate oscillators
for MCLK1 with a 2.048MHz oscillator. Testpoints for port 3 and port 4 are provided on the WAN card, and
testpoints for ports 1 and 2 are provided on the motherboard.
The quad T1/E1 board can be used with the quad T3/E3 board. When used in this manner, the quad T1/E1 board
is stacked underneath the quad T3/E3 board. Jumpers on the T3/E3 board are then used to tri-state or enable
individual ports on either board.
Figure 3. DS21458 Resource Card Floorplan
PORT 2
PORT 4
PORT 1
PORT 3
DS21458
QUAD-PORT
T1/E1
TRANSCEIVER
140 PIN CONNECTORS
TEST POINTS
FPGA
OSC
MCLK1, 2
J
TA
G
QUAD-PORT RJ45
QUAD
TRANSFORMER
RLOS LEDS
INT LED
DS33Z44DK
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PC BOARD ERRATA
• Silk screen for the serial resource card has VCC and ground indicators pointing the wrong direction for
configuration switches SW27, SW28, and SW32. This should be corrected with an adhesive label.
• Signal descriptions for JTAG connector are incorrect on the Quad T1E1 card. This should be corrected with an
adhesive label.
• In the PCB layout the transformer TX primary is on the wrong side (creating a 2:1 winding instead of a 1:2).
This has been corrected in the schematic, the PCB / assembly has been modified to correct this.
FILE LOCATIONS
This design kit relies upon several supporting files, which are provided on the CD and are available as a zip file
from the Maxim website at www.maxim-ic.com/DS33Z44DK.
All locations are given relative to the top directory of the CD/zip file.
• DS33Z44 register definition files and configuration files:
o .\cfg_demo_gui\DS33Z44_cfg_demo_gui\DS33Z44.def
o .\DS33Z44_cfg_demo_gui\SU_LI_PORT4.def (def files for port 3, 2, 1 not shown)
o .\DS33Z44_cfg_demo_gui\basic_config.mfg
• DS21458 register definition files and configuration files:
o .\DS33Z44_cfg_demo_gui\Qt1e1_DS21458\DS21458RC.def
o .\DS33Z44_cfg_demo_gui\Qt1e1_DS21458\DS21458RC_FPGA.def
o .\DS33Z44_cfg_demo_gui\Qt1e1_DS21458\e1_gapclk_crc4_hdb3_nocas.ini
o .\DS33Z44_cfg_demo_gui\Qt1e1_DS21458\gapclk_DS21458_T1_ESF_LBO0.ini
• DS3174 register definition files and configuration files:
o .\DS33Z44_cfg_demo_gui\Qt3e3_DS3184\ds3184_evbrd_reduced.def
o ….. 14 other low level def files ….
o .\DS33Z44_cfg_demo_gui\Qt3e3_DS3184\84_t3_sct_needscoaxlb.mfg
DS33Z44DK
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BASIC OPERATION
Powering Up the Design Kit
• Attach resource card to main board.
• Connect PCB 3.3V and GND banana plugs to power supply. At power-up the system should draw
approximately 1A.
• Set switches for software mode as described in Table 2 (short description follows).
• Top left bank: All low, except for MODEC0, which is high.
• Top right bank: A2, A1, A0 in mid position, SCANTRI low
• Bottom Bank: All high (AFCS, FULLDS, H1OS)
General
• Upon power-up, the processor FPGA Status LEDs (DS19 green) will be lit. Interrupt LEDs (DS42 red) will not
be lit. DS33Z44 Queue overflow LEDs (DS45, DS46, DS47, DS48 red) will not be lit. PHY LINK LED (DS02,
DS03, DS14 green) should be lit if the Ethernet is connected.
Following are several basic system initializations.
Basic DS33Z44 Initialization (Used for All Quick Setups)
This section covers four basic methods for configuring the Z44. Any one of these initializations can be used with
the following Quick Setup examples:
1. Upon power-up, the on-board device driver provides a basic configuration for the DS33Z44 and attached
serial cards. This enables traffic to pass from the Ethernet port to the serial port. Consult the device driver
documentation for further details. Device driver behavior is dependant upon jumper settings, which are
detailed in Table 2.
2. Register-Based Configuration. Launch ChipView.exe and select Register View. When prompted for a
definition file, pick the file named DS33Z44.def. After the definition file loads, go to the File menu and
select File→Memory Config File→Load .MFG file. When prompted, select the file named
4Portsbasic_config.mfg.
3. Hardware Mode. Set switches as described in the section for powering up the design kit, then change the
following: HWMODE←3.3V, A0←3.3VV, A1←3.3V, A2←0V. This sets the part for LSB first, scrambling off,
HDLC encapsulated. At this point traffic will pass from the Ethernet port to the serial port. In this mode
broadcast frames are not passed (i.e., ping).
4. EEPROM mode is available with the DK, but is beyond the scope of this manual.
Quick Setup #1 (Device Driver + CPLD Loopback)
• On the serial resource card install jumper 24. Jumpers JP16–JP19 should be set high. This places the card in
CPLD loopback and enables all four ports as described in Table 3.
• Complete the hardware configuration and one of the basic DS33Z44 configurations as described in the
previous section.
• Using a patch cable, connect the Ethernet connector to an ordinary PC, or network test equipment. This should
cause the link LED to turn on.
• At this point any packets sent to the DS33Z44 are echoed back. Incoming packets (i.e., ping) should cause the
RX LED to blink, after which the TX LED should also blink.
• To interact with the device driver select from the drop down menu:
• Tools→Plugins→Load Plugins. When asked if DLLs have already registered select yes
• Select Tools→Plugins→DS33Z44/11/41 Device Driver Demo
• A new form called ‘Zchip Configuration’ pops up.
• Preload basic configuration for the GUI by selecting File→Load Settings (in the ‘Zchip Configuration’ form).
Select the file named ‘basic_Config.eset’
DS33Z44DK
12 of 59
Quick Setup #2 (DS3174 T3E3)
• On the DS3174 serial resource card install jumper J24. Jumpers JP16–JP19 should be set high. This places
the card in DS3174 mode and enables all four ports as described in Table 3.
• Complete the hardware configuration and one of the basic DS33Z44 configurations as previously described.
• Using a patch cable, connect the Ethernet connector to an ordinary PC, or network test equipment. This should
cause the link LED to turn on.
• Launch ChipView.exe (or use existing session if it is already open) and select Register View. When prompted
for a definition file, pick the file name ds3184_evbrd_reduced.def. After the definition file loads, go to the File
menu and select File→Memory Config File→Load .MFG file. When prompted, select the file named
84_t3_sct_needscoaxlb.mfg.
• Place a loopback connector at the DS3174 network side.
• At this point, any packets sent to the DS33Z44 are echoed back. Incoming packets (i.e., ping) should cause the
RX LED to blink, after which the TX LED should also blink.
Quick Setup #3 (DS21458 T1E1)
• Complete the hardware configuration and one of the basic DS33Z44 configurations as previously described.
• Using a patch cable, connect the Ethernet connector to an ordinary PC, or network test equipment. This should
cause the link LED to turn on.
• Launch ChipView.exe (or use existing session if it is already open) and select Register View. When prompted
for a definition file, pick the file named DS21458.def. After the definition file loads, go to the File menu and
select File→Reg Ini File→Load Ini File. When prompted, pick the file named
e1_gapclk_crc4_hdb3_nocas.ini.
• Place a loopback connector at the DS21458 network side; RLOS LED should go out.
• At this point any packets sent to the DS33Z44 are echoed back. Incoming packets (i.e. ping) should cause the
RX LED to blink, after which the TX LED should also blink.
DS33Z44DK
13 of 59
CONFIGURATION SWITCHES AND JUMPERS
The DS33Z44DK has several configuration switches, banana plugs, oscillators, and jumpers. Table 2 provides a
description of these signals, given in order of appearance on the PC board (going from left to right, top to bottom).
Table 2. Main Board PC Board Configuration
BASIC SETTING
SILKSCREEN
REFERENCE FUNCTION SW MODE HW MODE DESCRIPTION
J25.9 + J25.10 Reserved Not Installed —
This jumper is not for use with the
DS33Z44 design kit. Pin J25.10 has
been removed to prevent accidental
installation.
J25.7 + J25.8 Enable device driver User decision —
When installed the device driver will
configure the DS33Z44 and the
Transceiver during power-up.
J25.5 + J25.6 Enable callbacks User decision — When installed the driver will
respond to interrupts.
GROUND
(banana plug) Power supply ground — — System Ground. Always connected
to power supply.
VDD 3.3V
(banana plug) Power supply VDD — — System VDD. Always connected to
power supply.
OnCe BDM — — Debug connector for processor
DCEDTES
(3pos switch)
DS33Z44 mode pin;
DTE/DCE selection Low Low Low for DTE
RMIIMII
(3pos switch) DS33Z44 mode pin Low Low High for RMII, low for MII
CKPHA
(3pos switch) DS33Z44 mode pin Low Low SPI EEPROM hardware mode
configuration switch
MODEC0
(3pos switch) DS33Z44 mode pin High Low Software mode selected
MODEC1
(3pos switch) DS33Z44 mode pin Low Low Software mode selected
HWMODE
(3pos switch) DS33Z44 mode pin Low Low Hardware/software mode (software
mode selected)
SCANMO
(3pos switch) DS33Z44 mode pin Low Low Set low for normal operation
SCANTRI
(3pos switch) DS33Z44 mode pin Low Low Set low for normal operation
….testpoints…. DS33Z44 testpoints — — Processor bus, JTAG and LAN side
testpoints for Zchip
Z-RESET (button) DS33Z44 reset — — System reset
A2, A1, A0
(3pos switches) DS33Z44/SPI pins Mid position Mid position
Address pin/EEPROM config switch.
Set to mid position to allow
connection to processor.
SDRAM CLOCK DS33Z44 SDRAM
clock Installed Installed
100MHz oscillator to drive SDRAM
clock
MII CLOCK PHY MII clock Installed Installed 25MHz oscillator to drive SDRAM
clock
spi_cs, spi_ck,
spi_miso,
spi_mosi
— — — SPI signals (for EEPROM memory)
….testpoints….. DS33Z44 testpoints — — DS33Z44 serial port testpoints
AFCS
(1 per port) DS33Z44 mode pin HW mode only High Set high to enable auto flow control.
DS33Z44DK
14 of 59
BASIC SETTING
SILKSCREEN
REFERENCE FUNCTION SW MODE HW MODE DESCRIPTION
FULLDS
(1 per port) DS33Z44 mode pin HW mode only High Set high to enable full duplex.
H10S
(1 per port) DS33Z44 mode pin HW mode only High Set high to confg for 100Mb.
GROUND/VDD
(banana plug)
Power supply
ground/3.3V — —
Redundant connection to system
power. Use plugs at either top or
bottom of board.
VDD 3.3V
(banana plug) Power supply VDD — —
Redundant connection to system
power. Use plugs at either top or
bottom of board.
Table 3. DS3174 Serial Reference Card Jumper Settings
JUMPER
SETTINGS MODE COMMENT
JP16 Port 4 tri-state
(at CPLD)
When the middle pin of this 3 position jumper is set to VCC, the
CPLD passes traffic from the DS3174 to the DS33Z44. When the pin
is set low, the CPLD tri-states this port.
JP17 Port 2 tri-state
(at CPLD)
When the middle pin of this 3 position jumper is set to VCC, the
CPLD passes traffic from the DS3174 to the DS33Z44. When the pin
is set low, the CPLD tri-states this port.
JP18 Port 3 tri-state
(at CPLD)
When the middle pin of this 3 position jumper is set to VCC, the
CPLD passes traffic from the DS3174 to the DS33Z44. When the pin
is set low, the CPLD tri-states this port.
JP19 Port 1 tri-state
(at CPLD)
When the middle pin of this 3 position jumper is set to VCC, the
CPLD passes traffic from the DS3174 to the DS33Z44. When the pin
is set low, the CPLD tri-states this port.
J243 CPLD loopback
CPLD loopback makes the following connections:
Zrser ← Ztser, Ztden ← 3.3V, Zrden ← 3.3V,
Ztclki ← OscY03, Zrclki ← OscY03
DS33Z44DK
15 of 59
ADDRESS MAP (ALL CARDS)
Motorola resource card address space begins at 0x81000000. All offsets given below are relative to the beginning
of the daughter card addre ss space (shown previously).
Table 4. Overview of Daughter Card Address Map
OFFSET DEVICE DESCRIPTION
0X0000 to
0X0087 FPGA Processor board identificat i on
0X1000 to
0X1FFF DS33Z44 DS33Z44. Uses CS_X1.
0X2000 to
0X2FFF DS21458 T1E1 DS21458 resource card. Uses CS_X2.
0X4000 to
0X4010 FPGA
FPGA on DS21458 resour ce card. Used to facilitate IBO mode.
Default configuration of FPGA is compat ible with non-IBO mode
functionality. The FPGA settings do not require modification for
use with the DS33Z44.
0X3000 to
0X3FFF DS3174 T3E3 resou r ce card. Uses CS_X3.
Registers in the DS33Z44, DS21458, and DS3174 can be easily modified using the ChipView host-based user-
interface software with the definition files previously mentioned.
DS33Z44 INFORMATION
For more information about the DS33Z44, consult the DS33Z44 data sheet available on our website at
www.maxim-ic.com/DS33Z44.
DS33Z44DK INFORMATION
For more information about the DS33Z44DK, including software downloads, consult the DS33Z44DK data sheet
available on the our websit e at www.maxim-ic.com/DS33Z44DK.
TECHNICAL S UPPORT
For additional technical support, go to www.maxim-ic.com/support.
DOCUMENT REVISION HISTORY
REVISION
DATE DESCRIPTION
032305 Initial DS33Z44DK data sheet release.
042205 Updated Basic DS33Z44 Initialization section; added step to
Quick Setup #1.
051105 Added new PC board e rrata.
110106 Updated schematics.
DS33Z44DK
16 of 59
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.
SCHEMATICS
The DS33Z44DK schematics are featured in the following pages. As this is a hierarchal schematic some
explanation is in order. The main board is composed of six hierarchal blocks: the processor block, the DS33Z44
block, and four Ethernet blocks inside the DS33Z44 block, which is a nested hierarchy block. Each serial card
(DS21458 and DS3174) consists of a single hierarchy block, which connects to a 140-pin AV bus that snaps into
the mainboard.
All signals inside a hierarchy block are local, with exception for VCC and ground. In-port and out-port connectors are
used to allow signals inside a hierarchy block to become accessible as pins on the hierarchy blocks symbol. From
here, blocks are wired together as if they were ordinary components. The system diagram is shown again below,
with schematic page numbers given for each functional block.
This system contained other hierarchy blocks that are not shown (primarily a single-port serial card and the
DS33Z11 mainboard). Due to this, page numbers will not be continuous and some gaps in numbering will be seen
when referring to the total page count. However, page numbers inside any given hierarchy block will be continuous.
DS33Z44 BLOCK
PAGE 20 SYMBOL
SCHEMATIC
PAGES 22-29
µP BLOCK
PAGE 21 SYMBOL
SCHEMATIC
PAGES 38-44
DS33Z44 MAINBOARD TOP LEVEL
PHY SYMBOLS ON
PAGES 26-27
PORT 1 ETHERNET
PHY
SCHEMATIC
PAGES 30-31
PORT 3 ETHERNET
PHY
SCHEMATIC
PAGES 36-37
PORT 2 ETHERNET
PHY
SCHEMATIC
PAGES 32-33
SERIAL INTERFACE
2 X 140 PIN CONNECTORS
DS21458 RESOURCE CARD
SCHEMATIC
PAGES 46-55
DS3184 RESOURCE CARD
SCHEMATIC
PAGES 56-63
P2 CONNECTOR (PLUG)
MOTHERBOARD CONNECTORS FOR WAN R.C.
DS33Z44 TOP LEVEL
P1 CONNECTOR (PLUG)
HIERARCHICAL BLOCK
PAGES 22-29
0
GND
V3_3
XA<15..0>
XD<7..0>
9
11
7
4
0
2
10
8
6
5
1
3
6
4
2
5
7
3
1
GND
Z44INT
PLUG
V3_3
GND
GND
GND
SIG_RETURN
Z44_TSER<2>
GND
GND
TDO_NU
TCK_NU
GND
GND
GND
GND
OSC3_NU
GND
OSC4_NU
OSC2_NU
V3_3
GND
GND
GND
V3_3
TMS_NU
TDI_NU
GND
FPGAGCLK1_NU
GND
GND
GND
V3_3
Z44_RCLK<2>
GND
GND
Z44_RSER<2>
GND
V3_3
GND
Z44_RCLK<1>
Z44_RDEN<1>
GND
Z44_RSER<1>
INT2
INT5
GND
Z44_TDEN<2>
RESET_B
XA<15..0>
Z44_RDEN<2>
SIG_RETURN
GND
GND
V3_3
GND
XD<7..0>
GND
Z44_TCLK<2>
GND
GND
GND
GND
GND
GND
INT4
INT2
Z44_TSER<1>
Z44_TCLK<1>
Z44_TDEN<1>
GND
SIG_RETURN
GND
V3_3
GND
ALE
CS_X4
GND
GND
GND
GND
GND
Z44_TSER<3>
Z44_TDEN<3>
GND
Z44_TCLK<3>
GND
Z44_TSER<4>
Z44_TDEN<4>
GND
SIG_RETURN
Z44_TCLK<4>
FPGAGCLK1_NU
GND
GND
GND
GND
GND
GND
CS_X3
V3_3
CS_X2
GND
GND
OSC1_NU
GND
V3_3
GND
GND
Z44_RCLK<4>
GND
Z44_RDEN<4>
GND
Z44_RSER<4>
GND
V3_3
GND
Z44_RSER<3>
GND
V3_3
GND
GND
GND
V3_3
GND
CS_X5
GND
GND
GND
GND
JB14
GND
GND
WR_X RW_X
PLUG
INT3
Z44INT
Z44_RSER<4..1>
Z44_RDEN<4..1>
Z44_TCLK<4..1>
Z44_TSER<4..1>
A_DUT<9..0>
D_DUT<7..0>
WR_DUT
CS_X1
Z44_TDEN<4..1>
BIS0_DUT
BIS1_DUT
Z44_RCLK<4..1>
BTS_DUT
RESET_B
JB10
RD_DUT
Z44_RCLK<3>
Z44_RDEN<3>
1/2(BLOCK)
09/16/2004
STEVE SCULLY
BLOCK
NAME:
_z44top_dn.
PARENT
BLOCK:
\_ztopdn_\
20/71(TOTAL)
DS33Z11/41/44DK01A0
CR-20
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I8@\_ZTOP_LIB\.\_Z44TOP_DN\(SCH_1):PAGE1
PRINTED
Fri
Oct
20
11:06:56
2006
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20A1
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20C5<> 20B8<> 20B5<> 20A8<> 20A5<>
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22B6v
22B7v
22B6v
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20C8<>
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25B7v
25D3v
25D7v
21B7<
22B6v
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22B6v
21C4>
22B6v
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22B6v
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25B2v
25B5v
25C5v
25D2v
20C8<
21C4>
25D2v
22B6v
20C7<>
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
8
81
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92
93 24
91
23
35
105
63
123
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70
69
48
41
38
37
45
110
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98
87
73
71
9
80
13
11
10
15
90
16
68
67
134
132
131
130
129
128
127
126
125
124
72
5
82
18
20
12
7
4
107
108
112
113 44
43
3
2
1
VDD
V3_3
8
81
83
84
85
92
93 24
91
23
35
105
63
123
6
14
17
22
19
21
26
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137
70
69
48
41
38
37
45
110
104
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87
73
71
9
80
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11
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132
131
130
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72
5
82
18
20
12
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107
108
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113 44
43
3
2
1
_z44andlan_dn
RESET_B
HWMODE
RCLKI<4..1>
MODEC1
MODEC0
TDEN<4..1>
CS
WR
DAT<7..0>
ADDR<9..0>
RD
TSER<4..1>
TCLKI<4..1>
RDEN<4..1>
RSER<4..1>
INT
PAGES 38-44
HIERARCHICAL BLOCK
CS_X1
XD<7..0>
XA<15..0>
WR_X
INT4
TDO_NU
TCK_NU
TDI_NU
TMS_NU
BTS_DUT
BIS1_DUT
BIS0_DUT
WR_DUT
RD_DUT
INT5
INT3
INT2
RESET_B
CS_X4
CS_X5
RW_X
CS_X2
CS_X3
D_DUT<7..0>
A_DUT<11..0>
I1
CR-21
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I8@\_ZTOP_LIB\.\_Z44TOP_DN\(SCH_1):PAGE2
BLOCK
NAME:
_z44top_dn.
PARENT
BLOCK:
\_ztopdn_\
2/2(BLOCK)
09/16/2004
21/71(TOTAL)
STEVE SCULLY
DS33Z11/41/44DK01A0
20A5<>
44A7v
20A5<> 42B3v
20A6 20A8 42C7v
20A3 20A5 42B3v
20C7<>
38B7v
20A7<> 44A7v20A7<> 44A7v20A8<>20A8<> 44A7v
20C1>
42C3v
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42C3v
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20C7<>
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20C3<> 42A4v
20C5<> 42A4v
20D3<
42B3v
20A3<> 42B3v
42B3v
20A5<> 42A4v
20D3<
42D5v
20D3<
42A5v42A6v
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
_motprocrescard_dn
CS_X1
CS_X2
CS_X3
RESET_B
CS_X5
CS_X4
TDO_NU
TCK_NU
TDI_NU
TMS_NU
INT2
INT3
INT4
INT5
RD_DUT
WR_DUT
D_DUT<7..0>
A_DUT<11..0>
BIS0_DUT
BIS1_DUT
BTS_DUT
XD<7..0>
XA<15..0>
WR
RW_X
UNMARKED RESISTORS ARE 30 OHM
U22
TPB02
RB181
TPB01
TP34
J32
RB246
RB282
R163
RB219
R158
RB226
RB217
R147
RB239
R166
SW18
SW08
SW04
Y02
RB79
RB74
RB332
DS42
UXB07
ZSPICS
INT
CS
ZADDR2
ZSPISCK
TMS_NU
DAT<7..0>
8
ZMOSI
SD_CLKI
SD_RAS
SD_CAS
WR
RESET_B
HWMODE
MODEC0
MODEC1
DCEDTES
RMIIMIIS
MDC
REF_CLK
ADDR<9..0>
2.7V
ZADDR2
2
7
6
SD_DQM3
INT
330
RED
SD_BA1
SD_DQM0
SD_DQM2
5
4
2
10K
0
ZADDR0
ZADDR1
ADDR<9..0>
1
0
10K
3
7
6
4
5
3
JTCLK
JTMS
JTRST
TCK_NU
TDI_NU
TDO_NU
JTDO
JTDI
1
SD_WE
SD_CS
SD_DQM1
SD_BA0
ZMISO
ZSPISCK
ZSPICS
ZMOSI
JTMS
JTDI
JTCLK
ZMISO
RD
SCANEN
SCANMOD
CKPHA
ZADDR0
JTDO
JTRST
ZADDR1
9
MDIO
REF_CLKO
BUFFER
SD_CLKO
R99
RB161
RB230
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20D3^
20D3^
20D3^
28D4<
20C2^
28D2<
20C2^
28D4<
20C2^
22B1<
20D3^
22C4<
20D3^
20D3^
BLOCK
NAME:
_z44andlan_dn.
PARENT
BLOCK:
\_z44top_dn\
DS33Z11/41/44DK01A0
STEVE SCULLY
22/71(TOTAL)
1/8(BLOCK)
09/16/2004
CR-22
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I8@\_ZTOP_LIB\.\_Z44TOP_DN\(SCH_1):PAGE1_I2@\_ZTOP_LIB\.\_Z44ANDLAN_DN\(SCH_1):PAGE1
F7
E4
D4
R8
A7
A6
D6
E13
E1
E2
C4
E7
E8
F6
D7
A15
D1
D8
T11
N11
F10
C15
P8
T7
T15
M7
D5
D3
R9
A5
C5
B15
F11
A1
P15
N7
R7
E5
E6
C3
B5
B2
B1
B7
C2
B4
A4
B3
A3
A2
C6
B6
T8
4
11
22
1
1
6
2
8
7
3
4
5
4
4
4
65
4
9
7
3
10
8
1
2
11
1
22C2<
22A2<>
22C2<
22C2<
28D5<
24C4<
24C4<
28D2<
28C4<
27B6>
27B3> 26B6> 26B3>
28A4<
22C4<
24C4<
20D2^
22A7>
24B4<
24C4<
24C4<
22D4<
22C4<
22D6<
22D6<
22D6<
22D6<>
22D6<
24C4<
24C4<
24C4<
24B4<
22C4<>
22B4<>
22A6>
22C4<>
22A5<>
22A5<>
22A5<>
22C2>
28B4<
28C4<
28B4<
22B2<>
22A5<>
22A5<>
22B2<>
27B6>
27B3> 26B6> 26B3>
24C3<
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
IN
OUT
OUT
OUT
V3_3
6
10
8
4
1
2
3
5
7
9
CONN_10P
SP3T
SP3T
SP3T
V3_3
AT25160A_U
SI
GND
WP*
HOLD*
VCC
SO
SCK
CS*
IN
V3_3
V3_3
NC7SZ86_U
OUT
IN
IN
IN
IO
DS33Z44_U1
JTAG
MICRO PORT/SPI MASTER PORT
SDRAM CONTROL
MII/RMII
SDMASK<0>
D<4>
D<7>
A<2>
A<5>
A<6>
A<8>
A<9>
A<4>
D<5>
A<1>
A<3>
D<3>
A<7>
JTRST
JTDO
SWE*
SCAS*
SRAS*
A<0>
MDC
REF_CLKO
D<6>
D<0>/MOSI
SBA<1>
INT*
HWMODE
SDMASK<1>
SYSCLKI
SDCLKO
SDCS*
REF_CLK
MDIO
SDMASK<3>
SDMASK<2>
RST*
CS*
DCEDTES
MODEC<1>
CKPHA
SCAN MODE
SCAN ENABLE
RMIIMIIS
WR*/RW*
RD*/DS*
SPI_CS*
MODEC<0>
D<1>/MISO
D<2>/SPICK
SBA<0>
JTCLK
JTDI
JTMS
UNMARKED RESISTORS ARE 30 OHM
UNMARKED RESISTORS ARE 30 OHMS
I182
NA
DS33Z44
V1_8ZCHIP
V1_8ZCHIP
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
10UF
10UF
16
17
10UF
10UF
10UF
10UF
470UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
0.1UF
0.1UF
0.1UF
0.1UF
470UF
2
19
SD_A<11..0>
10
11
9
8
7
6
5
4
3
2
1
0
31
29
28
27
26
25
24
23
22
21
20
18
15
11
10
9
8
7
6
5
4
3
1
0
SD_DQ<31..0>
BLACK
RED
12
14
13
10UF
RB233
RB247
RB242
RB213
RB212
RB191
RB211
RB210
RB218
RB267
RB249
R173
RB280
RB268
R169
RB265
RB281
RB248
RB241
RB279
RB240
RB197
R143
RB189
RB198
RB202
R136
R131
RB204
RB188
RB199
RB203
R150
RB196
RB190
RB223
RB216
RB205
RB224
RB231
RB232
RB225
RB266
R154
TP51
TP52
TP50
TP49
J48
J53
CB361
CB492
CB402
CB446
CB335
CB469
CB421
CB301
CB423
CB323
CB298
CB315
CB312
CB387
CB247
CB255
CB256
CB178
CB246
CB227
CB177
CB386
C102
CB162
CB400
CB47
CB240
C184
CB289
C90
CB408
CB417
C101
C88
C89
CB26
CB211
CB381
CB495
CB202
CB115
U22
DS33Z11/41/44DK01A0
STEVE SCULLY
09/16/2004
23/71(TOTAL)
BLOCK
NAME:
_z44andlan_dn.
PARENT
BLOCK:
\_z44top_dn\
2/8(BLOCK)
CR-23
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I8@\_ZTOP_LIB\.\_Z44TOP_DN\(SCH_1):PAGE1_I2@\_ZTOP_LIB\.\_Z44ANDLAN_DN\(SCH_1):PAGE2
1111
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
M14
P9
R11
T10
R10
G3
G4
H4
H6
H8
C1
E3
H7
D2
H5
H9
H10
G10
G1
F9
F8
F3
J4
J3
J6
J5
T9
P10
N8
M8
N10
N9
M9
P11
M10
K6
J7
K5
J8
J9
J10
K3
K4
L10
K7
K8
K9
K10
L3
L4
L5
L6
L7
L8
L9
M11
M12
N15
P13
P14
R14
R13
T14
T12
T13
P12
N12
R12
P4
N5
N4
M5
M3
M6
N6
P6
P7
R6
T6
T5
R5
T4
P5
R4
L12
M13
N13
F4
M4
A14
P2
N3
L13
K12
E14
F13
G12
G9
H3
G5
G6
G8
G7
29B6< 23D4<
29A4<>
29B6< 23B4<
29A4<>
24A3>
24D7
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
DS33Z44_U1
PWR/GND
SDRAM CONTROL
3.3VDD4
3.3VDD5
3.3VDD3
3.3VDD2
3.3VDD8
3.3VDD6
1.8VDD13
1.8VDD12
1.8VDD11
1.8VDD10
1.8VDD8
1.8VDD7
1.8VDD6
1.8VDD5
1.8VDD4
1.8VDD3
SDATA<27>
SDATA<28>
SDATA<29>
SDATA<0>
SDATA<1>
SDATA<2>
SDATA<3>
SDATA<4>
SDATA<5>
SDATA<6>
SDATA<7>
SDATA<9>
SDATA<8>
SDATA<10>
SDATA<11>
SDATA<12>
SDATA<13>
SDATA<14>
SDATA<15>
SDATA<16>
SDATA<17>
SDATA<18>
SDATA<19>
SDATA<20>
SDATA<21>
SDATA<22>
SDATA<23>
SDATA<24>
SDATA<25>
SDATA<26>
SDATA<30>
SDATA<31>
VSS24
VSS23
VSS22
VSS21
VSS20
VSS19
VSS18
VSS17
VSS16
VSS15
VSS14
VSS11
VSS10
VSS9
VSS8
VSS7
VSS6
VSS4
VSS5
VSS13
VSS12
SDA<3>
SDA<4>
SDA<5>
SDA<6>
SDA<7>
SDA<8>
SDA<10>
SDA<11>
VSS2
VSS3
VSS0
VSS1
NC1
NC2
NC3
NC4
3.3VDD7
3.3VDD15
3.3VDD14
3.3VDD10
1.8VDD1
3.3VDD12
1.8VDD2
1.8VDD0
3.3VDD13
3.3VDD11
3.3VDD9
3.3VDD1
3.3VDD0
SDA<0>
SDA<1>
SDA<2>
SDA<9>
1.8VDD9
V3_3
V3_3
CONN_BANANA_2P
B
A
CONN_BANANA_2P
B
A
V3_3
SYNCHRONOUS DRAM
MT48LC4M32B2 - 1 MEG X 32 X 4 BANKS
FROM Z11 SYSCLKO
SD_DQ<31..0>
SD_A<11..0>
SD_BA1
SD_BA0
SD_DQM3
SD_DQM2
SD_DQM1
SD_DQM0
SD_RAS
SD_CAS
SD_WE
SD_CS
SD_CLKO
30
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
10
11
9
8
7
6
5
4
3
1
2
0
UB09
DS33Z11/41/44DK01A0
STEVE SCULLY
09/16/2004
BLOCK
NAME:
_z44andlan_dn.
PARENT
BLOCK:
\_z44top_dn\
3/8(BLOCK)
24/71(TOTAL)
CR-24
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I8@\_ZTOP_LIB\.\_Z44TOP_DN\(SCH_1):PAGE1_I2@\_ZTOP_LIB\.\_Z44ANDLAN_DN\(SCH_1):PAGE3
43
29
55
3
68
20
67
18
17
16
19
71
28
59
22
23
25
26
60
27
61
63
62
65
64
66
24
21
10
11
13
74
76
77
79
80
83
82
85
31
33
34
37
36
39
42
40
47
45
48
50
51
53
49
41
8
15
1
5
7
4
2
54
56
84
52
78
46
32
38
6
12
72
86
44
58
75
81
35
9
23A2
23C8
22C8<
22C8<
22C8<
22C8<
22C8<
22C8<
22B8<
22B8<
22B8<
22C8<
22B8<
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
MT48LC4M32B2_TSOP_U
VDDQ2
VDDQ3
VDDQ8
VDDQ7
VSS2
VSS1
VSS4
VSS3
VSSQ2
VSSQ1
VSSQ4
VSSQ3
VSSQ5
VSSQ7
VSSQ6
VSSQ8
DQ<31>
DQ<30>
DQ<0>
DQ<1>
DQ<3>
DQ<2>
VDD1
VDD2
DQ<4>
VDDQ4
VDDQ5
DQ<29>
DQ<28>
DQ<27>
DQ<26>
DQ<24>
DQ<25>
DQ<22>
DQ<23>
DQ<21>
DQ<19>
DQ<20>
DQ<18>
DQ<17>
DQ<16>
DQ<15>
DQ<13>
DQ<14>
DQ<12>
DQ<11>
DQ<10>
DQ<9>
DQ<8>
DQ<7>
DQ<6>
DQ<5>
A<11>
A<10>
A<9>
A<7>
A<8>
A<5>
A<6>
A<4>
A<2>
A<3>
A<1>
A<0>
BA<1>
BA<0>
DQM<3>
DQM<2>
DQM<1>
RAS*
DQM<0>
WE*
CAS*
CKE
CS*
CLK
VDDQ1
VDDQ6
VDD3
VDD4
V3_3
V3_3
REV01A0 SCHEMATIC SYMBOL (AND PCB) FOR Z44 HAD ERRORS
TXD/RXD PINS FOR PHY CONNECTION WERE INCORRECT
CORRECT PINOUT SHOWN AT BOTTOM OF PAGE
PORT4 RXD0--RXD3 B13,C13,B14,C14
PORT3 RXD0--RXD3 G15,J14,J13,J12
PORT2 RXD0--RXD3 K13,K14,H15,K16
PORT1 RXD0--RXD3 B11,C11,D11,E11
PORT4 TXD0--TXD3 B16,C16,D16,E16
PORT3 TXD0--TXD3 F15,G14,H13,H14
PORT2 TXD0--TXD3 R15,R16,L15,N14
PORT1 TXD0--TXD3 B9, C9, D9, E9
PORT4 PIN T3
PORT2 PIN L2
PORT3 PIN N2
PORT1 PIN G2
RSER<1>
RCLKI<1> TCLKI<1>
RCLKI<4> TCLKI<4>
TDEN<4>
RXDV<4>
RX_CRS<4>
RX_ERR<4>
COL_DET<4>
FULLDS<4>
RX_CLK<4>
TX_CLK<4>
QOVF<4>
H10S<4>
AFCS<4>
RSER<4>
RDEN<4>
RXD0<4>
RXD1<4>
RXD2<4>
RXD3<4>
RCLKI<3> TCLKI<3>
TDEN<3>
RXDV<3>
RX_CRS<3>
RX_ERR<3>
COL_DET<3>
FULLDS<3>
RX_CLK<3>
TX_CLK<3>
QOVF<3>
H10S<3>
AFCS<3>
RSER<3>
RDEN<3>
RXD0<3>
RXD1<3>
RXD2<3>
RXD3<3>
RXDV<2>
RX_CRS<2>
RX_ERR<2>
COL_DET<2>
FULLDS<2>
RX_CLK<2>
TX_CLK<2>
QOVF<2>
H10S<2>
AFCS<2>
RXD0<2>
RXD1<2>
RXD2<2>
RXD3<2>
TX_EN<1>
TXD3<1>
TDEN<1>
TXD0<1>
TXD1<1>
TXD2<1>
30
30
TCLKI<2>
TDEN<2>
TX_EN<2>
TXD3<2>
TXD2<2>
TXD1<2>
TXD0<2>
TSER<2>
30
30
30
30
30
30 30
TSER<4>
30
TXD0<4>
30
TXD1<4>
30
TXD2<4>
30
TXD3<4>
30
TX_EN<4>
30
TSER<3>
30
TXD0<3>
30
TXD1<3>
30
TXD2<3>
30
TXD3<3>
30
TX_EN<3>
RCLKI<2>
RSER<2>
RDEN<2>
30
30
30
TSER<1>
RXD3<1>
RXD2<1>
RXD1<1>
AFCS<1>
H10S<1>
QOVF<1>
TX_CLK<1>
RX_CLK<1>
COL_DET<1>
RX_ERR<1>
RXDV<1>
30
RXD0<1>
RDEN<1>
RX_CRS<1>
FULLDS<1>
RB311
R97
R123
RB187
RB169
RB170
RB320
R126
RB171
RB167
RB168
R124
RB335
R105
R122
R96
R115
R98
RB339
RB164
RB165
RB180
RB121
RB179
TP57
TP59
TP58
TP63
TP65
TP64
TP54
TP56
TP55
TP60
TP62
TP61
U22
U22
U22
U22
20D2^
20D2^ 20D2^
20D2^ 20D2^
20D2^
20D2^
20D2^
20D2^ 20D2^
20D2^
20D2^
20D2^
20D2^
20D2^
20D2^
20D2^
20D2^
20D2^
20D2^
20D2^
20D2^
20D2^
20D2^
BLOCK
NAME:
_z44andlan_dn.
PARENT
BLOCK:
\_z44top_dn\
DS33Z11/41/44DK01A0
STEVE SCULLY
09/16/2004
4/8(BLOCK)
25/71(TOTAL)
CR-25
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I8@\_ZTOP_LIB\.\_Z44TOP_DN\(SCH_1):PAGE1_I2@\_ZTOP_LIB\.\_Z44ANDLAN_DN\(SCH_1):PAGE4
C14
B14
C13
B13
T1
T2
C12
B12
A8
A16
A13
G13
D16
E16
B16
C16
A12
F16
D14
F14
D15
R2
R3
R1
T3
J12
J13
J14
G15
N1
P1
J11
F12
B8
G16
H16
E15
H13
H14
F15
G14
H12
H11
G11
M15
K11
M2
P3
M1
N2
K16
H15
K14
K13
L1
K1
J16
L11
C8
M16
L16
L14
L15
N14
R15
R16
J15
P16
T16
N16
K15
J2
K2
J1
L2
E11
D11
C11
B11
H2
H1
C10
B10
C7
A9
A11
E10
D9
E9
B9
C9
A10
D13
E12
D12
D10
F2
F5
F1
G2
27C2>
27C2>
27C2>
27C2>
29B4<
27D2>
27D4<
29C8<>
29A4<
29A4<
27D2>
27D2>
27D2>
27D2>
27C5>
27C5>
27C5>
27C5>
29D4<
27D5>
27D8<
29C8<>
29C4<
29C4<
27D5>
27D5>
27D5>
27D5>
26C2>
26C2>
26C2>
26C2>
29B2<
26D2>
26D5<
29D8<>
29A2<
29B2<
26D2>
26D2>
26D2>
26D2>
26C8<
26D8<
26D8<
26D8<
26D8<
26C5<
26D5<
26D5<
26D5<
26D5<
27D4<
27D4<
27D4<
27D4<
27C4<
27D8<
27D8<
27D8<
27D8<
27C8<26D5>
26D5>
26D5>
29D2<
29C2<
29D8<>
26D8<
26D5>
26C5>
26C5>
26C5>
26D5>
26C5>
29D2<
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
DS33Z44_U1
PORT
RCLKI TCLKI
TDEN/TBSYNC
TSER
RXDV
RX_CRS/CRS_DV
RX_ERR
COL_DET
FULLDS
TXD1
TXD0
TXD3
TXD2
TX_EN
RX_CLK
TX_CLK
QOVF
H10S
AFCS
RSER
RDEN/RBSYNC
RXD0
RXD1
RXD2
RXD3
DS33Z44_U1
PORT
RCLKI TCLKI
TDEN/TBSYNC
TSER
RXDV
RX_CRS/CRS_DV
RX_ERR
COL_DET
FULLDS
TXD1
TXD0
TXD3
TXD2
TX_EN
RX_CLK
TX_CLK
QOVF
H10S
AFCS
RSER
RDEN/RBSYNC
RXD0
RXD1
RXD2
RXD3
DS33Z44_U1
PORT
RCLKI TCLKI
TDEN/TBSYNC
TSER
RXDV
RX_CRS/CRS_DV
RX_ERR
COL_DET
FULLDS
TXD1
TXD0
TXD3
TXD2
TX_EN
RX_CLK
TX_CLK
QOVF
H10S
AFCS
RSER
RDEN/RBSYNC
RXD0
RXD1
RXD2
RXD3
DS33Z44_U1
PORT
RCLKI TCLKI
TDEN/TBSYNC
TSER
RXDV
RX_CRS/CRS_DV
RX_ERR
COL_DET
FULLDS
TXD1
TXD0
TXD3
TXD2
TX_EN
RX_CLK
TX_CLK
QOVF
H10S
AFCS
RSER
RDEN/RBSYNC
RXD0
RXD1
RXD2
RXD3
IN
IO
IN
IN
IN
IN
IN
IN
OUT
IO
IN
OUT
IN
IN
IO
IN
IO
IN
OUT
IN
IN
IN
OUT
IN
CHASSIS GND FOR PHY
PAGES 30-31 PAGES 32-33
HIERARCHICAL BLOCKHIERARCHICAL BLOCK
100O100MZH
10UF
10UF
0.1UF
100O100MZH
MDIO
5.1K
5.1K
5.1K
330
5.1K
330
330
5.1K
RX_CLK<2>
RX_ERR<2>
RX_CRS<2>
RXD3<2>
RXD1<2>
RXD0<2>
RXDV<2>
MII_CLK<2>
MDC
LED_GDLINK_A2<2>
TXD3<2>
TXD2<2>
COL_DET<2>
LED_RX_A4<2>
5.1K
5.1K
5.1K
330
5.1K
330
330
5.1K
LED_DPLX_A0<1>
LED_COL_A1<1>
RXD2<2>
TXD1<2>
TXD0<2>
LED_TX_A3<2>
LED_DPLX_A0<2>
AMBER
RED
GREEN GREEN
AMBER
LED_TX_A3<1>
LED_RX_A4<1> LED_RX_A4<2>
LED_TX_A3<2>
LED_GDLINK_A2<2>
LED_DPLX_A0<2>
RED
LED_GDLINK_A2<1>
TX_CLK<2>
TX_EN<2>
LED_COL_A1<2>
10UF
LED_COL_A1<2>
RESET_B
LED_TX_A3<1>
LED_RX_A4<1>
COL_DET<1>
TXD2<1>
TXD3<1>
LED_COL_A1<1>
LED_DPLX_A0<1>
LED_GDLINK_A2<1>
TX_CLK<1>
TX_EN<1>
RESET_B
MDIO
MDC
MII_CLK<1>
RXDV<1>
RXD0<1>
RXD1<1>
RXD2<1>
RXD3<1>
RX_CRS<1>
RX_ERR<1>
RX_CLK<1>
TXD1<1>
TXD0<1>
RB75
RB80
R19
RB58
DS09
RB49
R13
R23
RB71
DS07
DS13
R22
R18
RB34
RB33
DS02
RB15
RB14
R14
DS01
RB42
DS05
L01
CB02
CB03
LB02
CB01
C04
26/71(TOTAL)
5/8(BLOCK)
BLOCK
NAME:
_z44andlan_dn.
PARENT
BLOCK:
\_z44top_dn\
STEVE SCULLY
DS33Z11/41/44DK01A0
CR-26
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I8@\_ZTOP_LIB\.\_Z44TOP_DN\(SCH_1):PAGE1_I2@\_ZTOP_LIB\.\_Z44ANDLAN_DN\(SCH_1):PAGE5
09/16/2004
1
2
1
2
1
2
1
2
2
1
1
2
1
2
1
2
1
2
32C5v22C8<27B6> 27B3>26B6>
32A7v
25A5<>
32A7v25A8<
32A7v25A8<
32A7v25A8<
32A7v25A8<
32A7v25B8<
32A7v25A8<
28A4< 30C5v32C5v22C8<27B6>27B3>26B6>
32C5v
26A4<>
32A5v 25A5<
32A5v 25A5<
32A7v25A8<
32C5v
26A4<>
30C5v 26C8<
30C5v 26C8<
32A7v25A8<
32A5v 25A5<
32A5v 25B5<
32C5v
26A4<>
32C5v 26B4<
30C5v 26C8<
30C5v 26C8< 32C5v 26C5<
32C5v 26C5<
32C5v 26C5<
32C5v 26C5<
30C5v 26C8<
32A5v
25A5<>
32A5v 25A5<
32C5v 26B4<
32C5v 26C5<
32C7v30C7v26B7<22A6<27C7>27C3>
30A7v
25C8<
30A5v 25C5<
30A5v 25C5<
30A5v
25C5<>
30A5v 25C5<
30C5v32C5v22C8<27B6> 27B3>26B3> 30C5v32C5v22C8<27B6>27B3>26B3>30C7v28A4<
30A7v25C8<
30A7v25C8<
30A7v25C8<
30A7v25C8<
30A7v25C8<
30A7v25C8<
30A7v25C8<
30A7v
25C5<>
30A5v 25C5<
30A5v 25C5<
20C3^
32C7v
30C5v
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
_mii_wan_dn
TXD0
TXD1
RX_CLK
RX_ERR
RX_CRS
RXD3
RXD2
RXD1
RXD0
RXDV
MII_CLK
MDC
MDIO
RESET_B
TX_EN
TX_CLK
LED_GDLINK_ADD2
LED_DPLX_ADD0
LED_COL_ADD1
TXD3
TXD2
COL_DET
LED_RX_ADD4
LED_TX_ADD3
_mii_wan_dn
TXD0
TXD1
RX_CLK
RX_ERR
RX_CRS
RXD3
RXD2
RXD1
RXD0
RXDV
MII_CLK
MDC
MDIO
RESET_B
TX_EN
TX_CLK
LED_GDLINK_ADD2
LED_DPLX_ADD0
LED_COL_ADD1
TXD3
TXD2
COL_DET
LED_RX_ADD4
LED_TX_ADD3
IN
V3_3
CHASSIS
V3_3
V3_3
HIERARCHICAL BLOCK
PAGES 36-37
HIERARCHICAL BLOCK
PAGES 34-35
LED_TX_A3<4>
TXD2<4>
TXD3<4>
LED_COL_A1<4>
LED_DPLX_A0<4>
LED_GDLINK_A2<4>
TX_CLK<4>
TX_EN<4>
MDIO
RXDV<4>
RXD0<4>
RXD1<4>
RXD2<4>
RXD3<4>
RX_CLK<4>
TXD1<4>
TXD0<4>
RXD3<3>
RXD2<3>
LED_TX_A3<3>
LED_RX_A4<3>
LED_COL_A1<3>
LED_DPLX_A0<3>
LED_GDLINK_A2<3>
TXD2<3>
TXD3<3>
TXD1<3>
TXD0<3>
RESET_B
MII_CLK<3>
RX_CRS<3>
RX_CLK<3>
RXD0<3>
RXD1<3>
330
5.1K
5.1K
330
330
5.1K
5.1K
5.1K
5.1K
330
330
5.1K
330
5.1K
5.1K
RED
AMBER
RED
AMBER
RESET_B
GREEN
LED_TX_A3<3>
LED_RX_A4<3> LED_RX_A4<4>
LED_TX_A3<4>
LED_GDLINK_A2<4>
LED_COL_A1<4>
LED_DPLX_A0<4>
RX_CRS<4>
RX_ERR<4>
COL_DET<4>
MII_CLK<4>
MDC
5.1K
GREEN
MDC
MDIO
LED_GDLINK_A2<3>
LED_DPLX_A0<3>
LED_COL_A1<3>
LED_RX_A4<4>
TX_EN<3>
TX_CLK<3>
R30
R29
RB73
R24
DS14
R20
RB59
RB53
R15
DS10
DS08
RB82
RB51
RB32
RB40
DS03
RB77
RB62
RB36
RB43
DS12
DS04
RX_ERR<3>
COL_DET<3>
RXDV<3>
27/71(TOTAL)
6/8(BLOCK)
DS33Z11/41/44DK01A0
09/16/2004
STEVE SCULLY
BLOCK
NAME:
_z44andlan_dn.
PARENT
BLOCK:
\_z44top_dn\
CR-27
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I8@\_ZTOP_LIB\.\_Z44TOP_DN\(SCH_1):PAGE1_I2@\_ZTOP_LIB\.\_Z44ANDLAN_DN\(SCH_1):PAGE6
1
2
1
2
1
2
1
2
1
2
1
2
34C5v
27A4<>
34A5v 25A1<
34A5v 25A1<
34C5v 27B4<
34C5v 27B4<
34C5v
27A4<>
34A5v
25A1<>
34A5v 25A1<
36C5v34C5v22C8<27B6> 26B6>26B3>
34A7v25A4<
34A7v25B4<
34A7v25B4<
34A7v25A4<
34A7v25A4<
34A7v
25A1<>
34A5v 25B1<
34A5v 25B1<
36A7v25C4<
36A7v25C4<
36C5v
27B8<
36C5v
27B8<
36A5v 25C1<
36A5v 25C1<
36A5v 25C1<
36A5v 25C1<
36C7v28A4<
36A7v25C4<
36A7v25C4<
36A7v
25C1<>
36A7v25C4<
36A7v25C4<
34C7v36C7v26B7<22A6<
20C3^
27C7>26B3>
36C5v 27C8<
36C5v 27C8< 34C5v 27C5<
34C5v 27C5<
34C5v 27C5<
34C5v 27C5<
34C5v 27C5<
34A7v25A4<
34A7v25A4<
34A7v25A4<
34C7v28A4< 36C5v34C5v22C8<27B6>26B6>26B3>
36C5v34C5v22C8<27B3> 26B6>26B3> 36C5v34C5v22C8<27B3>26B6>26B3>
36C5v 27C8<
36C5v 27C8<
36C5v 27C8<
34C5v
27A4<>
36A5v 25C1<
36A5v
25C1<>
36A7v25C4<
36A7v25C4<
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
_mii_wan_dn
TXD0
TXD1
RX_CLK
RX_ERR
RX_CRS
RXD3
RXD2
RXD1
RXD0
RXDV
MII_CLK
MDC
MDIO
RESET_B
TX_EN
TX_CLK
LED_GDLINK_ADD2
LED_DPLX_ADD0
LED_COL_ADD1
TXD3
TXD2
COL_DET
LED_RX_ADD4
LED_TX_ADD3
V3_3
V3_3
_mii_wan_dn
TXD0
TXD1
RX_CLK
RX_ERR
RX_CRS
RXD3
RXD2
RXD1
RXD0
RXDV
MII_CLK
MDC
MDIO
RESET_B
TX_EN
TX_CLK
LED_GDLINK_ADD2
LED_DPLX_ADD0
LED_COL_ADD1
TXD3
TXD2
COL_DET
LED_RX_ADD4
LED_TX_ADD3
SIGNAME_TRI DOES NOT
CONNECT ANYWHERE
(HELPS PCB NETLIST)
25.000MHZ_3.3V
MII_CLK<3>
2.0K
2.0K
2.0K
2.0K
2.0K
2.0K
2.0K
2.0K
30
3030
100.000MHZ_3.3V
MODEC0TRI
DCEDTESTRI
MODEC0
DCEDTES
HWMODETRI
MODEC1TRI
HWMODE
MODEC1
RMIIMIISTRI
SCANMODTRI
SCANENTRI
MII_CLK<1>
V3_3
SD_CLKI
OSC100MHZ
GND
BUFFER
CKPHATRI
CKPHA
RMIIMIIS
SCANMOD
SCANEN
30
30
30
30
REF_CLK
MII_CLK<2>
MII_CLK<4>
SW02
SW09
RB06
RB56
SW21
SW01
RB98
RB02
SW05
SW19
RB39
RB76
SW20
SW03
RB83
RB08
R25
R17
R100
RB61
R111
UXB03
R112
Y05
Y01
R116
7/8(BLOCK)
BLOCK
NAME:
_z44andlan_dn.
PARENT
BLOCK:
\_z44top_dn\
09/16/2004
28/71(TOTAL)
DS33Z11/41/44DK01A0
STEVE SCULLY
CR-28
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I8@\_ZTOP_LIB\.\_Z44TOP_DN\(SCH_1):PAGE1_I2@\_ZTOP_LIB\.\_Z44ANDLAN_DN\(SCH_1):PAGE7
2
4
1
3
2
1
2
1
2
4
1
3
2
4
1
3
2
1
2
1
2
4
1
3
2
4
1
3
2
1
2
1
4
1
1
8
4 5
1
8
4 5
2
4
1
3
2
4
1
3
2
1
2
1
2
4
1
3
27B6>
20C2^
22A6>
22A6<
20C2^
22A6>
20C2^
22A6>
26B6>
22B8<
22A5<
22A6<
22A5<
22A5<
22D8<>
26B2>
27B2>
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
SP3T
SP3T
SP3T
VCC
1
OSC
GND OUT
VCC
1
OSC
GND OUT
V3_3
V3_3
NC7SZ86_U
V3_3
V3_3
SP3T
SP3T
SP3T
SP3T
SP3T
V3_3
RED
RED
RED
AFCS<4>
QOVF<4>
QOVF<3>
QOVF<2>
QOVF<1>
H10S<4>
2.0K
V1_8ZCHIP
0.1UF
V1_8ZCHIP
H10STRI<4>
AFCSTRI<4>
FULLDSTRI<4>
FULLDS<4>
H10S<3>
AFCS<3>
H10STRI<3>
AFCSTRI<3>
FULLDSTRI<3>
H10S<2>
H10STRI<2>
AFCS<2>
AFCSTRI<2>
FULLDS<2>
FULLDSTRI<2>
H10S<1>
H10STRI<1>
AFCSTRI<1>
AFCS<1>
FULLDS<1>
FULLDSTRI<1>
1UF
1UF
1UF
1UF
10UF
1UF
1UF
1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
330
330
330
330
2.0K
2.0K
2.0K
2.0K
2.0K
2.0K
2.0K
2.0K
2.0K
2.0K
RED
FULLDS<3>
2.0K
SW30
RB341
RB338
SW31
SW29
RB340
SW35
RB348
SW34
RB347
SW33
RB346
SW38
RB353
SW37
SW36
RB351
RB352
RB363
SW40
SW41
RB362
RB361
SW39
DS45
DS46
RB344
RB350
DS47
RB354
DS48
RB360
CB368
CB380
CB261
CB366
CB231
CB367
CB248
CB228
CB254
CB15
TP67
TP68
TP73
TP76
CB279
CB411
CB439
CB241
CB358
CB185
C213
C214
CB176
2
1
C80
2
1
C51
2
1
CB133
2
1
U11
CB184
CB13
C64
1
2
CB468
2
1
8/8(BLOCK)
BLOCK
NAME:
_z44andlan_dn.
PARENT
BLOCK:
\_z44top_dn\
29/71(TOTAL)
09/16/2004
STEVE SCULLY
DS33Z11/41/44DK01A0
CR-29
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I8@\_ZTOP_LIB\.\_Z44TOP_DN\(SCH_1):PAGE1_I2@\_ZTOP_LIB\.\_Z44ANDLAN_DN\(SCH_1):PAGE8
2
4
1
3
2
1
2
4
1
3
2
1
2
4
1
3
2
1
2
4
1
3
2
4
1
3
2
4
1
3
2
4
1
3
2
1
2
4
1
3
2
4
1
3
2
1
2
1
2
1
2
4
1
3
1
2
1
2
2
1
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
4
1
3
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
4
1
3
2
1
2
1
3
4
2
8
5
6
7
1
2
1
1
2
1
2
25A1<
25A1>
25C1>
25A5>
25C5>
25A1<
23D4< 23B4<
29A4<>
29B6<23D4<23B4<
25A4<
25C1<
25C1<
25A5<
25A5<
25A8<
25C5<
25B5<
25C8<
25C4<
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
V3_3
MAX1792
IN
OUT
SET
GND
OUT
IN
SHDN
RST
V3_3
SP3T
SP3T
SP3T
SP3T
SP3T
V3_3
SP3T
SP3T
SP3T
SP3T
SP3T
SP3T
SP3T
V3_3
V3_3
0.2 BETWEEN CONNECTORS.
ALLOW USE OF A DIFFERENT PHY CARD IF DESIRED. PLACEMENT SHOULD ALLOW
ON Z44 CARD ALL 4 PORTS MUST BE PLACED WITH EQUAL SPACING AND A COMMON CENTER LINE
TESTPOINTS (SHOWN ABOVE) MUST BE PLACED THE SAME FOR EACH PORT TO
PLACEMENT NOTE:
LEDS NEED TO BE ATTACHED
OUTSIDE OF MODULE DUE TO
STRAP ADAPTING OPTION OF DP83847
COMPONETS FOR
C1 AND RBIAS MUST
BE PLACED CLOSE TO PIN
MII_CLK
RESET_B
LED_TX_ADD3
LED_COL_ADD1
LED_DPLX_ADD0
TXD0
TXD2
AN1
TXD1
MDC
10UF
5.1K
TX_CLK
TXD3
TX_EN
RXDV
RXD0
RXD1
RXD2
RXD3
10UF
10UF
10UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
LED_GDLINK_ADD2
30
LED_RX_ADD4
AN_V3_3
AN_V3_3
0.1UF
0.1UF
10UF
100O100MZH
RX_CLK
RX_ERR
COL_DET
RX_CRS
AN_EN
5.1K
AN0
5.1K
MDIO
0.1UF
10.0K
RBIAS
C1PIN
30/71(TOTAL)
BLOCK
NAME:
_mii_wan_dn.
PARENT
BLOCK:
\_z44andlan_dn\
PRINTED
Fri
Oct
20
11:06:58
2006
1/2(BLOCK)
09/16/2004
STEVE SCULLY
DS33Z11/41/44DK01A0
CR-30
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page5_i54@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page1
CR-30
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page5_i54@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page1
CR-30
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page5_i54@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page1
CR-30
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page5_i54@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page1
CR-30
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page5_i54@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page1
26C6^
1
3
2
JP12
1
3
2
JP07
1
3
2
JP01
RB09
RB30
RB37
R101
1
TP02
50
51
54
55
61
58
60
62
64
65
44
47
5
8
9
12
13
34
28
56
14
57
59
63
2
1
3
46
42
48
49
15
16
17
18
19
22
23
24
25
4
21
20
53
52
U02
R06
26C6^
26C7^
2
1
CB104
2
1
C41
31C8<
26D8^
31C8<
26D8^
31C8<
26D8^
31C8<
26D8^
31C4<
26D8^
31C8<
26C8^
65
4
9
7
3
10
8
1
2
J15
31C5<
26C6^
31B5<
26C6^
26C6^
31C6<>
31B8<
26D6^
31B8<
26D6^
31B8<
26D6^
31B8<
26D6^
65
4
9
7
3
10
8
1
2
J16
2
1
CB10
2
1
CB72
2
1
CB40
2
1
CB73
2
1
CB81
2
1
C25
1
2
L08
CB292
CB87
2
1
CB291
2
1
CB284
2
1
CB221
2
1
C18
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
IO
V3_3
V3_3
6
10
8
4
1
2
3
5
7
9
CONN_10P
V3_3
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
6
10
8
4
1
2
3
5
7
9
CONN_10P
IN
OUT
IN
IN
IN
V3_3
IN
IN
IN
CONTROL
DP83847_U1
RESERVED14
RESERVED15
LED_TX/PHYAD3
LED_GDLNK/PHYAD2
RESERVED3
MDC
MDIO
LED_DPLX/PHYAD0
LED_COL/PHYAD1
LED_RX/PHYAD4
LED_SPEED
AN_EN
AN_1
AN_0
X1
X2
C1
RESET*
RBIAS
RESERVED1
RESERVED2
VDD3
VDD2
VDD1
VDD/ANA_VDD
VDD/IO_VDD2
VDD/IO_VDD1
RESERVED9
RESERVED8
RESERVED7
RESERVED6
RESERVED5
RESERVED4
RESERVED11
RESERVED10
GND5
GND4
GND3
GND2
GND1
RESERVED18
RESERVED17
RESERVED16
RESERVED13
RESERVED12
V3_3
IO
IO
IO
IO
IO
IN
SHOULD BE PLACED CLOSE TO PHY
RESISTORS FOR TD+-/RD+-
SHOULD BE PLACED CLOSE TO XFRM
CAPS FOR XFRM CENTER TAP
DNP
RX_ERR
RD_P
BUFFER
BUFFER
.1UF
30
TD_P
SYM_1
.1UF
54.9
.1UF
54.9
49.9
RD_N
TD_N
10K
30
30
30
30
RXD1
RXD0
RXD2
RXD3
TXD2
RD_P
RD_N
TXD3
TX_EN
TXD0
TXD1
TD_N
TD_P
49.9
30
DNP
30
30
RX_CRS
RX_CLK
TX_CLK
RXDV
COL_DET
31/71(TOTAL)
2/2(BLOCK)
STEVE SCULLY
DS33Z11/41/44DK01A0
09/16/2004
BLOCK
NAME:
_mii_wan_dn.
PARENT
BLOCK:
\_z44andlan_dn\
CR-31
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page5_i54@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page2
CR-31
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page5_i54@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page2
CR-31
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page5_i54@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page2
CR-31
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page5_i54@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page2
CR-31
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page5_i54@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page2
2
RB139
RB125
RB112
RB100
9
2
8
6
3
4
10
1
5
J01
CB32
CB299
RB22
CB60
RB23
RB24
RB25
4
1
UX10
RB113
RB119
RB105
4
1
UX05
RB84
RB127
RB135
43
40
7
6
26
41
32
29
30
27
11
10
45
36
35
37
38
39
31
33
U02
R106
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
PORT
DP83847_U1
RX_ER/PAUSE_EN*
RX_DV
TXD<1>
TXD<0>
TX_EN
TX_ER
TX_CLK
CRS/LED_CFG*
TD+
TD-
RXD<2>
RXD<0>
RXD<1>
RX_CLK
TXD<3>
RXD<3>
RD-
RD+
TXD<2>
COL
CHASSIS
CHASSIS
CHASSIS
NC7SZ86_U
NC7SZ86_U
V3_3
CONN_HFJ11_2450_U
J1
J2
J3
J6
J4,5
J7,8
P5
P1
SH2
P4
P3
P6
P8
P2
SH1
0.2 BETWEEN CONNECTORS.
ALLOW USE OF A DIFFERENT PHY CARD IF DESIRED. PLACEMENT SHOULD ALLOW
ON Z44 CARD ALL 4 PORTS MUST BE PLACED WITH EQUAL SPACING AND A COMMON CENTER LINE
TESTPOINTS (SHOWN ABOVE) MUST BE PLACED THE SAME FOR EACH PORT TO
PLACEMENT NOTE:
LEDS NEED TO BE ATTACHED
OUTSIDE OF MODULE DUE TO
STRAP ADAPTING OPTION OF DP83847
COMPONETS FOR
C1 AND RBIAS MUST
BE PLACED CLOSE TO PIN
MII_CLK
RESET_B
LED_TX_ADD3
LED_COL_ADD1
LED_DPLX_ADD0
TXD0
TXD2
AN1
TXD1
MDC
10UF
5.1K
TX_CLK
TXD3
TX_EN
RXDV
RXD0
RXD1
RXD2
RXD3
10UF
10UF
10UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
LED_GDLINK_ADD2
30
LED_RX_ADD4
AN_V3_3
AN_V3_3
0.1UF
0.1UF
10UF
100O100MZH
RX_CLK
RX_ERR
COL_DET
RX_CRS
AN_EN
5.1K
AN0
5.1K
MDIO
0.1UF
10.0K
RBIAS
C1PIN
32/71(TOTAL)
BLOCK
NAME:
_mii_wan_dn.
PARENT
BLOCK:
\_z44andlan_dn\
PRINTED
Fri
Oct
20
11:06:59
2006
1/2(BLOCK)
09/16/2004
STEVE SCULLY
DS33Z11/41/44DK01A0
CR-32
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page5_i91@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page1
CR-32
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page5_i91@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page1
CR-32
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page5_i91@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page1
CR-32
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page5_i91@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page1
CR-32
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page5_i91@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page1
26C3^
1
3
2
JP11
1
3
2
JP06
1
3
2
JP03
RB16
RB31
RB38
R117
1
TP04
50
51
54
55
61
58
60
62
64
65
44
47
5
8
9
12
13
34
28
56
14
57
59
63
2
1
3
46
42
48
49
15
16
17
18
19
22
23
24
25
4
21
20
53
52
U05
R05
26C3^
26C3^
2
1
CB103
2
1
C37
33C8<
26D4^
33C8<
26D4^
33C8<
26D4^
33C8<
26D4^
33C4<
26D4^
33C8<
26C4^
65
4
9
7
3
10
8
1
2
J19
33C5<
26C2^
33B5<
26C2^
26C2^
33C6<>
33B8<
26D2^
33B8<
26D2^
33B8<
26D2^
33B8<
26D2^
65
4
9
7
3
10
8
1
2
J20
2
1
CB496
2
1
CB473
2
1
CB476
2
1
CB57
2
1
CB46
2
1
C13
1
2
L06
CB174
CB125
2
1
CB88
2
1
CB91
2
1
CB209
2
1
C209
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
IO
V3_3
V3_3
6
10
8
4
1
2
3
5
7
9
CONN_10P
V3_3
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
6
10
8
4
1
2
3
5
7
9
CONN_10P
IN
OUT
IN
IN
IN
V3_3
IN
IN
IN
CONTROL
DP83847_U1
RESERVED14
RESERVED15
LED_TX/PHYAD3
LED_GDLNK/PHYAD2
RESERVED3
MDC
MDIO
LED_DPLX/PHYAD0
LED_COL/PHYAD1
LED_RX/PHYAD4
LED_SPEED
AN_EN
AN_1
AN_0
X1
X2
C1
RESET*
RBIAS
RESERVED1
RESERVED2
VDD3
VDD2
VDD1
VDD/ANA_VDD
VDD/IO_VDD2
VDD/IO_VDD1
RESERVED9
RESERVED8
RESERVED7
RESERVED6
RESERVED5
RESERVED4
RESERVED11
RESERVED10
GND5
GND4
GND3
GND2
GND1
RESERVED18
RESERVED17
RESERVED16
RESERVED13
RESERVED12
V3_3
IO
IO
IO
IO
IO
IN
SHOULD BE PLACED CLOSE TO PHY
RESISTORS FOR TD+-/RD+-
SHOULD BE PLACED CLOSE TO XFRM
CAPS FOR XFRM CENTER TAP
DNP
RX_ERR
RD_P
BUFFER
BUFFER
.1UF
30
TD_P
SYM_1
.1UF
54.9
.1UF
54.9
49.9
RD_N
TD_N
10K
30
30
30
30
RXD1
RXD0
RXD2
RXD3
TXD2
RD_P
RD_N
TXD3
TX_EN
TXD0
TXD1
TD_N
TD_P
49.9
30
DNP
30
30
RX_CRS
RX_CLK
TX_CLK
RXDV
COL_DET
33/71(TOTAL)
2/2(BLOCK)
STEVE SCULLY
DS33Z11/41/44DK01A0
09/16/2004
BLOCK
NAME:
_mii_wan_dn.
PARENT
BLOCK:
\_z44andlan_dn\
CR-33
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page5_i91@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page2
CR-33
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page5_i91@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page2
CR-33
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page5_i91@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page2
CR-33
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page5_i91@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page2
CR-33
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page5_i91@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page2
2
RB132
RB116
RB108
RB97
9
2
8
6
3
4
10
1
5
J05
CB25
CB282
RB26
C05
RB27
RB28
RB29
4
1
UX02
RB122
R28
RB103
4
1
UX07
RB85
RB131
R21
43
40
7
6
26
41
32
29
30
27
11
10
45
36
35
37
38
39
31
33
U05
R27
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
PORT
DP83847_U1
RX_ER/PAUSE_EN*
RX_DV
TXD<1>
TXD<0>
TX_EN
TX_ER
TX_CLK
CRS/LED_CFG*
TD+
TD-
RXD<2>
RXD<0>
RXD<1>
RX_CLK
TXD<3>
RXD<3>
RD-
RD+
TXD<2>
COL
CHASSIS
CHASSIS
CHASSIS
NC7SZ86_U
NC7SZ86_U
V3_3
CONN_HFJ11_2450_U
J1
J2
J3
J6
J4,5
J7,8
P5
P1
SH2
P4
P3
P6
P8
P2
SH1
0.2 BETWEEN CONNECTORS.
ALLOW USE OF A DIFFERENT PHY CARD IF DESIRED. PLACEMENT SHOULD ALLOW
ON Z44 CARD ALL 4 PORTS MUST BE PLACED WITH EQUAL SPACING AND A COMMON CENTER LINE
TESTPOINTS (SHOWN ABOVE) MUST BE PLACED THE SAME FOR EACH PORT TO
PLACEMENT NOTE:
LEDS NEED TO BE ATTACHED
OUTSIDE OF MODULE DUE TO
STRAP ADAPTING OPTION OF DP83847
COMPONETS FOR
C1 AND RBIAS MUST
BE PLACED CLOSE TO PIN
PRINTED
Fri
Oct
20
11:07:00
2006
MII_CLK
RESET_B
LED_TX_ADD3
LED_COL_ADD1
LED_DPLX_ADD0
TXD0
TXD2
AN1
TXD1
MDC
10UF
5.1K
TX_CLK
TXD3
TX_EN
RXDV
RXD0
RXD1
RXD2
RXD3
10UF
10UF
10UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
LED_GDLINK_ADD2
30
LED_RX_ADD4
AN_V3_3
AN_V3_3
0.1UF
0.1UF
10UF
100O100MZH
RX_CLK
RX_ERR
COL_DET
RX_CRS
AN_EN
5.1K
AN0
5.1K
MDIO
0.1UF
10.0K
RBIAS
C1PIN
34/71(TOTAL)
BLOCK
NAME:
_mii_wan_dn.
PARENT
BLOCK:
\_z44andlan_dn\
1/2(BLOCK)
09/16/2004
STEVE SCULLY
DS33Z11/41/44DK01A0
CR-34
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page6_i1@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page1
CR-34
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page6_i1@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page1
CR-34
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page6_i1@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page1
CR-34
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page6_i1@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page1
CR-34
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page6_i1@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page1
27C3^
1
3
2
JP13
1
3
2
JP08
1
3
2
JP04
RB17
RB35
RB41
R102
1
TP01
50
51
54
55
61
58
60
62
64
65
44
47
5
8
9
12
13
34
28
56
14
57
59
63
2
1
3
46
42
48
49
15
16
17
18
19
22
23
24
25
4
21
20
53
52
U06
R09
27C3^
27C3^
2
1
CB101
2
1
C35
35C8<
27D4^
35C8<
27D4^
35C8<
27D4^
35C8<
27D4^
35C4<
27D4^
35C8<
27C4^
65
4
9
7
3
10
8
1
2
J21
35C5<
27C2^
35B5<
27C2^
27C2^
35C6<>
35B8<
27D2^
35B8<
27D2^
35B8<
27D2^
35B8<
27D2^
65
4
9
7
3
10
8
1
2
J22
2
1
CB128
2
1
CB196
2
1
CB283
2
1
CB51
2
1
CB38
2
1
C11
1
2
L05
CB357
CB64
2
1
CB74
2
1
CB71
2
1
CB167
2
1
CB474
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
IO
V3_3
V3_3
6
10
8
4
1
2
3
5
7
9
CONN_10P
V3_3
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
6
10
8
4
1
2
3
5
7
9
CONN_10P
IN
OUT
IN
IN
IN
V3_3
IN
IN
IN
CONTROL
DP83847_U1
RESERVED14
RESERVED15
LED_TX/PHYAD3
LED_GDLNK/PHYAD2
RESERVED3
MDC
MDIO
LED_DPLX/PHYAD0
LED_COL/PHYAD1
LED_RX/PHYAD4
LED_SPEED
AN_EN
AN_1
AN_0
X1
X2
C1
RESET*
RBIAS
RESERVED1
RESERVED2
VDD3
VDD2
VDD1
VDD/ANA_VDD
VDD/IO_VDD2
VDD/IO_VDD1
RESERVED9
RESERVED8
RESERVED7
RESERVED6
RESERVED5
RESERVED4
RESERVED11
RESERVED10
GND5
GND4
GND3
GND2
GND1
RESERVED18
RESERVED17
RESERVED16
RESERVED13
RESERVED12
V3_3
IO
IO
IO
IO
IO
IN
SHOULD BE PLACED CLOSE TO PHY
RESISTORS FOR TD+-/RD+-
SHOULD BE PLACED CLOSE TO XFRM
CAPS FOR XFRM CENTER TAP
DNP
RX_ERR
RD_P
BUFFER
BUFFER
.1UF
30
TD_P
SYM_1
.1UF
54.9
.1UF
54.9
49.9
RD_N
TD_N
10K
30
30
30
30
RXD1
RXD0
RXD2
RXD3
TXD2
RD_P
RD_N
TXD3
TX_EN
TXD0
TXD1
TD_N
TD_P
49.9
30
DNP
30
30
RX_CRS
RX_CLK
TX_CLK
RXDV
COL_DET
35/71(TOTAL)
2/2(BLOCK)
STEVE SCULLY
DS33Z11/41/44DK01A0
09/16/2004
BLOCK
NAME:
_mii_wan_dn.
PARENT
BLOCK:
\_z44andlan_dn\
CR-35
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page6_i1@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page2
CR-35
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page6_i1@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page2
CR-35
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page6_i1@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page2
CR-35
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page6_i1@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page2
CR-35
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page6_i1@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page2
2
RB140
RB137
R125
RB128
9
2
8
6
3
4
10
1
5
J03
CB29
C106
RB19
CB34
RB18
RB20
RB21
4
1
UX09
RB120
RB115
RB104
4
1
UX08
RB86
RB123
RB133
43
40
7
6
26
41
32
29
30
27
11
10
45
36
35
37
38
39
31
33
U06
RB138
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
PORT
DP83847_U1
RX_ER/PAUSE_EN*
RX_DV
TXD<1>
TXD<0>
TX_EN
TX_ER
TX_CLK
CRS/LED_CFG*
TD+
TD-
RXD<2>
RXD<0>
RXD<1>
RX_CLK
TXD<3>
RXD<3>
RD-
RD+
TXD<2>
COL
CHASSIS
CHASSIS
CHASSIS
NC7SZ86_U
NC7SZ86_U
V3_3
CONN_HFJ11_2450_U
J1
J2
J3
J6
J4,5
J7,8
P5
P1
SH2
P4
P3
P6
P8
P2
SH1
0.2 BETWEEN CONNECTORS.
ALLOW USE OF A DIFFERENT PHY CARD IF DESIRED. PLACEMENT SHOULD ALLOW
ON Z44 CARD ALL 4 PORTS MUST BE PLACED WITH EQUAL SPACING AND A COMMON CENTER LINE
TESTPOINTS (SHOWN ABOVE) MUST BE PLACED THE SAME FOR EACH PORT TO
PLACEMENT NOTE:
LEDS NEED TO BE ATTACHED
OUTSIDE OF MODULE DUE TO
STRAP ADAPTING OPTION OF DP83847
COMPONETS FOR
C1 AND RBIAS MUST
BE PLACED CLOSE TO PIN
MII_CLK
RESET_B
LED_TX_ADD3
LED_COL_ADD1
LED_DPLX_ADD0
TXD0
TXD2
AN1
TXD1
MDC
10UF
5.1K
TX_CLK
TXD3
TX_EN
RXDV
RXD0
RXD1
RXD2
RXD3
10UF
10UF
10UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
LED_GDLINK_ADD2
30
LED_RX_ADD4
AN_V3_3
AN_V3_3
0.1UF
0.1UF
10UF
100O100MZH
RX_CLK
RX_ERR
COL_DET
RX_CRS
AN_EN
5.1K
AN0
5.1K
MDIO
0.1UF
10.0K
RBIAS
C1PIN
36/71(TOTAL)
BLOCK
NAME:
_mii_wan_dn.
PARENT
BLOCK:
\_z44andlan_dn\
PRINTED
Fri
Oct
20
11:07:00
2006
1/2(BLOCK)
09/16/2004
STEVE SCULLY
DS33Z11/41/44DK01A0
CR-36
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page6_i34@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page1
CR-36
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page6_i34@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page1
CR-36
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page6_i34@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page1
CR-36
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page6_i34@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page1
CR-36
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page6_i34@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page1
27C6^
1
3
2
JP10
1
3
2
JP05
1
3
2
JP02
RB50
RB03
RB01
R26
1
TP05
50
51
54
55
61
58
60
62
64
65
44
47
5
8
9
12
13
34
28
56
14
57
59
63
2
1
3
46
42
48
49
15
16
17
18
19
22
23
24
25
4
21
20
53
52
U03
R11
27C6^
27C7^
2
1
C28
2
1
C34
37C8<
27D8^
37C8<
27D8^
37C8<
27D8^
37C8<
27D8^
37C4<
27D8^
37C8<
27C8^
65
4
9
7
3
10
8
1
2
J17
37C5<
27C6^
37B5<
27C6^
27C6^
37C6<>
37B8<
27D6^
37B8<
27D6^
37B8<
27D6^
37B8<
27D6^
65
4
9
7
3
10
8
1
2
J18
2
1
CB164
2
1
C29
2
1
CB76
2
1
CB77
2
1
CB83
2
1
C31
1
2
L07
CB20
CB470
2
1
C17
2
1
CB326
2
1
CB325
2
1
C24
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
IO
V3_3
V3_3
6
10
8
4
1
2
3
5
7
9
CONN_10P
V3_3
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
6
10
8
4
1
2
3
5
7
9
CONN_10P
IN
OUT
IN
IN
IN
V3_3
IN
IN
IN
CONTROL
DP83847_U1
RESERVED14
RESERVED15
LED_TX/PHYAD3
LED_GDLNK/PHYAD2
RESERVED3
MDC
MDIO
LED_DPLX/PHYAD0
LED_COL/PHYAD1
LED_RX/PHYAD4
LED_SPEED
AN_EN
AN_1
AN_0
X1
X2
C1
RESET*
RBIAS
RESERVED1
RESERVED2
VDD3
VDD2
VDD1
VDD/ANA_VDD
VDD/IO_VDD2
VDD/IO_VDD1
RESERVED9
RESERVED8
RESERVED7
RESERVED6
RESERVED5
RESERVED4
RESERVED11
RESERVED10
GND5
GND4
GND3
GND2
GND1
RESERVED18
RESERVED17
RESERVED16
RESERVED13
RESERVED12
V3_3
IO
IO
IO
IO
IO
IN
SHOULD BE PLACED CLOSE TO PHY
RESISTORS FOR TD+-/RD+-
SHOULD BE PLACED CLOSE TO XFRM
CAPS FOR XFRM CENTER TAP
DNP
RX_ERR
RD_P
BUFFER
BUFFER
.1UF
30
TD_P
SYM_1
.1UF
54.9
.1UF
54.9
49.9
RD_N
TD_N
10K
30
30
30
30
RXD1
RXD0
RXD2
RXD3
TXD2
RD_P
RD_N
TXD3
TX_EN
TXD0
TXD1
TD_N
TD_P
49.9
30
DNP
30
30
RX_CRS
RX_CLK
TX_CLK
RXDV
COL_DET
37/71(TOTAL)
2/2(BLOCK)
STEVE SCULLY
DS33Z11/41/44DK01A0
09/16/2004
BLOCK
NAME:
_mii_wan_dn.
PARENT
BLOCK:
\_z44andlan_dn\
CR-37
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page6_i34@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page2
CR-37
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page6_i34@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page2
CR-37
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page6_i34@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page2
CR-37
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page6_i34@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page2
CR-37
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page1_i2@\_ztop_lib\.\_z44andlan_dn\(sch_1):page6_i34@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page2
2
RB141
RB114
RB107
RB96
9
2
8
6
3
4
10
1
5
J02
C09
C112
RB10
CB33
RB11
RB12
RB13
4
1
UX01
RB111
RB117
RB99
4
1
UX06
RB81
RB124
RB136
43
40
7
6
26
41
32
29
30
27
11
10
45
36
35
37
38
39
31
33
U03
RB130
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
PORT
DP83847_U1
RX_ER/PAUSE_EN*
RX_DV
TXD<1>
TXD<0>
TX_EN
TX_ER
TX_CLK
CRS/LED_CFG*
TD+
TD-
RXD<2>
RXD<0>
RXD<1>
RX_CLK
TXD<3>
RXD<3>
RD-
RD+
TXD<2>
COL
CHASSIS
CHASSIS
CHASSIS
NC7SZ86_U
NC7SZ86_U
V3_3
CONN_HFJ11_2450_U
J1
J2
J3
J6
J4,5
J7,8
P5
P1
SH2
P4
P3
P6
P8
P2
SH1
PROCESSOR RESOURCE CARD
MMC2107
PRINTED
Fri
Oct
20
11:07:01
2006
I64
1
2
1
2
14
15
22
1
PD<31..0>
2
PA<22..0>
VDDSYN
GND
14
15
16
I68
11
12
13
16
18
17
19
18
20
21
10
17
9
8
7
6
23
24
25
26
28
19
27
29
30
31
5
4
3
2
0
20
0.0
.1UF
0
1
4
21
3
5
6
7
9
8
10
11
12
13
22
SOT143
2.93V
MAX811SEUS-T
I70
RESET_B
I51
RW
FLASH_VPP
TEA
VRH
OE
RCON
TA
MMC2107
NA
TQFP
I69
MMC2107
NA
TQFP
INT3
USER_LED2
RUN_KIT_USR
INT4
XTAL
MISO
MOSI
YCO
INT2
ONCE_TMS
CS0
RESET_B
CPUCLK_OUT
PROC_RESET_OUT
SCK
ONCE_DE_B
CS2
CS1
CSE0
TC2
TIM_16H_8L
CSE1
2107_TDO
ONCE_TDI
TC1
CS3
SS
ONCE_TRST_B
ONCE_TCLK
OSC_MCU
TIM_STATUS
TEST
USER_LED1
SCI1_IN
SCI1_OUT
SCI2_IN
SCI2_OUT
ICOC10
ICOC11
ICOC12
ICOC13
ICOC20
ICOC21
ICOC22
ICOC23
EB3
EB2
EB1
EB0
PQB3
PQB2
PQB1
PQB0
PQA4
PQA3
PQA1
PQA0
DS33Z11/41/44DK01A0
1/7(BLOCK)
09/16/2004
STEVE SCULLY
BLOCK
NAME:
_motprocrescard_dn.
PARENT
BLOCK:
\_z44top_dn\
38/71(TOTAL)
CR-38
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page2_i1@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page1
CR-38
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page2_i1@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page1
C87
RB159
45
9
19
17
20
21
22
25
27
30
31
34
35
16
15
12
10
7
5
4
3
2
1
36
37
38
39
40
41
42
43
46
48
51
114
73
126
140
127
76
64
44
32
18
8
50
49
47
29
28
26
24
23
13
11
6
139
137
136
134
132
131
122
121
119
117
116
144
14
112
59
65
33
123
141
129
77
87
115
74
103
102
92
113
95
97
99
U19
4
3
1
2
SW07
69
68
82
84
75
79
124
91
90
80
71
138
86
118
128
120
93
143
83
85
62
67
98
100
101
104
105
106
88
96
60
135
133
78
81
110
111
109
108
107
94
142
130
125
53
52
55
54
58
57
56
72
63
61
66
89
70
U19
3
1
4
2
UB01
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
MAX811_U
RESET*
VCC
GND
MR*
MMC2107
CONTROL
RXD1
INT7*
TXD2
ICOC10
TEST
INT1*
ICOC13
ICOC12
ICOC11
ICOC21
ICOC20
ICOC23
ICOC22
EXTAL
TCLK
TRST*
SS*
PQB0
PQA4
PQA3
PQA0
PQA1
CS3*
TC1
TDI
TDO
CSE1
EB3*
INT6*
PQB1
PQB2
PQB3
EB0*
EB1*
EB2*
TC2
CSE0
CS1*
CS2*
DE*
SCK
RSTOUT*
CLKOUT
RESET*
CS0*
TMS
INT0*
YC0
MOSI
MISO
XTAL
INT3*
INT2*
INT5*
INT4
RXD2
TXD1
MMC2107
PORT
TA*
SHS*
OE*
VRH
VSTBY
TEA*
VDDH
VDDF
VDDA
VPP
VDD6
VDD7
VDD8
VDDSYN
VDD3
VDD5
RW
VRL
A8
D31
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A7
A6
A5
A4
A3
A2
A1
A0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSSSYN
VSSF
VSSA
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
VDD2
VDD1
VDD4
V3_3
FLASH ENABLE
INTERNAL
XTAL W/ PLL
MASTER MODE
FULL DRIVE
RESET CONFIGURATION
BOOT
INTERN/EXTERN
BOOT EXT
BOOT INTERNAL
WHEN SET FOR
D18 HAS A 10.5K LOAD TO V3V
RESET AND CHIP CONFIGURATION
D18 HAS A 10K LOAD TO GND
2
1
2
1
2
1
1
2
1
2
2
1
1
2
1
2
1
2
1
2
1
2
2
1
2
1
INT5
INT4
INT3
30
PA<17..1>PA<17..1>
PD<23..16>
PD<31..24>
PD<18>
PD<19>
PD<28>
PD<22>
USERFPGA2
PD<23>
PD<21>
BIS0OBSXI
RCON
BIS1OBSXI
PD<16>
BTS_OBSXI
PD<17>
FLASH_VPP
PD<26>
16
10K
10K
10K
10K
10K
10K
10K
17
10K
1.0K
10K
1.0K
1.0K
1.0K
1.0K
18
I69
ECJ-2VB1C104K
.1UF
0L_SMT0805_10PCT
AMBER
I65
1.0K
1.0K
1.0K
20
9
10
11
12
8
7
6
5
19
13
14
16
15
17
4
3
2
1
24
21
25
26
27
28
29
30
31
10K
22
9
10
11
12
13
14
16
17
23
8
7
6
5
4
3
2
1
15
I18
OE
EB1
CS0
NA
CY62128V
CY62128V
I54
OE
EB0
CS0
NA
CY62128V
CY62128V
BLOCK
NAME:
_motprocrescard_dn.
PARENT
BLOCK:
\_z44top_dn\
39/71(TOTAL)
2/7(BLOCK)
DS33Z11/41/44DK01A0
STEVE SCULLY
09/16/2004
CR-39
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page2_i1@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page2
CR-39
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page2_i1@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page2
19
18
14
21
15
20
17
13
31
27
28
10
26
11
25
12
9
32
16
24
29
1
23
2
3
4
5
6
7
8
30
22
U14
RB237
19
21
18
15
17
14
20
13
31
27
28
4
26
3
25
2
5
32
16
24
29
1
23
12
11
10
9
8
7
6
30
22
UB05
RB126
RB143
R251
1
2
DS17
RB118
CB149
2
7
8
16
15
12
11
10
9
6
5
4
3
14
13
1
SW22
RB147
RB150
2
1
R244
2
1
R250
R93
2
1
RB157
R153
RB300
2
1
RB238
RB301
RB263
2
1
R92
R127
2
1
RB264
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
V5_0
SWITCH
8 POS
V3_3
V3_3
V3_3
CY62128V
CE1*
CE2
A7
A6
A5
A4
A3
A2
A1
A0
N_C
WE*
OE*
GND
VCC
A16
A15
A14
A13
A12
A11
A10
A9
A8 IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
V3_3
CY62128V
CE1*
CE2
A7
A6
A5
A4
A3
A2
A1
A0
N_C
WE*
OE*
GND
VCC
A16
A15
A14
A13
A12
A11
A10
A9
A8 IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
V3_3
JTAG CONFIGURATION
ALIGN KEY
PIN
ONCETDI
MMC2107
ONCETDO
PIN
TDI
...FPGA+FLASH...
BUT DO NOT POPULATE
PLACE PADS FOR CAP
10UF
5.6
1UF
1UF
1UF
1UF
.1UF
8.0MHZ
I47
1.0M
1UF
10K
10K
I35
10K
10K
10K
1UF
10UF
1UF
10K
1UF
1UF
1UF
I13
I11
XTAL
ONCE_TCLK
VDDSYN
PRT1_OUT
PRT1_IN
68UF
1UF
330
22.0UH
SMT1206_5PCT
ERJ-8GEYJ5R6V
68UF
1
2
2
1
2
1
2
1
2
1
2
1
OSC_MCU
I1
RESET_B
2107_TDO
ONCE_TDI
ONCE_TMS
ONCE_DE_B
ONCE_TRST_B
NA
CON14P
CON14P
I31
PRT1_IN
SCI1_OUT
SCI1_IN
PRT1_OUT
NA
MAX3233E
MAX3233E
40/71(TOTAL)
BLOCK
NAME:
_motprocrescard_dn.
PARENT
BLOCK:
\_z44top_dn\
DS33Z11/41/44DK01A0
STEVE SCULLY
09/16/2004
3/7(BLOCK)
CR-40
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page2_i1@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page3
CR-40
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page2_i1@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page3
13
9
7
5
11
3
1
10
12
8
6
4
14
2
J41
2
1
C104
3
4
2
1
8
5
6
7
U09
2
1
C36
1
2
L09
1
2
CB262
2
1
CB35
1
2
C84
2
1
C83
2
1
R78
R91
1
2
C39
1
2
C91
1
2
C118
CB114
1
2
C47
1
2
C43
2
1
RB200
20
1
8
4
5
6
7
9
10
11
12
13
14
15
16
17
18
19
3
2
UB07
RB286
RB287
9
5
4
2
1
3
6
7
8
J36
R118
2
1
R108
2
1
CB199
R90
1
2
X02
R107
1
2
CB148
1
2
CB484
1
2
CB466
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
V3_3
V3_3
CONN_DB9P
H
G
F
C
A
B
D
E
J
V3_3
MAX3233E
INVALID*
T2IN
T2OUT
GND
V-
C2-
C2+
C1-
C1+
V+2
V+1
FORCEOFF*
VCC
T1OUT
R1OUT
FORCEON
T1IN
R1IN
R2OUT R2IN
V3_3
V5_0
MAX1675
LX
GND
SHDN
OUT FB
LBI
REF
LBO*
CON14P
RED
RED
RED
1
2
1
2
1
2
8
7
6
31
30
29
28
27
26
25
16
24
23
22
21
20
5
4
3
2
1
15
0
16
17
18
19
RED
14
RED
RED
330
330
330
330
GREEN
5
13
4
3
2
1
5
4
3
2
1
12
11
10
9
OE
RW
TA
CS1
CS2
EB0
EB1
CS0
TEA
SCI2_IN
SCI2_OUT
SPARE_B<5..0>
USER_LED1
TIM_INTERUPT
PROC_RESET_OUT
CFG_DIN
PA<16..0>
X_INIT
PD<31..16>
USER_LED2
TIM_INTERUPT_IND
BLOCK
NAME:
_motprocrescard_dn.
PARENT
BLOCK:
\_z44top_dn\
41/71(TOTAL)
09/16/2004
4/7(BLOCK)
STEVE SCULLY
DS33Z11/41/44DK01A0
CR-41
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page2_i1@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page4
CR-41
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page2_i1@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page4
L12
M13
B6
B4
G13
E14
A9
D12
B10
E13
A3
G15
B11
A5
A4
A6
B3
C9
F14
A7
B5
A8
E7
H14
J13
E6
F12
E10
D5
L16
C5
K13
L15
H16
H15
G16
H13
R16
F15
E16
P16
L13
F13
D7
D14
C15
A10
A11
C12
F16
E15
A13
C16
D16
B12
C8
D9
N15
N14
C6
L14
C7
C10
N16
M16
K14
K16
J16
K15
J15
M14
M15
E11
A12
B16
D11
G14
D10
T15
G12
B8
B7
K12
J14
A14
C11
D6
C13
B13
B9
D8
U16
1
2
DS27
1
2
DS37
1
2
DS40
RB193
2
1
R194
R195
RB146
1
2
DS19
65
4
9
7
3
10
8
1
2
J25
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
6
10
8
4
1
2
3
5
7
9
CONN_10P
V3_3
XC2S50_BGA
BANK 2
BANK 0
BANK 3
BANK 1
IO10_1
IO9_1\VREF
IO1_1\CS*
IO2_1\WRITE*
IO3_1
IO4_1\VREF
IO5_1
IO4_0
IO3_0
IO2_0\VREF
GCK3
IO15_3
IO14_3
IO23_3
IO22_3
IO21_3
IO20_3
IO19_3
IO18_3
IO17_3
IO16_3
IO13_3\TRDY
IO12_3
IO11_3\D4
IO10_3\VREF
IO9_3
IO8_3\D5
IO7_3\D6
IO6_3
IO5_3
IO4_3\VREF
IO3_3
IO2_3\D7
IO1_3\INIT*
IO24_2
IO23_2
IO22_2
IO21_2
IO20_2
IO19_2
IO18_2
IO17_2
IO16_2
IO15_2
IO14_2
IO13_2\(DOUT,BUSY)
IO12_2\(DIN,D0)
IO11_2
IO10_2\VREF
IO9_2
IO8_2
IO7_2\D1
IO6_2\D2
IO5_2
IO4_2
IO3_2\D3
IO2_2\VREF
IO2_1\IRDY
IO22_1
IO21_1
IO20_1
IO19_1
IO18_1
IO17_1
IO16_1
IO15_1
IO14_1
IO13_1
IO12_1
IO11_1
IO8_1
IO7_1
IO6_1
GCK2
IO20_0
IO19_0
IO18_0
IO17_0
IO16_0
IO15_0
IO14_0
IO13_0
IO12_0
IO11_0
IO10_0
IO9_0
IO8_0
IO7_0\VREF
IO6_0
IO5_0
IO1_0
RW ALSO FUNCTIONS AS ALT_RD_DS
WE ALSO FUNCTIONS AS ALT_WR_RW
BUS MODE
DETECTION (DUT AT CS_X2)
D_DUT<7..0>
A_DUT<11..0>
5
0
CS_X2
BTS_DUT
WR_DUT
ALE_DUT
RD_DUT
CS_X3
CS_X4
CS_X5
CS_X6
ALE
CPUCLK_OUT
I46
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
SPARE_A<10..1>
6
8
9
5
4
7
3
2
1
10
10
5
9
8
7
6
I34
CONN_THRU-HOLE
NA
NA
4
3
2
1
XD<7..0>XD<7..0>
0
1
2
3
4
6
7
8
9
10
XA<11..0>
0
1
2
3
4
5
6
7
8
9
10
11
11
USERFPGA2
INT5
CS_X1
RW_X
WR
BIS0_DUT
BIS1_DUT
DS33Z11/41/44DK01A0
STEVE SCULLY
09/16/2004
5/7(BLOCK)
BLOCK
NAME:
_motprocrescard_dn.
PARENT
BLOCK:
\_z44top_dn\
42/71(TOTAL)
CR-42
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page2_i1@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page5
CR-42
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page2_i1@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page5
65
4
9
7
3
10
8
1
2
J26
N8
T10
R6
T7
R5
M2
T12
T6
M1
T5
N2
P1
T3
T2
R10
T13
N12
B1
N10
L2
T4
T11
P12
F2
P13
P8
N11
R13
N5
M6
P11
F1
N9
C2
L3
R7
G5
G4
H2
K3
P7
T8
T9
P10
C1
R11
D1
E1
K4
G3
H3
M10
G1
A2
E3
D2
F3
E2
J4
R12
K5
L5
M7
N7
R8
E4
H4
P9
F5
F4
G2
L4
N6
L1
R1
N1
P5
M3
K1
M11
P6
J1
H1
J2
T14
R9
J3
M4
K2
U16
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
BANK 5
BANK 7
XC2S50_BGA
BANK 6
BANK 4
IO11_7
IO19_5
IO4_6\VREF
IO2_4
IO5_5
IO1_6\TRDY
IO2_6
IO3_6
IO5_6
IO6_6
IO7_6
IO8_6
IO9_6
IO10_6\VREF
IO11_6
IO12_6
IO13_6
IO14_6
IO15_6
IO16_6
IO17_6
IO3_4\VREF
IO1_4
IO1_5
GCK1
IO23_7
IO22_7
IO21_7
IO20_7
IO19_7
IO18_7
IO17_7
IO16_7
IO15_7
IO14_7
IO13_7
IO12_7\IRDY
IO10_7
IO9_7\VREF
IO8_7
IO7_7
IO6_7
IO5_7
IO4_7
IO3_7\VREF
IO2_7
IO1_7
IO23_6
IO22_6
IO21_6
IO20_6
IO19_6
IO18_6
IO18_5
IO17_5
IO16_5
IO15_5
IO14_5
IO13_5
IO12_5
IO11_5
IO10_5
IO9_5
IO8_5\VREF
IO7_5
IO6_5
IO4_5
IO3_5
IO2_5\VREF
IO22_4
IO21_4
IO20_4
IO19_4
IO18_4
IO17_4
IO16_4
IO15_4
IO14_4
IO13_4
IO12_4
IO11_4
IO10_4
IO9_4\VREF
IO8_4
IO7_4
IO6_4
IO5_4
IO4_4
GCK0
6
10
8
4
1
2
3
5
7
9
CONN_10P
MBVER
CS_X1
CS_X6
RD_DUT
WR_DUT
CS_X2
CS_X3
ALE_DUT
CS_X5
CS_X4
SS
SCK
MISO
MOSI
RESET_B
D_DUT<7..0>
0
1
2
3
7
6
5
4
2
1
0
10K
10K
10K
10K
7
6
5
4
A_DUT<11..0>
11
10
9
8
A_DUT<11..0>
INT4
INT2
INT3
INT5
INT4
INT5
INT3
INT2
TDO_NU
RESET_B
BIS0_DUT
BTS_DUT
BIS1_DUT
TCK_NU
TMS_NU
TDI_NU
RW_X
WR_DUT
RD_DUT
XA<15..0>
A_DUT<11..0>
D_DUT<7..0>
XD<7..0>
CS_X3
CS_X2
CS_X1
CS_X5
CS_X4
WR
3
6/7(BLOCK)
DS33Z11/41/44DK01A0
STEVE SCULLY
09/16/2004
BLOCK
NAME:
_motprocrescard_dn.
PARENT
BLOCK:
\_z44top_dn\
43/71(TOTAL)
CR-43
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page2_i1@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page6
CR-43
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page2_i1@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page6
21B7^
42C3<>
21B6^
44A6<>
21B6^
44A6<>
21B6^
44A6<>
21B5^
42B3<>
21B5^
43A6<>42C3<>
21B7^
43A6<>42C3<>
42B7
21B5^
43C643B742A6
21B7^
45
39
41
43
47
1
3
5
23
21
17
11
9
7
27
25
29
37
35
33
31
15
13
24
22
50
12
14
26
28
30
32
40
46
48
42
34
6
4
10
8
2
36
38
49
44
20
18
16
19
J27
2
1
R249
2
1
R246
2
1
R245
2
1
R247
21C7^
43C6<>
39C3<>38A7<>
21C7^
43C6<>42A6<>
39C3<>
21C7^
43C6<>
39D3<>38A7<>
21C7^
43C6<>
38A7<>
21B6^
44A6<>
44B1<43A7<
21C5^
40C3<>
38B5<>
38A4>
21C5^
43B6<>42A4<>
21C5^
43B6<>42B3<>
21C5^
43B6<>42B3<>
21C5^
43B6<>42A4<>
21B5^
42B3<>
21C5^
43B6<>42A4<>
21B7^
42C3<>
21B7^
42C3<>
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
V3_3
V3_3
CONN_50P_T1E1
USER6
INT2
CS1
CS6
AD0
5V2
AD3
AD4
A11
A8
INT5
A10
A9
AD5
AD1
RD
WR
AD2
AD6
AD7
CS2
CS3
INT3
INT4
ALE
CS5
CS4
USER3
USER4
USER12
USER13
USER14
USER15
USER11
USER9
USER10
GND4
USER1
USER2
USER5
USER7
USER8
GND3
GND2
GND1
5V1
3.3V2
3.3V1
USER16
USER17
IO
IO
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
DONE
CCLK
XRST
JTD_SPART2FLASH
XI_TMS
V2_5XI
10UF
330
1UF
1UF
1UF
.1UF
.1UF
.1UF
1UF
.1UF
.1UF
.1UF
.1UF
1UF
1UF
1UF
1UF
1UF
TMS_NU
TDO_NU
TDI_NU
10K
JTD_FLASH_TDO
X_INIT
CFG_DIN
CCLK
JTD_SPART2FLASH
XI_TMS
ONCE_TCLK
DONE
XRST
V2_5XI
XI_TMS
JTD_FLASH_TDO
TCK_NU
10K
ONCE_TCLK
RESET_B
ONCE_TCLK
.1UF
JTD_SPART_TDI
JTD_SPART_TDI
1
2
1
2
1
2
1
2
1
2
2
1
2
1
2
1
1
2
2
1
2
1
1
2
2
1
2
1
1
2
2
1
2
1
2
1
7/7(BLOCK)
09/16/2004
STEVE SCULLY
DS33Z11/41/44DK01A0
44/71(TOTAL)
BLOCK
NAME:
_motprocrescard_dn.
PARENT
BLOCK:
\_z44top_dn\
CR-44
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page2_i1@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page7
CR-44
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i8@\_ztop_lib\.\_z44top_dn\(sch_1):page2_i1@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page7
CB489
1
2
CB316
1
2
CB457
CB295
CB100
CB78
CB373
CB409
CB378
CB187
CB353
CB375
CB352
CB372
CB195
CB270
CB171
1
2
R89
7
9
2
10
6
5
4
20
18
16
15
14
13
12
11
3
8
19
17
1
U12
RB364
E8
F9
H11
H12
J11
L9
M9
L8
M8
J5
J6
H5
H6
C14
D4
D13
E12
M5
M12
N13
P3
P14
D3
A15
C4
B14
D15
R14
N3
P2
R3
R4
P4
L6
J10
H9
G11
F7
F6
B15
B2
A16
A1
F8
E9
F10
F11
G6
G7
G8
G9
G10
H7
H8
H10
J7
J8
J9
K6
K7
K8
K9
K10
K11
L7
L10
L11
R2
R15
T1
T16
P15
N4
C3
E5
J12
U16
65
4
9
7
3
10
8
1
2
J43
R238
CB157
3
4
2
8
5
6
7
1
UB11
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
MAX1792
IN
OUT
SET
GND
OUT
IN
SHDN
RST
V3_3
V3_3
6
10
8
4
1
2
3
5
7
9
CONN_10P
XC2S50_BGA
CONTROL
VCCO8
VCCINT5
VCCINT1
VCCINT9
PROGRAM*
GND36
GND35
GND34
GND33
GND32
GND31
GND30
GND28
GND27
GND26
GND25
GND24
GND23
GND21
GND20
GND19
GND18
GND16
GND15
GND13
GND12
GND11
GND10
GND9
GND8
GND7
VCCO3
VCCO2
GND1
GND2
GND3
GND4
GND5
GND6
GND14
GND17
GND22
GND29
NC1
NC2
M2
M1
M0
DONE
CCLK
TDO
TCK
TDI
TMS
VCCINT12
VCCINT11
VCCINT10
VCCINT8
VCCINT7
VCCINT6
VCCINT4
VCCINT3
VCCINT2
VCCO16
VCCO15
VCCO14
VCCO13
VCCO12
VCCO11
VCCO10
VCCO9
VCCO7
VCCO6
VCCO5
VCCO4
VCCO1
CE*
TCK
TMS
CLK
D0
DNC1
OE/RST*
DNC2
TDI
CF*
XILINX_XCF01S
VCCJ
VCCO
VCCINT
TDO
DNC3
GND
DNC6
CEO*
DNC5
DNC4
V3_3
V3_3 V3_3
V3_3
DS21458 WAN INTERFACE BLOCK
2.048MHZ_3.3V
RB160
RB184
LIUC
MCLK
MCLK
30
30
ONCE_TCLK
I73
RESET_AH
10UF
10UF
0.1UF
0.1UF
0.1UF
WR
CS
0.1UF
0.1UF
RESET_B
0.1UF
0.1UF
ESIBR0
ESIBRD
0.1UF
RD
MUX
BTS
10UF
6
5
4
3
2
1
7
0
6
5
4
3
2
1
0
8
7
9
NA
BUFFER
RED
330
I37
I38
NC7SZ86
NA
INVERTER
I41
ADDR<9..0>
DAT<7..0>
RESET_AH
10UF
10UF
10UF
10UF
10UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
10UF
ESIBR1
WAN_INT
XI_TMS
NC7SZ86
WAN_INT
U20
UX11
DS25
R114
1
2
UXB05
CB112
CB340
CB151
C103
CB154
CB126
CB236
C48
C42
CB205
2
1
CB138
CB204
CB120
2
1
CB156
CB160
CB161
CB144
CB179
CB220
CB200
CB127
2
1
CB155
2
1
YB02
JTDO458
JTD_FLASH_TDO
MCLK2FPGA
46A1<>
55A3<> 54C7<>
55A4<
55A2<> 54C7<>
55A755A554C7
55A455A254C3
55D5> 46A4<>
PRINTED
Fri
Oct
20
11:07:03
2006
46/71(TOTAL)
09/16/2004
1/10(BLOCK)
STEVE SCULLY
DS33Z11/41/44DK01A0
BLOCK NAME: _quadte1wan_dn. PARENT BLOCK: \_wan4z44_dn\
CR-46
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE1
P4
P5
P6
R6
N13
H10
J12
C12
C11
E4
D4
F4
L13
M13
F3
H1
J16
A9
T8
A11
T6
B11
F1
F2
L16
L15
H9
H4
D9
H5
E10
H3
H2
K14
J15
G4
N7
B9
T7
G2
H6
J11
P8
D10
N8
P7
M7
R7
G1
G3
B10
R8
H8
J8
J9
D13
D12
D11
N6
N5
N4
C9
A10
M8
K15
J13
J14
G8
K13
C10
K16
L14
M16
E2
M15
E1
B12
A12
T5
R5
T13
T9
A4
T12
D16
A8
A5
H16
E16
M1
J1
N1
E9
P3
K9
C13
D3
E3
N14
M14
4
11
2
4
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
8
4 5
51D7<
46D7<
46C7<
52C1< 52C8<> 52A7<>
52B1< 55D6<>
51C7<
51C7<
51B7<
51C7<
46B7<
51C7<
52C1< 52C8<> 52A7<>
55D5>46C7>
52A7<>
52C6<>
53B6<>
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
VCC
1
OSC
GND OUT
V3_3
V3_3
V3_3
IO
V3_3
NC7SZ86_U
V3_3
NC7SZ86_U
CONTROL
DS21458_U
DVDD42
DVDD43
DVDD32
DVDD31
DVDD23
NC1
NC2
NC3
RVSS11
RVSS12
RVSS13
RVSS21
RVSS22
RVSS31
RVSS32
RVSS23
RVSS41
RVSS33
RVSS43
RVSS42
TVSS11
TVSS12
TVSS21
TVSS22
TVSS31
TVSS41
TVSS32
TVSS42
DVDD41
JTCLK
JTDI
JTDO
RPOSI
TEST1
TEST2
TSTRST
CS*
RD*
WR*
DVSS11
DVSS12
DVSS13
DVSS21
DVSS22
DVSS23
ESIBS<1>
ESIBS<0>
ESIBRD
MUX
BTS
AD<7>
AD<6>
AD<5>
AD<4>
AD<3>
AD<2>
AD<1>
AD<0>
A<9>
A<8>
A<7>/ALE_AS
A<6>
A<5>
A<4>
A<3>
JTMS
JTRST
A<0>
A<2>
A<1>
INT*
LIUC
MCLK1
RCLKI
TVDD41
TVDD42
TVDD32
TVDD31
TVDD22
TVDD12
TVDD21
RVDD4
RVDD3
RVDD2
RVDD1
DVDD33
DVSS42
DVSS41
DVSS33
DVSS31
DVSS32
DVDD21
DVDD22
MCLK2
RNEGI
DVSS43
TVDD11
DVDD13
DVDD12
DVDD11
IN
IN
IN
IN
OUT
V3_3
IN
PORT1_RRING = PIN L1
PORT2_RRING = PIN F16
RLOS1
TRING2
TTIP2
TRING1
TTIP1
RRING1
TCLK1
RTIP1
TSER1
RCLK1
RSER1
RRING2
RSER2
RLOS2
RSYNC2
TCLK2
RTIP2
TSER2
TSYSCLK2
RSYSCLK1
BPCLK1
TSYSCLK1
RSYNC1
TSSYNC1
RCLK2
TSYNC1
TSSYNC2
TSYNC2
RSYSCLK2
RGAPCLK2 TGAPCLK2
RGAPCLK1 TGAPCLK1
U20
U20
53B2<>
53B2<>
53B7<>
53C2<
53A7<>
53C2<
53A7<>
53A2<>
53B2<>
53B7<>
53B7<> 53A2<>
53B7<> 53A2<>
BLOCK
NAME:
_quadte1wan_dn.
PARENT
BLOCK:
\_wan4z44_dn\
47/71(TOTAL)
2/10(BLOCK)
09/16/2004
STEVE SCULLY
DS33Z11/41/44DK01A0
CR-47
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE2
F16
H14
G15
G10
G11
F15
B14
D14
J10
E15
F14
H15
E14
A14
A13
E13
H12
C16
B16
H13
B13
E11
D15
G14
G13
A15
G12
H11
F10
G16
C15
C14
G9
F13
A16
E12
B15
F11
F12
L1
J4
K2
K3
L2
M2
T3
M4
H7
K5
L3
J3
K6
R3
R4
N2
J6
P1
N3
J5
T4
L7
J7
K4
M3
T2
L5
J2
K8
K1
P2
R1
M6
L4
R2
M5
T1
K7
L6
51A6<>
49B5<
49C5<
49D8<
49D8<
49C8<
49C8<
49A5<
51A6<>
53D5<>
49A5<
53D7<
53D7<
53C6<>
53D7<
53D5<>
53D5<>
53D4<>
53D4<>
53D4<>
53D7<
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
IN
IN
OUT
OUT
IN
IN IO
IN IO
OUT
OUT
PORT
DS21458_U
TCLKI
TLINK
TNEGO
TNEGI
TPOSO
TPOSI
TSER
RCLKO
RLINK
RTIP
RCLK
RNEGO
TCLK
TCLKO
RMSYNC
RFSYNC
TCHCLK
TSIG
TRINGB
BPCLK
TSYNC
TLCLK
RPOSO
TCHBLK
TRINGA
TTIPA
RSYNC
RSYSCLK
RSIGF
RLOS/LOTC
TSYSCLK
TSSYNC
TTIPB
RLCLK
RCHCLK
RCHBLK
RSIG
RSER
RRING
PORT
DS21458_U
TCLKI
TLINK
TNEGO
TNEGI
TPOSO
TPOSI
TSER
RCLKO
RLINK
RTIP
RCLK
RNEGO
TCLK
TCLKO
RMSYNC
RFSYNC
TCHCLK
TSIG
TRINGB
BPCLK
TSYNC
TLCLK
RPOSO
TCHBLK
TRINGA
TTIPA
RSYNC
RSYSCLK
RSIGF
RLOS/LOTC
TSYSCLK
TSSYNC
TTIPB
RLCLK
RCHCLK
RCHBLK
RSIG
RSER
RRING
IN
PORT4_RRING = PIN T11
PORT3_RRING = PIN A6
TSYSCLK3 TSYSCLK4
TSSYNC4
RSYSCLK4
TTIP3
RCLK4
TRING4
TTIP4
TRING3 RRING4
RSER4
RLOS4
RSYNC4
TCLK4
RTIP4
TSER4
RRING3
RLOS3
RSYSCLK3
TCLK3
RCLK3
RTIP3
TSER3RSER3
RSYNC3
TSSYNC3
TSYNC4TSYNC3
RGAPCLK3 TGAPCLK3 RGAPCLK4 TGAPCLK4
U20
U20
53B7<>
53C2<
53A7<>
53A2<>
53B2<>
53A2<>
53B7<>
53B2<>
53C2<
53A7<>
53B7<> 53A2<> 53B7<> 53A2<>
BLOCK
NAME:
_quadte1wan_dn.
PARENT
BLOCK:
\_wan4z44_dn\
09/16/2004
STEVE SCULLY
DS33Z11/41/44DK01A0
48/71(TOTAL)
3/10(BLOCK)
CR-48
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE3
T11
P9
R10
R11
M9
R12
P16
M11
L8
P12
N11
R9
N12
P15
N15
R13
N10
T14
R14
N9
N16
K11
P13
P11
M10
R16
L9
P10
K12
T10
T15
P14
K10
L10
R15
M12
T16
L12
L11
A6
C8
B7
C7
D7
B6
C2
A3
D8
D6
E7
B8
B5
C1
D1
C5
F9
C4
B3
E8
D2
F5
B4
C6
E6
B2
F6
F8
G5
A7
C3
A2
G6
D5
B1
E5
A1
G7
F7
53C7< 53C7<
53D4<>
53D7<
50D8<
50B5<
50C5<
50D8< 50A5<
51A6<>
53D4<>
50A5<
50C8<
51A6<>
53D7<
50C8<
53D4<>
53D4<>
53D4<>
53D4<>
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
IN
IN
OUT
OUT
IN
IN
IO
IO
IN
OUT
OUT
PORT
DS21458_U
TCLKI
TLINK
TNEGO
TNEGI
TPOSO
TPOSI
TSER
RCLKO
RLINK
RTIP
RCLK
RNEGO
TCLK
TCLKO
RMSYNC
RFSYNC
TCHCLK
TSIG
TRINGB
BPCLK
TSYNC
TLCLK
RPOSO
TCHBLK
TRINGA
TTIPA
RSYNC
RSYSCLK
RSIGF
RLOS/LOTC
TSYSCLK
TSSYNC
TTIPB
RLCLK
RCHCLK
RCHBLK
RSIG
RSER
RRING
PORT
DS21458_U
TCLKI
TLINK
TNEGO
TNEGI
TPOSO
TPOSI
TSER
RCLKO
RLINK
RTIP
RCLK
RNEGO
TCLK
TCLKO
RMSYNC
RFSYNC
TCHCLK
TSIG
TRINGB
BPCLK
TSYNC
TLCLK
RPOSO
TCHBLK
TRINGA
TTIPA
RSYNC
RSYSCLK
RSIGF
RLOS/LOTC
TSYSCLK
TSSYNC
TTIPB
RLCLK
RCHCLK
RCHBLK
RSIG
RSER
RRING
IN
THE PCB LAYOUT INCORRECTLY USES PINS 38-40, 33-35, 28-30 AND 23-25
AS THE TX PRIMARY. THIS HAS BEEN CORRECTED IN THE SCHEMATIC,
THE PCB / ASSEMBLY HAS BEEN MODIFIED TO ACCOMMODATE THIS.
RJ45_4PORT
I13
R207
R208
CB390
RB313
RB312
RB321
RB322
L10
JB12
CB395
RB317
RB316
RB327
RB328
L10
R203
R204 C173
1UF
I14
0
0
61.9
61.9
0.1UF
I25
RJ45_4PORT
I26
0
0
61.9
61.9
0.1UF
0
0
0
0
TRING2
TTIP2
RRING1
RTIP1
RRING2
RTIP2
TTIP1
TRING1
JB12
1UF
C176
I11
L10
I2
L10
CR-49
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE4
4/10(BLOCK)
49/71(TOTAL)
BLOCK
NAME:
_quadte1wan_dn.
PARENT
BLOCK:
\_wan4z44_dn\
09/16/2004
STEVE SCULLY
DS33Z11/41/44DK01A0
7
6
33
34
35
2
1
C6
C4
C3
C5
C2
C1
C7
C8
8
31
10
32
9
2
1
2
1
2
1
2
1
17
16
23
24
25
1
2
A6
A4
A3
A5
A2
A1
A7
A8
18
21
20
22
19
2
1
2
1
2
1
2
1
2
1
1
2
2
1
2
1
2
1
2
1
47C2>
47C2>
47C4<
47C4<
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
RCV
6
5
RJ45
7
4
3
2
1
8
XMIT
RCV
6
5
RJ45
7
4
3
2
1
8
XMIT
THE PCB LAYOUT INCORRECTLY USES PINS 38-40, 33-35, 28-30 AND 23-25
THE PCB / ASSEMBLY HAS BEEN MODIFIED TO ACCOMMODATE THIS.
AS THE TX PRIMARY. THIS HAS BEEN CORRECTED IN THE SCHEMATIC,
CB396
RB319
RB318
R201
R202
RB329
L10
CB391
RB315
RB314
RB323
RB324
R206
R205
C174
L10
JB12
TRING3
TTIP3
TTIP4
TRING4
RTIP3
RRING3
RRING4
RTIP4
I9
I8
RJ45_4PORT
0.1UF
61.9
61.9
0
0
I25
0.1UF
61.9
61.9
RJ45_4PORT
I19
0
0
0
0
1UF
0
0
RB330
1UF
C175
JB12
I24
L10
I7
L10
5/10(BLOCK)
50/71(TOTAL)
DS33Z11/41/44DK01A0
09/16/2004
STEVE SCULLY
BLOCK
NAME:
_quadte1wan_dn.
PARENT
BLOCK:
\_wan4z44_dn\
CR-50
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE5
2
1
2
1
2
1
2
1
2
1
D6
D4
D3
D5
D2
D1
D7
D8
2
1
2
1
1
2
2
1
38
39
40
3
36
5
37
4
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
12
11
28
29
30
B6
B4
B3
B5
B2
B1
B7
B8
13
26
15
27
14
48C1>
48C1>
48C4<
48C4<
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
RCV
6
5
RJ45
7
4
3
2
1
8
XMIT
RCV
XMIT
6
5
RJ45
7
4
3
2
1
8
ALL UNMARKED BIAS RESISTORS ARE 10K
MOT
NOTMUX
RLOS1
RLOS2
RLOS3
RLOS4
LIUC
ESIBRD
ESIBR0
ESIBR1
MUX
BTS
2.0K
2.0K
2.0K
330
2.0K
330
330
330
2.0K
2.0K
RB185
RB209
RB192
RB228
DS30
RB221
DS32
DS33
DS34
RB234
RB251
RB284
RB183
RB303
BLOCK
NAME:
_quadte1wan_dn.
PARENT
BLOCK:
\_wan4z44_dn\
51/71(TOTAL)
DS33Z11/41/44DK01A0
STEVE SCULLY
09/16/2004
6/10(BLOCK)
CR-51
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE6
1
2
2
1
1
2
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
47A8>
47A4>
48A8>
48A4>
46C7<
46A2<>
46A2<>
46A2<>
46A2<
46A2<
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
XRST
DONE
CCLK
JTD_SPART2FLASH
ONCE_TCLK
JTD_SPART_TDI
XI_TMS
0.1UF
0.1UF
0.1UF
0.1UF
.1UF
.1UF
0.1UF
0.1UF
JTDO458
JTD_SPART_TDI
ONCE_TCLK
XI_TMS
TDI_NU
X_INIT
CFG_DIN
.1UF
330
1UF
.1UF
.1UF
.1UF
.1UF 1UF
1UF
1UF
.1UF
1UF
10K
V2_5XI
XRST
DONE
JTD_SPART2FLASH
CCLK
V2_5XI
XI_TMS
ONCE_TCLK
JTD_FLASH_TDO
TMS_NU
TCK_NU
TDO_NU
1UF
1UF
10UF
1UF
RESET_B
1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
RB129
1
2
CB274
1
2
CB230
1
2
C86
1
2
C114
1
2
UB06
CB66
2
1
CB65
2
1
C192
2
1
CB269
1
2
CB338
2
1
CB278
2
1
CB337
1
2
CB216
2
1
CB135
2
1
C23
2
1
C22
2
1
C188
2
1
CB275
1
2
C77
2
1
U10
R84
1
2
U08
JB07
C108
CB134
CB168
CB150
CB190
CB257
C125
C142
C123
CB62
C135
C85
1
2
CB245
09/16/2004
STEVE SCULLY
DS33Z11/41/44DK01A0
7/10(BLOCK)
52/71(TOTAL)
BLOCK
NAME:
_quadte1wan_dn.
PARENT
BLOCK:
\_wan4z44_dn\
CR-52
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE7
E8
F9
H11
H12
J11
L9
M9
L8
M8
J5
J6
H5
H6
C14
D4
D13
E12
M5
M12
N13
P3
P14
D3
A15
C4
B14
D15
R14
N3
P2
R3
R4
P4
L6
J10
H9
G11
F7
F6
B15
B2
A16
A1
F8
E9
F10
F11
G6
G7
G8
G9
G10
H7
H8
H10
J7
J8
J9
K6
K7
K8
K9
K10
K11
L7
L10
L11
R2
R15
T1
T16
P15
N4
C3
E5
J12
7
9
2
10
6
5
4
20
18
16
15
14
13
12
11
3
8
19
17
1
65
4
9
7
3
10
8
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
3
4
2
8
5
6
7
1
52B8<>
52B8<>
52C8<>
46C7>
52C1<
52C1<46C7<
52C8<>
52C1<46C7<
52C8<>
53B2<>
52B8<
52B1<
52B1<>
52B1<>
52C1<
46C7<
52A7<>
52C1<
46C7<
52A7<>
46C7<
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
MAX1792
IN
OUT
SET
GND
OUT
IN
SHDN
RST
V3_3
V3_3
V3_3
6
10
8
4
1
2
3
5
7
9
CONN_10P
CE*
TCK
TMS
CLK
D0
DNC1
OE/RST*
DNC2
TDI
CF*
XILINX_XCF01S
VCCJ
VCCO
VCCINT
TDO
DNC3
GND
DNC6
CEO*
DNC5
DNC4
XC2S50_BGA
CONTROL
VCCO8
VCCINT5
VCCINT1
VCCINT9
PROGRAM*
GND36
GND35
GND34
GND33
GND32
GND31
GND30
GND28
GND27
GND26
GND25
GND24
GND23
GND21
GND20
GND19
GND18
GND16
GND15
GND13
GND12
GND11
GND10
GND9
GND8
GND7
VCCO3
VCCO2
GND1
GND2
GND3
GND4
GND5
GND6
GND14
GND17
GND22
GND29
NC1
NC2
M2
M1
M0
DONE
CCLK
TDO
TCK
TDI
TMS
VCCINT12
VCCINT11
VCCINT10
VCCINT8
VCCINT7
VCCINT6
VCCINT4
VCCINT3
VCCINT2
VCCO16
VCCO15
VCCO14
VCCO13
VCCO12
VCCO11
VCCO10
VCCO9
VCCO7
VCCO6
VCCO5
VCCO4
VCCO1
V3_3 V3_3
V3_3
TSER PULLDNS USED IN IBO MODE
(IMPLEMENTS IMUX)
TSER1
CFG_DIN
RGAPCLK4
RGAPCLK3
RGAPCLK2
RGAPCLK1
TSSYNC4
TSSYNC1
BPCLK1
RSYSCLK1
RSYSCLK2
TSYSCLK3
RSYSCLK3
RSYSCLK
2.0K
2.0K
2.0K
RSER4
RSYNC1
TSER2
TSER3
TSER4
TCLK1
TCLK2
TCLK3
TCLK4
X_INIT
RSER3
RSER2
RSER1
RCLK4
RCLK3
RCLK2
RCLK1
TSYNC4
RSYNC4
TSSYNC3
RSYNC3
RSYNC2
TSSYNC2
TSYNC1
TSYNC2
TSYNC3
TSYSCLK4
TSYSCLK2
TSYSCLK1
RSYSCLK4
2.0K
RSER1
RSER2
RSER3
RSER4
SPARE_TP1
SPARE_TP2
U10
R88
R113
R104
R94
TGAPCLK4
TGAPCLK3
TGAPCLK2
TGAPCLK1
TP30
TP32
TSYSCLK
MCLK2FPGA
STEVE SCULLY
8/10(BLOCK)
BLOCK
NAME:
_quadte1wan_dn.
PARENT
BLOCK:
\_wan4z44_dn\
53/71(TOTAL)
09/16/2004
DS33Z11/41/44DK01A0
CR-53
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE8
A7
A5
C6
B4
A3
B3
D8
A6
C8
D7
E7
B5
D6
A4
E6
D5
C5
C9
B11
A11
C10
A8
C12
D12
B12
A13
D11
A12
B10
D10
A10
E10
A9
H16
H15
G16
H13
G13
F15
E16
F14
D16
F13
E13
D14
C15
H14
J13
G14
G15
G12
F16
F12
E15
E14
C16
B16
N15
N14
M13
L14
P16
L13
N16
M16
K14
K16
J16
K15
J15
M14
M15
L12
L16
K13
L15
K12
J14
T15
R16
B8
B7
C7
B6
E11
C11
A14
C13
B13
B9
D9
1 1
47B5<
52C8<>
48B4<
48B8<
47B4<
47B8<
48B1<
47B6<
47B6>
47B8<
47B4<
48B5<
48B8<
53C2< 48B4>
47B8<>
47B1<
48B5<
48B1<
47C5<
47C1<
48C5<
48C1<
52B8<>
53C2< 48B8>
53C2< 47B4>
53C2< 47B8>
48C4>
48C8>
47C4>
47C8>
48B1<>
48B4<>
48B5<
48B8<>
47B4<>
47B2<
47B6<>
47B2<>
48B5<>
48B1<
47B2<
47B6<
48B4<
53A7<>
47B8>
53A7<>
47B4>
53A7<>
48B8>
53A7<>
48B4>
48B1<>
48B5<>
47B1<>
47B5<>
46D7<
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
XC2S50_BGA
BANK 2
BANK 0
BANK 3
BANK 1
IO10_1
IO9_1\VREF
IO1_1\CS*
IO2_1\WRITE*
IO3_1
IO4_1\VREF
IO5_1
IO4_0
IO3_0
IO2_0\VREF
GCK3
IO15_3
IO14_3
IO23_3
IO22_3
IO21_3
IO20_3
IO19_3
IO18_3
IO17_3
IO16_3
IO13_3\TRDY
IO12_3
IO11_3\D4
IO10_3\VREF
IO9_3
IO8_3\D5
IO7_3\D6
IO6_3
IO5_3
IO4_3\VREF
IO3_3
IO2_3\D7
IO1_3\INIT*
IO24_2
IO23_2
IO22_2
IO21_2
IO20_2
IO19_2
IO18_2
IO17_2
IO16_2
IO15_2
IO14_2
IO13_2\(DOUT,BUSY)
IO12_2\(DIN,D0)
IO11_2
IO10_2\VREF
IO9_2
IO8_2
IO7_2\D1
IO6_2\D2
IO5_2
IO4_2
IO3_2\D3
IO2_2\VREF
IO2_1\IRDY
IO22_1
IO21_1
IO20_1
IO19_1
IO18_1
IO17_1
IO16_1
IO15_1
IO14_1
IO13_1
IO12_1
IO11_1
IO8_1
IO7_1
IO6_1
GCK2
IO20_0
IO19_0
IO18_0
IO17_0
IO16_0
IO15_0
IO14_0
IO13_0
IO12_0
IO11_0
IO10_0
IO9_0
IO8_0
IO7_0\VREF
IO6_0
IO5_0
IO1_0
PORTS ARE ENABLED BY DEFAULT ON T1 BRD, AND ARE DISABLED USING JUMPERS ON T3 BRD
WR
Z41TSYNC
5
30
OBS_TCLK<3>
OBS_RSER<3>
OBS_RDEN<4>
30
Z44_TCLK<4>
30
OBS_TCLK<4>
T3ENH_T1ENLPRT1
T3ENH_T1ENLPRT2
T3ENH_T1ENLPRT3
T3ENH_T1ENLPRT4
2.0K
2.0K
2.0K
2.0K
1
30
OBS_RDEN<3>
30
Z44_TDEN<4>
OBS_TDEN<4>
OBS_TDEN<3>
30
Z44_TDEN<3>
Z44_RDEN<3>
Z44_TCLK<3>
Z44_RCLK<3>
Z44_RSER<3>
30
30
Z44_RSER<2>
Z44_TCLK<2>
Z44_RCLK<2>
Z44_RDEN<2>
Z44_TDEN<2>
Z44_RSER<1>
Z44_RCLK<1>
Z44_RDEN<1>
Z44_TCLK<1>
Z44_TDEN<1>
30
30
30
30
30
30
30
30
0
0
2
3
4
6
2
DAT<7..0>
7
1
Z44_RDEN<4>
30
Z44_RCLK<4>
30
RD
Z44_TSER<1>
Z44_TSER<2>
T3ENH_T1ENLPRT1
T3ENH_T1ENLPRT2
T3ENH_T1ENLPRT3
T3ENH_T1ENLPRT4
ADDR<9..0>
30
Z41RSYNC
30
30
CS_X4
Z44_TSER<3>
OBS_RCLK<3>
OBS_RSER<4>
OBS_RCLK<4>
Z44_RSER<4>
30
Z44_TSER<4>
U10
M3
T11
T9
J4
T7
K2
T5
T10
T8
P5
K3
L5
P1
M1
T14
T3
T2
K5
N2 L3
M4
R50
R51
R49
R53
R54
R45
R72
R52
R46
R73
R43
R42
RB94
RB101
R44
R41
R39
RB93
RB92
R40
TP29
TP27
TP15
TP16
TP28
TP26
TP24
TP12
TP25
TP13
TP14
TP17
RB04
RB05
RB45
RB46
R48
R47
09/16/2004
STEVE SCULLY
DS33Z11/41/44DK01A0
54/71(TOTAL)
BLOCK
NAME:
_quadte1wan_dn.
PARENT
BLOCK:
\_wan4z44_dn\
9/10(BLOCK)
CR-54
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE9
N8
R11
M11
N11
T12
R13
P13
M10
R10
P10
R12
P11
T13
N12
P12
N10
T4
N6
R5
R6
M7
P8
N5
M6
N7
T6
P7
R7
M2
C2
B1
C1
E4
D1
E1
F2
G3
H3
G4
G1
A2
E3
D2
F3
E2
F1
F4
F5
G2
H2
H4
R8
N9
P9
K1
R1
N1
L4
K4
L2
L1
J1
H1
J2
P6
R9
J3
G5
1111
111
1
11 1 1
46B7<
55A3<>
55C6<>
55B1<>
55D6<> 54A6<>
55C6<> 54A5<>
55C2<> 54A5<>
55B2<> 54A5<>
55B1<>
55C1<>
55C4<>
55B1<>
55B4<>
55C4<>
55C8<>
55C6<>
55C8<>
55C8<>
55C6<>
55D8<>
55C8<>
55C8<>
55C6<>
55C6<>
55A4 55A2
46B1<>
55B4<>
55B4<>
46B7<
55A2<>
55D6<>
55C6<>
54A8<
55D6<>
54A8<
55C6<>
54A8<
55C2<>
54A8<
55B2<>
55A7 55A5
46C2<
55C6<>
55D2<>
55C1<>
55B4<>
55B1<>
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
BANK 5
BANK 7
XC2S50_BGA
BANK 6
BANK 4
IO11_7
IO19_5
IO4_6\VREF
IO2_4
IO5_5
IO1_6\TRDY
IO2_6
IO3_6
IO5_6
IO6_6
IO7_6
IO8_6
IO9_6
IO10_6\VREF
IO11_6
IO12_6
IO13_6
IO14_6
IO15_6
IO16_6
IO17_6
IO3_4\VREF
IO1_4
IO1_5
GCK1
IO23_7
IO22_7
IO21_7
IO20_7
IO19_7
IO18_7
IO17_7
IO16_7
IO15_7
IO14_7
IO13_7
IO12_7\IRDY
IO10_7
IO9_7\VREF
IO8_7
IO7_7
IO6_7
IO5_7
IO4_7
IO3_7\VREF
IO2_7
IO1_7
IO23_6
IO22_6
IO21_6
IO20_6
IO19_6
IO18_6
IO18_5
IO17_5
IO16_5
IO15_5
IO14_5
IO13_5
IO12_5
IO11_5
IO10_5
IO9_5
IO8_5\VREF
IO7_5
IO6_5
IO4_5
IO3_5
IO2_5\VREF
IO22_4
IO21_4
IO20_4
IO19_4
IO18_4
IO17_4
IO16_4
IO15_4
IO14_4
IO13_4
IO12_4
IO11_4
IO10_4
IO9_4\VREF
IO8_4
IO7_4
IO6_4
IO5_4
IO4_4
GCK0
P1 CONNECTOR (RECEPTICAL)
P2 CONNECTOR (RECEPTICAL)
WAN R.C. CONNECTOR TO MOTHERBOARD
NOTE 3184 IS ON CS3 WHILE 21455 IS ON CS2/CS4
RECEPTACLE
GND
INT2
RESET_B
T3ENH_T1ENLPRT1
Z44_TSER<1>
Z44_TDEN<1>
Z44_TCLK<1>
Z44_TCLK<2>
TMS_NU
TDI_NU
8
Z44_RSER<1>
GND
GND
Z41RSYNC
Z41TSYNC
RECEPTACLE
INT5
Z44_RDEN<1>
I28
GND
RD
GND
GND
GND
Z44_RSER<2>
GND
Z44_RDEN<3>
TCK_NU
TDO_NU
GND
OSC4_NU
OSC2_NU
V3_3
Z44_RCLK<2>
Z44_RDEN<2>
GND
GND
GND
GND
V3_3
GND
GND
V3_3
GND
GND
GND
GND
GND
OSC3_NU
GND
GND
GND
V3_3
GND
GND
GND
V3_3
GND
Z44_TDEN<2>
V3_3
7
4
2
0
6
5
3
GND
9
1
GND
ADDR<9..0>
ADDR<9..0>
GND
0
3
5
7
2
4
DAT<7..0>
GND
V3_3
GND
ALE
CS_X4
GND
GND
GND
GND
GND
Z44_TDEN<3>
GND
Z44_TCLK<3>
GND
GND
GND
GND
GND
V3_3
GND
GND
GND
GND
GND
GND
GND
V3_3
GND
GND
GND
V3_3
GND
CS_X5
GND
GND
GND
GND
I27
Z44_TCLK<4>
SIG_RETURN
GND
GND
Z44_RCLK<1>
GND
V3_3
INT2
SIG_RETURN
Z44_TDEN<4>
INT3
WAN_INT
GND
GND
OSC1_NU
GND
GND
V3_3
CS_X3
6
DAT<7..0>
I29
CS_X2
CS
GND
Z44_RCLK<4>
GND
Z44_RSER<4>
Z44_RDEN<4>
Z44_RSER<3>
V3_3
Z44_RCLK<3>
GND
GND
Z44_TSER<4>
Z44_TSER<3>
T3ENH_T1ENLPRT3
T3ENH_T1ENLPRT4
WR
GND
GND
SIG_RETURN
Z44_TSER<2>
T3ENH_T1ENLPRT2
GND
SIG_RETURN
1
J12 J09
09/16/2004
55/71(TOTAL)
10/10(BLOCK)
STEVE SCULLY
DS33Z11/41/44DK01A0
BLOCK
NAME:
_quadte1wan_dn.
PARENT
BLOCK:
\_wan4z44_dn\
CR-55
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE10
55D7<>
52B1<
46A2<>
54A8<
54A6<>
54B8<>
54B8<
54B8<
54B8<
52A8<>
52A8<>
54B8<
54C7<
54C7<
54B8<
46B7<
54C7<>
54A8<
54B1<
52A8<>
52A8<>
54B8<
54B8< 54B8<
55A754C7
46C2<
55A5 54C7
46C2<
55A4
54C3 46B1<>
54C7<>
54B1<
54B1<
54B1<
54B8<
55D6<>
55C6<>
55A1>
54A1<
46C7>
46A4<>
55A2 54C3 46B1<>
46B7<
54B1<
54B1<
54B1<
54B1<
54B1<
54B1<>
54B1<>
54A8<
54A5<>
54A8<
54A5<>
46B7<
54C7<>
55C6<>55B2<>
55A1>
54B8<>
54A8<
54A5<>
55C6<>55B2<>
55A1>
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
8
81
83
84
85
92
93 24
91
23
35
105
63
123
6
14
17
22
19
21
26
27
25
29
32
30
33
31
34
36
39
40
46
47
49
54
52
50
51
53
58
56
55
57
59
62
60
61
66
28
42
65
64
74
78
77
76
75
79
89
88
86
94
95
99
97
96
100
103
102
101
109
106
114
111
115
120
119
118
117
116
122
121
135
133
136
140
139
138
137
70
69
48
41
38
37
45
110
104
98
87
73
71
9
80
13
11
10
15
90
16
68
67
134
132
131
130
129
128
127
126
125
124
72
5
82
18
20
12
7
4
107
108
112
113
44
43
3
2
1
VDD
V3_3
8
81
83
84
85
92
93 24
91
23
35
105
63
123
6
14
17
22
19
21
26
27
25
29
32
30
33
31
34
36
39
40
46
47
49
54
52
50
51
53
58
56
55
57
59
62
60
61
66
28
42
65
64
74
78
77
76
75
79
89
88
86
94
95
99
97
96
100
103
102
101
109
106
114
111
115
120
119
118
117
116
122
121
135
133
136
140
139
138
137
70
69
48
41
38
37
45
110
104
98
87
73
71
9
80
13
11
10
15
90
16
68
67
134
132
131
130
129
128
127
126
125
124
72
5
82
18
20
12
7
4
107
108
112
113 44
43
3
2
1
DS3184 WAN INTERFACE BLOCK
VALUE NOT SHOWN FOR 10K RES
0.0
DAT<7..0>
1
JTDI
JTMS
CLKA
T3_INT
330
4
5
3
0.0
0.0
2
6
7
1
5
0
4
3
2
0
9
10
7
8
6
CS
RD
WR
CLKB
ADDR<10..0>
CLKB
JTRST
JTDO84
RESET_B
10K
TDI_NU
JTDI
TMS_NU
JTDOCPLD
TDO_NU
TCK_NU
JTRST
10K
JTCLK
10K
JTMS
10K
JTCLK
RED
T3_INT
CLKB
0.0
R144
RB227
R156
R142
R151
R146
RB222
RB186
R135
RB229
RB206
R121
J39
UX12
DS41
RB331
UB08
TP66
RB283
RB308
RB250
RB309
63A563A362A562A3
63D5> 62D5>
56A6<>
63A5< 62A5<
63A3> 62A3>
63A4<>
62A4<>
63A763A662A762A6
63D6<>
62D6<>
56/71(TOTAL)
BLOCK
NAME:
_quadte3wan_dn.
PARENT
BLOCK:
\_wan4z44_dn\
09/16/2004
DS33Z11/41/44DK01A0
STEVE SCULLY
1/8(BLOCK)
PRINTED
Fri
Oct
20
11:07:05
2006
CR-56
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I2@\_ZTOP_LIB\.\_QUADTE3WAN_DN\(SCH_1):PAGE1
65
4
9
7
3
10
8
4
R6
R7
R8
A2
F7
F6
F3
E4
G4
J3
F4
G18
K19
K20
K16
R4
P4
V3
N4
T3
U3
P3
W2
N3
P2
U2
P1
U1
N2
C3
D3
E3
G3
D2
H3
E2
T2
K10
N6
W1
R15
R14
R13
P15
P14
P13
N15
K9
K8
J10
J9
J8
M7
M6
L7
L6
K7
K6
J7
J6
A1
N10
N9
M10
M9
M8
L10
L9
L8
R12
R11
R10
R9
P12
P11
P10
P9
Y1
N12
N11
M13
M20
E20
F18
F19
G2
H2
E1
H1
P8
D20
E19
D19
N7
N8
P6
P7
G6
J20
A17
A19
W16
V15
Y16
Y17
B17
B18
R20
R19
R18
T20
T19
L3
K3
K4
B1
L5
M3
R3
B16
K1
L1
L2
L17
L16
K18
J19
L18
L19
K2
L4
K17
J5
T4
F8
G7
H8
H7
H6
G8
1
2
56D8<>
61C2< 60C2<
56D8<>
60B1<
60B1< 56C7< 56B4<
60B1< 56B4<
56B8<>
56D8<>
60C2<
63B7<>62B7<>
56C7<
63B7<>62B7<>
61C2<
63B6<>62B6<>
63B6<>62B6<>
56C7<
61D2<
60D2< 56C7<
61C2<
60C2< 56C7<
61D2< 60D2<
56D8<>
63D5>62D5>56B8>
60B1<56C7<
56B8<>
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
GND
V3_3
V3_3
V3_3
CONTROL
DS3184
VDD4
VDD3
VDD2
VDD1
VDD5
VDD7
D<14>
D<15>
TDXA<1>/TPXA
INT*
RDY*
RMOD<1>
RMOD<0>
RERR
RVAL
REOP
RSOX
CLKC
CLKB
CLKA
RST*
HIZ*
TEST*
WIDTH
MODE
WR*
RD*
CS*
RADR<4>
RADR<3>
RADR<2>
RADR<1>
RADR<0>
TMOD<1>
TMOD<0>
TERR
TSX
TEOP
TSOX
TEN
TPRTY
TSCLK
VDD6
VDD15
VDD16
VDD17
VDD18
TDXA<4>
TDXA<3>
TDXA<2>
VDD14
A<0>/BSWAP
A<1>
A<2>
A<3>
RDXA<2>
RDXA<3>
RDXA<4>
RSCLK
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS28
VSS27
VSS26
VSS25
VSS24
VSS23
VSS22
VSS21
VSS20
VSS19
VSS18
VSS17
VSS16
VSS15
VSS14
VSS13
VSS12
VSS11
VSS10
VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VDD27
VDD26
VDD25
VDD24
VDD23
VDD22
VDD21
VDD20
VDD19
VSS1
D<3>
A<4>
A<6>
A<5>
A<7>
A<8>
A<9>
A<10>
ALE
D<1>
D<0>
D<4>
D<2>
D<6>
D<5>
D<7>
D<9>
D<8>
D<11>
D<10>
D<12>
D<13>
TSPA
RPRTY*
RDXA1/RPXA
REN*
JTMS
JTDI
JTDO
JTRST*
JTCLK
VDD9
VDD8
VDD10
VDD11
VDD12
VDD13
V3_3
NC7SZ86_U
6
10
8
4
1
2
3
5
7
9
CONN_10P
V3_3
V3_3
V3_3
V3_3
OUT
IN
IN
IN
IN
IO
IN
PORT1=PINB8 PORT3=PINA12
PORT2=PINW8PORT4=PINY12
TE3_RGAPCLK<4..1>TE3_RGAPCLK<4..1>
TE3_TGAPCLK<4..1>TE3_TGAPCLK<4..1>
TE3_RGAPCLK<4..1>TE3_RGAPCLK<4..1>
TE3_TGAPCLK<4..1>TE3_TGAPCLK<4..1>
TE3_TXN<4..1>
TE3_TXP<4..1>
TE3_RCLK<4..1>TE3_RCLK<4..1>
TE3_TCLK<4..1>TE3_TCLK<4..1>
TE3_RCLK<4..1>TE3_RCLK<4..1>
TE3_TCLK<4..1>TE3_TCLK<4..1>
TE3_RXN<4..1>
TE3_RSER<4..1>
TE3_TXP<4..1>
TE3_TXN<4..1>
2
2
2
2
2
2
2
2
2
2
TE3_TSER<4..1>
TE3_RXN<4..1>
TE3_RXP<4..1>
TE3_RSER<4..1>
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
1
1
1
1
1
1
1
TE3_TXN<4..1>
TE3_TXP<4..1>
TE3_RSER<4..1>
TE3_RXN<4..1>
TE3_RXP<4..1>
TE3_TSER<4..1>
TE3_TXN<4..1>
TE3_TXP<4..1>
TE3_TSER<4..1>
1
1
1
TE3_TSER<4..1>
TE3_RXP<4..1>
TE3_RSER<4..1>
TE3_RXP<4..1>
TE3_RXN<4..1>
UB08
UB08UB08
UB08
61B3>60B3>57C5>57C2>57A5>61B3>60B3>57C5>57C2>57A1>
61B3>61A3> 60B3>60A3>57C5>57C2>57A5>61B3>61A3>60B3>60A3>57C5>57C2>57A1>
61B3>60B3>57C5>57A5>57A1>61B3>60B3>57C2>57A5>57A1>
61B3>61A3>60B3>60A3>57C5>57A5>57A1>
61B3>61A3> 60B3>60A3>57C2>57A5>57A1>
61C4> 61B4>60B4>57C5>57C2>57A5>
61C4>61B4> 60B4>57C5> 57C2>57A1>
61B4>60B4>57C5>57C2>57A5>61B4>60B4>57C5>57C2>57A1>
61C4>61B4>60B4>57C5>57A5>57A1>
61B4>60B4>57C5>57A5>57A1>61B4>60B4>57C2>57A5>57A1>
61B4> 60B4>57C5>57C2>57A5>
57C8< 57C5<
57A4< 61B4> 60B4>
61B4>60B4>57C5>57A5>57A1>
57C5<
57A8< 57A4< 61B4> 60B4>
57/71(TOTAL)
2/8(BLOCK)
STEVE SCULLY
DS33Z11/41/44DK01A0
09/16/2004
BLOCK
NAME:
_quadte3wan_dn.
PARENT
BLOCK:
\_wan4z44_dn\
CR-57
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I2@\_ZTOP_LIB\.\_QUADTE3WAN_DN\(SCH_1):PAGE2
B13
C13
A10
D13
A14
E14
D11
D12
C11
B12
A11
B11
C10
B10
C12
A13
D14
E13
E10
E12
E11
A6
B6
B14
C14
A15
B15
A12
A5
B5
U6
T6
V9
V5
W4
T5
U8
W7
Y8
T8
U9
T9
W9
Y9
Y7
U7
Y2
U5
U10
V7
V8
M1
M2
U4
V4
W3
Y3
W8
R1
R2
W13
V13
Y10
U13
Y14
T14
U11
U12
V11
W12
Y11
W11
V10
W10
V12
Y13
U14
T13
T10
T12
T11
Y6
W6
W14
V14
Y15
W15
Y12
Y5
W5
D6
E6
C9
C5
B4
E5
D8
B7
A8
E8
D9
E9
B9
A9
A7
D7
B2
D5
D10
C7
C8
J1
J2
D4
C4
B3
A3
B8
F1
F2
59C8<59C4<59A8< 59A4<57C5>57C2>57A2>
59C8<59C4<59A8< 59A4<57C5>57C2>57A2> 59C8< 59C4<59A8<59A4<57C5>57C2>57A5>
59C8<59C4< 59A8<59A4<57C5>57C2>57A5>
59D8< 59D4< 59B8<
59B4< 57C8< 57C5< 57A4<
59D8< 59D4< 59B8<
59B4< 57C8< 57C5< 57A4<
59C8<59C4<59A8<59A4<57C5>57A5>57A2>
59C8<59C4<59A8<59A4<57C5>57A5>57A2>
59D8<
59D4< 59B8<
59B4< 57C8<
57A8< 57A4<
59D8< 59D4< 59B8<
59B4< 57C5< 57A8< 57A4<
59D8<
59D4<
59B8<
59B4<
57C5<
57A8<
57A4<
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
IN
OUT
OUT
OUT
OUT
OUT
IN
PORT
DS3184
RXP
RXN
RLCLK
RPOS
RNEG
TPOS
TNEG
TXP
TXN
TOHCLK
TOHSOF
ROH
ROHCLK
ROHSOF
TCLKO
TSOFO
TPDENO
TPDAT
RSER
RCLKO
RSOFO
TLCLK
TSOFI
TOH
TOHEN
TCLKI
TPDENI
RPDAT
TSER
RPDENI
OUT
OUT
OUT
OUT
OUT
IN
PORT
DS3184
RXP
RXN
RLCLK
RPOS
RNEG
TPOS
TNEG
TXP
TXN
TOHCLK
TOHSOF
ROH
ROHCLK
ROHSOF
TCLKO
TSOFO
TPDENO
TPDAT
RSER
RCLKO
RSOFO
TLCLK
TSOFI
TOH
TOHEN
TCLKI
TPDENI
RPDAT
TSER
RPDENI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
PORT
DS3184
RXP
RXN
RLCLK
RPOS
RNEG
TPOS
TNEG
TXP
TXN
TOHCLK
TOHSOF
ROH
ROHCLK
ROHSOF
TCLKO
TSOFO
TPDENO
TPDAT
RSER
RCLKO
RSOFO
TLCLK
TSOFI
TOH
TOHEN
TCLKI
TPDENI
RPDAT
TSER
RPDENI
PORT
DS3184
RXP
RXN
RLCLK
RPOS
RNEG
TPOS
TNEG
TXP
TXN
TOHCLK
TOHSOF
ROH
ROHCLK
ROHSOF
TCLKO
TSOFO
TPDENO
TPDAT
RSER
RCLKO
RSOFO
TLCLK
TSOFI
TOH
TOHEN
TCLKI
TPDENI
RPDAT
TSER
RPDENI
NC PINS UNUSED????
0.0
0.0
0.0
0.0
RED RED
330
RED
330
GPIO1
GPIO3
GPIO3
GPIO2
GPIO1
RED
GPIO2
GPIO4
330
GPIO4
330
UB08
R132
RB194
R137
RB208
DS21
RB153
TP37
DS22
RB155
TP38
DS23
RB154
TP39
DS24
RB152
TP40
STEVE SCULLY
DS33Z11/41/44DK01A0
BLOCK
NAME:
_quadte3wan_dn.
PARENT
BLOCK:
\_wan4z44_dn\
58/71(TOTAL)
3/8(BLOCK)
09/16/2004
CR-58
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I2@\_ZTOP_LIB\.\_QUADTE3WAN_DN\(SCH_1):PAGE3
Y4
A4
T1
D1
G13
G15
H13
H14
H15
C18
C16
C17
T17
T16
W17
V17
W18
B19
C20
W20
F15
N13
V2
C2
V1
C1
P5
R5
G5
F5
G16
F16
H16
J16
E17
F17
G17
H17
J17
H18
E18
J18
G19
H19
G20
H20
M16
N16
P16
R16
M17
N17
P17
P18
P19
P20
N18
N19
M18
N20
L20
M19
G14
E15
D15
A16
M12
M11
L12
L13
L11
M15
M14
L14
L15
K15
K14
J15
J14
Y20
K13
K12
K11
J13
J12
J11
H11
H12
G12
G11
G10
G9
F12
F11
F10
F9
A20
H10
H9
M4
M5
H4
H5
N14
J4
N1
E7
T7
G1
N5
C6
V6
K5
U15
T15
U16
U17
D18
D17
C19
F20
E16
D16
R17
Y18
W19
U18
V19
V18
U19
V20
T18
U20
C15
A18
F14
F13
B20
Y19
V16
1
2
1
1
2
1
1
2
1
1
2
1
2
1
2
1
2
1
2
1
58B3<>
58B3<>
58A2<>
58B2<>
58B2<>
58B3<>
58A2<>
58B3<>
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
DATA & I/O PORT
DS3184
TDATA<15>
VDD30
VDD40
VDD39
VDD38
TADR<0>
TADR<4>
TDATA<0>
TDATA<1>
TDATA<2>
TDATA<3>
TDATA<5>
TDATA<4>
TDATA<6>
TDATA<10>
TDATA<13>
TDATA<16>
TDATA<22>
TDATA<23>
TDATA<24>
TDATA<25>
TDATA<26>
TDATA<27>
TDATA<28>
TDATA<29>
TDATA<30>
TDATA<31>
AVDDC
AVDDJ4
AVDDJ3
AVDDJ2
AVDDJ1
AVDDT4
AVDDT3
AVDDT2
AVDDT1
VDD28
NC<3>
NC<2>
NC<1>
NC<0>
VSS68
VSS67
VSS66
VSS65
VSS64
VSS63
VSS62
VSS61
VSS60
VSS59
VSS58
VSS56
VSS57
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS43
VSS44
VSS42
VSS41
VSS40
VSS38
VSS39
VSS37
VSS36
TADR<1>
TADR<3>
TADR<2>
VDD35
RDATA<1>
RDATA<0>
RDATA<3>
RDATA<2>
RDATA<4>
RDATA<5>
RDATA<6>
RDATA<7>
RDATA<8>
RDATA<9>
RDATA<10>
RDATA<11>
RDATA<12>
RDATA<13>
RDATA<14>
RDATA<15>
RDATA<16>
RDATA<17>
RDATA<18>
RDATA<19>
RDATA<21>
RDATA<20>
RDATA<22>
RDATA<23>
RDATA<24>
RDATA<25>
RDATA<26>
RDATA<27>
RDATA<28>
RDATA<29>
RDATA<31>
RDATA<30>
GPIO<1>
GPIO<2>
GPIO<3>
GPIO<4>
GPIO<5>
GPIO<7>
GPIO<6>
GPIO<8>
VDD29
VDD37
TDATA<7>
TDATA<8>
TDATA<9>
TDATA<11>
TDATA<12>
TDATA<14>
TDATA<17>
TDATA<18>
TDATA<19>
TDATA<21>
TDATA<20>
VDD31
VDD32
VDD33
VDD34
VDD36
AVDDR1
AVDDR2
AVDDR3
AVDDR4
RREF1
TREF1
TREF2
RREF2 RREF4
TREF3
RREF3
TREF4
TE3_RXP<4..1>
TE3_RXN<4..1>
TE3_RXP<4..1>
TE3_RXN<4..1>
TE3_TXP<4..1>
TE3_TXN<4..1>
TE3_RXP<4..1>
TE3_RXN<4..1>
TE3_TXP<4..1>
TE3_TXN<4..1>
TE3_TXP<4..1>
TE3_TXN<4..1>
TE3_TXN<4..1>
TE3_TXP<4..1>
TE3_RXN<4..1>
TE3_RXP<4..1>
332
51
51
51
51
51
51
51
51
3
3
332
3
3
4
4
4
4
2
2
2
2
332
1
1
1
1
75 OHM VERT
75 OHM VERT 75 OHM VERT
75 OHM VERT
75 OHM RA
332
75 OHM RA
75 OHM RA
75 OHM RA
332
332
332
332
TB01
R213
TB01
R200
R212
TB01
TB01
TB01
R199
TB01
R210
TB01
R211
RB306
TB01
R198
J57
J58 J59
J56
J52
J49
J50
J51
RB368
RB358
RB371 RB356
RB355
RB370
RB357
RB369
STEVE SCULLY
BLOCK
NAME:
_quadte3wan_dn.
PARENT
BLOCK:
\_wan4z44_dn\
09/16/2004
59/71(TOTAL)
4/8(BLOCK)
DS33Z11/41/44DK01A0
CR-59
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I2@\_ZTOP_LIB\.\_QUADTE3WAN_DN\(SCH_1):PAGE4
20
19
14
13
32
31
2
1
2
1
28
27
6
5
2
1
2
1
26
25
8
7
2
1
3
5
4
2
1
3
5
4
2
1
3
5
4
2
1
2
1
3
5
4
2
1
3
5
4
2
1
3
5
4
2
1
3
5
4
2
1
3
5
4
2
1
18
17
16
15
2
1
2
1
2
1
2
1
2
1
2
1
22
21 12
11
2
1
2
1
2
1
2
1
30
29
4
3
24
23
10
9
2
1
59D8<
59D4<
59B4<
57C8<
57C5<
57A8<
57A4<
59D8<
59D4<
59B4<
57C8<
57C5<
57A8<
57A4<
59D8< 59B8< 59B4< 57C8< 57C5< 57A8< 57A4<
59D8< 59B8< 59B4< 57C8< 57C5< 57A8< 57A4<
59C8< 59A8< 59A4< 57C5> 57C2> 57A5> 57A2>
59C8< 59A8< 59A4< 57C5> 57C2> 57A5> 57A2>
59D8< 59D4< 59B8< 57C8< 57C5< 57A8< 57A4<
59D8< 59D4< 59B8< 57C8< 57C5< 57A8< 57A4<
59C8< 59C4< 59A8< 57C5> 57C2> 57A5> 57A2>
59C8< 59C4< 59A8< 57C5> 57C2> 57A5> 57A2>
59C8<
59C4<
59A4<
57C5>
57C2>
57A5>
57A2>
59C8<
59C4<
59A4<
57C5>
57C2>
57A5>
57A2>
59C4<
59A8<
59A4<
57C5>
57C2>
57A5>
57A2>
59C4<
59A8<
59A4<
57C5>
57C2>
57A5>
57A2>
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
2:1
2:1
2:1
2:1
CONN_BNC_5P
CONN_BNC_5P CONN_BNC_5P
CONN_BNC_5P
CONN_BNC_5P
CONN_BNC_5P
CONN_BNC_5P
CONN_BNC_5P
2:1
2:1
2:1
2:1
Z44 CONNECTIONS
AND ARE DISABLED USING JUMPERS ON T3 BRD
PORTS ARE ENABLED BY DEFAULT ON T1 BRD
TE3_TGAPCLK<4..1>
TE3_TSER<4..1>
TE3_TCLK<4..1>
TE3_RGAPCLK<4..1>
TE3_RSER<4..1>
TE3_RCLK<4..1>
TE3_RSER<4..1>
TE3_TSER<4..1>
TE3_TGAPCLK<4..1>
TE3_TCLK<4..1>
4
R85
J24
TP31
RB148
RB149
JP17
JP19
R64
R61
R60
R63
R62
R69
R66
R65
R68
R67
UB03
Y08
RB145
JMP_2
Z44_TCLK<2>
T3ENH_T1ENLPRT2
T3ENH_T1ENLPRT1
Z44_TCLK<1>
Z44_RDEN<1>
Z44_TDEN<1>
OSC_A
CLKA
JTDT_NEXTCPLD
JTDO84
JTMS
JTCLK
XILINX_CPLD
30
30
30
30
30
30
30
2
2
2
2
2
4
4
4
4
4
JMP_3
JMP_3
30
30
30
30
Z44_RCLK<2>
CLKB
44.736MHZ_5.0V
30
Z44_RSER<2>
Z44_RDEN<2>
Z44_TDEN<2>
Z44_RSER<1>
30
Z44_RCLK<1>
2.0K
2
TE3_RCLK<4..1>
XILINX_CPLD
UB04
3
8
9
12
4
6
14
29
15
17
60
72
70
64
68
74
25
65
54
55
63
58
56
32
33
35
28
36
37
39
41
42
49
18
50
52
53
20
87
85
99
1
97
Z44_TSER<2>
OSC_A
T3ENH_T1ENLPRT1
T3ENH_T1ENLPRT2
Z44_TSER<1>
LOOPBACK_CTRL
SPARE_TP1
TE3_RGAPCLK<4..1>
09/16/2004
60/71(TOTAL)
5/8(BLOCK)
STEVE SCULLY
DS33Z11/41/44DK01A0
BLOCK
NAME:
_quadte3wan_dn.
PARENT
BLOCK:
\_wan4z44_dn\
CR-60
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I2@\_ZTOP_LIB\.\_QUADTE3WAN_DN\(SCH_1):PAGE5
8
4 5
78
79
77
81
82
89
90
91
92
93
94
95
96
86
10
11
13
40
27
59
61
66
67
71
76
30
23
22
3
3
98
5
88
51
38
26
47
48
57
100
84
75
69
62
44
31
21
83
45
1
2
1
61B3>61A3> 60A3>57C5>57C2>57A5>57A1>
57C8<57C5<57A8<57A4<61B4>60B4>
61B4>60B4>57C5>57C2>57A5>57A1>
61B3> 60B3>57C5>57C2>57A5>57A1>
61B4>60B4>57C5>57C2>57A5>57A1>
61C4> 61B4>60B4>57C5>57C2>57A5>57A1>
61B4>60B4>57C5>57C2>57A5>57A1>
57C8<57C5<57A8<57A4<61B4>60B4>
61B3>61A3>60B3>57C5>57C2>57A5>57A1>
61B4>60B4>57C5>57C2>57A5>57A1>
63C6<>62C6<>
63C6<>62C6<>60C8<>
63D6<>62D6<>60C8<>
63C6<>62C6<>
63C8<>62C8<>
63C6<>62C6<>
61B7<>60B7<>
56B8<
61C2<
56C7<>
61C2<56C7<
56D8<>
61D2<56C7<
56D8<>
63C8<>62C8<>
56C7< 56B4<
56B8<>
63C8<>62C8<>
63C8<>62C8<>
63C6<>62C6<>
63D8<>62D8<>
63C8<>62C8<>
61C4> 61B4>60B4>57C5>57C2>57A5>57A1>
63C6<>62C6<>
60B1<
61B7<>
63D6<> 62D6<> 60A8<>
63C6<> 62C6<> 60A8<>
63D6<>62D6<>
61C3<>
61B3>60B3>57C5>57C2>57A5>57A1>
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
XILINX_XC9572XL
TDI
TDO
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
3.3V2
TCK
TMS
NC<8-0>
2.5V_3.3V1
2.5V_3.3V2
2.5V_3.3V3
2.5V_3.3V4
3.3V1
3.3V3
V3_3
XILINX_XC9572XL
GCK1
GCK2
GCK3
IO17
IO18
IO34
IO24
IO23
IO54
IO53
IO52
IO51
IO50
IO49
IO48
IO47
IO46
IO45
IO44
IO43
IO42
IO41
IO40
IO39
IO38
IO37
IO19
IO20
IO21
IO22
IO25
IO26
IO27
IO28
IO29
IO30
IO31
IO32
IO33
IO35
IO36
IO16
IO15
IO14
IO13
IO12
IO11
IO10
IO9
IO8
IO7
IO6
IO5
IO4
IO3
IO1
IO61
IO72
IO71
IO70
IO69
IO68
IO67
IO66
IO65
IO64
IO63
IO62
IO60
IO59
IO58
IO55
IO57
IO56
IO2
VCC
1
OSC
GND OUT
V3_3
V3_3
Z44 CONNECTIONS
76
53
61
1
TP33
LOOPBACK_CTRL
TE3_RCLK<4..1>
39
TE3_RSER<4..1>
TE3_RGAPCLK<4..1>
TE3_TCLK<4..1>
TE3_TGAPCLK<4..1>
TP08
TP09
TP20
TP18
TP06
TP19
TP07
TP21
TP23
TP11
TP22
TP10
JP18
JP16
99
25
28
87
85
14
79
78
77
13
37
35
17
32
36
70
71
72
54
18
74
42
60
33
16
8
20
3
1
97
95
6
4
15
UB03
R35
RB91
R33
RB95
R34
R36
RB90
R38
RB89
R37
UB04
SPARE_TP3
NA
TINYTESTPOINT
Z44_TSER<4>
T3ENH_T1ENLPRT4
T3ENH_T1ENLPRT3
Z44_TDEN<4>
30
JTDT_NEXTCPLD
XILINX_CPLD
1
1
1
3
3
3
3
JMP_3
JMP_3
JTDOCPLD
JTCLK
JTMS
30
30
30
30
30
30
30
Z44_TCLK<3>
Z44_RSER<4>
30
3
TE3_TGAPCLK<4..1>
TE3_TSER<4..1>
TE3_TCLK<4..1>
TE3_RSER<4..1>
TE3_RGAPCLK<4..1>
TE3_RCLK<4..1>
TE3_TSER<4..1>
Z44_RDEN<3>
Z44_RCLK<3>
Z44_RDEN<4>
Z44_TCLK<4>
Z44_RCLK<4>
T3ENH_T1ENLPRT4
Z44_TDEN<3>
1
1
3
XILINX_CPLD
Z44_RSER<3>
30
Z44_TSER<3>
I79
NA
T3ENH_T1ENLPRT3
OSC_A
9
41
49
52
BLOCK
NAME:
_quadte3wan_dn.
PARENT
BLOCK:
\_wan4z44_dn\
09/16/2004
STEVE SCULLY
DS33Z11/41/44DK01A0
6/8(BLOCK)
61/71(TOTAL)
CR-61
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I2@\_ZTOP_LIB\.\_QUADTE3WAN_DN\(SCH_1):PAGE6
98
5
88
51
38
26
47
48
57
100
84
75
69
62
44
31
21
83
45
81
82
89
90
91
92
93
94
96
86
10
12
40
29
27
55
56
58
59
63
64
65
66
67
68
30
50
23
22
3
3
11111
11111 11
1
60C4<>
61B4>60B4>57C5>57C2>57A5>57A1>
61B4>60B4>57C5>57C2>57A5>57A1>
61B3>60B3>57C5>57C2>57A5>57A1>
61B4>60B4>57C5>57C2>57A5>57A1>
61A3>60B3>60A3>57C5>57C2>57A5>57A1>
63B2<>62B2<>
63B2<> 62B2<> 61A8<>
63C2<>62C2<>61C8<>
60C2<
56D8<>
60D2<56C7<
56D8<>
60C2<56C7<
56D8<>
61B3>60B3>60A3>57C5>57C2>57A5>57A1>
57C8<57C5<57A8<57A4<61B4>60B4>
61B4>60B4>57C5>57C2>57A5>57A1>
61B4>60B4>57C5>57C2>57A5>57A1>
61B3>60B3>57C5>57C2>57A5>57A1>
61C4>60B4>57C5>57C2>57A5>57A1>
57C8<57C5<57A8<57A4<61B4>60B4>
63B2<>62B2<>61C8<>
63C2<>62C2<>
63C2<> 62C2<> 61A8<>
60B1<
60B7<>
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
XILINX_XC9572XL
GCK1
GCK2
GCK3
IO17
IO18
IO34
IO24
IO23
IO54
IO53
IO52
IO51
IO50
IO49
IO48
IO47
IO46
IO45
IO44
IO43
IO42
IO41
IO40
IO39
IO38
IO37
IO19
IO20
IO21
IO22
IO25
IO26
IO27
IO28
IO29
IO30
IO31
IO32
IO33
IO35
IO36
IO16
IO15
IO14
IO13
IO12
IO11
IO10
IO9
IO8
IO7
IO6
IO5
IO4
IO3
IO1
IO61
IO72
IO71
IO70
IO69
IO68
IO67
IO66
IO65
IO64
IO63
IO62
IO60
IO59
IO58
IO55
IO57
IO56
IO2
XILINX_XC9572XL
TDI
TDO
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
3.3V2
TCK
TMS
NC<8-0>
2.5V_3.3V1
2.5V_3.3V2
2.5V_3.3V3
2.5V_3.3V4
3.3V1
3.3V3
V3_3
NOTE 3184 IS ON CS3 WHILE 21455 IS ON CS2/CS4
P1 CONNECTOR (RECEPTICAL)
WAN R.C. CONNECTOR TO MOTHERBOARD
P2 CONNECTOR (RECEPTICAL)
I35
I36
0
1
3
5
7
2
4
6
1
3
5
8
6
10
0
2
4
7
9
RD
DAT<7..0>
SIG_RETURN
GND
DAT<7..0>
CS
T3_INT
V3_3
GND
ADDR<10..0>
ADDR<10..0>
RECEPTACLE
GND
V3_3
GND
INT3
GND
INT2
RESET_B
GND
T3ENH_T1ENLPRT1
GND
Z44_TDEN<1>
Z44_TCLK<1>
GND
GND
T3ENH_T1ENLPRT2
GND
SIG_RETURN
Z44_TSER<2>
Z44_TDEN<2>
Z44_TCLK<2>
GND
GND
GND
GND
GND
TDO_NU
TCK_NU
GND
GND
GND
GND
OSC3_NU
GND
OSC4_NU
OSC2_NU
V3_3
GND
GND
GND
V3_3
TMS_NU
TDI_NU
GND
FPGAGCLK1_NU
GND
GND
GND
GND
V3_3
Z44_RCLK<2>
GND
Z44_RDEN<2>
GND
Z44_RSER<2>
GND
V3_3
GND
Z44_RCLK<1>
GND
Z44_RDEN<1>
GND
SIG_RETURN
Z44_RSER<1>
V3_3
GND
INT2
INT5
GND
GND
Z44_TSER<1>
INT4
RECEPTACLE
T3ENH_T1ENLPRT3
GND
V3_3
GND
ALE
CS_X4
GND
GND
GND
GND
GND
GND
Z44_TSER<3>
Z44_TDEN<3>
GND
Z44_TCLK<3>
GND
T3ENH_T1ENLPRT4
Z44_TSER<4>
GND
Z44_TDEN<4>
GND
SIG_RETURN
Z44_TCLK<4>
FPGAGCLK1_NU
GND
GND
GND
GND
GND
RW
GND
WR
CS_X3
V3_3
CS_X2
GND
GND
OSC1_NU
GND
V3_3
GND
GND
Z44_RCLK<4>
GND
Z44_RDEN<4>
GND
Z44_RSER<4>
GND
Z44_RCLK<3>
V3_3
Z44_RDEN<3>
GND
Z44_RSER<3>
GND
GND
V3_3
GND
GND
GND
V3_3
GND
CS_X5
GND
GND
J07
J10
STEVE SCULLY
09/16/2004
DS33Z11/41/44DK01A0
BLOCK
NAME:
_quadte3wan_dn.
PARENT
BLOCK:
\_wan4z44_dn\
62/71(TOTAL)
7/8(BLOCK)
CR-62
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I2@\_ZTOP_LIB\.\_QUADTE3WAN_DN\(SCH_1):PAGE7
56B8<63A3>
63C8<>63C6<>63B3<>
63A1>
62C8<>62C6<>62B3<>
63A5 63A3 62A3 56C3<>
63A5< 56B7<
63D5>56B8>
56A6<>
63A763A662A6
56D4<
63D6<>
63D7<>63D6<>62D7<>
56B8<
63D6<>
63D6<>60C8<>60A8<>
60D5<
63C6<>
60D5<
63C6<>
63C6<>60C8<>60A8<>
63C8<>63C6<>63B3<>
63A1>
62C8<>62B3<>
62A1>
63C6<>60D7<>
60D6<
63C6<>
60D6<
63C6<>
63B6<>56D6<>
63B6<>56D7<>
63A6<>
63A7<>
63A7<>
63B7<> 56D6<>
63B7<> 56D6<>
62B3<>
60D6<
63C8<>
60D6<
63C8<>
60D7<
63C8<>
60D5<
63C8<>
60D5<
63C8<>
63C8<> 63C6<>
63B3<>
63A1>
62C6<> 62B3<>
62A1>
60D6<
63D8<>
63D7<> 63D6<> 62D6<>
63D7<>
63D6<>60D6<>
63D6<>
63C2<>61C8<>61A8<>
63D3<>
63D3<>
63C2<>61D6<>
61D5<
63C2<>
61D5<
63C2<>
63B2<>61C8<>61A8<>
63B2<>61D7<>
61D6<
63B2<>
63C8<>63C6<>63B3<>
63A1>
62C8<>62C6<>
62A1>
61D6<
63B2<>
62B7<>
63A3<>
56B8<
63A4<>
63A4<>
63A4<>
63A4<>
61D6<
63B5<>
61D6<
63B5<>
61D7<
63B5<>
61D5<
63C5<>
61D5<
63C5<>
61D6<
63C5<>
63D4<>
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
8
81
83
84
85
92
93 24
91
23
35
105
63
123
6
14
17
22
19
21
26
27
25
29
32
30
33
31
34
36
39
40
46
47
49
54
52
50
51
53
58
56
55
57
59
62
60
61
66
28
42
65
64
74
78
77
76
75
79
89
88
86
94
95
99
97
96
100
103
102
101
109
106
114
111
115
120
119
118
117
116
122
121
135
133
136
140
139
138
137
70
69
48
41
38
37
45
110
104
98
87
73
71
9
80
13
11
10
15
90
16
68
67
134
132
131
130
129
128
127
126
125
124
72
5
82
18
20
12
7
4
107
108
112
113 44
43
3
2
1
VDD
8
81
83
84
85
92
93 24
91
23
35
105
63
123
6
14
17
22
19
21
26
27
25
29
32
30
33
31
34
36
39
40
46
47
49
54
52
50
51
53
58
56
55
57
59
62
60
61
66
28
42
65
64
74
78
77
76
75
79
89
88
86
94
95
99
97
96
100
103
102
101
109
106
114
111
115
120
119
118
117
116
122
121
135
133
136
140
139
138
137
70
69
48
41
38
37
45
110
104
98
87
73
71
9
80
13
11
10
15
90
16
68
67
134
132
131
130
129
128
127
126
125
124
72
5
82
18
20
12
7
4
107
108
112
113 44
43
3
2
1
V3_3
NOTE 3184 IS ON CS3 WHILE 21455 IS ON CS2/CS4
DS21458 CONNECTS TO MOTHERBOARD BY STACKING ONTO T3E3 BRD
P1 CONNECTOR (PLUG)
PLUG STYLE CONNECTORS GO ON BOTTOM OF T3E3 WAN CARD
P2 CONNECTOR (PLUG)
WAN R.C. CONNECTOR TO MOTHERBOARD
GND
1
GND
GND
GND
GND
GND
Z44_RDEN<3>
GND
GND
Z44_TCLK<1>
T3ENH_T1ENLPRT2
SIG_RETURN
Z44_TSER<2>
TDO_NU
TCK_NU
V3_3
TMS_NU
3
WR
6
T3ENH_T1ENLPRT1
RESET_B
INT2
Z44_TCLK<3>
I25
PLUG
GND
Z44_RSER<1> Z44_TSER<1>
INT3
I17
I15
I14
I13
I7
I6
ADDR<10..0> ADDR<10..0>
GND
V3_3
CS
GND
SIG_RETURN
DAT<7..0>
RD
9
7
4
2
0
10
6
8
5
4
7
5
3
1
0
T3_INT
GND
V3_3
GND
INT4
GND
GND
GND
Z44_TDEN<1>
GND
GND
GND
Z44_TDEN<2>
Z44_TCLK<2>
GND
GND
GND
OSC3_NU
GND
OSC4_NU
OSC2_NU
V3_3
GND
GND
GND
TDI_NU
GND
GND
GND
GND
GND
V3_3
Z44_RCLK<2>
GND
Z44_RDEN<2>
GND
Z44_RSER<2>
GND
V3_3
GND
Z44_RCLK<1>
GND
Z44_RDEN<1>
GND
SIG_RETURN
V3_3
GND
INT2
INT5
GND
GND
I8
V3_3
GND
ALE
CS_X4
GND
GND
GND
GND
GND
GND
Z44_TSER<3>
Z44_TDEN<3>
GND
GND
Z44_TSER<4>
GND
Z44_TDEN<4>
GND
SIG_RETURN
Z44_TCLK<4>
GND
GND
GND
GND
GND
RW
V3_3
GND
GND
OSC1_NU
GND
V3_3
GND
GND
Z44_RCLK<4>
GND
Z44_RDEN<4>
GND
Z44_RSER<4>
GND
Z44_RCLK<3>
V3_3
GND
Z44_RSER<3>
GND
GND
V3_3
GND
GND
V3_3
GND
CS_X5
GND
GND
PLUG
T3ENH_T1ENLPRT3
T3ENH_T1ENLPRT4
CS_X3
CS_X2
2
DAT<7..0>
JB05
JB06
DS33Z11/41/44DK01A0
09/16/2004
STEVE SCULLY
8/8(BLOCK)
63/71(TOTAL)
BLOCK
NAME:
_quadte3wan_dn.
PARENT
BLOCK:
\_wan4z44_dn\
CR-63
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I2@\_ZTOP_LIB\.\_QUADTE3WAN_DN\(SCH_1):PAGE8
26
88
28
35
114
108
1
2
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5
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63
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68
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70
140
139
138
137
136
135
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133
132
131
130
129
128
127
126
125
124
123
122
121
120
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118
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113
110
109
111
112
107
106
105
104
103
102
101
100
99
98
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96
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92
91
90
89
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84
83
82
81
80
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77
76
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74
73
72
71
40
9
26
88
28
35
114
108
1
2
3
4
5
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140
139
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135
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109
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112
107
106
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71
40
9
61D5<
62C5<>
60D5<
62C6<>
62C6<>60C8<>60A8<>
63C8<>63B3<>
63A1>
62C8<>62C6<>62B3<>
62A1>
62C6<>60D7<>
62B6<>56D6<>
62B6<>56D7<>
62B7<> 56D6<>
56B8<
62A4<>
62D6<>60C8<>60A8<>
56B8<
62D6<>
63D7<>62D7<>62D6<>
61D5<
62C2<>
60D6<
62D8<> 62D6<>60D6<>
62D6<>
63A6
62A762A6
56D4<
62A5< 56B7<
63C8<>63C6<>63B3<> 62C8<>62C6<>62B3<>
62A1>
56B8<62A3>
62D5>56B8>
56A6<>
62D6<>
60D5<
62C6<>
60D6<
62C6<>
60D6<
62C6<>
62A6<>
62A7<>
62A7<>
62B7<> 56D6<>
60D6<
62C8<>
60D6<
62C8<>
60D7<
62C8<>
60D5<
62C8<>
60D5<
62C8<>
63C6<> 63B3<>
63A1>
62C8<> 62C6<> 62B3<>
62A1>
63D6<> 62D7<> 62D6<>
62D7<>
62D3<>
62D3<>
62C2<>61D6<>
61D5<
62C2<>
62B2<>61D7<>
61D6<
62B2<>
63C8<>63C6<>
63A1>
62C8<>62C6<>62B3<>
62A1>
61D6<
62B2<>
62A3<>
62A4<>
61D6<
62B5<>
61D6<
62B5<>
61D7<
62B5<>
61D5<
62C5<>
61D6<
62C5<>
62D4<>
62C2<>61C8<>61A8<>
62B2<>61C8<>61A8<>
62A4<>
62A4<>
63A3 62A5 62A3 56C3<>
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
8
81
83
84
85
92
93 24
91
23
35
105
63
123
6
14
17
22
19
21
26
27
25
29
32
30
33
31
34
36
39
40
46
47
49
54
52
50
51
53
58
56
55
57
59
62
60
61
66
28
42
65
64
74
78
77
76
75
79
89
88
86
94
95
99
97
96
100
103
102
101
109
106
114
111
115
120
119
118
117
116
122
121
135
133
136
140
139
138
137
70
69
48
41
38
37
45
110
104
98
87
73
71
9
80
13
11
10
15
90
16
68
67
134
132
131
130
129
128
127
126
125
124
72
5
82
18
20
12
7
4
107
108
112
113 44
43
3
2
1
VDD
8
81
83
84
85
92
93 24
91
23
35
105
63
123
6
14
17
22
19
21
26
27
25
29
32
30
33
31
34
36
39
40
46
47
49
54
52
50
51
53
58
56
55
57
59
62
60
61
66
28
42
65
64
74
78
77
76
75
79
89
88
86
94
95
99
97
96
100
103
102
101
109
106
114
111
115
120
119
118
117
116
122
121
135
133
136
140
139
138
137
70
69
48
41
38
37
45
110
104
98
87
73
71
9
80
13
11
10
15
90
16
68
67
134
132
131
130
129
128
127
126
125
124
72
5
82
18
20
12
7
4
107
108
112
113 44
43
3
2
1
V3_3
