SPIO-4 Precision Signal-Path Controller Board Users' Guide December 2010 Table of Contents 1.0 SPIO-4 System Overview ...................................................................................................................... 3 1.0 SPIO-4 System Overview ...................................................................................................................... 3 1.1 SPIO-4 System Features................................................................................................................ 3 1.2 Packing List .................................................................................................................................... 3 1.3 Board Layout Overview .................................................................................................................. 4 1.4 Component Description .................................................................................................................. 5 1.5 SPIO-4 Board Test Points .............................................................................................................. 5 2 System Functionality .............................................................................................................................. 6 2.1 System Block Diagram ................................................................................................................... 6 2.2 General System Overview.............................................................................................................. 6 2.3 Automatic Device Detection & Configuration ................................................................................. 7 2.4 LED Indicators ................................................................................................................................ 7 2.5 DUT Interface (GPSI-16/32) ........................................................................................................... 7 2.5.1 Level Shifters........................................................................................................................... 9 2.6 Auxiliary Interface ......................................................................................................................... 12 2.7 Computer Interface ....................................................................................................................... 12 2.8 Memory......................................................................................................................................... 12 2.9 Power Requirements .................................................................................................................... 12 3 SPIO-4 Bill of Materials ........................................................................................................................ 13 4 SPIO-4 Schematics .............................................................................................................................. 14 Table 1 - Main component reference designators ........................................................................................ 5 Table 2 - Test Points ..................................................................................................................................... 5 Table 3 - LED Behavior................................................................................................................................. 7 Table 4 GPSI-32 Signals............................................................................................................................. 12 Figure 1 - SPIO-4 Board Layout - Component Side .................................................................................... 4 Figure 2 - SPIO-4 System Block Diagram .................................................................................................... 6 Figure 3 - GPSI 16 DUT to SPIO4 Mating .................................................................................................... 8 Figure 4 - GPSI 32 DUT to SPIO4 Mating .................................................................................................... 9 National Semiconductor Page 2 www.national.com 1.0 SPIO-4 System Overview The SPIO-4 is one of several National Semiconductor digital controller/capture boards that are used by multiple evaluation systems. The objective of these software/hardware evaluation systems is to allow our customers to easily and accurately evaluate National's signal-path devices in a lab setting. At the time of SPIO-4's release, two different evaluation system software (GUIs) make use of this board: the WaveVision-5 and the Sensor AFE. The board ships with the current version of the WaveVision-5 software. In addition to the controller/capture board (i.e., the SPIO-4) and the evaluation GUI software (e.g., WaveVision-5 or Sensor AFE), the third essential element of an evaluation system is the device or signalpath evaluation board that plugs into the controller board. This eval board is generically referred to as the "DUT board". Each DUT board comes with its own Users' Guide which documents its specific features. Each DUT board also comes with some software that the user must install before using it. In the case of the WaveVision-5 GUI, this software is essentially a device-specific module that adds support for the future device eval boards. In the case of Sensor AFE device family, the eval board comes with a complete, custom Sensor AFE that is specifically paired with that device. The WaveVision-5 and Sensor AFE GUI software have their own Users' Guide documents that describe how to interact with the GUI. This User's Guide describes only the SPIO-4 board. The user is expected to refer to this guide only if necessary. The DUT Users' Guide and the GUI Users' Guide are the primary documents that describe how to work with a National signal-path evaluation board. The latest version of this document may be obtained from National Semiconductor's web site at www.national.com. 1.1 SPIO-4 System Features Captures or sources multiple signal-path data streams and transfers them to/from the PC based application software through a USB 2.0 connection (USB1.1 compatible). Supports jumper-less, plug-and-play configuration. The GUI automatically discovers the attached DUT board and loads the appropriate software module for it. Supports a wide variety of signal-path evaluation board through a standardized connector (GPSI16/GPSI-32). Capable of storing up to 8MBytes of signal-path data. DUT interface can be SPI, I2C or parallel. Powered either by PC via USB or external supply. 1.2 Packing List The SPIO-4 kit (National order number SPIO-4/NOPB ) consists of the following components: SPIO-4 Board USB cable User's Guide (This Document) WaveVision-5 GUI software National Semiconductor Page 3 www.national.com 1.3 Board Layout Overview Figure 1 - SPIO-4 Board Layout - Component Side National Semiconductor Page 4 www.national.com 1.4 Component Description The following table describes both the on-board connectors and the main components used in the SPIO-4 System shown in Figure 1. Component J1 J2 J3 J4 (DBG) J6 (GPSI-32) J7 (micro_SD) J8 (USB) J9 (JTAG) J10 (POWER) J14 (USNAP) JP1 U1 U4 U5 1.4.1.1 Description Serial Debug connector Header to provide access to the FPGA's JTAG interface for debug Jumper to select J4 IO voltage (3.3V or programmable) Debug/Development Connector(See section 2.6). GPSI-16/32 Connector to DUT. This holds the microSD card for storage or development purposes USB cable Connection. Atmel Processor JTAG Debug Header. +5-6V Power Supply Connection -Optional (See Section Error! Reference source not found.). Additional header providing power and serial interface to processor Jumpers for test purposes only. Atmel SAM3U Processor 8Mx16 PSRAM Xilinx Spartan LX16 FPGA D1-D4 D6 D7 D8 D10 D11 FPGA Status LEDs (See section 2.4) 1.8V PSRAM Core voltage Surface mount power LED. 3.3V DUT supply voltage Surface mount power LED. 5.0V DUT supply voltage Surface mount power LED. USB input power LED. 1.2V FPGA Core voltage Surface mount power LED. SW1 SW2 Reset switch Power On pushbutton Table 1 - Main component reference designators 1.5 SPIO-4 Board Test Points The following table describes the main Test Points available. Test point TP1, TP3, TP16, TP18(GND) TP11 TP12 TP13 TP14 TP15 National Semiconductor Description Ground test points. 3.3V Digital IO Voltage for SPIO Board 1.2V for FPGA core voltage 1.8V for PSRAM core voltage 3.3V for DUT Digital Supply 5.0V for DUT Analog Supply Table 2 - Test Points Page 5 www.national.com 2 System Functionality 2.1 System Block Diagram Debug Connector(J1) Debug Connector(J9) 12MHZ Xtal 32kHZ Xtal GPSI 32 Connector (J6) SD Card (J7) > Level Shifters GPSI A GPSI A USB Connector (J8) GPIO Micro-Controller Atmel SAM3U (U1) USB GPSI A Pins 1,3,7,8,16 GPSI A Pins 5,6,9 DUT3.3V_EN < Level Shifters VDDIO I2C(SCL) Pin 12 I2C(SDA) Pin 11 DUT 3.3V DUT 5V Pin 13 Pin 14 3.3V_DUT NCS3/FPGA_CFG NCS2 USB 5V Pin 15 3.3V_DUT Static Mem intrfc A23-1 D15-0 I2C NCS0 NWR NRD NBS0-1 8MBx16 PSRAM (U4) Spartan 6 XC6SLX16 (U5) GPSI B IO Voltage 1.2V Pins 23-30 3.3V 1.8V JTAG (J2) Ext Pwr (J10) Input Protection LP3910 Multiple Supply Switching Regulator (U11) DEBUG (J4) 3.3V DUT3.3V_EN DUT 3.3V Boost Regulator (U12) Filter DUT 5V Figure 2 - SPIO-4 System Block Diagram 2.2 General System Overview The SPIO-4 board is controlled via the Atmel SAM3U micro-controller that is based on an ARM M3, 32-bit embedded core. It provides the interface to the computer via a USB interface. The DUT board interfaces to the SPIO-4 via J6, the GPSI-16/32 connector. The GPSI-16/32 interface provides control, data and power to the DUT board. The interfaces on the GPSI-32 can be I2C, SPI with multiple-device capability, and parallel interface. The dedicated I2C interface on the GPSI-16/32 is primarily for control and DUT identification, while the dedicated SPI interface may be used for control or for data transfer. The I2C interface is derived from the peripheral of the microcontroller. As there can be a wide variety of SPI requirements for DUTs, the SPI interface can be provided via a processor peripheral and over the dedicated SPI lines as shown in this document, or the on-board Xilinx Spartan XC6SLX16 FPGA may be used. In fact, the FPGA may be used to implement DUT interfaces other than SPI - such as high-speed I2C for data purposes and parallel data-plus-clock interfaces. A large external SRAM 8Mx16 is connected to both the processor and the FPGA which is used to provide additional device data storage in case the microcontroller's or FPGA's on-board memory is insufficient. Power is provided to the system via the USB cable, or external power jack. A switching regulator is used to produce the 3.3 volt supply required by the microcontroller and GPSI-32 devices. A boost regulator creates the regulated 5 volt supply required by the devices interfaced to the GPSI-32 connector. National Semiconductor Page 6 www.national.com 2.3 Automatic Device Detection & Configuration The SPIO-4 system supports automatic hardware detection and configuration of the device under test. The GUI software actually carries out the device detection and configuration task. The FPGA is reconfigured on the fly by the host PC when the SPIO-4 Board is powered on, or whenever ADC evaluation boards are exchanged and SPIO-4 power is cycled. Each DUT board has either an FPGA configuration file, or a microcontroller firmware module, unique to it. The GUI software, in conjunction with the USB micro-controller, determines which DUT board has been plugged in. It then loads a configuration file tailored for that DUT board into the FPGA and/or the microcontroller. Normally, the configuration process is totally transparent to the user, and requires no intervention. However, some devices may allow this process to be overridden. Refer to the evaluation board manual for more information. Important Note: Many of our device evaluation boards do require jumper configurations to select channels, voltages, or other options. Please consult the manual that came with the evaluation board for specific information. Important Note: Please be aware that DUT boards are NOT hot swappable. Please power down both the SPIO-4 board and the DUT board prior to swapping DUT board. 2.4 LED Indicators There are several LED indicators on the SPIO4 board. the ones described bleow are driven directly by separate power rails on the SPIO4 board but as those rails can only be controlled by the processor they not only indicate a particular rails is on, they also show a state of the SPIO4 firmware as discussed below. Led D# D10 D5 D6 D11 D7 & D8 Description Indicates power (USB or External) is present to SPIO board 3.3V Digital IO Voltage for SPIO Board is up (required for all operations) 1.2V for FPGA core voltage - Indicates processor has completed low level hardware initialization and is ready to program the FPGA 1.8V for PSRAM core voltage - Indicates processor has completed low level hardware initialization and is able to use the PSRAM 3.3V & 5V DUT Supplies - Indicates the processor has detected a DUT board inserted and has powered it Table 3 - LED Behavior 2.5 DUT Interface (GPSI-16/32) The SPIO-4 Data Capture Board is connected to the DUT through the GPSI-16/32 (J6) connector. As described previously, the GPSI-32 interface provides control, data and power to the DUT board. See Table 1 below for signal specifics. The GPSI-16/32 interface also supports a subset within it called GPSI16 which consists of the lower order pins 1-16. A given DUT board may use a 16-pin, GPSI-16 port only, or may use the whole 32-pin port. GPSI-16 has level shifters allowing some of the DUT interface voltages to go from 1.65V to 5.5V LVTTL levels under the direct control of the DUT board circuitry. To achieve that voltage range the voltage level shifters are NOT bidirectional. A DUT board requiring bidirectional signals must use the upper-order portion of the GPSI-32. Note, however, that upper order portion of GPSI-32 requires adherence to 3.3V LVTTL voltage levels as it does not have level shifters. National Semiconductor Page 7 www.national.com Below are two photos demonstrating the proper mating of a GPSI16 and a GPSI32 DUT board to the SPIO4. Figure 3 - GPSI 16 DUT to SPIO4 Mating National Semiconductor Page 8 www.national.com Figure 4 - GPSI 32 DUT to SPIO4 Mating 2.5.1 Level Shifters The board incorporates level shifters to allow flexible output voltages on the uni-directional SPI signals of GPSI-16 port, as shown in the board block diagram. VDDIO - a supply voltage from the GPSI-16/32 connector coming from the DUT board - provides the voltage to the output side of the level translators. If the DUT has no special requirements for voltage and simply needs basic 3.3V signal levels, the 3.3V output from the GPSI connector could be connected to VDDIO on the DUT board. The level shifters are uni-directional. If VDDIO is not provided, the level shifters enter a shutdown state with all input pins tristated. The state passed along to the processor in this case would be logic low. National Semiconductor Page 9 www.national.com GPSI Connector (J6) Pin Description Pin Signal Name/Function # Pins 1-16 form the GPSI-16 subset: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SCS0_A~ SerialBus A - Chip Select for device 0. GND SCK_A Serial Bus A - Serial Clock from the master to the device. DUT_Present~ The DUT board shall ground this pin. The SPIO-4 senses this pin to determine the DUT board's presence. SMISO_A Serial Bus A - Data from the slave (device) to the master. The device may implement this as a tri-state signal that can be driven by multiple devices on Serial Bus A in a bussed fashion. The pull-up resistor, if required, is on the DUT board. Dev_INT~/SDRDY_A~ In certain applications, if required, this pin serves as the DRDY~ signal from the DUT to the SPIO-4. In other cases, this pin may be a general interrupt pin from the device to the SPIO-4. On the SPIO-4 board this signal connects to an interrupt pin on the microcontroller. SMOSI_A Serial Bus A - Data from the master to the slave (device). SCS1_A~ SerialBus A - Chip Select for device 1. Ref_CLK Reference clock from the DUT board to the SPIO-4 board.If not used, the DUT board should ground this pin. Voltage Level Direction (From SPIO-4) 1.65 to 5.5V OUTPUT 1.65 to 5.5V N/A OUTPUT 1.65 to 5.5V INPUT 1.65 to 5.5V INPUT 1.65 to 5.5V 1.65 to 5.5V 1.65 to 5.5V OUTPUT INPUT OUTPUT INPUT GND SDA Data line of the I2C bus. Pulled-up to +3.3V_DUT on the SPIO-4 board through a 1.5k resistor. SCL Clock line of the I2C bus. Pulled-up to +3.3V_DUT on the SPIO-4 board through a 1.5k resistor. +3.3V_DUT Switched by the SPIO-4 conditional on the DUT_Present~ having been seen. The ID EEPROM and the entire I2C bus on the DUT board must be unconditionally powered by this supply. Max. peak current: 50mA (subject to total power budget limit of 200mW over both supplies). Maximum capacitor loading for this node is not to exceed 50uF. +5V_DUT This supply is sourced by the SPIO-4 and is intended to power the core functionality of the DUT board - if desired. Nominal current: 35mA. Max. peak current: 50mA (subject to total power budget limit of 200mW over both supplies). If power from the SPIO-4 is not required, National Semiconductor Page 10 3.3V Birdirectional 3.3V Birdirectional 3.3V OUTPUT 5.0V OUTPUT www.national.com 15 16 17 18 19 20 21 22 23 the DUT board must leave this pin open. Maximum capacitor loading for this node is not to exceed 50uF. VDDIO Interface Supply always provided by the DUT board. Both the DUT board and the SPIO-4 board power their I/O drivers with this supply (except the I2C bus - which is always +3.3V). Only the SPI_A related signals on the GPSI-16 subset are affected by this I/O supply. Voltage Range: 1.6V to 5.5V. Capable of supplying 100mA. SCS2_A~ SerialBus A - Chip Select for device 2. DUT_PWR_Enable For those DUT boards that support intelligent power-up control, this signal from the SPIO-4 enables the DUT power regulators. 1.65 to 5.5V INPUT 1.65 to 5.5V 3.3V OUTPUT Available for implementation specific use. Refer to the DUT board manual. If unused, leave it open. (Possible use: DUT_RESET~) Available for implementation specific use. Refer to the DUT board manual. If unused, leave it open. Available for implementation specific use. Refer to the DUT board manual. If unused, leave it open. Available for implementation specific use. Refer to the DUT board manual. If unused, leave it open. Available for implementation specific use. Refer to the DUT board manual. If unused, leave it open. Available for implementation specific use. Refer to the DUT board manual. If unused, leave it open. 3.3V Available for implementation specific use. Refer to the DUT board manual. If unused, leave it open. 3.3V Available for implementation specific use. Refer to the DUT board manual. If unused, leave it open. 3.3V Available for implementation specific use. Refer to the DUT board manual. If unused, leave it open. 3.3V Available for implementation specific use. Refer to the DUT board manual. If unused, leave it open. 3.3V OUTPUT 3.3V 3.3V 3.3V 3.3V 3.3V If a second SPI bus is implemented, then use this pin as shown: SCS0_B~ SerialBus B - Chip Select for device 0. 24 If a second SPI bus is implemented, then use this pin as shown: SDRDY_B~ In certain SPI applications, if required, this pin serves as the DRDY~ signal from the DUT to the SPIO-4. 25 If a second SPI bus is implemented, then use this pin as shown: SCK_B Serial Bus B - Serial Clock from the master to the device. 26 If a second SPI bus is implemented, then use this pin as shown: SCS1_B~ SerialBus B - Chip Select for device 1. 27 If a second SPI bus is implemented, then use this pin as shown: SMISO_B National Semiconductor Page 11 www.national.com Serial Bus B - Data from the slave (device) to the master. The device may implement this as a tri-state signal that can be driven by multiple devices on Serial Bus B in a bussed fashion. The pull-up resistor, if required, is on the DUT board. 28 Available for implementation specific use. Refer to the DUT board manual. If unused, leave it open. 3.3V Available for implementation specific use. Refer to the DUT board manual. If unused, leave it open. 3.3V Available for implementation specific use. Refer to the DUT board manual. If unused, leave it open. 3.3V If a second SPI bus is implemented, then use this pin as shown: SCS2_B~ SerialBus B - Chip Select for device 2. 29 If a second SPI bus is implemented, then use this pin as shown: SMOSI_B Serial Bus B - Data from the master to the slave (device). 30 31 32 If a second SPI bus is implemented, then use this pin as shown: SCS3_B~ SerialBus B - Chip Select for device 3. Reserved for future use. The DUT board shall leave this pin open. GND 3.3V Table 4 GPSI-32 Signals 2.6 Auxiliary Interface The SPIO-4 Board can be connected to auxiliary test equipment through debug connector J4 located on the board. 2.7 Computer Interface The SPIO-4 Board communicates with a PC via standard USB 2.0 at high-speed (up to a 480 Mbits/sec signaling rate). It is fully backward compatible with USB 1.1 devices and cables. 2.8 Memory The SPIO-4 Board comes with 8M x 16bits of PSRAM for data storage. It is a single Micron MT45W8MW16BGX PSRAM configured for asynchronous accesses. In asynchronous configuration the fastest access speed is 70ns latency or approximately 14.2 MHz per 16 bit transfer. Both the processor and the FPGA have read/write access to the PSRAM. The processor's Static Memory Interface mastership is controlled by firmware with in the processor as there is no hardware mechanism to share the bus. 2.9 Power Requirements The SPIO-4 Data Capture Board can be solely powered via the USB interface power but can also be powered by external power supply. The SPIO-4 Data Capture Board consumes up to 500 mA of current depending on the DUT load. ADC evaluation boards differ widely in their power consumption - please consult the manual that came with your evaluation board, and verify if an external supply is required for your DUT board. External power can be supplied via J10 and must be greater than 4.5V and less than 6.0V DC with a current rating of at least 1A. National Semiconductor Page 12 www.national.com 3 SPIO-4 Bill of Materials Item 1 2 3 4 5 6 7 Description CAP CER 10000PF 25V Y5V 0603 CAP CER .47UF 10V X7R 0603 CAP .10UF 16V CERAMIC X7R 0603 Qty. 1 1 58 CAP CERAMIC 10PF 50V NP0 0603 CAP CER 15PF 50V C0G 5% 0603 CAP CER 4.7UF 10V Y5V 0603 CAP CER 10UF 6.3V Y5V 0603 2 4 5 22 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 CAP CER 1.0UF 10V X7R 0603 9 CAP CER 100UF 10V X5R 1210 3 CAP CER 10UF 10V X5R 0805 6 CAP CER 1.0UF 16V X7R 20% 1206 1 LED TOPLED 570NM GREEN CLR SMD 10 DIODE ZENER 6.2V 3W DO214AA 1 DIODE SCHOTTKY 1A 20V SOD-123 1 RES 0.0 OHM 1/2W 1210 SMD 1 PTC RESETTABLE 1.10A 16V 1812 1 CONN HEADER VERT 5POS .100 TIN 1 CON PWR JCK 2.0 X 6.5MM W/O SW 1 CONN HEADER 10POS 2MM VERT T/H 1 CONN HEADER VERT SGL 6POS GOLD 1 BERGSTIK II .100" SR STRAIGHT 1 CONN FEMALE 32POS DL .1" R/A TIN 1 CONN MICRO SD R/A HING TYPE SMD 1 CONN RCPT USB TYPE B R/A PCB 1 CONN HEADER 2.54MM 20POS GOLD 1 BERGSTIK II .100" SR STRAIGHT 1 INDUCTOR 10UH 100MA 0805 2 INDUCTOR 2.2UH 1.20A 20% 1210 3 FERRITE CHIP 2700 OHM 200MA 0805 3 TRANSISTOR NPN GP 40V SOT23 1 RES 33.0 OHM 1/10W 1% 0603 SMD 8 RES 39 OHM 1/10W 5% 0603 SMD 2 RES 10K OHM 1/10W 1% 0603 SMD 17 34 35 36 37 38 39 40 RES 46.4K OHM 1/10W 1% 0603 SMD RES 68K OHM 1/10W 5% 0603 SMD RES 1.5K OHM 1/10W 5% 0603 SMD RES 6.8K OHM 1/10W 1% 0603 SMD RES 100K OHM 1/10W 1% 0603 SMD RES 649 OHM 1/10W 1% 0603 SMD RES 0.0 OHM 1/10W 0603 SMD 5 1 7 1 2 1 15 41 42 43 44 45 46 47 RES 4.64K OHM 1/10W 1% 0603 SMD RES 121K OHM 1/10W 1% 0603 SMD RES 680K OHM 1/10W 5% 0603 SMD RES 9.1K OHM 1/10W 5% 0603 SMD RES 750 OHM 1/10W 1% 0603 SMD SWITCH TACT SPST W/O GND SMD PC TEST POINT MINIATURE SMT 1 1 1 1 6 2 14 48 49 50 51 52 53 54 55 56 57 ATSAM3U4EA-AU-ND 1 LP3910SQ-AA 1 LM2750LD-5.0CT-ND 1 IC LOAD SWITCH INTEGRATED SC70-6 1 IC PSRAM 128MBIT 70NS 54VFBGA 1 XC6SLX16-2CSG324C 1 IC BUS TRANSCVR 2BIT N-INV SM8 5 CRYSTAL 12.00 MHZ 8PF SMD 1 CRYSTAL 32.768KHZ 12.5PF SMD 1 PCB Fab 1 Reference C1 C103 C2,C4,C6,C7,C8,C9,C10,C11,C12,C14,C15,C16,C17,C18,C20,C2 3,C26,C27,C31,C33,C35,C36,C40,C41,C42,C43,C44,C46,C48,C5 0,C51,C52,C53,C54,C55,C56,C57,C60,C61,C64,C65,C66,C68,C6 9,C70,C71,C72,C74,C76,C79,C85,C93,C98,C99,C104,C105,C108 ,C112 C21,C78 C24,C25,C29,C30 C28,C32,C77,C84,C86 C3,C5,C13,C19,C22,C37,C38,C39,C45,C58,C62,C73,C75,C80,C8 2,C83,C87,C88,C89,C90,C91,C102 C34,C47,C49,C59,C63,C67,C81,C106,C109 C92,C100,C101 C94,C95,C97,C107,C110,C111 C96 D1,D2,D3,D4,D5,D6,D7,D8,D10,D11 D12 D9 F1 F2 J1 J10 J14 J2 J3 J6 J7 J8 J9 JP1 L1,L2 L3,L4,L5 L6,L7,L8 Q1 R13,R14,R15,R16,R17,R18,R19,R20 R2,R3 R21,R26,R30,R31,R32,R33,R34,R43,R46,R47,R48,R49,R60,R61, R64,R72,R85 R22,R23,R24,R25,R28 R29 R39,R41,R44,R45,R79,R80,R82 R4 R40,R62 R42 R5,R6,R27,R35,R37,R53,R55,R56,R57,R58,R59,R66,R74,R76,R7 8 R51 R52 R63 R86 R9,R10,R11,R12,R36,R38 SW1,SW2 TP1,TP3,TP4,TP5,TP7,TP11,TP12,TP13,TP14,TP15,TP16,TP17, TP18,TP19 U1 U11 U12 U14 U4 U5 U6,U7,U8,U9,U10 Y1 Y2 Fab National Semiconductor Page 13 Mfg. Name MURATA ELECTRONICS (VA) TAIYO YUDEN (VA) YAGEO (VA) Mfg. No. GRM188F51E103ZA01D LMK107B7474KA-T CC0603KRX7R7BB104 KEMET (VA) TDK CORPORATION (VA) MURATA ELECTRONICS (VA) TDK CORPORATION (VA) C0603C100J5GACTU C1608C0G1H150J GRM188F51A475ZE20D C1608Y5V0J106Z TAIYO YUDEN (VA) TAIYO YUDEN (VA) JOHANSON DIELECTRICS INC (VA) TDK CORPORATION (VA) OSRAM OPTO SEMICONDUCTORS INC(VA) MICRO COMMERCIAL CO (VA) MICRO COMMERCIAL CO (VA) VISHAY/DALE (VA) BOURNS INC (VA) TYCO ELECTRONICS AMP CUI INC 3M 3M FCI SULLINS CONNECTOR SOLUTIONS HIROSE ELECTRIC CO LTD (VA) FCI SULLINS CONNECTOR SOLUTIONS FCI MURATA ELECTRONICS (VA) TDK CORPORATION (VA) MURATA ELECTRONICS (VA) MICRO COMMERCIAL CO (VA) YAGEO (VA) PANASONIC - ECG (VA) STACKPOLE ELECTRONICS INC (VA) LMK107B7105KA-T LMK325BJ107MM-T 100R15X106KV4E C3216X7R1C105M/0.85 LG M67K-G1J2-24-0-2-R18-Z 3SMBJ5920B-TP MBRX120LF-TP CRCW12100000Z0EA MF-MSMF110/16-2 640454-5 PJ-037A 951110-8622-AR 961106-6404-AR 68000-203HLF PPTC162LJBN-RC DM3C-SF 61729-0010BLF SBH11-PBPC-D10-ST-BK 68001-202HLF LQM21FN100M70L NLCV32T-2R2M-PFR BLM21BD272SN1L MMBT3904-TP RC0603FR-0733RL ERJ-3GEYJ390V RMCF0603FT10K0 STACKPOLE ELECTRONICS INC (VA) PANASONIC - ECG (VA) STACKPOLE ELECTRONICS INC (VA) STACKPOLE ELECTRONICS INC (VA) STACKPOLE ELECTRONICS INC (VA) PANASONIC - ECG (VA) STACKPOLE ELECTRONICS INC (VA) RMCF0603FT46K4 ERJ-3GEYJ683V RMCF0603JT1K50 RMCF0603FT6K80 RMCF0603FT100K ERJ-3EKF6490V RMCF0603ZT0R00 PANASONIC - ECG (VA) STACKPOLE ELECTRONICS INC (VA) PANASONIC - ECG (VA) PANASONIC - ECG (VA) STACKPOLE ELECTRONICS INC (VA) OMRON ELECTRONICS INC-ECB DIV (VA) KEYSTONE ELECTRONICS (VA) ERJ-3EKF4641V RMCF0603FT121K ERJ-3GEYJ684V ERJ-3GEYJ912V RMCF0603FT750R B3U-1000P 5015 FAIRCHILD SEMICONDUCTOR (VA) MICRON TECHNOLOGY INC (VA) TEXAS INSTRUMENTS (VA) NDK (VA) ABRACON CORPORATION (VA) National Semiconductor ATSAM3U4EA-AU-ND LP3910SQ-AA LM2750LD-5.0CT-ND FDG6342L MT45W8MW16BGX-701 IT TR XC6SLX16-2CSG324C SN74LVC2T45DCTR NX5032GA 12MHZ AT-W ABS10-32.768KHZ-T 551600474-001 www.national.com 4 SPIO-4 Schematics Following pages show the schematics of the board. These are provided for general information purposes only. National reserves the right to make modifications to the board design at any time. National Semiconductor Page 14 www.national.com BY USING THIS PRODUCT, YOU ARE AGREEING TO BE BOUND BY THE TERMS AND CONDITIONS OF NATIONAL SEMICONDUCTOR'S END USER LICENSE AGREEMENT. DO NOT USE THIS PRODUCT UNTIL YOU HAVE READ AND AGREED TO THE TERMS AND CONDITIONS OF THAT AGREEMENT. IF YOU DO NOT AGREE WITH THEM, CONTACT THE VENDOR WITHIN TEN (10) DAYS OF RECEIPT FOR INSTRUCTIONS ON RETURN OF THE UNUSED PRODUCT FOR A REFUND OF THE PURCHASE PRICE PAID, IF ANY. The SPIO-4 Board is intended for product evaluation purposes only and is not intended for resale to end consumers, is not authorized for such use and is not designed for compliance with European EMC Directive 89/336/EEC, or for compliance with any other electromagnetic compatibility requirements. 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National Semiconductor Page 15 www.national.com 8 7 6 5 4 3 2 1 SPIO45 Interface Board Block Diag E E D D C C B B A A National Semiconductor, Santa Clara, CA 95052 Title Size SPIO4 Block Diagram 2010 National Semiconductor Document Number B Date: 8 7 6 5 4 3 Rev 2.0 870600474-001 Wednesday, November 17, 2010 2 Sheet 1 of 1 12 8 7 6 5 4 3 2 1 Atmel ARM Microcontroller - Power, Debug, Analog 3p3V JP1 E JP U1B SAM3U VANA E C1 137 138 142 135 136 10nF 9 R1 RSTN DNS ERASE TEST JTAGSEL FWUP SHDN SW1 A B 39 VBG DGND DGND 11 NRST_PWR 9 9 9 9 9 9 D DHSD_P DHSD_M R2 R3 39R 39R DFSD_M DFSD_P 16 27 44 50 86 125 C5 10uF DGND VCORE DGND C6 0.1uF C7 0.1uF C8 0.1uF C9 0.1uF C10 0.1uF C11 0.1uF 17 51 85 104 127 VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 XIN XOUT C4 0.1uF C3 10uF 34 VDDPLL XIN32 XOUT32 36 35 XIN_CLK XOUT1 C2 0.1uF VDDCORE1 VDDCORE2 VDDCORE3 VDDCORE4 VDDCORE5 VDDCORE6 DHSDP DHSDM DFSDM DFSDP 144 143 XIN32_CLK XOUT32 2 VDDOUT TDI TDO/TRACESWO TMS/SWDIO TCK/SWCLK 37 38 41 42 3p3V 3 VDDIN NRST NRSTB 1 4 7 9 TDI TDO TMS TCK ADVREF AD12BVREF VBG 11 141 74 76 C12 0.1uF C13 10uF D DGND 3p3V VUTMI 18 52 60 90 126 VBG XIN32_CLK C25 GND1 GND2 GND3 GND4 GND5 15pF 140 C R4 6.8K Y2 32.768KHz 15pF DGND 73 GNDANA 139 VDDBU 3p3V DGND 0R R66 DGND 3p3V XIN_CLK C24 C19 10uF C C27 0.1uF 3p3V VUTMI C18 0.1uF C23 0.1uF VDDBU L1 10uH/100mA C17 0.1uF VANA GNDUTMI DGND DGND C16 0.1uF GNDPLL 75 C30 C15 0.1uF DGND VDDANA 43 XOUT32 C14 0.1uF C20 0.1uF GNDBU 33 C21 10pF 40 VDDUTMI DGND C59 1.0uF 15pF DGND B C26 0.1uF R5 0R Y1 12.000MHz C22 10uF XOUT1 C28 B C29 15pF DGND 3p3V 4.7uF DGND DGND VANA R69 DNS 499R 3p3V L2 10uH/100mA CLK_12MHZ2_R 3p3V U2 1 R67 CLK_12MHZ 5 2 DNS 3p3V C31 0.1uF R6 0R U3 1 C32 A 1 3 2 4.7uF DGND OE VDD GND OUT 4 3 R8 CLK_12MHZA_R 2 CLK_12MHZA GND VCC 1Y 2Y 1.0K 6 4 DNS CLK_12MHZ1_R GND OUT R68 Size 6 5 DGND 4 XIN32_CLK DNS Date: 3 A SPIO4 CPU Power 2010 National Semiconductor Document Number B 7 R7 CLK_32K_R National Semiconductor, Santa Clara, CA 95052 Title R71 DNS DGND 8 3 DNS XIN_CLK DGND 4 DGND R70 DNS 74LVC2G06 DNS DNS OSCIL_12M_SMD_3.3V 1A 2A 5 VDD DNS OSC_32768HZ_SMD VCORE U13 OE Rev 2.0 870600474-001 Wednesday, November 17, 2010 2 Sheet 2 of 1 12 8 7 6 5 4 3 2 1 Atmel ARM Microcontroller, Port Connection D[15:0] 4,5 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D9 D11 D12 D13 D14 D15 U1A SAM3U E 9,11 VUSB_DET 8 CD 7 DUTCLKIN 8 CK 8 CDA 8 DA0 8 DA1 8 DA2 8 DA3 11 SDA 11 SCL CK CDA DA0 DA1 DA2 DA3 RXD_IN TXD_OUT 1 TP19 CD TP17 DUT_SDA 1 7 7 7 7 DUT_SCL CPUMISO_A CPU_MOSI_A CPU_SCLK_A CPU_CS0N_A USNAP_SCLK_N USNAP_MOSI USNAP_MISO D 11 11 ONSTAT USBISEL USNAP_SEL_N USNAP_IRQ_N TP4 1 TP7 7 DUT_SDA 7 DUT_SCL 5 SCC_TD 5 PCK 5 SCC_CLK 7 DUTDRDYN_A 5 SCC_TF 4 SRAM_CNTRL_REG 1 SDA SCL A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 C 7 CPU_CS2N_A 4,5 NBS1 NBS1 109 111 113 115 117 119 121 123 128 130 132 133 134 87 88 91 93 95 99 100 101 102 77 103 105 106 107 64 45 46 78 48 110 112 114 116 118 120 122 124 129 131 89 92 94 98 28 81 PA0/WKUP0 PA1/WKUP1 PA2/WKUP2 PA3/CK PA4/CDA PA5/DA0 PA6/DA1 PA7/DA2 PA8/DA3 PA9/TWD0 PA10/TWCK0 PA11/URXD PA12/UTXD PA13/MISO PA14/MOSI PA15/SPCK PA16/NPCS0 PA17/WKUP7 PA18/WKUP8 PA19/WKUP9 PA20/TXD1 PA21/RXD1 PA22/RTS1 PA23/CTS2 PA24/WKUP11 PA25/WKUP12 PA26/TD PA27/PCK0 PA28/TK PA29/PWMH1 PA30/TF PA31/RF PB0/PWMH0 PB1/PWMH1 PB2/PWMH2 PB3/AD12BAD2 PB4/AD12BAD3 PB5/AD1 PB6/D15 PB7/A0/NBS0 PB8/A1 PB9/D0 PB10/D1 PB11/D2 PB12/D3 PB13/D4 PB14/D5 PB15/D6 PB16/D7 PB17/NANDOE PB18/NANDWE PB19/NRD PB20/NCS0 PB21/A21/NANDALE PB22/A22/NANDCLE PB23/NWR0/NWE PB24/NANDRDY PB25/D8 PB26/D9 PB27/D10 PB28/D11 PB29/D12 PB30/D13 PB31/D14 PC0/A2 PC1/A3 PC2/A4 PC3/A5 PC4/A6 PC5/A7 PC6/A8 PC7/A9 PC8/A10 PC9/A11 PC10/A12 PC11/A13 PC12/NCS1 PC13/RXD3 PC14/NPCS2 PC15/NWR1/NBS1 PC16/NCS2 PC17/AD12BAD6 PC18/AD12BAD7 PC19/NPCS1 PC20/A14 PC21/A15 PC22/A16 PC23/A17 PC24/A18 PC25/A19 PC26/PWMH2 PC27/A23 PC28/DA4 PC29/DA5 PC30/DA6 PC31/DA7 53 55 57 79 80 65 66 67 68 31 30 59 61 62 29 97 96 26 25 24 23 21 20 19 15 14 13 12 10 8 6 5 82 83 84 32 108 22 47 49 54 56 58 63 69 70 71 72 FPGA_INIT_N 5 FPGA_M0 5 FPGA_M1 5 FPGA_PRGM_N 6 FPGA_DONE_N 6 DUT_PWR_EN 7 D15 NBS0 A1 D0 D1 D2 D3 D4 D5 D6 D7 NBS0 4,5 E A[23:1] IRQ_PWR_N 11 DUT_PRSNT_N 7 NRD 4,5 NCS0 4,5 NRD NCS0 A21 A22 NWE NWE PCK1 D8 D9 D10 D11 D12 D13 D14 4,5 5 NCS2 5 NCS3 5 NWAIT 4,5 CPU_CS1N_A 7 A14 A15 A16 A17 A18 A19 A20 A23 USNAP_RST_N DUT_3VEN DUT_5VEN 4,5 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 D C 11 11 B B USNAP INTERFACE J14 A 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 PCB REVISION RESISTORS USNAP_SEL_N USNAP_IRQ_N USNAP_SCLK_N USNAP_MOSI USNAP_MISO USNAP_RST_N USNAP_RST_N UART Debug Interface header R82 1.5K J1 USNAP_IRQ_N 1 2 3 4 5 R83 DNS 3p3V DGND R82 REV ___ R83 ___ PCB ______ DNS DNS A 2mm_hdr_6pin 1 2 3 4 5 RXD_IN TXD_OUT 3p3V Title hdr_5pin 1.5K DNS B Size DNS 1.5K C Date: 7 6 5 SPIO4 ARM CPU Ports 2010 National Semiconductor Document Number B DGND DGND 8 A National Semiconductor, Santa Clara, CA 95052 4 3 Rev 2.0 870600474-001 Wednesday, November 17, 2010 2 Sheet 3 of 1 12 5 4 3 2 1 D D 3,5 3,5 A[23:1] U4 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 C B 3,5 3,5 3,5 3,5 NCS0 NRD NWE 3,5 3,5 NBS1 NBS0 A3 A4 A5 B3 B4 C3 C4 D4 H2 H3 H4 H5 G3 G4 F3 F4 E4 D3 H1 G2 H6 E3 J4 B5 A2 G5 B2 A1 A6 J3 J2 SRAM_CNTRL_REG A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 CS OE WE D[15:0] MT45W8MW16BGX DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 WAIT RFU3 RFU4 B6 C5 C6 D5 E5 F5 F6 G6 B1 C1 C2 D2 E2 F2 F1 G1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 C J1 NWAIT 3,5 J5 J6 3p3V 1p8V UB LB VCCQ VCC CRE ADV CLK VSSQ VSSQ 3p3V E1 D6 B C33 0.1uF C34 1.0uF C35 0.1uF D1 E6 MT45W8MW16BGX DGND C36 0.1uF C37 10uF DGND DGND A A National Semiconductor, Santa Clara, CA 95052 Title Size B Date: 5 4 3 2 SPIO4 PSRAM 2010 National Semiconductor Document Number Rev 2.0 870600474-001 Wednesday, November 17, 2010 Sheet 1 4 of 12 5 3,4 4 2 1 D[15:0] D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D9 D11 D12 D13 D14 D15 D 3,4 3 U5-2 NOTE:D0-7 SWAPPED GOING INTO CONFIG BITS U5-3 D2 3 FPGA_INIT_N 3,4 NCS0 3,4 NWE 3,4 3,4 3,4 3,4 NRD NBS0 NBS1 NWAIT NCS0 D4 D15 D14 D13 D12 D11 D10 D9 D8 A[23:1] A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 C NRD NBS0 NBS1 NWAIT FPGA_CFG_CSN D5 D6 3 FPGA_M0 D3 3 NCS2 CCLK R15 3 D1 FPGA_CCLK DATA_D7_CFG_D0 FPGA_M1 2 CLK_12MHZ 3 PCK1 D0 R3 U3 T4 U5 T5 V7 U7 T7 V8 U8 T8 V10 U10 T10 U11 T11 V13 U13 T13 V14 T14 T15 V16 U16 V6 V3 V4 V5 V9 T6 V11 T3 R15 R13 N12 P12 R11 R10 R8 T9 R7 R5 N5 P6 3p3V IO_L62P_D5_2 VCCO_2 IO_L65P_INIT_B_2 VCCO_2 IO_L63P_2 VCCO_2 IO_L49P_D3_2 VCCO_2 IO_L48N_RDWR_B_VREF_2 VCCO_2 IO_L43N_2 VCCO_2 IO_L43P_2 IO_L46N_2 IO_L41N_VREF_2 IO_L41P_2 IO_L31N_GCLK30_D15_2 IO_L30N_GCLK0_USERCCLK_2 IO_L30P_GCLK1_D13_2 IO_L29N_GCLK2_2 IO_L23P_2 IO_L16N_VREF_2 IO_L14N_D12_2 IO_L14P_D11_2 IO_L3N_MOSI_CSI_B_MISO0_2 IO_L12N_D2_MISO3_2 IO_L12P_D1_MISO2_2 IO_L1N_M0_CMPMISO_2 IO_L2N_CMPMOSI_2 IO_L2P_CMPCLK_2 IO_L45N_2 IO_L65N_CSO_B_2 IO_L63N_2 IO_L49N_D4_2 IO_L32N_GCLK28_2 IO_L45P_2 IO_L23N_2 IO_L62N_D6_2 IO_L1P_CCLK_2 IO_L3P_D0_DIN_MISO_MISO1_2 IO_L13P_M1_2 IO_L13N_D10_2 IO_L16P_2 IO_L29P_GCLK3_2 IO_L31P_GCLK31_D14_2 IO_L32P_GCLK29_2 IO_L46P_2 IO_L48P_D7_2 IO_L64P_D8_2 IO_L64N_D9_2 P9 R12 R6 U14 U4 U9 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 XC6SLX9CSG324 B REQUIRED SIGNALS TO CONFIG FPGA VIA SERIAL OR BYTE WIDE (SELECTMAP) D7 R5 CSI_B T13 D6 T3 RDWR_B T5 D5 R3 D4 V5 INIT U3 D3 U5 M1 N12 D2 V14 M0 T15 D1 T14 DO_DIN R13 D7 0R R74 3 3p3V IO_L44N_A2_M1DQ7_1 VCCO_1 IO_L45N_A0_M1LDQSN_1 VCCO_1 IO_L45P_A1_M1LDQS_1 VCCO_1 IO_L41N_GCLK8_M1CASN_1 VCCO_1 IO_L44P_A3_M1DQ6_1 VCCO_1 IO_L42P_GCLK7_M1UDM_1 VCCO_1 IO_L41P_GCLK9_IRDY1_M1RASN_1 IO_L36N_A8_M1BA1_1 IO_L29P_A23_M1A13_1 IO_L29N_A22_M1A14_1 IO_L31P_A19_M1CKE_1 IO_L31N_A18_M1A12_1 IO_L33P_A15_M1A10_1 IO_L33N_A14_M1A4_1 IO_L35N_A10_M1A2_1 IO_L35P_A11_M1A7_1 IO_L1N_A24_VREF_1 IO_L1P_A25_1 IO_L38N_A4_M1CLKN_1 IO_L38P_A5_M1CLK_1 IO_L43N_GCLK4_M1DQ5_1 IO_L43P_GCLK5_M1DQ4_1 IO_L37N_A6_M1A1_1 IO_L37P_A7_M1A0_1 IO_L49N_M1DQ11_1 IO_L49P_M1DQ10_1 IO_L51P_M1DQ12_1 IO_L52P_M1DQ14_1 IO_L48N_M1DQ9_1 IO_L48P_HDC_M1DQ8_1 IO_L50N_M1UDQSN_1 IO_L74P_AWAKE_1 IO_L74N_DOUT_BUSY_1 IO_L47N_LDC_M1DQ1_1 IO_L47P_FWE_B_M1DQ0_1 IO_L50P_M1UDQS_1 IO_L53N_VREF_1 IO_L46N_FOE_B_M1DQ3_1 IO_L46P_FCS_B_M1DQ2_1 IO_L42N_GCLK6_TRDY1_M1LDM_1 IO_L51N_M1DQ13_1 IO_L52N_M1DQ15_1 IO_L30P_A21_M1RESET_1 IO_L30N_A20_M1A11_1 IO_L32P_A17_M1A8_1 IO_L32N_A16_M1A9_1 IO_L34P_A13_M1WE_1 IO_L34N_A12_M1BA2_1 IO_L36P_A9_M1BA0_1 IO_L39P_M1A3_1 IO_L39N_M1ODT_1 IO_L40P_GCLK11_M1A5_1 IO_L40N_GCLK10_M1A6_1 IO_L53P_1 IO_L61P_1 IO_L61N_1 D C B XC6SLX9CSG324 3p3V DNS R73 C47 1.0uF NCS3 0R R76 3 E17 G15 J14 J17 M15 R17 DATA_D7_CFG_D0 SCC_TD 3 J18 K18 K17 K16 J16 L15 K15 H14 C17 C18 D17 D18 E16 E18 F18 F17 F16 F15 G18 G16 H18 H17 H16 H15 P18 P17 T17 U17 N18 N17 N16 P15 P16 M18 M16 N15 N14 L18 L17 L16 T18 U18 F14 G14 H12 G13 K12 K13 H13 J13 K14 L12 L13 M14 L14 M13 C40 0.1uF C41 0.1uF C42 0.1uF C43 0.1uF C44 0.1uF C45 10uF FPGA_CFG_CSN SCC_TF DNS R75 DGND DGND A A 3 PCK 0R R78 3 National Semiconductor, Santa Clara, CA 95052 FPGA_CCLK SCC_CLK DNS R77 RSTUFF OPTIONS TO SUPPORT Title SERIAL AND PARALLEL FPGA CONFIG Size B Date: 5 4 3 2 SPIO4 FPGA SRAM & Configuration Intrfc 2010 National Semiconductor Document Number Rev 2.0 870600474-001 Wednesday, November 17, 2010 Sheet 1 5 of 12 5 4 3 2 1 XILINX JTAG HDR FOR CONFIG OR CHIPSCOPE 3p3V JUMER TO SELECT BANK VOUT 3p3V DGND DBG1 DBG3 DBG5 DBG7 DBG9 DBG11 DBG13 DBG15 DBG17 DBG19 DBG21 DBG23 DBG25 DBG27 DBG29 DBG31 DBG33 DBG35 DBG37 DBG39 DBG41 DBG43 DBG45 DBG47 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 DBG2 DBG4 DBG6 DBG8 DBG10 DBG12 DBG14 DBG16 DBG18 DBG20 DBG22 DBG24 DBG26 DBG28 DBG30 DBG32 DBG34 DBG36 DBG38 DBG40 DBG42 DBG44 DBG46 DBG48 U5-4 DBG1 DBG2 DBG3 DBG4 DBG5 DBG6 DBG7 DBG8 DBG9 DBG10 DBG11 DBG12 DBG13 DBG14 DBG15 DBG16 DBG17 DBG18 DBG19 DBG20 DBG21 DBG22 DBG23 DBG24 DBG25 DBG26 DBG27 DBG28 DBG29 DBG30 DBG31 3p3V 50PIN_MALE_HDR B J3 DBG32 DBG33 DBG34 DBG35 DBG36 DBG37 DBG38 DBG39 DBG40 DBG41 DBG42 DBG43 DBG44 DBG45 DBG46 DBG47 DBG48 3p3V R9 750R R10 750R R11 750R R12 750R D1 D2 GRN_LED GRN_LED D3 GRN_LED D3 E4 E3 F6 F5 F4 F3 G6 H7 H6 H5 H4 H3 J7 J6 K6 J3 K3 K4 K5 L5 L7 L6 L4 C2 C1 D2 D1 E1 F2 F1 G1 G3 H1 H2 J1 K2 K1 L1 L2 M1 N2 N1 N3 P1 P2 P3 T1 T2 U1 U2 M3 P4 N4 M5 L3 IO_L54N_M3A11_3 VCCO_3 IO_L54P_M3RESET_3 VCCO_3 IO_L50P_M3WE_3 VCCO_3 IO_L55P_M3A13_3 VCCO_3 IO_L55N_M3A14_3 VCCO_3 IO_L51P_M3A10_3 VCCO_3 IO_L51N_M3A4_3 IO_L53N_M3A12_3 IO_L53P_M3CKE_3 IO_L49P_M3A7_3 IO_L49N_M3A2_3 IO_L44P_GCLK21_M3A5_3 IO_L44N_GCLK20_M3A6_3 IO_L47P_M3A0_3 IO_L47N_M3A1_3 IO_L45N_M3ODT_3 IO_L40P_M3DQ6_3 IO_L42N_GCLK24_M3LDM_3 IO_L42P_GCLK25_TRDY2_M3UDM_3 IO_L43N_GCLK22_IRDY2_M3CASN_3 IO_L43P_GCLK23_M3RASN_3 IO_L45P_M3A3_3 IO_L31P_3 IO_L39P_M3LDQS_3 IO_L83P_3 IO_L83N_VREF_3 IO_L52P_M3A8_3 IO_L52N_M3A9_3 IO_L50N_M3BA2_3 IO_L48P_M3BA0_3 IO_L48N_M3BA1_3 IO_L46N_M3CLKN_3 IO_L46P_M3CLK_3 IO_L41N_GCLK26_M3DQ5_3 IO_L41P_GCLK27_M3DQ4_3 IO_L40N_M3DQ7_3 IO_L38P_M3DQ2_3 IO_L38N_M3DQ3_3 IO_L37N_M3DQ1_3 IO_L37P_M3DQ0_3 IO_L36N_M3DQ9_3 IO_L35P_M3DQ10_3 IO_L35N_M3DQ11_3 IO_L1N_VREF_3 IO_L34N_M3UDQSN_3 IO_L34P_M3UDQS_3 IO_L2N_3 IO_L33N_M3DQ13_3 IO_L33P_M3DQ12_3 IO_L32N_M3DQ15_3 IO_L32P_M3DQ14_3 IO_L36P_M3DQ8_3 IO_L2P_3 IO_L1P_3 IO_L31N_VREF_3 IO_L39N_M3LDQSN_3 D4 GRN_LED E2 G4 J2 J5 M4 R2 BNK3_VDDIO DGND 3p3V hdr_3pin hdr_6pin R72 10.0K VTEST 3 3p3V U5-5 A17 D15 B18 D16 R16 P13 V17 V2 A1 A18 B13 B7 C16 C3 D10 D5 E15 G12 G17 G2 G5 H10 H8 J11 J15 J4 J9 K10 K8 L11 L9 FPGA_TCK FPGA_TDI FPGA_TMS FPGA_TDO DGND FPGA_DONE_N 3 FPGA_PRGM_N PROGRAM V2 DONE V17 TP20 1 U5-6 E7 E8 F7 E6 G8 F8 G11 F10 F11 E11 D12 C12 C13 A13 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18 NC19 NC20 NC21 NC22 NC23 NC24 NC25 NC26 NC27 NC28 NC29 NC30 NC31 NC32 F12 E12 U15 V15 T12 V12 N10 P11 M10 N9 M11 N11 N7 P8 M8 N8 N6 P7 TCK TDI TMS TDO SUSPEND CMPCS_B_2 DONE_2 PROGRAM_B_2 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND DGND XC6SLX9CSG324 B1 B17 E14 E5 E9 G10 J12 K7 M9 P10 P14 P5 G7 H11 H9 J10 J8 K11 K9 L10 L8 M12 M7 M17 M2 M6 N13 R1 R14 R18 R4 R9 T16 U12 U6 V1 V18 1p2V C DGND B C53 0.1uF C54 0.1uF C55 0.1uF C56 0.1uF C57 0.1uF 1p2V C58 10uF C101 100uF C50 0.1uF C51 0.1uF C52 0.1uF C60 0.1uF C61 0.1uF 3p3V C100 100uF C62 10uF A TP1 C63 1.0uF TP3 National Semiconductor, Santa Clara, CA 95052 DGND DGND DGND DGND Title SPIO4 FPGA DEBUG, JTAG Interfaces & Pwr Size B DGND Date: 5 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT GND GND GND GND GND GND GND GND GND GND GND GND GND GND XC6SLX9CSG324 BNK3_VDDIO C49 1.0uF 1 2 3 D XC6SLX9CSG324 A C48 0.1uF 1 2 3 1 2 3 4 5 6 1 C 1 2 3 4 5 6 J4 1 D J2 4 3 2 2010 National Semiconductor Document Number Rev 2.0 870600474-001 Wednesday, November 17, 2010 Sheet 1 6 of 12 5 4 3 2 1 3p3V DUT INPUT LEVEL SHIFTERS U6 8 1 VCCB VCCA DUT_VDDIO 7 6 REF_CLKA SDRDYN_A B1 B2 A1 A2 DIRA2B GND D 7 6 SMISO_A VCCB VCCA B1 B2 A1 A2 DIRA2B GND DUTCLKIN_R R14 33R DUTDRDYN_R 7 6 SCS1N_A_R R17 33R SCLK_A B1 B2 A1 A2 SCLK_A_R DIRA2B GND D 1 U5-1 DGND R15 33R 2 3 DUTMISO_A_R 5 4 CPUMISO_A_R DUTMISO_A CPUMISO_A 3 R53 0R RSTUFF OPTIONS TO SUPPORT CPU ONLY 8 R18 33R SCS0N_A 7 6 SCS0N_A_R R19 33R SMOSI_A VCCB VCCA B1 B2 A1 A2 SMOSI_A_R DIRA2B GND R20 33R SCS2N_A 7 6 SCS2N_A_R VCCB VCCA B1 B2 A1 A2 DIRA2B GND CAPABILITY (NO FPGA) 3p3V CPU_CS1N_A 3 R55 0R DUTCS1N_A DUTSCLK_A 5 4 CPU_SCLK_A 3 R59 0R 1 SCS0N_B SCLK_B SMISO_B SMOSI_B SDRDYN_B SCS1N_B SCS2N_B SCS3N_B DGND CPU_CS0N_A 3 2 3 R56 0R DUTCS0N_A DUTMOSI_A 5 4 CPU_MOSI_A 3 R57 0R SN74LVC2T45SSOP U10 8 DGND 2 3 SN74LVC2T45SSOP U9 C 3 3p3V DUT OUTPUT LEVEL SHIFTERS U8 8 1 VCCB VCCA R16 33R DUTDRDYN_A 5 4 SN74LVC2T45SSOP SCS1N_A DUTCLKIN 3 DUTCLKIN 2 3 SN74LVC2T45SSOP U7 8 R13 33R 1 DGND DUTCS2N_A 2 3 CPU_CS2N_A 3 R58 0R 5 4 SN74LVC2T45SSOP DGND C99 0.1uF C98 0.1uF C70 0.1uF C71 0.1uF C72 0.1uF C73 10uF DUT_PWR_EN C68 0.1uF B C69 0.1uF C105 0.1uF C104 0.1uF C106 1.0uF A8 A11 A12 A10 A9 A14 A15 A16 A3 A5 A6 A4 A7 D4 C4 B2 A2 D6 C6 B3 B4 C5 C7 B6 D8 C8 B8 D9 C9 B9 D11 C11 C10 G9 F9 B11 B12 B14 F13 E13 C15 D14 C14 B16 IO_L33N_0 VCCO_0 IO_L39N_0 VCCO_0 IO_L41N_0 VCCO_0 IO_L37N_GCLK12_0 VCCO_0 IO_L35N_GCLK16_0 VCCO_0 IO_L62N_VREF_0 VCCO_0 IO_L64N_SCP4_0 IO_L66N_SCP0_0 IO_L4N_0 IO_L6N_0 IO_L8N_VREF_0 IO_L5N_0 IO_L10N_0 IO_L1P_HSWAPEN_0 IO_L1N_VREF_0 IO_L2P_0 IO_L2N_0 IO_L3P_0 IO_L3N_0 IO_L4P_0 IO_L5P_0 IO_L6P_0 IO_L10P_0 IO_L8P_0 IO_L11P_0 IO_L11N_0 IO_L33P_0 IO_L34P_GCLK19_0 IO_L34N_GCLK18_0 IO_L35P_GCLK17_0 IO_L36P_GCLK15_0 IO_L36N_GCLK14_0 IO_L37P_GCLK13_0 IO_L38P_0 IO_L38N_VREF_0 IO_L39P_0 IO_L41P_0 IO_L62P_0 IO_L63P_SCP7_0 IO_L63N_SCP6_0 IO_L64P_SCP5_0 IO_L65P_SCP3_0 IO_L65N_SCP2_0 IO_L66P_SCP1_0 B10 B15 B5 D13 D7 E10 C B XC6SLX9CSG324 DGND DGND DGND R54 DNS DUT_PRSNT_N 3 J6 3 DUT_SDA 3p3V_DUT 11 DUT_VDDIO 3 DUT_PWR_EN SCS0N_A SCLK_A SMISO_A SMOSI_A REF_CLKA DUT_SDA DUT_VDDIO DUT_PWR_EN C109 1.0uF A SCS0N_B SCLK_B SMISO_B SMOSI_B DGND 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 SDRDYN_A SCS1N_A DUT_SCL SCS2N_A 3p3V_DUT DUT_SCL 3 DGND C103 0.47uF 5p0V_DUT SDRDYN_B SCS1N_B SCS2N_B SCS3N_B C46 0.1uF C108 0.1uF C67 1.0uF C66 0.1uF C64 0.1uF DGND A DGND National Semiconductor, Santa Clara, CA 95052 Title DUT_SCL R80 1.5K DUT_SDA Size B Date: 5 C65 0.1uF 5VDUT_FLTERD 32PIN_FEM_HDR_RA R79 1.5K 3p3V 4 3 2 SPIO4 FPGA GPSI32 Intrfc 2010 National Semiconductor Document Number Rev 2.0 870600474-001 Wednesday, November 17, 2010 Sheet 1 7 of 12 8 7 6 5 4 3 2 1 Micro SD Card E E 3p3V 3p3V R22 46.4K R21 10.0K R23 46.4K R24 46.4K 3p3V R25 46.4K R26 10.0K J7 D 3 3 3 DA2 DA3 CDA 3 CK 3 3 DA0 DA1 1 2 3 4 5 6 7 8 DA2 DA3 CDA CK DA0 DA1 DAT2 CD/DAT3 CMD VDD CLK VSS DAT0 DAT1 CD GND1 GND2 GND3 GND4 13 CD CD D 3 9 10 11 12 MICRO_SD DGND DGND C C 3p3V C74 0.1uF C75 10uF DGND B B A A National Semiconductor, Santa Clara, CA 95052 Title Size SPIO4 SD Card 2010 National Semiconductor Document Number B Date: 8 7 6 5 4 3 Rev 2.0 870600474-001 Wednesday, November 17, 2010 2 Sheet 8 of 1 12 8 7 6 5 4 3 2 1 USB, CPU JTAG E E J8 USB TYPE B PORT R27 D 2 2 6 5 3 2 4 1 VUSB_RTN DHSD_P DHSD_M VUSB_DET 3,11 VUSB_DET 0R R28 46.4K 0R VUSB R29 68K C78 10pF C76 0.1uF C77 E_GND1 E_GND0 D+ DGND VBUS D VUSB_IN F1 4.7uF DGND DGND DGND DGND C C 3p3V R30 10.0K R31 10.0K R32 10.0K R33 10.0K R34 10.0K J9 IDC20-2.54mm 2 2 2 TDI TMS TCK 2 2 TDO RSTN B R35 0R 1 3 5 7 9 11 13 15 17 19 VTref Vsupply nTRST GND1 TDI GND2 TMS GND3 TCK GND4 RTCK GND5 TDO GND6 nSRST GND7 DBGRQ GND8 DBGACK GND9 2 4 6 8 10 12 14 16 18 20 C79 0.1uF C80 10uF B DGND DGND A A National Semiconductor, Santa Clara, CA 95052 Title Size SPIO4 USB JTAG 2010 National Semiconductor Document Number B Date: 8 7 6 5 4 3 Rev 2.0 870600474-001 Wednesday, November 17, 2010 2 Sheet 9 of 1 12 8 7 6 5 4 3 2 1 E E D D C C B B A A National Semiconductor, Santa Clara, CA 95052 Title Size SPIO4 Power Block Diagram 2010 National Semiconductor Document Number B Date: 8 7 6 5 4 3 Rev 2.0 870600474-001 Wednesday, November 17, 2010 2 Sheet 10 of 1 12 8 7 6 5 4 3 2 1 3p3V 3.3V, 1.2V, 1.8V, DUT Power Supply out 7 21 22 36 VIN 5VIN C86 PTC_1A_1812 D12 DIODE ZENER 2 RING in 2 C38 4.7uF C39 10uF C87 10uF C82 10uF C83 10uF C84 10uF 4.7uF C85 0.1uF 46 42 41 DGND PJ037A DGND DGND 47 R44 1.5K 3p3V 45 VUSB R45 1.5K VIN1 VIN2 VIN3 VIN4 VLDO1 VLDO2 VFB1 VBUCK1 BCKGND1 VDD1 VDD2 VDD3 VDDIO VFB2 VBUCK2 BCKGND2 CHG_DET USBPWR VBBFB VBBOUT VBBL1 VBBL2 BBGND1 BBGND2 VBATT 3 SDA 3 SCL SW2 A B 29 27 PWR_ON 26 17 5 9 37 38 D DGND R49 10.0K TP_PWRACK TP_USBSP 1 TP9 DGND 3 USBISEL TP10 1 2 44 43 VBATT C102 J12 3p3V + - TP_PWRACK 1 2 10uF C92 100uF 1 TMP_SNS 12 11 DNS R61 10.0K TP8 I2C_SDA I2C_SCL ON/~OFF BUCK1EN LDO2EN POWERACK USBSUSP USBISEL ~NRST ONSTAT ~IRQB CHG STAT VBATT1 VBATT2 VBATT3 VREFH I_SEN I_REF TS ADC1 ADC2 DGND AGND DAP LP3910 GRN_LED C81 1.0uF DGND 8 6 3p3V_DUT R36 750R 5p0V_DUT R39 1.5K C88 1 1V2_SW D8 2 L3 2.2uH 10uF C89 GRN_LED 3p3V 28 25 23 24 10uF DGND R41 1.5K 3V3_DUT_SW 2 L4 DGND 31 32 35 33 34 39 DGND 2.2uH GRN_LED C90 3p3V 3p3V 3p3V 10uF DGND 3V3_D_SW1 1 2.2uH R46 R47 R48 10.0K 10.0K 10.0K C91 DGND GRN_LED 1p2V 1 R51 IREF 4.64k_1% R52 Q1 R43 10.0K MMBT3904 TP21 1 VREFH ISEN D 1 NRST_PWR 2 ONSTAT 3 IRQ_PWR_N 3 TP_CHG TP_STAT 4 10 48 D11 650 10uF DGND 3V3_D_SW2 14 30 13 15 16 R42 2 L5 D10 VIN 1 E GRN_LED 1p2V 18 20 19 D7 1p8V 3 TIP D9 1 F2 D6 2 U11 DIODE_SCHOTTKY_1A 1 1 R37 0R VTEST TP5 J10 D5 GRN_LED 1p8V E R38 750R TP22 C93 0.1uF 121K 40 3 49 DGND DGND DGND 1 3,9 J13 1 2 3 C 1 2 3 7 VUSB_DET DGND R60 DUT_VDDIO 10.0K C DUT_VDDIO_MEAS DNS R86 9.2K R62 100K DGND Connector for using LI-Ion w/internal temp sense DGND C112 3p3V_DUT 100MHZ FERRITE U14 0.1uF 4 3V3_DUT_SW R63 680K 6 5 B R1/C1 OFF VOUTA VOUTB R2 3 2 C111 10uF 1 10uF R40 100K FDG6342L_SC70-6 DUT_3VEN C94 L8 R85 10.0K 1.0uF DGND DGND 3 CP1+ C96 CP1- 10 7 4 VIN1 VIN2 VOUT1 VOUT2 GND1 GND2 GND3 GND4 SD_N R64 10.0K DGND 3 5 6 DAP 5p0V_DUT 100MHZ FERRITE 100MHZ FERRITE 5V_DUT_OUT C95 C97 10uF C1+ C1- DUT_5VEN DGND 1 2 L6 L7 C107 C110 10uF 10uF 10uF B DGND DGND DGND LM2750 DGND DGND Test Points A TP16 TP18 3p3V 1p2V 1p8V 3p3V_DUT 5p0V_DUT DGND TP11 TP12 TP13 TP14 1 1 1 1 1 1 DGND TP15 Size 7 6 5 4 3 SPIO4 POWER Supplies 2010 National Semiconductor Document Number B Date: 8 A National Semiconductor, Santa Clara, CA 95052 Title 1 3 VIN U12 8 9 Rev 2.0 870600474-001 Wednesday, November 17, 2010 2 Sheet 11 of 1 12 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service 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