SPIO-4
Precision Signal-Path Controller Board
Users' Guide
December 2010
National Semiconductor Page 2 www.national.com
Table of Contents
1.0 SPIO-4 System Overview ......................................................................................................................3
1.0 SPIO-4 System Overview ......................................................................................................................3
1.1 SPIO-4 System Features................................................................................................................3
1.2 Packing List ....................................................................................................................................3
1.3 Board Layout Overview..................................................................................................................4
1.4 Component Description..................................................................................................................5
1.5 SPIO-4 Board Test Points..............................................................................................................5
2 System Functionality ..............................................................................................................................6
2.1 System Block Diagram ...................................................................................................................6
2.2 General System Overview..............................................................................................................6
2.3 Automatic Device Detection & Configuration .................................................................................7
2.4 LED Indicators................................................................................................................................7
2.5 DUT Interface (GPSI-16/32)...........................................................................................................7
2.5.1 Level Shifters...........................................................................................................................9
2.6 Auxiliary Interface.........................................................................................................................12
2.7 Computer Interface.......................................................................................................................12
2.8 Memory.........................................................................................................................................12
2.9 Power Requirements....................................................................................................................12
3 SPIO-4 Bill of Materials ........................................................................................................................13
4 SPIO-4 Schematics..............................................................................................................................14
Table 1 - Main component reference designators........................................................................................5
Table 2 - Test Points.....................................................................................................................................5
Table 3 - LED Behavior.................................................................................................................................7
Table 4 GPSI-32 Signals.............................................................................................................................12
Figure 1 - SPIO-4 Board Layout – Component Side ....................................................................................4
Figure 2 - SPIO-4 System Block Diagram ....................................................................................................6
Figure 3 - GPSI 16 DUT to SPIO4 Mating....................................................................................................8
Figure 4 - GPSI 32 DUT to SPIO4 Mating....................................................................................................9
National Semiconductor Page 3 www.national.com
1.0 SPIO-4 System Overview
The SPIO-4 is one of several National Semico nductor digital controller/capture boards that are used by
multiple evaluation systems. The objective of these software/hardware evaluation systems is to allow our
customers to easily and accurately evaluate National’s signal-path devices in a lab setting. At the time of
SPIO-4’s release, two different evaluation system software (GUIs) make use of this board: the
WaveVision-5 and the Sensor AFE. The board shi ps with the current version of the WaveVision-5
software.
In addition to the controller/capture board (i.e., the SPIO-4) and the evaluation GUI software (e.g.,
WaveVision-5 or Sensor AFE), the third essential element of an evaluation system is the device or signal-
path evaluation board that plugs into th e controller board. This eval board is generically referred to as the
“DUT board”. Each DUT board comes with its own Users’ Guide which documents its specific features.
Each DUT board also comes with some soft ware that the user must install before using it. In the case of
the WaveVision-5 GUI, this software is essentially a device -spe cific module that adds support for the
future device eval boards. In the case of Sensor AFE device family, the eval board comes with a
complete, custom Sensor AFE that is specifically paired with that device.
The WaveVision-5 and Sensor AFE GUI software have their own Users’ Guide documents that describe
how to interact with the GUI.
This User’s Guide describe s only the SPIO-4 board. The user is expected to refer to this guide only if
necessary. The DUT Users’ Guide and the GUI Users’ Guide are the primary docume nts that describe
how to work with a National signal-path evaluation board.
The latest version of this document may be obtained from National Semiconduct or’s web site at
www.national.com.
1.1 SPIO-4 System Features
Captures or sources multiple signal-path data streams and transfers them to/from the PC based
application software through a USB 2.0 con nection (USB1.1 compatible).
Supports jumper-less, plug-and-play configuration. The GUI automatically discovers the attached
DUT board and loads the appropriate software module for it.
Supports a wide variety of signal-path evaluation board through a standardized connector (GPSI-
16/GPSI-32).
Capable of storing up to 8MBytes of signal-path data.
DUT interface can be SPI, I2C or parallel.
Powered either by PC via USB or external supply.
1.2 Packing List
The SPIO-4 kit (National order number SPIO-4/NOPB ) consists of the following components:
SPIO-4 Board
USB cable
User’s Guide (This Do cument)
WaveVision-5 GUI software
National Semiconductor Page 4 www.national.com
1.3 Board Layout Overview
Figure 1 - SPIO-4 Board Layout – Component Side
National Semiconductor Page 5 www.national.com
1.4 Component Description
The following table describ es both the on-board connectors and the main components used in the SPIO-4
System shown in Figure 1.
Component 1.4.1.1 Description
J1 Serial Debug connector
J2 Header to provide access to the FPGA’s JTAG interface for debug
J3 Jumper to select J4 IO voltage (3.3V or program mable)
J4 (DBG) Debug/Development Connector(See section 2.6).
J6 (GPSI-32) GPSI-16/32 Connector to DUT.
J7 (micro_SD) This holds the microSD card for storage or development purposes
J8 (USB) USB cable Connection.
J9 (JTAG) Atmel Processor JTAG Debug Header.
J10 (POWER) +5-6V Power Supply Connection – Optional (See Section Error! Reference
source not found.).
J14 (USNAP) Additional header providing power and seri al interface to processor
JP1 Jumpers for t e st purposes only.
U1 Atmel SAM3U Processor
U4 8Mx16 PSRAM
U5 Xilinx Spartan LX16 FPGA
D1-D4 FPGA Status LEDs (See section 2.4)
D6 1.8V PSRAM Core voltage Surface mount power LED.
D7 3.3V DUT supply voltage Surface mount power LED.
D8 5.0V DUT supply voltage Surface mount power LED.
D10 USB input power LED.
D11 1.2V FPGA Core voltage Surface mount power LED.
SW1 Reset switch
SW2 Power On pushbutton
Table 1 - Main component reference designators
1.5 SPIO-4 Board Test Points
The following table describes the main Test Points available.
Test point Description
TP1, TP3, TP16, TP18(GND) Ground test points.
TP11 3.3V Digital IO Voltage for SPIO Board
TP12 1.2V for FPGA core voltage
TP13 1.8V for PSRAM core voltage
TP14 3.3V for DUT Digital Supply
TP15 5.0V for DUT Analog Supply
Table 2 - Test Points
National Semiconductor Page 6 www.national.com
2 System Functionality
2.1 System Block Diagram
Micro-Controller
Atmel SAM3U
(U1)
>
Level Shifters
USB
Connector
(J8)
LP3910
Multiple
Supply
Switching
Regulator
(U11) Boost
Regulator
(U12)
Filter
12MHZ
Xtal
Debug
Connector(J9)
SD Card
(J7)
Ext
Pwr
(J10)
Input
Protection
32kHZ
Xtal
8MBx16
PSRAM
(U4)
JTAG
(J2)
Static Mem intrfc
GPIO
GPSI 32
Connector
(J6)
<
Level Shifters
GPSI A GPSI A
GPSI A
GPSI A
Pins 1,3,7,8,16
Pins 23-30
Pin 15
Pin 13
Pin 14
Pin 11
GPSI B
Pins 5,6,9
VDDIO
Debug
Connector(J1)
3.3V_DUT
I2C(SCL)
DUT 3.3V
DUT 5V
3.3V_DUT
I2C(SDA)
Pin 12
DUT 5V
Spartan 6
XC6SLX16
(U5)
3.3V
IO Voltage 3.3V
NBS0-1
D15-0
NCS0
NWR
NRD
A23-1
NCS2
NCS3/FPGA_CFG
USB
USB
5V
1.8V
1.2V
DUT 3.3V
DEBUG
(J4)
I2C
DUT3.3V_EN
DUT3.3V_EN
Figure 2 - SPIO-4 System Block Diagram
2.2 General System Overview
The SPIO-4 board is controlled via the Atmel SAM3U mi cro-controller that is based on an ARM M3, 32-bit
embedded core. It provides the interface to the computer via a USB interface. The DUT board interfaces
to the SPIO-4 via J6, the GPSI-16/32 connector. The GPSI-16/32 interface provides control, data and
power to the DUT board. The interfaces on the GPSI-32 can be I2C, SPI with multiple-device capability,
and parallel interface. The dedicated I2C interfa ce o n the GPSI-16/32 is primarily for control and DUT
identification, while the dedicated SPI interface may be used for control or for data transfer. The I2C
interface is derived from the peripheral o f the microcontrolle r. As there can be a wide variety of SPI
requirements for DUTs, the SPI interface can be provided via a processor peripheral and over the
dedicated SPI lines as sho wn in this d ocument, or the on-board Xilinx Spartan XC6SLX16 FPGA may be
used. In fact, the FPGA may be used to implement DUT interfaces other than SPI – such as high-speed
I2C for data purposes and parallel data-plus-clock interfaces. A large external SRAM 8Mx16 is connected
to both the processor and the FPGA which is used to provide additional device data storage in case the
microcontroller’s or FPGA’s on-board memory is in sufficient.
Power is provided to the system via the USB cable, or external power jack. A switching regulator is used
to produce the 3.3 volt supply required b y the microcontrolle r and GPSI-32 devices. A boost regulator
creates the regulated 5 volt supply required by the devices interfaced to the GPSI-32 connector.
National Semiconductor Page 7 www.national.com
2.3 Automatic Device Detection & Configuration
The SPIO-4 system supports automatic hardware d etection and configuration of the device under test.
The GUI software actually carries out the device detection and configuration task. The FPGA is re-
configured on the fly by the host PC when the SPIO-4 Board is powered on, or whenever ADC evaluation
boards are exchange d and SPIO-4 power is cycled.
Each DUT board has either an FPGA configuration file, or a microcontroller firmware module, unique to it.
The GUI software, in conjunction with the USB micro-controller, determines which DUT board has been
plugged in. It then loads a configuration file tailored for that DUT board into the FPGA and/or the
microcontroller.
Normally, the configuration process is totally transparent to the user, and requires no interve ntion.
However, some devices may allow thi s proce s s to be overridden . Refer to the evaluation board manual
for more information.
Important Note: Many of our device evaluation boards do require jumper configurations to select
channels, voltages, or other options. Please consult the manual that came with the evaluation board for
specific information.
Important Note: Please be aware that DUT boards are NOT hot swappable. Please power
down both the SPIO-4 board and the DUT board prior to swapping DUT board.
2.4 LED Indicators
There are several LED indicators on the SPIO4 board. the ones described bleow are driven directly by
separate power rails on the SPIO4 board but as those rails can only be controlled by the processor they
not only indicate a particular rails is on, they also show a state of the SPIO4 firmware as discussed below.
Led D# Description
D10 Indicates power (USB or External) is present to SPIO board
D5 3.3V Digital IO Voltage for SPIO Board is up (required for all
operations)
D6 1.2V for FPGA core voltage – Indicates proce ssor h as completed
low level hardware initialization and is ready to program the FPGA
D11 1.8V for PSRAM core voltage - Indicates processor has completed
low level hardware initialization and is able to use the PSRAM
D7 & D8 3.3V & 5V DUT Supplies – Indicates the processor has detected a
DUT board inserted and has powered it
Table 3 - LED Behavior
2.5 DUT Interface (GPSI-16/32)
The SPIO-4 Data Capture Board is connected to the DUT through the GPSI-16/32 (J6) conne ctor. As
described previously, the GPSI-32 interface provides control, data a nd power to the DUT board. See
Table 1 below for signal specifics. The GPSI-16/32 interface also supports a subset within it called GPSI-
16 which consists of the lower ord er pins 1-16. A given DUT board may use a 16-pin, GPSI-16 port only,
or may use the whole 32-pin port. GPSI-16 has level shifters allowing some of the DUT interface
voltages to go from 1.65V to 5.5V LVTTL levels under the direct control of the DUT board circuitry. To
achieve that voltage range the voltage level shifters are NOT bidirection al. A DUT boa rd requiring bi-
directional signals must use the upper-order portion of the GPSI-32. Note, however, that upper order
portion of GPSI-32 requires adherence to 3.3V LVTTL voltage levels as it does not have leve l shifters.
National Semiconductor Page 8 www.national.com
Below are two photos demonstrating the proper mating of a GPSI16 and a GPSI32 DUT board to the
SPIO4.
Figure 3 - GPSI 16 DUT to SPIO4 Mating
National Semiconductor Page 9 www.national.com
Figure 4 - GPSI 32 DUT to SPIO4 Mating
2.5.1 Level Shifters
The board incorporates level shifters to allow flexible output voltages on the uni-directional SPI signals of
GPSI-16 port, as shown in the board bloc k diagram. VDDIO – a supply voltage from the GPSI-16/32
connector coming from the DUT board – provides the voltage to the output side of the level translators. If
the DUT has no special re quirements for voltage and simply needs basic 3.3V signal levels, the 3.3V
output from the GPSI connector could be connected to VDDIO on the DUT board. The level shifters are
uni-directional. If VDDIO is not provided, the level shifters enter a sh utdown state with all input pins tri-
stated. The state passed along to the proce ssor in this case would be logic low.
National Semiconductor Page 10 www.national.com
GPSI Connector (J6) Pin Description
Pin
#
Signal Name/Function Voltage
Level
Direction (From
SPIO-4)
Pins 1-16 form the GPSI-16 subset:
1
SCS0_A~
SerialBus A – Chip Select for device 0.
1.65 to
5.5V
OUTPUT
2 GND
3
SCK_A
Serial Bus A – Serial Clock from the master to the device.
1.65 to
5.5V
OUTPUT
4 DUT_Present~
The DUT board shall ground this pin. The SPIO-4 senses this pin to
determine the DUT board’s presence.
N/A
INPUT
5
SMISO_A
Serial Bus A – Data from the slave (device) to the master. The device
may implement this as a tri-state signal that can be driven by multiple
devices on Serial Bus A in a bussed fashion. The pull-up resistor, if
required, is on the DUT board.
1.65 to
5.5V
INPUT
6 Dev_INT~/SDRDY_A~
In certain applications, if required, this pin serves as the DRDY~
signal from the DUT to the SPIO-4. In other cases, this pin may be a
general interrupt pin from the device to the SPIO-4.
On the SPIO-4 board this signal connects to an interrupt pin on the
microcontroller.
1.65 to
5.5V
INPUT
7
SMOSI_A
Serial Bus A – Data from the master to the slave (device).
1.65 to
5.5V
OUTPUT
8 SCS1_A~
SerialBus A – Chip Select for device 1.
1.65 to
5.5V
OUTPUT
9 Ref_CLK
Reference clock from the DUT board to the SPIO-4 board.If not used,
the DUT board should ground this pin.
1.65 to
5.5V
INPUT
10 GND
11 SDA
Data line of the I2C bus.
Pulled-up to +3.3V_DUT on the SPIO-4 board through a 1.5k resistor.
3.3V Birdirectional
12 SCL
Clock line of the I2C bus.
Pulled-up to +3.3V_DUT on the SPIO-4 board through a 1.5k resistor.
3.3V Birdirectional
13
+3.3V_DUT
Switched by the SPIO-4 conditional on the DUT_Present~ having been
seen. The ID EEPROM and the entire I2C bus on the DUT board must
be unconditionally powered by this supply. Max. peak current: 50mA
(subject to total power budget limit of 200mW over both supplies).
Maximum capacitor loading for this node is not to exceed 50uF.
3.3V
OUTPUT
14 +5V_DUT
This supply is sourced by the SPIO-4 and is intended to power the core
functionality of the DUT board – if desired. Nominal current: 35mA.
Max. peak current: 50mA (subject to total power budget limit of
200mW over both supplies). If power from the SPIO-4 is not required,
5.0V
OUTPUT
National Semiconductor Page 11 www.national.com
the DUT board must leave this pin open. Maximum capacitor loading
for this node is not to exceed 50uF.
15 VDDIO
Interface Supply always provided by the DUT board. Both the DUT
board and the SPIO-4 board power their I/O drivers with this supply
(except the I2C bus – which is always +3.3V). Only the SPI_A related
signals on the GPSI-16 subset are affected by this I/O supply. Voltage
Range: 1.6V to 5.5V. Capable of supplying 100mA.
1.65 to
5.5V
INPUT
16 SCS2_A~
SerialBus A – Chip Select for device 2.
1.65 to
5.5V
OUTPUT
17 DUT_PWR_Enable
For those DUT boards that support intelligent power-up control, this
signal from the SPIO-4 enables the DUT power regulators.
3.3V
OUTPUT
18
Available for implementation specific use. Refer to the DUT
board manual.
If unused, leave it open. (Possible use: DUT_RESET~)
3.3V
19
Available for implementation specific use. Refer to the DUT
board manual.
If unused, leave it open.
3.3V
20
Available for implementation specific use. Refer to the DUT
board manual.
If unused, leave it open.
3.3V
21
Available for implementation specific use. Refer to the DUT
board manual.
If unused, leave it open.
3.3V
22
Available for implementation specific use. Refer to the DUT
board manual.
If unused, leave it open.
3.3V
23
Available for implementation specific use. Refer to the DUT
board manual.
If unused, leave it open.
If a second SPI bus is implemented, then use this pin as shown:
SCS0_B~
SerialBus B – Chip Select for device 0.
3.3V
24
Available for implementation specific use. Refer to the DUT
board manual.
If unused, leave it open.
If a second SPI bus is implemented, then use this pin as shown:
SDRDY_B~
In certain SPI applications, if required, this pin serves as the DRDY~
signal from the DUT to the SPIO-4.
3.3V
25
Available for implementation specific use. Refer to the DUT
board manual.
If unused, leave it open.
If a second SPI bus is implemented, then use this pin as shown:
SCK_B
Serial Bus B – Serial Clock from the master to the device.
3.3V
26
Available for implementation specific use. Refer to the DUT
board manual.
If unused, leave it open.
If a second SPI bus is implemented, then use this pin as shown:
SCS1_B~
SerialBus B – Chip Select for device 1.
3.3V
27
Available for implementation specific use. Refer to the DUT
board manual.
If unused, leave it open.
If a second SPI bus is implemented, then use this pin as shown:
SMISO_B
3.3V
National Semiconductor Page 12 www.national.com
Serial Bus B – Data from the slave (device) to the master. The device
may implement this as a tri-state signal that can be driven by multiple
devices on Serial Bus B in a bussed fashion. The pull-up resistor, if
required, is on the DUT board.
28
Available for implementation specific use. Refer to the DUT
board manual.
If unused, leave it open.
If a second SPI bus is implemented, then use this pin as shown:
SCS2_B
~
SerialBus B – Chip Select for device 2.
3.3V
29
Available for implementation specific use. Refer to the DUT
board manual.
If unused, leave it open.
If a second SPI bus is implemented, then use this pin as shown:
SMOSI_B
Serial Bus B – Data from the master to the slave (device).
3.3V
30
Available for implementation specific use. Refer to the DUT
board manual.
If unused, leave it open.
If a second SPI bus is implemented, then use this pin as shown:
SCS3_B~
SerialBus B – Chip Select for device 3.
3.3V
31
Reserved for future use. The DUT board shall leave this pin open.
3.3V
32 GND
Table 4 GPSI-32 Signals
2.6 Auxiliary Interface
The SPIO-4 Board can be connected to auxiliary test equipment through debug connector J4 located on
the board.
2.7 Computer Interface
The SPIO-4 Board communicates with a PC via standard USB 2.0 at high-speed (up to a 480 Mbits/sec
signaling rate). It is fully backward compatible with USB 1.1 devices and ca bles.
2.8 Memory
The SPIO-4 Board comes with 8M x 16bits of PSRAM for data storage. It is a single Micron
MT45W8MW16BGX PSRAM configured for asynchronous accesses. In asynchronous configuration the
fastest access speed is 70ns latency or approximately 14.2 MHz p er 16 bit tran sfer. Both the processor
and the FPGA have read/write access t o the PSRAM. The proce ssor’s Static M emory Interface
mastership is controlled by firmware wit h in the processor as there is no hardware mechanism to share
the bus.
2.9 Power Requirements
The SPIO-4 Data Capture Board can be solely powered via the USB interface power but can also be
powered by external power supply. The SPIO-4 Data Capture Board consumes up to 500 mA of current
depending on the DUT load. ADC evaluation boards differ widely in their power consumption – please
consult the manual that came with your evaluation board, and verify if an external supply is required for
your DUT board. External power can be supplied via J10 and must be greater than 4.5V and less than
6.0V DC with a current rating of at least 1A.
National Semiconductor Page 13 www.national.com
3 SPIO-4 Bill of Materials
Item Description Qty. Reference Mfg. Name Mfg. No.
1 CAP CER 10000PF 25V Y5V 0603 1 C1 MURATA ELECTRONICS (VA) GRM188F51E103ZA01D
2 CAP CER .47UF 10V X7R 0603 1 C103 TAIYO YUDEN
(
VA
)
LMK107B7474KA-T
3 CAP .10UF 16V CERAMIC X7R 0603 58 C2,C4,C6,C7,C8,C9,C10,C11,C12,C14,C15,C16,C17,C18,C20,C2
3,C26,C27,C31,C33,C35,C36,C40,C41,C42,C43,C44,C46,C48,C5
0,C51,C52,C53,C54,C55,C56,C57,C60,C61,C64,C65,C66,C68,C6
9,C70,C71,C72,C74,C76,C79,C85,C93,C98,C99,C104,C105,C108
,C112
YAGEO (VA) CC0603KRX7R7BB104
4 CAP CERAMIC 10PF 50V NP0 0603 2 C21,C78 KEMET
(
VA
)
C0603C100J5GACTU
5 CAP CER 15PF 50V C0G 5% 0603 4 C24,C25,C29,C30 TDK CORPORATION
(
VA
)
C1608C0G1H150J
6 CAP CER 4.7UF 10V Y5V 0603 5 C28,C32,C77,C84,C86 MURATA ELECTRONICS
(
VA
)
GRM188F51A475ZE20D
7 CAP CER 10UF 6.3V Y5V 0603 22 C3,C5,C13,C19,C22,C37,C38,C39,C45,C58,C62,C73,C75,C80,C8
2,C83,C87,C88,C89,C90,C91,C102 TDK CORPORATION (VA) C1608Y5V0J106Z
8 CAP CER 1.0UF 10V X7R 0603 9 C34,C47,C49,C59,C63,C67,C81,C106, C109 TAIYO YUDEN
(
VA
)
LMK107B7105KA-T
9 CAP CER 100UF 10V X5R 1210 3 C92,C100,C101 TAIYO YUDEN
(
VA
)
LMK325BJ107MM-T
10 CAP CER 10UF 10V X5R 0805 6 C94,C95,C97,C107,C110,C111 JOHANSON DIELECTRICS INC
(
VA
)
100R15X106KV4E
11 CAP CER 1.0UF 16V X7R 20% 1206 1 C96 TDK CORPORATION
(
VA
)
C3216X7R1C105M/0.85
12 LED TOPLED 570NM GREEN CLR SMD 10 D1,D2,D3,D4,D5,D6,D7,D8,D10,D11 OSRAM OPTO SEMICONDUCTORS INC
(
VA
)
LG M67K-G1J2-24-0-2-R18-Z
13 DIODE ZENER 6.2V 3W DO214AA 1 D12 MICRO COMMERCIAL CO
(
VA
)
3SMBJ5920B-TP
14 DIODE SCHOTTKY 1A 20V SOD-123 1 D9 MICRO COMMERCIAL CO
(
VA
)
MBRX120LF-TP
15 RES 0.0 OHM 1/2W 1210 SMD 1 F1 VISHAY/DALE
(
VA
)
CRCW12100000Z0EA
16 PTC RESETTABLE 1.10A 16V 1812 1 F2 BOURNS INC
(
VA
)
MF-MSMF110/16-2
17 CONN HEADER VERT 5POS .100 TIN 1 J1 TYCO ELECTRONICS AMP 6 40454-5
18 CON PWR JCK 2.0 X 6.5MM W/O SW 1 J10 CUI INC PJ-037A
19 CONN HEADER 10POS 2MM VERT T/H 1 J14 3M 951110-8622-AR
20 CONN HEADER VER T SGL 6POS GOLD 1 J2 3M 961106-6404-AR
21 BERGSTIK II .100" SR STRAIGHT 1 J3 FCI 68000-203HLF
22 CONN FEMALE 32POS DL .1" R/A TIN 1 J6 SULLINS CONNECTOR SOLUTIONS PPTC162LJBN-RC
23 CONN MICRO SD R/A HING TYPE SMD 1 J7 HIROSE ELECTRIC CO LTD
(
VA
)
DM3C-SF
24 CONN RCPT USB TYPE B R/A PCB 1 J8 FCI 61729-0010BLF
25 CONN HEADER 2.54MM 20POS GOLD 1 J9 SULLINS CONNECTOR SOLUTIONS SBH11-PBPC-D10-ST-BK
26 BERGSTIK II .100" SR STRAIGHT 1 JP1 FCI 68001-202HLF
27 INDUCTOR 10UH 100MA 0805 2 L1,L2 MURATA ELECTRONICS
(
VA
)
LQM21FN100M70L
28 INDUCTOR 2.2UH 1.20A 20% 1210 3 L3,L4,L5 TDK CORPORATION
(
VA
)
NLCV32T-2R2M-PFR
29 FERRITE CHIP 2700 OHM 200MA 0805 3 L6,L7,L8 MURATA ELECTRONICS
(
VA
)
BLM21BD272SN1L
30 TRANSISTOR NPN GP 40V SOT23 1 Q1 MICRO COMMERCIAL CO
(
VA
)
MMBT3904-TP
31 RES 33.0 OHM 1/10W 1% 0603 SMD 8 R13,R14,R15,R16,R17,R18,R19,R20 YAGEO
(
VA
)
RC0603FR-0733RL
32 RES 39 OHM 1/10W 5% 0603 SMD 2 R2,R3 PANASONIC - ECG
(
VA
)
ERJ-3GEYJ390V
33 RES 10K OHM 1/10W 1% 0603 SMD 17 R21,R26,R30,R31,R32,R33,R34,R43,R46,R47,R48,R49,R60,R61,
R64,R72,R85 STACKPOLE ELECTRONICS INC (VA) RMCF0603FT10K0
34 RES 46.4K OHM 1/10W 1% 0603 SMD 5 R22,R23,R24,R25,R28 STACKPOLE ELECTRONICS INC
(
VA
)
RMCF0603FT46K4
35 RES 68K OHM 1/10W 5% 0603 SMD 1 R29 PANASONIC - ECG
(
VA
)
ERJ-3GEYJ683V
36 RES 1.5K OHM 1/10W 5% 0603 SMD 7 R39,R41,R44,R45,R79,R80,R82 STACKPOLE ELECTRONICS INC
(
VA
)
RMCF0603JT1K50
37 RES 6.8K OHM 1/10W 1% 0603 SMD 1 R4 STACKPOLE ELECTRONICS INC
(
VA
)
RMCF0603FT6K80
38 RES 100K OHM 1/10W 1% 0603 SMD 2 R40,R62 STACKPOLE ELECTRONICS INC
(
VA
)
RMCF0603FT100K
39 RES 649 OHM 1/10W 1% 0603 SMD 1 R42 PANASONIC - ECG
(
VA
)
ERJ-3EKF6490V
40 RES 0.0 OHM 1/10W 0603 SMD 15 R5,R6,R27,R35,R37,R53,R55,R56,R57,R58,R59,R66,R74,R76,R7
8STACKPOLE ELECTRONICS INC (VA) RMCF0603ZT0R00
41 RES 4.64K OHM 1/10W 1% 0603 SMD 1 R51 PANASONIC - ECG
(
VA
)
ERJ-3EKF4641V
42 RES 121K OHM 1/10W 1% 0603 SMD 1 R52 STACKPOLE ELECTRONICS INC
(
VA
)
RMCF0603FT121K
43 RES 680K OHM 1/10W 5% 0603 SMD 1 R63 PANASONIC - ECG
(
VA
)
ERJ-3GEYJ684V
44 RES 9.1K OHM 1/10W 5% 0603 SMD 1 R86 PANASONIC - ECG
(
VA
)
ERJ-3GEYJ912V
45 RES 750 OHM 1/10W 1% 0603 SMD 6 R9,R10,R11,R12,R36,R38 STACKPOLE ELECTRONICS INC
(
VA
)
RMCF0603FT750R
46 SWITCH TACT SPST W/O GND SMD 2 SW1,SW2 OMRON ELECTRONICS INC-ECB DIV
(
VA
)
B3U-1000P
47 PC TEST POINT MINIATURE SMT 14 TP1,TP3,TP4,TP5,TP7,TP11,TP12,TP13,TP14,TP15,TP16,TP17,
TP18,TP19 KEYSTONE ELECTRONICS (VA) 5015
48 ATSAM3U4EA-AU-ND 1 U1
A
TSAM3U4EA-AU-ND
49 LP3910SQ-AA 1 U11 LP3910SQ-AA
50 LM2750LD-5.0CT-ND 1 U12 LM2750LD-5.0CT-ND
51 IC LOAD SWITCH INTEGRATED SC70-6 1 U14 FAIRCHILD SEMICONDUCTOR
(
VA
)
FDG6342L
52 IC PSRAM 128MBIT 70NS 54VFBGA 1 U4 MICRON TECHNOLOGY INC
(
VA
)
MT45W8MW16BGX-701 IT TR
53 XC6SLX16-2CSG324C 1 U5 XC6SLX16-2CSG324C
54 IC BUS TRANSCVR 2BIT N-INV SM8 5 U6,U7,U8,U9,U10 TEXAS INSTRUMENTS
(
VA
)
SN74LVC2T45DCTR
55 CRYSTAL 12.00 MHZ 8PF SMD 1 Y1 NDK
(
VA
)
NX5032GA 12MHZ AT-W
56 CRYSTAL 32.768KHZ 12.5PF SMD 1 Y2
A
BRACON CORPORATION
(
VA
)
A
BS10-32.768KHZ-T
57 PCB Fab 1 Fab National Semiconductor 551600474-001
National Semiconductor Page 14 www.national.com
4 SPIO-4 Schematics
Following pages show the schematics of the board. These are provided for general information purposes
only. National reserves the right to make modifications to the board design at any time.
National Semiconductor Page 15 www.national.com
BY USING THIS PRODUCT, YOU ARE AGREEING TO BE BOUND BY THE TERMS AND CONDITIONS OF
NATIONAL SEMICONDUCTOR'S END USER LICENSE AGREEMENT. DO NOT USE THIS PRODUCT UNTIL
YOU HAVE READ AND AGREED TO THE TERMS AND CONDITIONS OF THAT AGREEMENT. IF YOU DO NOT
AGREE WITH THEM, CONTACT THE VENDOR WITHIN TEN (10) DAYS OF RECEIPT FOR INSTRUCTIONS ON
RETURN OF THE UNUSED PRODUCT FOR A REFUND OF THE PURCHASE PRICE PAID, IF ANY.
The SPIO-4 Board is intended for product e valuation purposes only and is not intended for resale to end consumers,
is not authorized for such use and is not designed for compliance with European EMC Directive 89/336/EEC, or for
compliance with any other electromagnetic compatibilit y requirements.
National Semiconductor Corporation does not assume any responsibility for use of any circuitry and/or software
supplied or described. No circ uit patent licenses are implied.
LIFE SUPPORT POLICY
NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical
implant into the body, or (b) support or sustain
life, and whose failure to perform, when properly
used in accordance with instructions for use
provided in the labeling, can be reasonably
expected to result in a significant injury to the
user.
2. A critical component is any component in a life
support device or system whose failure to
perform can be reasonably expected to cause
the failure of the life support device or system , or
to affect its safety or effectiveness.
National Semiconductor Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
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Fax: +49 (0) 1 80-530 85 86
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Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
www.national.com
National does not assume any responsibility for any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
SPIO45 Interface Board Block Diag
Title
Size Document Number Rev
Date: Sheet of
2.0
SPIO4 Block Diagram
B
112Wednesday, November 17, 2010
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National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
Title
Size Document Number Rev
Date: Sheet of
2.0
SPIO4 Block Diagram
B
112Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
Title
Size Document Number Rev
Date: Sheet of
2.0
SPIO4 Block Diagram
B
112Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Atmel ARM Microcontroller - Power, Debug, Analog
OSC_32768HZ_SMD
74LVC2G06
OSCIL_12M_SMD_3.3V
1.0K
499R
DFSD_M
DFSD_P
XOUT1
XIN_CLK
VBG
XOUT32
XIN32_CLK
XOUT1
XIN_CLK
VBG
CLK_12MHZA_R
CLK_32K_R XIN32_CLK
CLK_12MHZA
XIN32_CLK
XOUT32
CLK_12MHZ1_R
CLK_12MHZ2_R
XIN_CLK
VDDBU
DGND
DGND
DGND
VUTMI
VANA
DGND
DGND
DGND
DGND
3p3V
3p3V
DGND
DGND
DGND
DGND
3p3V
3p3V
DGND
3p3V
3p3V
VCORE
DGND
3p3V
3p3V
VCORE
VUTMI
VANA
DGND
DGND
DGND
DGND
DGND
DGND
DGND
VANA
3p3V
3p3V
DGND
NRST_PWR11
TDI9 TDO9 TMS9 TCK9
DHSD_M9 DHSD_P9
RSTN9
CLK_12MHZ 5
Title
Size Document Number Rev
Date: Sheet of
2.0
SPIO4 CPU Power
B
212Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
Title
Size Document Number Rev
Date: Sheet of
2.0
SPIO4 CPU Power
B
212Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
Title
Size Document Number Rev
Date: Sheet of
2.0
SPIO4 CPU Power
B
212Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
C31
0.1uF
C31
0.1uF
C9
0.1uF
C9
0.1uF
SW1SW1
A B
C23
0.1uF
C23
0.1uF
U3
DNS
U3
DNS
OE
1
GND
2OUT 3
VDD 4
C6
0.1uF
C6
0.1uF
C18
0.1uF
C18
0.1uF
C21
10pF
C21
10pF
R3 39RR3 39R
C19
10uF
C19
10uF
C24 15pFC24 15pF
L1
10uH/100mA
L1
10uH/100mA
Y2
32.768KHz
Y2
32.768KHz
R7
DNS
R7
DNS
C17
0.1uF
C17
0.1uF
R5
0R
R5
0R C22
10uF
C22
10uF
C15
0.1uF
C15
0.1uF
C26
0.1uF
C26
0.1uF
C3
10uF
C3
10uF
R71
DNS
R71
DNS
JP1 JPJP1 JP
C13
10uF
C13
10uF
U1B
SAM3U
U1B
SAM3U
NRST
11
TDI
1
TDO/TRACESWO
4
TMS/SWDIO
7
TCK/SWCLK
9
VBG
39
DHSDP
37
DHSDM
38
DFSDM
41
DFSDP
42
FWUP
135
SHDN
136
ERASE
137
TEST
138
NRSTB
141
XIN32
144
XOUT32
143
XIN
36
XOUT
35
ADVREF 74
AD12BVREF 76
VDDCORE1 16
VDDCORE2 27
VDDCORE3 44
VDDCORE4 50
VDDCORE5 86
VDDCORE6 125
VDDOUT 2
VDDIN 3
VDDIO1 17
GND1
18
GNDPLL
33
VDDUTMI 40
GNDUTMI
43
VDDIO2 51
GND2
52
GND3
60
VDDANA 73
GNDANA
75
VDDIO3 85
GND4
90
VDDIO4 104
GND5
126
VDDIO5 127
VDDBU 139
GNDBU
140
VDDPLL 34
JTAGSEL
142
C30 15pFC30 15pF
C12
0.1uF
C12
0.1uF
C28
4.7uF
C28
4.7uF
U13
DNS
U13
DNS
1A
1
GND
22A
3
2Y 4
VCC 5
1Y 6
C59
1.0uF
C59
1.0uF
C14
0.1uF
C14
0.1uF
C29 15pFC29 15pF
C16
0.1uF
C16
0.1uF
R67
DNS
R67
DNS
L2
10uH/100mA
L2
10uH/100mA
C4
0.1uF
C4
0.1uF C5
10uF
C5
10uF
R69
DNS
R69
DNS
C8
0.1uF
C8
0.1uF
R4
6.8K
R4
6.8K
Y1
12.000MHz
Y1
12.000MHz
R660R R660R
C20
0.1uF
C20
0.1uF
R6
0R
R6
0R
R68
DNS
R68
DNS
C10
0.1uF
C10
0.1uF
C2
0.1uF
C2
0.1uF
R8
DNS
R8
DNS
R2 39RR2 39R C11
0.1uF
C11
0.1uF
C32
4.7uF
C32
4.7uF
C1
10nF
C1
10nF
C27
0.1uF
C27
0.1uF
R70
DNS R70
DNS
U2
DNS
U2
DNS
OE
1
GND
2OUT 3
VDD 4
C7
0.1uF
C7
0.1uF
R1 DNSR1 DNS
C25 15pFC25 15pF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Atmel ARM Microcontroller, Port Connection
UART Debug Interface header
USNAP INTERFACE
PCB REVISION RESISTORS
R82 R83 PCB REV
DNS DNS A
1.5K DNS B
DNS 1.5K C
___ ___ ______
D0
D1
D2
D3
D7
D4
D6
D5
D11
D8
D9
D15
D12
D9
D13
D14
A13
A5
A9
A4
A8
A2
A11
A3
A7
A6
A12
A10
A17
A21
A16
A20
A14
A15
A19
A18
A22
A1
A23
RXD_IN
TXD_OUT
USNAP_SEL_N
USNAP_IRQ_N
USNAP_SCLK_N
USNAP_MOSI
USNAP_MISO
USNAP_RST_N
NWE
A22
D14
D10
D11
D8
D9
D13
A17
A14
A15
A16
A23
A20
A18
A19
D12
A21
NCS0
NBS0
D15
D2
D0
A1
D6
D5
D4
D3
D1
NRD
D7
USNAP_RST_N
A13
A5
A9
DA3
DA2
DA1
DA0
CDA
NBS1
A4
A8
A2
A11
A3
A7
A6
A12
A10
CK
RXD_IN
TXD_OUT
USNAP_SCLK_N
USNAP_MOSI
USNAP_MISO
USNAP_SEL_N
USNAP_IRQ_N
DUT_SDA
DUT_SCL
SDA
SCL
CD
USNAP_RST_N
USNAP_IRQ_N
3p3V
DGND
3p3V
DGND
DGND
D[15:0] 4,5
A[23:1] 4,5
NWE 4,5
NWAIT 4,5
NCS0 4,5
NRD 4,5
NBS0 4,5
NCS3 5
DUT_PWR_EN 7
DUT_PRSNT_N 7
FPGA_DONE_N 6
FPGA_M0 5
FPGA_M1 5
FPGA_PRGM_N 6
FPGA_INIT_N 5
PCK1 5
IRQ_PWR_N 11
CPU_CS1N_A 7
NCS2 5
CPU_MOSI_A7
SDA11
CPU_CS2N_A7
SCL11
NBS14,5
DA28 DA38
DA08 DA18
CDA8 CK8
VUSB_DET9,11
CPU_SCLK_A7 CPU_CS0N_A7
DUT_SDA7 DUT_SCL7
ONSTAT11 USBISEL11
SCC_TD5
SCC_TF5
PCK5 SCC_CLK5
SRAM_CNTRL_REG4
DUTDRDYN_A
7
CPUMISO_A7
DUT_5VEN 11
DUT_3VEN 11
DUTCLKIN7 CD8
Title
Size Document Number Rev
Date: Sheet of
2.0
SPIO4 ARM CPU Ports
B
312Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
Title
Size Document Number Rev
Date: Sheet of
2.0
SPIO4 ARM CPU Ports
B
312Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
Title
Size Document Number Rev
Date: Sheet of
2.0
SPIO4 ARM CPU Ports
B
312Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
TP17TP17
1
R82 1.5KR82 1.5K
TP19TP19
1
J1
hdr_5pin
J1
hdr_5pin
11
22
33
44
55
TP7TP7
1
J14
2mm_hdr_6pin
J14
2mm_hdr_6pin
11
22
33
44
55
66
77
88
99
10 10
U1A
SAM3U
U1A
SAM3U
PA0/WKUP0
109
PA1/WKUP1
111
PA2/WKUP2
113
PA3/CK
115
PA4/CDA
117
PA5/DA0
119
PA6/DA1
121
PA7/DA2
123
PA8/DA3
128
PA9/TWD0
130
PA10/TWCK0
132
PA11/URXD
133
PA12/UTXD
134
PA13/MISO
87
PA14/MOSI
88
PA15/SPCK
91
PA16/NPCS0
93
PA17/WKUP7
95
PA18/WKUP8
99
PA19/WKUP9
100
PA20/TXD1
101
PA21/RXD1
102
PA22/RTS1
77
PA23/CTS2
103
PA24/WKUP11
105
PA25/WKUP12
106
PA26/TD
107
PA27/PCK0
64
PA28/TK
45
PA29/PWMH1
46
PA30/TF
78
PA31/RF
48
PB0/PWMH0 53
PB1/PWMH1 55
PB2/PWMH2 57
PB3/AD12BAD2 79
PB4/AD12BAD3 80
PB5/AD1 65
PB6/D15 66
PB7/A0/NBS0 67
PB8/A1 68
PB9/D0 31
PB10/D1 30
PB11/D2 59
PB12/D3 61
PB13/D4 62
PB14/D5 29
PB15/D6 97
PB16/D7 96
PB17/NANDOE 26
PB18/NANDWE 25
PB19/NRD 24
PB20/NCS0 23
PB21/A21/NANDALE 21
PB22/A22/NANDCLE 20
PB23/NWR0/NWE 19
PB24/NANDRDY 15
PB25/D8 14
PB26/D9 13
PB27/D10 12
PB28/D11 10
PB29/D12 8
PB30/D13 6
PB31/D14 5
PC0/A2
110
PC1/A3
112
PC2/A4
114
PC3/A5
116
PC4/A6
118
PC5/A7
120
PC6/A8
122
PC7/A9
124
PC8/A10
129
PC9/A11
131
PC10/A12
89
PC11/A13
92
PC12/NCS1
94
PC13/RXD3
98
PC14/NPCS2
28
PC15/NWR1/NBS1
81
PC16/NCS2 82
PC17/AD12BAD6 83
PC18/AD12BAD7 84
PC19/NPCS1 32
PC20/A14 108
PC21/A15 22
PC22/A16 47
PC23/A17 49
PC24/A18 54
PC25/A19 56
PC26/PWMH2 58
PC27/A23 63
PC28/DA4 69
PC29/DA5 70
PC30/DA6 71
PC31/DA7 72
R83 DNS
R83 DNS
TP4TP4
1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MT45W8MW16BGX
D0
D1
D2
D3
D7
D4
D6
D5
D11
D8
D10
D15
D12
D9
D13
D14
A4
A14
A3
A8
A5
A2
A15
A6
A10
A12
A16
A7
A13
A9
A11
A19
A18
A17
A1
A22
A21
A20
A23
DGND
1p8V
3p3V
DGND
3p3V
DGND
A[23:1]3,5
D[15:0]3,5
NWAIT 3,5
NCS03,5 NRD3,5 NWE3,5
NBS13,5 NBS03,5
SRAM_CNTRL_REG3,5
Title
Size Document Number Rev
Date: Sheet of
2.0
SPIO4 PSRAM
B
412Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
Title
Size Document Number Rev
Date: Sheet of
2.0
SPIO4 PSRAM
B
412Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
Title
Size Document Number Rev
Date: Sheet of
2.0
SPIO4 PSRAM
B
412Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
C34
1.0uF
C34
1.0uF C35
0.1uF
C35
0.1uF C37
10uF
C37
10uF
C33
0.1uF
C33
0.1uF C36
0.1uF
C36
0.1uF
U4
MT45W8MW16BGX
U4
MT45W8MW16BGX
A1
A4 A0
A3
CRE
A6
A2
A5
LB
A1
OE
A2
DQ8 B1
UB
B2
A3
B3
A4
B4
CS
B5
DQ0 B6
DQ9 C1
DQ10 C2
A5
C3
A6
C4
DQ1 C5
DQ2 C6
VSSQ D1
DQ11 D2
A17
D3
DQ14 F1
DQ13 F2
VSSQ E6
DQ6 F6
DQ4 E5
VCCQ E1
A16
E4 A15
F4 A14
F3
DQ15 G1
DQ5 F5
A7
D4
DQ12 E2
DQ3 D5
VCC D6
A9
H3
A18
H1
A8
H2
A20
H6
A10
H4
A11
H5
A19
G2
A12
G3
A13
G4
WE
G5
DQ7 G6
WAIT J1
CLK
J2 ADV
J3
RFU3 J5
RFU4 J6
A21
E3
A22
J4
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
REQUIRED SIGNALS TO CONFIG FPGA
RDWR_B T5
VIA SERIAL OR BYTE WIDE (SELECTMAP)
CSI_B T13
CCLK R15
DO_DIN R13
D1 T14
D2 V14
D3 U5
D4 V5
D5 R3
D6 T3
D7 R5
INIT U3
M0 T15
M1 N12
RSTUFF OPTIONS TO SUPPORT
SERIAL AND PARALLEL FPGA CONFIG
NOTE:D0-7 SWAPPED GOING INTO CONFIG BITS
D2
D1
D0
D4
FPGA_CFG_CSN
D6
D5
D11
D8
D10
D15
D12
D9
D13
D14
A1
A23
A4
A14
A3
A8
A5
A2
A15
A6
A10
A12
A16
A7
A13
A9
A11
A19
A18
A17
A22
A21
A20
NBS1
NBS0
NWAIT
NCS0
NRD
A1
A17
A21
A16
A20
A14
A15
A19
A18
A22
A23
D0
D1
D2
D3
D7
D4
D6
D5
D11
D8
D9
D15
D12
D9
D13
D14
A13
A5
A9
A4
A8
A2
A11
A3
A7
A6
A12
A10
FPGA_CCLK
FPGA_CFG_CSN
DATA_D7_CFG_D0
FPGA_CCLK
D7
DATA_D7_CFG_D0
DATA_D7_CFG_D0
D3
DGND
3p3V
DGND
3p3V
3p3V
NWE3,4
FPGA_INIT_N3
FPGA_M13
FPGA_M03
NRD3,4
NCS03,4
NBS13,4 NBS03,4
NWAIT3,4
D[15:0]
3,4
A[23:1]
3,4
SCC_TD3
NCS33
SCC_TF3
CLK_12MHZ2
PCK13
PCK3
SCC_CLK3
NCS23
Title
Size Document Number Rev
Date: Sheet of
2.0
SPIO4 FPGA SRAM & Configuration Intrfc
B
512Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
Title
Size Document Number Rev
Date: Sheet of
2.0
SPIO4 FPGA SRAM & Configuration Intrfc
B
512Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
Title
Size Document Number Rev
Date: Sheet of
2.0
SPIO4 FPGA SRAM & Configuration Intrfc
B
512Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
R73
DNS R73
DNS
R75
DNS R75
DNS
R77
DNS R77
DNS
C43
0.1uF
C43
0.1uF C44
0.1uF
C44
0.1uF C45
10uF
C45
10uF
R74
0R R74
0R
R76
0R R76
0R
R78
0R R78
0R
U5-2
XC6SLX9CSG324
U5-2
XC6SLX9CSG324
IO_L44N_A2_M1DQ7_1
J18
IO_L45N_A0_M1LDQSN_1
K18
IO_L45P_A1_M1LDQS_1
K17
IO_L41N_GCLK8_M1CASN_1
K16
IO_L44P_A3_M1DQ6_1
J16
IO_L42P_GCLK7_M1UDM_1
L15
IO_L41P_GCLK9_IRDY1_M1RASN_1
K15
IO_L36N_A8_M1BA1_1
H14
IO_L29P_A23_M1A13_1
C17
IO_L29N_A22_M1A14_1
C18
IO_L31P_A19_M1CKE_1
D17
IO_L31N_A18_M1A12_1
D18
IO_L33P_A15_M1A10_1
E16
IO_L33N_A14_M1A4_1
E18
IO_L35N_A10_M1A2_1
F18
IO_L35P_A11_M1A7_1
F17
IO_L1N_A24_VREF_1
F16
IO_L1P_A25_1
F15
IO_L38N_A4_M1CLKN_1
G18
IO_L38P_A5_M1CLK_1
G16
IO_L43N_GCLK4_M1DQ5_1
H18
IO_L43P_GCLK5_M1DQ4_1
H17
IO_L37N_A6_M1A1_1
H16
IO_L37P_A7_M1A0_1
H15
IO_L49N_M1DQ11_1
P18
IO_L49P_M1DQ10_1
P17
IO_L51P_M1DQ12_1
T17
IO_L52P_M1DQ14_1
U17
IO_L48N_M1DQ9_1
N18
IO_L48P_HDC_M1DQ8_1
N17
IO_L50N_M1UDQSN_1
N16
IO_L74P_AWAKE_1
P15
IO_L74N_DOUT_BUSY_1
P16
IO_L47N_LDC_M1DQ1_1
M18
IO_L47P_FWE_B_M1DQ0_1
M16
IO_L50P_M1UDQS_1
N15
IO_L53N_VREF_1
N14
IO_L46N_FOE_B_M1DQ3_1
L18
IO_L46P_FCS_B_M1DQ2_1
L17
IO_L42N_GCLK6_TRDY1_M1LDM_1
L16
IO_L51N_M1DQ13_1
T18
IO_L52N_M1DQ15_1
U18
IO_L30P_A21_M1RESET_1
F14
IO_L30N_A20_M1A11_1
G14
IO_L32P_A17_M1A8_1
H12
IO_L32N_A16_M1A9_1
G13
IO_L34P_A13_M1WE_1
K12
IO_L34N_A12_M1BA2_1
K13
IO_L36P_A9_M1BA0_1
H13
IO_L39P_M1A3_1
J13
IO_L39N_M1ODT_1
K14
IO_L40P_GCLK11_M1A5_1
L12
IO_L40N_GCLK10_M1A6_1
L13
IO_L53P_1
M14
IO_L61P_1
L14
IO_L61N_1
M13
VCCO_1 E17
VCCO_1 G15
VCCO_1 J14
VCCO_1 J17
VCCO_1 M15
VCCO_1 R17
C41
0.1uF
C41
0.1uF
U5-3
XC6SLX9CSG324
U5-3
XC6SLX9CSG324
IO_L62P_D5_2
R3
IO_L65P_INIT_B_2
U3
IO_L63P_2
T4
IO_L49P_D3_2
U5
IO_L48N_RDWR_B_VREF_2
T5
IO_L43N_2
V7
IO_L43P_2
U7
IO_L46N_2
T7
IO_L41N_VREF_2
V8
IO_L41P_2
U8
IO_L31N_GCLK30_D15_2
T8
IO_L30N_GCLK0_USERCCLK_2
V10
IO_L30P_GCLK1_D13_2
U10
IO_L29N_GCLK2_2
T10
IO_L23P_2
U11
IO_L16N_VREF_2
T11
IO_L14N_D12_2
V13
IO_L14P_D11_2
U13
IO_L3N_MOSI_CSI_B_MISO0_2
T13
IO_L12N_D2_MISO3_2
V14
IO_L12P_D1_MISO2_2
T14
IO_L1N_M0_CMPMISO_2
T15
IO_L2N_CMPMOSI_2
V16
IO_L2P_CMPCLK_2
U16
IO_L45N_2
V6
IO_L65N_CSO_B_2
V3
IO_L63N_2
V4
IO_L49N_D4_2
V5
IO_L32N_GCLK28_2
V9
IO_L45P_2
T6
IO_L23N_2
V11
IO_L62N_D6_2
T3
IO_L1P_CCLK_2
R15
IO_L3P_D0_DIN_MISO_MISO1_2
R13
IO_L13P_M1_2
N12
IO_L13N_D10_2
P12
IO_L16P_2
R11
IO_L29P_GCLK3_2
R10
IO_L31P_GCLK31_D14_2
R8
IO_L32P_GCLK29_2
T9
IO_L46P_2
R7
IO_L48P_D7_2
R5
IO_L64P_D8_2
N5
IO_L64N_D9_2
P6
VCCO_2 P9
VCCO_2 R12
VCCO_2 R6
VCCO_2 U14
VCCO_2 U4
VCCO_2 U9
C40
0.1uF
C40
0.1uF C42
0.1uF
C42
0.1uF
C47
1.0uF
C47
1.0uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
XILINX JTAG HDR FOR CONFIG OR CHIPSCOPE
JUMER TO SELECT BANK VOUT
DONE V17 PROGRAM V2
DBG4
DBG6
DBG8
DBG10
DBG12
DBG14
DBG16
DBG18
DBG20
DBG22
DBG2
DBG26
DBG28
DBG30
DBG32
DBG34
DBG36
DBG38
DBG40
DBG42
DBG44
DBG24
DBG46
DBG48
DBG3
DBG5
DBG7
DBG9
DBG11
DBG13
DBG15
DBG17
DBG19
DBG21
DBG25
DBG27
DBG29
DBG31
DBG33
DBG35
DBG37
DBG39
DBG41
DBG43
DBG23
DBG47
DBG45
DBG1
FPGA_TDO
FPGA_TMS
FPGA_TCK
FPGA_TDI
BNK3_VDDIO
DBG9
DBG10
DBG11
DBG12
DBG13
DBG14
DBG15
DBG16
DBG17
DBG18
DBG19
DBG20
DBG31
DBG21
DBG22
DBG23
DBG24
DBG25
DBG26
DBG27
DBG28
DBG29
DBG30
DBG7
DBG8
DBG1
DBG2
DBG3
DBG4
DBG5
DBG6
DBG47
DBG45
DBG46
DBG48
DBG43
DBG44
DBG34
DBG35
DBG36
DBG37
DBG38
DBG39
DBG40
DBG41
DBG42
DBG32
DBG33
BNK3_VDDIO
DGND
3p3V1p2V
DGND DGND DGND
3p3V
3p3V
DGND
3p3V
VTEST
DGND
DGND
DGND
1p2V
3p3V
DGNDDGND
3p3V
3p3V
FPGA_DONE_N3 FPGA_PRGM_N3
Title
Size Document Number Rev
Date: Sheet of
2.0
SPIO4 FPGA DEBUG, JTAG Interfaces & Pwr
B
612Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
Title
Size Document Number Rev
Date: Sheet of
2.0
SPIO4 FPGA DEBUG, JTAG Interfaces & Pwr
B
612Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
Title
Size Document Number Rev
Date: Sheet of
2.0
SPIO4 FPGA DEBUG, JTAG Interfaces & Pwr
B
612Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
C52
0.1uF
C52
0.1uF
U5-5
XC6SLX9CSG324
U5-5
XC6SLX9CSG324
TCK
A17
TDI
D15
TMS
B18
TDO
D16
SUSPEND
R16
CMPCS_B_2
P13
DONE_2
V17
PROGRAM_B_2
V2
GND
A1
GND
A18
GND
B13
GND
B7
GND
C16
GND
C3
GND
D10
GND
D5
GND
E15
GND
G12
GND
G17
GND
G2
GND
G5
GND
H10
GND
H8
GND
J11
GND
J15
GND
J4
GND
J9
GND
K10
GND
K8
GND
L11
GND
L9
VCCAUX B1
VCCAUX B17
VCCAUX E14
VCCAUX E5
VCCAUX E9
VCCAUX G10
VCCAUX J12
VCCAUX K7
VCCAUX M9
VCCAUX P10
VCCAUX P14
VCCAUX P5
VCCINT G7
VCCINT H11
VCCINT H9
VCCINT J10
VCCINT J8
VCCINT K11
VCCINT K9
VCCINT L10
VCCINT L8
VCCINT M12
VCCINT M7
GND M17
GND M2
GND M6
GND N13
GND R1
GND R14
GND R18
GND R4
GND R9
GND T16
GND U12
GND U6
GND V1
GND V18
C56
0.1uF
C56
0.1uF
C49
1.0uF
C49
1.0uF
D1 GRN_LED
D1 GRN_LED
C57
0.1uF
C57
0.1uF
D3 GRN_LED
D3 GRN_LED
C58
10uF
C58
10uF C60
0.1uF
C60
0.1uF
R9 750RR9 750R
C61
0.1uF
C61
0.1uF C62
10uF
C62
10uF
TP20TP20
1
U5-4
XC6SLX9CSG324
U5-4
XC6SLX9CSG324
IO_L54N_M3A11_3
D3
IO_L54P_M3RESET_3
E4
IO_L50P_M3WE_3
E3
IO_L55P_M3A13_3
F6
IO_L55N_M3A14_3
F5
IO_L51P_M3A10_3
F4
IO_L51N_M3A4_3
F3
IO_L53N_M3A12_3
G6
IO_L53P_M3CKE_3
H7
IO_L49P_M3A7_3
H6
IO_L49N_M3A2_3
H5
IO_L44P_GCLK21_M3A5_3
H4
IO_L44N_GCLK20_M3A6_3
H3
IO_L47P_M3A0_3
J7
IO_L47N_M3A1_3
J6
IO_L45N_M3ODT_3
K6
IO_L40P_M3DQ6_3
J3
IO_L42N_GCLK24_M3LDM_3
K3
IO_L42P_GCLK25_TRDY2_M3UDM_3
K4
IO_L43N_GCLK22_IRDY2_M3CASN_3
K5
IO_L43P_GCLK23_M3RASN_3
L5
IO_L45P_M3A3_3
L7
IO_L31P_3
L6
IO_L39P_M3LDQS_3
L4
IO_L83P_3
C2
IO_L83N_VREF_3
C1
IO_L52P_M3A8_3
D2
IO_L52N_M3A9_3
D1
IO_L50N_M3BA2_3
E1
IO_L48P_M3BA0_3
F2
IO_L48N_M3BA1_3
F1
IO_L46N_M3CLKN_3
G1
IO_L46P_M3CLK_3
G3
IO_L41N_GCLK26_M3DQ5_3
H1
IO_L41P_GCLK27_M3DQ4_3
H2
IO_L40N_M3DQ7_3
J1
IO_L38P_M3DQ2_3
K2
IO_L38N_M3DQ3_3
K1
IO_L37N_M3DQ1_3
L1
IO_L37P_M3DQ0_3
L2
IO_L36N_M3DQ9_3
M1
IO_L35P_M3DQ10_3
N2
IO_L35N_M3DQ11_3
N1
IO_L1N_VREF_3
N3
IO_L34N_M3UDQSN_3
P1
IO_L34P_M3UDQS_3
P2
IO_L2N_3
P3
IO_L33N_M3DQ13_3
T1
IO_L33P_M3DQ12_3
T2
IO_L32N_M3DQ15_3
U1
IO_L32P_M3DQ14_3
U2
IO_L36P_M3DQ8_3
M3
IO_L2P_3
P4
IO_L1P_3
N4
IO_L31N_VREF_3
M5
IO_L39N_M3LDQSN_3
L3
VCCO_3 E2
VCCO_3 G4
VCCO_3 J2
VCCO_3 J5
VCCO_3 M4
VCCO_3 R2
J4
50PIN_MALE_HDR
J4
50PIN_MALE_HDR
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
R11 750RR11 750R
R10 750RR10 750R
U5-6
XC6SLX9CSG324
U5-6
XC6SLX9CSG324
NC1
E7
NC2
E8
NC3
F7
NC4
E6
NC5
G8
NC6
F8
NC7
G11
NC8
F10
NC9
F11
NC10
E11
NC11
D12
NC12
C12
NC13
C13
NC14
A13
NC15 F12
NC16 E12
NC17 U15
NC18 V15
NC19 T12
NC20 V12
NC21 N10
NC22 P11
NC23 M10
NC24 N9
NC25 M11
NC26 N11
NC27 N7
NC28 P8
NC29 M8
NC30 N8
NC31 N6
NC32 P7
C101
100uF
C101
100uF
C54
0.1uF
C54
0.1uF
C53
0.1uF
C53
0.1uF
R12 750RR12 750R
C48
0.1uF
C48
0.1uF TP1TP1
1
D4 GRN_LED
D4 GRN_LED
C55
0.1uF
C55
0.1uF C100
100uF
C100
100uF
R72
10.0K
R72
10.0K
D2 GRN_LED
D2 GRN_LED
J3
hdr_3pin
J3
hdr_3pin
1
1
2
2
3
3
C63
1.0uF
C63
1.0uF
C51
0.1uF
C51
0.1uF
J2
hdr_6pin
J2
hdr_6pin
11
22
33
44
55
66
TP3TP3
1
C50
0.1uF
C50
0.1uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DUT INPUT LEVEL SHIFTERS
DUT OUTPUT LEVEL SHIFTERS
RSTUFF OPTIONS TO SUPPORT CPU ONLY
CAPABILITY (NO FPGA)
DUT_VDDIO
REF_CLKA
SDRDYN_A
SCS1N_A_R
SCLK_A_R
SCS0N_A_R
SMOSI_A_R
SCS2N_A_R
DUTCS2N_A
SCS0N_A
SCLK_A
DUT_SDA
DUT_VDDIO
SMISO_A
DUT_SCL
SMOSI_A SDRDYN_A
REF_CLKA
SCS0N_B
SCLK_B
SMISO_B
SMOSI_B
SCS1N_B
SCS2N_B
SCS3N_B
SDRDYN_B
SCS2N_B
SCS3N_B
SDRDYN_B
SCS1N_B
SCS0N_B
SCLK_B
SMISO_B
SMOSI_B
DUTCLKIN_R
DUTMISO_A_R
SCS1N_A
SCLK_A
SCS0N_A
SMOSI_A
SCS2N_A
DUTDRDYN_R
DUTSCLK_A
DUTCLKIN
DUTMISO_A
DUT_SDA
DUT_SCL
CPUMISO_A_R
SMISO_A
SCS2N_A
SCS1N_A
DUT_PWR_EN
DUT_PWR_EN
5VDUT_FLTERD
DUTMOSI_A
DUTCS0N_A
DUTCS1N_A
3p3V
3p3V
DGND
DGND
DGND
DGND
DGND
3p3V
DGND
3p3V_DUT
DGND
DGND
3p3V
3p3V_DUT
DGND
DGND
DGND
DGND
5p0V_DUT
DUTCLKIN 3
DUT_SDA3
DUT_PWR_EN3
DUT_SCL 3
CPU_CS1N_A 3
DUTDRDYN_A 3
CPUMISO_A 3
CPU_SCLK_A 3
CPU_CS0N_A 3
CPU_MOSI_A 3
DUT_PRSNT_N 3
CPU_CS2N_A 3
DUT_VDDIO11
Title
Size Document Number Rev
Date: Sheet of
2.0
SPIO4 FPGA GPSI32 Intrfc
B
712Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
Title
Size Document Number Rev
Date: Sheet of
2.0
SPIO4 FPGA GPSI32 Intrfc
B
712Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
Title
Size Document Number Rev
Date: Sheet of
2.0
SPIO4 FPGA GPSI32 Intrfc
B
712Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
U5-1
XC6SLX9CSG324
U5-1
XC6SLX9CSG324
IO_L33N_0
A8
IO_L39N_0
A11
IO_L41N_0
A12
IO_L37N_GCLK12_0
A10
IO_L35N_GCLK16_0
A9
IO_L62N_VREF_0
A14
IO_L64N_SCP4_0
A15
IO_L66N_SCP0_0
A16
IO_L4N_0
A3
IO_L6N_0
A5
IO_L8N_VREF_0
A6
IO_L5N_0
A4
IO_L10N_0
A7
IO_L1P_HSWAPEN_0
D4
IO_L1N_VREF_0
C4
IO_L2P_0
B2
IO_L2N_0
A2
IO_L3P_0
D6
IO_L3N_0
C6
IO_L4P_0
B3
IO_L5P_0
B4
IO_L6P_0
C5
IO_L10P_0
C7
IO_L8P_0
B6
IO_L11P_0
D8
IO_L11N_0
C8
IO_L33P_0
B8
IO_L34P_GCLK19_0
D9
IO_L34N_GCLK18_0
C9
IO_L35P_GCLK17_0
B9
IO_L36P_GCLK15_0
D11
IO_L36N_GCLK14_0
C11
IO_L37P_GCLK13_0
C10
IO_L38P_0
G9
IO_L38N_VREF_0
F9
IO_L39P_0
B11
IO_L41P_0
B12
IO_L62P_0
B14
IO_L63P_SCP7_0
F13
IO_L63N_SCP6_0
E13
IO_L64P_SCP5_0
C15
IO_L65P_SCP3_0
D14
IO_L65N_SCP2_0
C14
IO_L66P_SCP1_0
B16
VCCO_0 B10
VCCO_0 B15
VCCO_0 B5
VCCO_0 D13
VCCO_0 D7
VCCO_0 E10
R53 0RR53 0R
R17 33RR17 33R
C99
0.1uF
C99
0.1uF
C66
0.1uF
C66
0.1uF C64
0.1uF
C64
0.1uF
R55 0RR55 0R
R57 0R
R57 0R
C108
0.1uF
C108
0.1uF
U8
SN74LVC2T45SSOP
U8
SN74LVC2T45SSOP
VCCA 1
A1 2
A2 3
GND 4
DIRA2B 5
B2
6B1
7VCCB
8
C67
1.0uF
C67
1.0uF
C69
0.1uF
C69
0.1uF
R79 1.5KR79 1.5K
C73
10uF
C73
10uF
R20 33RR20 33R
R80 1.5KR80 1.5K
C105
0.1uF
C105
0.1uF
R18 33RR18 33R
R16 33RR16 33R
R13 33RR13 33R
C46
0.1uF
C46
0.1uF
C104
0.1uF
C104
0.1uF
R54 DNS
R54 DNS
J6
32PIN_FEM_HDR_RA
J6
32PIN_FEM_HDR_RA
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
U7
SN74LVC2T45SSOP
U7
SN74LVC2T45SSOP
VCCA 1
A1 2
A2 3
GND 4
DIRA2B 5
B2
6B1
7VCCB
8
R59 0R
R59 0R
R58 0R
R58 0R
C70
0.1uF
C70
0.1uF
C98
0.1uF
C98
0.1uF
U10
SN74LVC2T45SSOP
U10
SN74LVC2T45SSOP
VCCA 1
A1 2
A2 3
GND 4
DIRA2B 5
B2
6B1
7VCCB
8
C103
0.47uF
C103
0.47uF
C106
1.0uF
C106
1.0uF
C65
0.1uF
C65
0.1uF
R15 33RR15 33R
C68
0.1uF
C68
0.1uF
R56 0R
R56 0R
C71
0.1uF
C71
0.1uF
U6
SN74LVC2T45SSOP
U6
SN74LVC2T45SSOP
VCCA 1
A1 2
A2 3
GND 4
DIRA2B 5
B2
6B1
7VCCB
8
C72
0.1uF
C72
0.1uF
C109
1.0uF
C109
1.0uF
R14 33RR14 33R
R19 33RR19 33R
U9
SN74LVC2T45SSOP
U9
SN74LVC2T45SSOP
VCCA 1
A1 2
A2 3
GND 4
DIRA2B 5
B2
6B1
7VCCB
8
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Micro SD Card
DA2
CDA
DA3
CK
DA0
DA1
CD
DGND
DGND
DGND
3p3V3p3V
3p3V
3p3V
DA23 DA33
DA03 DA13
CDA3
CK3
CD 3
Title
Size Document Number Rev
Date: Sheet of
2.0
SPIO4 SD Card
B
812Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
Title
Size Document Number Rev
Date: Sheet of
2.0
SPIO4 SD Card
B
812Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
Title
Size Document Number Rev
Date: Sheet of
2.0
SPIO4 SD Card
B
812Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
C74
0.1uF
C74
0.1uF
R23
46.4K
R23
46.4K R24
46.4K
R24
46.4K
R22
46.4K
R22
46.4K
C75
10uF
C75
10uF
R21
10.0K
R21
10.0K
R25
46.4K
R25
46.4K R26
10.0K
R26
10.0K
J7
MICRO_SD
J7
MICRO_SD
DAT2
1
CD/DAT3
2
CMD
3
VDD
4
CLK
5
VSS
6
DAT0
7
DAT1
8
GND1 9
GND2 10
GND3 11
GND4 12
CD 13
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
USB, CPU JTAG
VUSB_DET
VUSB_RTN
VUSB_IN
DGND
DGND
DGND
DGND
DGND
3p3V
VUSB
DGND
DHSD_M2 DHSD_P2
RSTN2
TDI2
TCK2
TDO2
TMS2
VUSB_DET3,11
Title
Size Document Number Rev
Date: Sheet of
2.0
SPIO4 USB JTAG
B
912Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
Title
Size Document Number Rev
Date: Sheet of
2.0
SPIO4 USB JTAG
B
912Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
Title
Size Document Number Rev
Date: Sheet of
2.0
SPIO4 USB JTAG
B
912Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
R30
10.0K
R30
10.0K
R28 46.4KR28 46.4K
C79
0.1uF
C79
0.1uF
R33
10.0K
R33
10.0K
R32
10.0K
R32
10.0K
R31
10.0K
R31
10.0K
C78
10pF
C78
10pF F1
0R
F1
0R
J8
USB TYPE B PORT
J8
USB TYPE B PORT
VBUS
1D-
2D+
3
GND
4
E_GND0
5E_GND1
6
C76
0.1uF
C76
0.1uF
R27 0RR27 0R
R34
10.0K
R34
10.0K
C77
4.7uF
C77
4.7uF
J9
IDC20-2.54mm
J9
IDC20-2.54mm
VTref
1Vsupply 2
nTRST
3GND1 4
TDI
5GND2 6
TMS
7GND3 8
TCK
9GND4 10
RTCK
11 GND5 12
TDO
13 GND6 14
nSRST
15 GND7 16
DBGRQ
17 GND8 18
DBGACK
19 GND9 20
R29
68K
R29
68K
R35 0RR35 0R
C80
10uF
C80
10uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
2.0
SPIO4 Power Block Diagram
B
10 12Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
Title
Size Document Number Rev
Date: Sheet of
2.0
SPIO4 Power Block Diagram
B
10 12Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
Title
Size Document Number Rev
Date: Sheet of
2.0
SPIO4 Power Block Diagram
B
10 12Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
3.3V, 1.2V, 1.8V, DUT Power Supply
Test Points
Connector for using LI-Ion w/internal temp sense
TMP_SNS
1V2_SW
3V3_D_SW1
ISEN
IREF
VREFH
VBATT
5VIN VIN
CP1+
CP1-
VIN
PWR_ON
VBATT
DUT_VDDIO_MEAS
TP_CHG
TP_STAT
TP_USBSP
TP_PWRACK
3V3_D_SW2
TP_PWRACK
3V3_DUT_SW
3V3_DUT_SW
5V_DUT_OUT
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
1p2V
3p3V
1p8V
3p3V
DGND
DGND
DGND
DGND
DGND
DGND
1p2V 3p3V_DUT 5p0V_DUT3p3V 1p8V
DGND DGND
5p0V_DUT
3p3V
1p8V
1p2V
3p3V_DUT
VUSB
DGND
3p3V
VTEST
3p3V
DGND
DGND
3p3V
DGND
DGND
DGND
DGND
DGND
DGND
DGND
3p3V_DUT
3p3V
DGND
5p0V_DUT
DGND
DGND
SCL3
IRQ_PWR_N 3
ONSTAT 3
NRST_PWR 2
SDA3
DUT_VDDIO7
USBISEL3
VUSB_DET3,9
DUT_3VEN3 DUT_5VEN
3
Title
Size Document Number Rev
Date: Sheet of
2.0
SPIO4 POWER Supplies
B
11 12Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
Title
Size Document Number Rev
Date: Sheet of
2.0
SPIO4 POWER Supplies
B
11 12Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
Title
Size Document Number Rev
Date: Sheet of
2.0
SPIO4 POWER Supplies
B
11 12Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
R62 100KR62 100K
TP22TP22
1
C81
1.0uF
C81
1.0uF
TP10TP10
1
TP16TP16
1
C86
4.7uF
C86
4.7uF
F2
PTC_1A_1812
F2
PTC_1A_1812
in
1out 2
C90
10uF
C90
10uF
TP18TP18
1
U12
LM2750
U12
LM2750
VIN1
8
VIN2
9
C1+
10
C1-
7
VOUT1 1
VOUT2 2
SD_N
4GND1 3
GND2 5
GND3 6
GND4 DAP
TP14TP14
1
D10
GRN_LED
D10
GRN_LED
R43 10.0KR43 10.0K
C91
10uF
C91
10uF
R52 121KR52 121K
TP9TP9
1
C110
10uF
C110
10uF
C87
10uF
C87
10uF
TP21TP21
1
D12
DIODE ZENER
D12
DIODE ZENER C89
10uF
C89
10uF
PJ037A
J10
PJ037A
J10
TIP 1
RING 2
TP8TP8
1
TP11TP11
1
C107
10uF
C107
10uF
R41 1.5KR41 1.5K
C38
10uF
C38
10uF
L6
100MHZ FERRITE
L6
100MHZ FERRITE
U14
FDG6342L_SC70-6
U14
FDG6342L_SC70-6
R2 1
VOUTB 2
VOUTA 3
VIN
4
OFF
5R1/C1
6
D6
GRN_LED
D6
GRN_LED
C94
10uF
C94
10uF
R48
10.0K
R48
10.0K
C111
10uF
C111
10uF
L8
100MHZ FERRITE
L8
100MHZ FERRITE
C93
0.1uF
C93
0.1uF
R47
10.0K
R47
10.0K
J13
DNS
J13
DNS
11
22
33
C92
100uF
C92
100uF
R63 680KR63 680K C97
10uF
C97
10uF
D5
GRN_LED
D5
GRN_LED
U11
LP3910
U11
LP3910
TS
1
VBATT1
2
AGND 3
VREFH 4
LDO2EN
5
VLDO2 6
VIN1
7VLDO1 8
POWERACK
9
I_SEN 10
ADC2
11 ADC1
12
~IRQB 13
~NRST 14
CHG 15
STAT 16
BUCK1EN
17
VFB1 18
BCKGND1 19
VBUCK1 20
VIN2
21
VIN3
22
VBUCK2 23
BCKGND2 24
VFB2 25
ON/~OFF
26 I2C_SCL
27
VDDIO 28
I2C_SDA
29
ONSTAT 30
VBBFB 31
VBBOUT 32
VBBL2 33
BBGND1 34
VBBL1 35
VIN4
36
USBSUSP
37
USBISEL
38
BBGND2 39
DGND 40
VDD3
41 VDD2
42
VBATT3
43 VBATT2
44
USBPWR
45
VDD1
46
CHG_DET
47
I_REF 48
DAP 49
D11
GRN_LED
D11
GRN_LED
J12
DNS
J12
DNS
+1
-2
R60
10.0K
R60
10.0K
R46
10.0K
R46
10.0K
L3 2.2uHL3 2.2uH
1 2
R45 1.5KR45 1.5K
R37 0RR37 0R
R44 1.5KR44 1.5K
C95
10uF
C95
10uF
C88
10uF
C88
10uF
C112
0.1uF
C112
0.1uF
Q1
MMBT3904
Q1
MMBT3904
32
1
TP5TP5
1
D7
GRN_LED
D7
GRN_LED
R85
10.0K
R85
10.0K
TP15TP15
1
C85
0.1uF
C85
0.1uF
C39
10uF
C39
10uF
C83
10uF
C83
10uF R39 1.5KR39 1.5K
C82
10uF
C82
10uF
R42
650
R42
650
R64
10.0K
R64
10.0K
R36 750RR36 750R
C102
10uF
C102
10uF
R86
9.2K
R86
9.2K
L7
100MHZ FERRITE
L7
100MHZ FERRITE
C96
1.0uF C96
1.0uF
R40
100K
R40
100K
L4 2.2uHL4 2.2uH
1 2
R38 750RR38 750R
D8
GRN_LED
D8
GRN_LED
C84
4.7uF
C84
4.7uF
L5 2.2uHL5 2.2uH
1 2
R49 10.0KR49 10.0K
R61 10.0KR61 10.0K
TP12TP12
1
SW2SW2
A B
D9
DIODE_SCHOTTKY_1A
D9
DIODE_SCHOTTKY_1A
R51 4.64k_1%R51 4.64k_1%
TP13TP13
1
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