DS04-27235-2Ea
FUJITSU MICROELECTRONICS
DATA SHEET
Copyright©2002-2008 FUJITSU MICROELECTRONICS LIMITED Al l rights reserv ed
2006.8
ASSP For Power Supply Applications
(General Purpose DC/DC Converter)
2-Channel DC/DC Converter IC
with Overcurrent Protection Symmetrical-Phase Type
MB39A106
DESCRIPTION
The MB39A106 is a symmetrical-phase type of two-channel, DC/DC converter IC using pulse width modulation
(PWM) , incorporating an overcurrent protection circuit (requiring no current sense resistor) and an overvoltage
protection circuit. Providing high output driving capabilities, the MB39A106 is suitable for down-conversion.
The MB39A106 adopts both synchronous rectification to provide high efficiency and symmetrical phasing (two
anti-phase triangular wa ves) which contributes to making the input capacitor small.
The MB39A106 contains a Bootstrap diode resulting in a reduced number of components used. It also contains
a v ariety of protect ion feature s which output the protection status upon detection of an ov ervolt age or ov ercurrent
while reducing the number of external protective devices required.
The result is an ideal built-in power supply for driving products with high speed CPU’s such as home TV game
devices and notebook PC’s.
FEATURES
Built-in bootstrap diode
Built-in timer-latch overcurrent protection circuit (requiring no current sense resistor)
Built-in timer-latch overvoltage protection circuit
Synchronous rectification system providing high efficiency
Power supply v oltage range: 6.5 V to 18 V
PWRGOOD terminals (open-drain) to output the protection stat us
Symmetr ic al-phas e system redu cing the input capacitor loss
Built-in chan n el con trol fu nc tion
One type of package (TSSOP-30pin : 1 type)
Reference voltage: 3.5 V ± 1 %
Error amplifier threshold voltage: 1.23 V ± 1 % (Ta = 0 °C to + 85 °C)
Support for frequency setting using an external resistor (Frequency setting capacito r integrated)
Oscillation frequency range: 100 kHz to 500 kHz
Standby current : 0 µA (Typ)
Built-in circuit for load-independent soft-start and discharge control
Built-in totem-pole output for N-ch MOS FET
One type of package (TSSOP-30 pin : 1 type)
APPLICATION
Home Video Game
IP phone
Printer etc.
MB39A106
2
PIN ASSIGNMENT (TOP VIEW)
(FPT-30P-M04)
INE1 :
FB1 :
CS1 :
NC :
RT :
CTL :
SGND :
VREF :
CTL1 :
CTL2 :
CSCP :
PWRGOOD :
CS2 :
FB2 :
INE2 :
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
: CB1
: OUT1-1
: VS1
: OUT2-1
: PGND1
: ILIM1
: VCC
: ILIM2
: VB
: NC
: PGND2
: OUT2-2
: VS2
: OUT1-2
: CB2
MB39A106
3
PIN DESCRIPTION
Pin No. Symbol I/O Descriptions
1INE1 I CH1 error amp inverted input terminal
2 FB1 O CH1 error amp output terminal
3CS1CH1 soft-start capacit or connection terminal
4NCNo connection
5RTTriangular waveform oscillation frequency setting resistor connection
terminal
6CTLI
Power supply control terminal
“H” level : IC operating mode
“L” level : IC Standby mode
7SGNDGround terminal
8 VREF O Reference voltage output terminal
9CTL1I
CH1 control terminal
“H” level : CH1 ON state
“L” level : CH1 OFF state and prot ection status reset
10 CTL2 I CH2 control terminal
“H” level : CH2 ON state
“L” level : CH2 OFF state and prot ection status reset
11 CSCP Timer-latch short-circuit protection capacitor connection terminal
12 PWRGOOD O CH1, CH2 protection status output terminal
13 CS2 CH2 soft-start capacit or connection terminal
14 FB2 O CH2 error amp output terminal
15 INE2 I CH2 error amp inverted input terminal
16 CB2 CH2 boot capacitor connection terminal
Connect a capacitor between the CB2 and VS2 terminals.
17 OUT1-2 O CH2 totem-pole output terminal (External main- side FET gate drive)
18 VS2 CH2 external main-side FET source connection terminal
19 OUT2-2 O CH2 totem-pole output terminal (External synchronous-rectification-side FET
gate drive)
20 PGND2 Ground terminal
21 NC No connection
22 VB O Output circuit bias output terminal
23 ILIM2 I CH2 overcurrent detection resistor connection terminal
24 VCC Reference voltage, control circuit power supply terminal
25 ILIM1 I CH1 overcurrent detection resistor connection terminal
26 PGND1 Ground terminal
27 OUT2-1 O CH1 totem-pole output terminal (External synchronous-rectification-side FET
gate drive)
28 VS1 CH1 external main-side FET source connection terminal
29 OUT1-1 O CH1 totem-pole output terminal (External main- side FET gate drive)
30 CB1 CH1 boot capacitor connection terminal
Connect a capacitor between the CB1 and VS1 terminals.
MB39A106
4
BLOCK DIAGRAM
+
+
VREF
Buff
100
k
6 k
Error
Amp1
1.23 V
1.38 V
118 µA
+
+PWM
Comp.1
+
+
9
1
Open : CH1 ON
L : CH1 OFF
VTH = 1.4 V
3
CTL1
FB1
INE1
CS1
Drv
1-1
Drv
2-1
230
29
28
27
26
25
Dead Time
Modulation 1
Current
Protection
Logic
22
CB1
OUT1-1
VS1
OUT2-1
PGND1
ILIM1
VB
VB Reg.
+
+
VREF
Buff
100
k
6 k
1.23 V
1.38 V
118 µA
3 µA
3 µA
+
+
+
+
10
15
Open : CH2 ON
L : CH2 OFF
VTH = 1.4 V
13
CTL2
FB2
INE2
CS2
Drv
1-2
Drv
2-2
14 16
17
18
19
20
23
Dead Time
Modulation 2
Current
Protection
Logic
CB2
OUT1-2
VS2
OUT2-2
PGND2
ILIM2
CTL2 = H
Max Duty 81%
Dtr ± 6%
+
+
SCP Comp.
3.1 V
11CSCP
12
4
21
8
5SGND
bias 1.23 V VCC
VREF
VREF VR1 Power
ON/OFF
CTL
RT
CTL
CTL1
CTL2
CTL
CTL1
CTL2
10 µA
VREF
UVLO OSC
45 pF 3.5 V
S
Latch
Latch2
R
SQ
R
Latch1
PWRGOOD
Protection
control
signal
3.0 V
CT1
1.8 V
3.0 V
CT2
1.8 V
OVP
Comp.1
Error
Amp2
OVP
Comp.2
PWM
Comp.2
7
6
NC
NC
CTL
Max Duty 81%
Dtr ± 6%
24
VCC
6 V
CH1
CH2
CTL1 = H H: at OCP
H: at OCP
H: at OVP
H: at OVP
H: at OVP
H: at OCP
H: at SCP
L: at protection
operation
to Error amp reference
H: at
UVLO release
H: priority
L priority
L priority
L priority
L priority
OCP
Comp.2
H : ON (Power On)
L : OFF (Standby mode)
VTH = 1.4 V
MB39A106
5
ABSOLUTE MAXIMUM RATINGS
* : The packages are mounted on the dual-sided epoxy board (10 cm × 10 cm) .
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Parameter Symbol Condition Rating Unit
Min Max
Power-supply voltage VCC ⎯⎯20 V
Boot voltage VCB CB terminal 25 V
Output current IO⎯⎯120 mA
Peak output curr e nt IOP Duty 5%
(t = 1 / fOSC × Duty) 800 mA
Power dissipation PDTa +25 °C 1390* mW
Storage temperature TSTG ⎯−55 +125 °C
MB39A106
6
RECOMMENDED OPERATING CONDITIONS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended ope rating condition ranges. Oper ation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
representatives beforehand.
Parameter Symbol Condition Value Unit
Min Typ Max
Power-supply voltage VCC 6.5 12 18 V
Boot voltage VCB CB terminal ⎯⎯24 V
Reference voltage output current IOR VREF terminal 1 0mA
Bias output current IOB VB terminal 1 0mA
Input voltage
VIN INE terminal 0 VCC 1.8 V
VCTL CTL1, CTL2 terminal 0 VREF V
CTL terminal 0 VCC V
Output voltage VPG PWRGOOD te rminal 0 15 V
Output current IO⎯− 100 ⎯+100 mA
Peak output curr e nt IOP Duty 5%
(t = 1 / fOSC × Duty) 700 ⎯+700 mA
Oscillation frequency fOSC 100 300 500 kHz
Timing resistor RT30 47 130 k
Boot capacitor CB⎯⎯0.1 1.0 µF
Reference voltage output
capacitor CREF VREF ter minal 0.1 1.0 µF
Bias output capacitor CVB VB terminal 1.0 4.7 10 µF
Soft-start capacitor CS⎯⎯0.1 1 µF
Short-circuit detection capacitor CSCP ⎯⎯0.01 1 µF
Overcurrent detection setting
resistor RLIM 0.1 1 10 k
Operating ambient temperature Ta ⎯− 30 + 25 + 85 °C
MB39A106
7
ELECTRICAL CHARACTERISTICS (VCC = 12 V, VB = 0 mA, VREF = 0 mA, Ta = +25 °C)
(Continued)
Parameter Symbol Pin
No. Conditions Value Unit
Min Typ Max
Reference
Voltage
Block [REF]
Output voltage VREF 8Ta = + 25 °C 3.465 3.500 3.535 V
VREF/
VREF 8Ta = 0 °C to + 85 °C 0.5* ⎯%
Input stability Line 8 VCC = 6.5 V to 18 V 110mV
Load stability Load 8 VREF = 0 mA to 1 mA 310mV
Short-circuit
output current IOS 8VREF = 0 V 40 20 10 mA
Bias Voltage
Block [VB] Output voltage VB22 5.88 6.00 6.12 V
Triangular
Waveform
Oscillator
Block [OSC]
Oscillation
frequency fOSC 17, 29 RT = 47 k270 300 330 kHz
Frequency/
temperature
variation
fOSC/
fOSC 17, 29 Ta = 0 °C to + 85 °C 1* ⎯%
Undervoltage
(VCC)
Lockout Circuit
Block [UVLO]
Threshold
voltage VTH 8VREF = 2.6 2.8 3.0 V
Hysteresis
width VH8⎯⎯0.2* V
Reset voltage VRST 8VREF = 1.7 2.1 2.5 V
Short-circuit
Protection
Circuit Block
[SCP]
Threshold
voltage VTH 11 0.65 0.70 0.75 V
Input source
current ICSCP 11 ⎯− 14 10 6µA
Overcurrent
Protection
Circuit Block
[OCP]
ILIM terminal
input current ILIM 23, 25 RT = 47 k106 118 130 µA
Offset voltage VIO 23, 25 ⎯⎯1* mV
Overvoltage
Protection
Circuit Block
[OVP]
Threshold
voltage VTH 1, 15 INE = 1.35 1.38 1.41 V
Input bias
current IB1, 15 INE = 0 V 730 110 nA
Protection
Status
Output Circuit
Block
[PWRGOOD]
Output leakage
current ILEAK 12 PWRGOOD = 5 V ⎯⎯40 µA
Output “L” level
voltage VOL 12 PWRGOOD = 1 mA 0.1 0.4 V
Soft-start
Circuit Block
[CS] Charge current ICS 3, 13 ⎯− 4.2 3.0 1.8 µA
MB39A106
8
(VCC = 12 V, VB = 0 mA, VREF = 0 mA, Ta = +25 °C)
(Continued)
Parameter Symbol Pin
No. Conditions Value Unit
Min Typ Max
Error Amp
Block
[Error Amp]
Threshold
voltage
VTH1 1, 15 FB = 2.4 V,
Ta = + 25 °C1.221 1.230 1.239 V
VTH2 1, 15 FB = 2.4 V,
Ta = 0 °C to + 85 °C1.218 1.230 1.242 V
Input bias
current IB1, 15 INE = 0 V 730 110 nA
Voltage gain AV2, 14 DC 60 100 dB
Frequency
bandwidth BW 2, 14 AV = 0 dB 1.5* MHz
Output voltage VFBH 2, 14 3.2 3.4 V
VFBL 2, 14 ⎯⎯40 200 mV
Output so urce
current ISOURCE 2, 14 FB = 2.4 V ⎯− 21mA
Output sink
current ISINK 2, 14 FB = 2.4 V 150 250 ⎯µA
PWM
Comparator
Block
[PWM Comp.]
Threshold
voltage
VTL 2, 14 Duty cycle = 0 %1.7 1.8 V
VTH 2, 14 Duty cycle = Dtr 2.86 3.00 V
Dead Time
Control Block
[DTC]
Maximum duty
cycle Dtr 17, 29 RT = 47 k75 81 87 %
Output Block
[Drive]
Output
current
(main side)
ISOURCE1 17, 29
OUT1 = 12 V, CB = 17 V,
VS = 12 V,
Duty 5 %
(t = 1/ fOSC × Duty)
⎯− 700* mA
ISINK1 17, 29
OUT1 = 17 V, CB = 17 V,
VS = 12 V,
Duty 5 %
(t = 1/ fOSC × Duty)
900* mA
Output voltage
(main side)
VOH1 17, 29 OUT1 = 100 mA,
CB = 17 V, VS = 12 V VCB
2.5 VCB
0.9 V
VOL1 17, 29 OUT1 = 100 mA,
CB = 17 V, VS = 12 V VS
+ 0.9 VS
+ 1.4 V
Output current
(synchronous
rectification
side)
ISOURCE2 19, 27 OUT2 = 0 V,
Duty 5 %
(t = 1/ fOSC × Duty) ⎯− 750* mA
ISINK2 19, 27 OUT2 = 6 V,
Duty 5 %
(t = 1/ fOSC × Duty) 900* mA
MB39A106
9
(Continued) (VCC = 12 V, VB = 0 mA, VREF = 0 mA, Ta = + 25 °C)
*: Standard design value
Parameter Symbol Pin
No. Conditions Value Unit
Min Typ Max
Output Block
[Drive]
Output voltage
(synchronous
rectification
side)
VOH2 19, 27 OUT2 = 100 mA 3.5 5.1 V
VOL2 19, 27 OUT2 = 100 mA 1.0 1.4 V
Diode voltage VD16, 30 VB = 10 mA 0.8 1.0 V
Dead time
tD1 29, 27,
17, 19
OUT1 = OUT2 = OPEN,
VS = 0 V
OUT2 : OUT1 : 40 80 120 ns
tD2 29, 27,
17, 19
OUT1 = OUT2 = OPEN,
VS = 0 V
OUT1 : OUT2 : 60 120 180 ns
Control Block
[CTL, CTL1,
CTL2]
Output ON
condition VON 9, 10 2VREF V
Output OFF
condition VOFF 9, 10 00.8 V
Output ON
condition VON 62VCC V
Output OFF
condition VOFF 600.8 V
Input curren t ICTL 9, 10 CTL1 = CTL2 = 0 V 44 35 29 µA
6CTL = 5 V 50 75 µA
General
Standby
current ICCS 24 CTL = 0 V 010µA
Power-supply
current ICC 24 CTL = 5 V 15 23 mA
MB39A106
10
TYPICAL CHARACTERISTICS
(Continued)
Ta = +25 °C
VCC = 12 V
CTL = 5 V
5
4
3
2
1
00 5 10 15 20 25
Power Supply current ICC (mA)
Reference volt ag e VREF (V)
Power Supply Current vs. Power Supply Voltage Reference Voltag e vs. Power Supply Voltage
Power supply voltage VCC (V) Power supply voltage VCC (V)
CTL Terminal Current, Reference Voltage
vs. CTL Terminal Voltage
Reference voltage VREF (%)
Ambient temperature Ta (°C)
Reference voltage VREF (V)
Reference Voltage vs. Ambient Temperature
CTL terminal voltag e VCTL (V)
CTL terminal current ICTL (µA)
Triangular Wave Oscillation Frequency
vs. Timing Resistor
Triangular wave oscillation
frequency fOSC (kHz)
Timing resistor RT ()
Ta = +25 °C
CTL = 5 V
20
18
16
14
12
10
8
6
4
2
00 5 10 15 20
Ta = +25 °C
CTL = 5 V
VREF = 0 mA
6
5
4
3
2
1
00 5 10 15 20
VCC = 12 V
CTL = 5 V
VREF = 0 mA
2.0
1.5
1.0
0.5
0.0
0.5
1.0
1.5
2.0
40 20 0 +20 +40 +60 +80 +100
Ta = +25 °C
VCC = 12 V
VREF = 0 mA
500
400
300
200
100
0
5
4
3
2
1
0
0 5 10 15 20
ICTL
VREF
Ta = +25 °C
VCC = 12 V
CTL = 5 V
1000
100
1010 100 1000
Reference Voltag e vs. Load Current
Reference vo ltag e VREF (V)
Load current IREF (mA)
MB39A106
11
(Continued)
+
+
+
1
(15)
3
(13) 2
(14)
IN OUT
Error Amp1
(Error Amp2)
1 µF10 k
10 k1.23 V
4.2 V VCC = 12 V
10 k
2.4 k
240 k
10 k
40
30
20
10
0
10
20
30
40
180
90
0
90
180
100 1 k 10 k 100 k 1 M 10 M
Ta = +25 °C
A
V
ϕ
VCC = 12 V
CTL = 5 V
1.244
1.242
1.240
1.238
1.236
1.234
1.232
1.230
1.228
1.226
1.224
1.222
1.220
1.218
40 20 0 +20 +40 +60 +80 +100
Ta = +25 °C
RT = 47 k
CTL = 5 V
330
325
320
315
310
305
300
295
290
285
280
275
270 0 5 10 15 20
Triangular Wave Oscillation Frequency
vs. Ambient Temperature
Triangular wave oscillation
frequency fOSC/fOSC (%)
Ambient temperature Ta ( °C)
Error Amplifier Threshold Voltage
vs. Ambient Temperature
Error amplifier threshold
voltage VTH (V)
Gain AV (dB)
Frequency f (Hz)
Triangular Wave Oscillation Frequency
vs. Power Supply Voltage
Power supply voltage VCC (V)
Triangular wave oscillation
frequency fosc (kHz)
Ambient temperature Ta ( °C)
Phase φ (deg)
VCC = 12 V
RT = 47 k
CTL = 5 V
2
1.5
1
0.5
0
0.5
1
1.5
2
40 20 0 +20 +40 +60 +80 +100
Error Amplifier, Gain, Phase
vs. Frequency
MB39A106
12
(Continued)
1600
1400
1200
1000
800
600
400
200
0
1390
40 20 0 +20 +40 +60 +80 +100
Power Dissipation vs. Ambient Te mperature
Power dissipation PD (mW)
Ambient temperature Ta ( °C)
MB39A106
13
FUNCTIONS
1. DC/DC Converter Functions
(1) Reference voltage block (Ref)
The reference voltage circuit generates a temperature-compensated reference voltage (typically 3.5 V) using
the v o lta ge supplie d from the powe r supply te rminal (pin 24) . The voltage is use d as the r eference volta ge for
the IC’s interna l ci rcu it.
The reference voltage can be used to supply a load current of up to 1 mA to an external device through the
VREF terminal (pin 8) .
(2) Triangular-wave oscillator block (OSC)
The triangular waveform oscillator incorporates a triangular oscillation frequency setting capacitor connected
respectively to the RT terminal (pin 5) to generate triangular oscillation waveforms CT1 (amplitude of 1.8 V to
3.0 V) and CT2 (amplitude of 1.8 V to 3.0 V in antiphase with CT1). The symmetrical-phase system using the
two opposite-p ha se triangular waves reduces the input ripple curren t, re su ltin g in a s m alle r input capa cit or.
The triangular oscillation waveforms are input to the IC’s internal PWM comparator.
(3) Error amplifier block (Error Amp1, Error Amp2)
The error amplifier detects the DC/DC con verter output voltage and outputs PWM control signals. By connecting
a feedbac k resistor and capacitor between the output terminal and inv erted input terminal, it is possible to create
any desired level of loop gain, thereby providing stable phase compensation to the system.
Also, it is possible to prevent rush current at power supply star t-up by connecting a soft-star t capacitor to the
CS1 terminal (pin 3) or CS2 terminal (pin 13), the non-inver ted input terminal for Error Amp. The use of Error
Amp for soft-start detection makes it possible for a system to operate on a fixed soft-start time that is independent
of the output load on the DC/ DC converter.
(4) PWM comparator block (PWM Comp.)
The PWM comparator is a voltage-pulse width modulator that controls the output duty depending on the
input/output voltage.
Main side : Turns the output transistor on in the intervals in which the error amplifier output voltage is higher
than the triangular wave v oltage .
Synchronous rectificatio n side : Turns the output tran sistor on in the intervals in which th e error amplifier ou tput
voltage is lower than the triangular wave voltage.
(5) Output block
The output circuits on the main side and on the synchronous rectification side are both in the totem pole
configuratio n, capable of driving an external N-ch MOS FET.
In addition, because the output drive ability (700 mA Max : Duty 5%) is high, the gate source capacity is
large and the FET of low ON resistor can be use d .
MB39A106
14
2. Channel Control Function
Channels , main, VB and PWRGOO D are turned on and off d epending on the v oltage le v els at the CTL terminal
(pin 6), CTL1 terminal (pin 9) and CTL2 terminal (pin 10).
Channel On/Off Setting Conditions
*: Undefined
3. Protective Functions
(1) Undervoltage lockout protection circuit (UVLO)
The transien t state or a mome ntary drops in supply v olt age , which occu rs when the po w er supp ly is turned on,
may cause the control IC to malf uncti on , result ing in br ea kd own or deg r ada t ion of th e system. To prevent su ch
malfunctions , the undervoltage lock out protection circuit detects the internal reference v oltage lev el with respect
to the power supply voltage, turns off the output transistor, and sets the dead time to 100% while holding the
CSCP terminal (pin 11) at the “L” level and setting the PWRGOOD terminal (pin 12) to the “L” level.
The system is restored when the supply voltage reaches the threshold voltage of the undervoltage lockout
protection circuit.
(2) Timer-latch overcurrent protection circuit block (OCP)
The timer-latch overcurrent protection circuit is actuated upon completion of the soft-start period. When an
overcurrent flow s , th e circuit dete cts t he increa se in t he voltage betw een the main-sid e FET’s drain and so urce
using the main-side FET ON resistor, actuates the timer circuit, and starts charging the capacitor CSCP connected
to the CSCP terminal (pin 11). If the overcurr ent r ema ins flowing beyond the predet ermined period of time, the
circuit sets the latch to tur n off th e FETs on the ma in side and synchronous rectification side of each channel
while setting the PWRGO OD terminal (pin 12) to t he “L” lev el. The det ection current v alue can be set by re sistor
RLIM1 connected bet ween the main-side FET’ s dr ain and the ILIM1 terminal (pin 25) and resistor RLIM2 connected
betwee n the drain and the ILIM2 terminal (pin 23).
To reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal
(pin 6) to the “L” level to lower the VREF terminal (pin 8) voltage to 1. 7 V (Min ) or less. It can also be r eset by
setting both of t he CTL1 t erminal (pin 9) and CTL 2 t erminal (pin 10) t o the “ L” level. (Refer to “1. Setting Time r-
Latch Overcurrent Detection Curren t” in ABOUT TIMER-LATCH PROTECTION CIRCUIT.)
(3) Timer-latch short-circuit protection circuit (SCP)
The shor t-circuit detection comparator (SCP Comp.) detects the output voltage level and, if the error amplifier
output voltage of either channel reaches the short-circuit detection voltage (typically 3.1 V), the timer circuit is
actuated to start charging the external capacitor Cscp connected to the CSCP terminal (pin 11).
When the capaci tor voltage reaches about 0.7 V, the circuit turns off the output t ransistor and sets the dead time
to 100%.
The PWRGOOD terminal (pin 12) is fixed at the “L” level.
To reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal
(pin 6) to the “L” level to lower the VREF terminal (pin 8) voltage to 1. 7 V (Min ) or less. It can also be r eset by
setting both of the CTL1 t er minal (pin 9) and CTL 2 ter minal ( pin 10) to the “L” level. (Refer to “2. Setting Time
Constant for Timer-Latch Short-Circuit Protection Circuit” in ABOUT TIMER-LATCH PROTECTION CIRCUIT.)
CTL CTL1 CTL2 Power CH1 CH2 VB PWRGOOD
L** OFF OFF OFF OFF OFF
HLL ON OFF OFF ON ON
HHL ON ON OFF ON ON
HLHON OFF ON ON ON
HHH ON ON ON ON ON
MB39A106
15
(4) Timer-latch overvoltage protection circuit block (OVP)
When the over voltage detection comparator (OVP Comp.) provided for each channel detects the DC/DC con-
verter’s output voltage level exceeding its threshold voltage, the timer-latch overvoltage protection circuit actuates
the timer circuit and starts charging the capacitor CSCP connected to the CSCP terminal (pin 11). If the overvoltage
remains applied beyond the predetermined period of time, the circuit sets the latch to turn off the FET on the
main side of each channel while setting the PWRGOOD terminal (pin 12) to the “L” level.
To reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal
(pin 6) to the “L” level to lower the VREF terminal (pin 8) voltage to 1. 7 V (Min ) or less. It can also be r eset by
setting both of the CTL1 terminal (pin 9) and CTL2 terminal (pin 10) to the “L” level. (Refer to “3. Setting
Overvoltage Detection by the Timer-Latch Overvoltage Protection Circuit” in ABOUT TIMER-LATCH PRO-
TECTION CIRCUIT.)
(5) Protection status output c ircuit block (PWRGOOD)
The protection status output circuit outputs the “L” level signal to the PWRGOOD terminal (pin 12) when each
protection circuit is actuated.
MB39A106
16
SETTING THE OUTPUT VOLTAGE
< CH1, CH2 >
SETTING THE TRIANGULAR OSCILLATION FREQUENCY
The triangular oscillation frequency is determined by the timing resistor (RT) connected to the RT terminal (pin 5).
Triangular oscillation frequency: fOSC
+
+
15
1
13
(CS2)
CS1
(INE2)
INE1
V
O
R1
R2
1.23 V
Error Amp 1.23
R2
V
O
(V) =(R1 + R2)
3
fOSC (kHz) := 14100
RT (k)
MB39A106
17
SETTING THE SOFT-START AND DISCHARGE TIMES
To prevent rush currents when the IC is turned on, you can set a soft-start by connecting soft-start capacitors
(CS1 and CS2) to the CS1 terminal (pin 3) f or ch annel 1 and the CS2 terminal (pin 13) f or cha nnel 2, respectiv ely.
Setting the e ach control t erminals (CTL1 and CTL2) fr om “L” to “OPEN” switches SW1 a nd SW2 fr om B to A to
charge the external soft-st a rt capacitors (CS1 and CS2) conne cted to the CS1 and CS2 te rminals at 3 µA.
The error amplifier output (FB1 or FB2) is determined by comparison between the lower one of the potentials
at two no ninverted input terminals (1.23 V, CS terminal volta ges) and the in v erted input terminal voltage (-INE).
The FB terminal voltage during the soft-star t period is therefore deter mined by comparison between the -INE
ter min al an d CS te rminal voltages. The DC/DC c onverter outpu t voltage ri ses in p roportion to the CS termin al
voltage as the soft-s tart capacitor connected to the CS terminal is charged.
The soft-start time is obtained from the following equation:
Soft-start time: ts (time to output 100%)
ts (s) := 0.41 × CS (µF)
Setting the each control terminals (CTL1 and CTL2) from “OPEN” to “L” switches SW1 and SW2 from A to B.
Then the IC discharges the soft-start capacitors (CS1 and CS2) charged at about 3.4 V using the internally set
discharge resistor (Rs := 6 k) and lowers the output voltage regardless of the DC/DC converter load current.
The discharge time is obta ined from the following equation:
Discharge time: toff (time to output 10%)
toff (s) := 0.02 0 × CS (µF)
OPEN
L
t
CS terminal voltage
:= 3.4 V
:= 1.23 V
:= 0.123 V
:= 0 V
Error Amp block comparison
voltage to INE voltage
CTL signal
Soft-start time (ts) Discharge time (toff)
MB39A106
18
<Soft-start circuit>
TREATMENT OF UNUSED CS TERMINALS
When the soft-start function is not used, the CS1 terminal (pin 3) and CS2 t erminal (pin 13) should be left open.
< Operation Without Soft-start Setting >
+
+
9
10
1
13
R1
R2
(CS2)
CS1
INE1
CTL2
CTL1
VREF
Open : CH ON
L : CH OFF
VTH = 1.4 V
Buff
CTL1 = H
A
B
100 k
SW1 (SW2)
6 k
Error Amp
1.23 V
3 µA
3
Soft-start
Discharge
L priority
13 CS2
3CS1
“OPEN”
“OPEN”
MB39A106
19
ABOUT TIMER-LATCH PROTECTION CIRCUIT
1. Setting Timer-Latch Overcurrent Detection Current
The overcurrent protection circuit is actuated upon completion of the soft-start period. When an overcurrent
flows, the circuit detects the increase in the voltage between the main-side FET’s drain and source using the
main-side FET ON resistor (RON), actuates the timer circuit, and starts charging the capacitor CSCP connected
to the CSCP terminal (pin 11). I f the overcurrent remains flo wing be yond the predetermined period of time, the
circuit sets the latch to tur n off th e FETs on the ma in side and synchronous rectification side of each channel
while setting the PWRGOOD ter minal (pin 12) to th e "L" level. The detection curr ent value can b e set by the
resistors (RLIM1 and RLIM2) connected between the main-side FET’s drain and the ILIM1 terminal (pin 25) and
betwee n the drain and the ILIM2 terminal (pin 23), respectively.
The internal current (ILIM) can be set by the timing resistor (RT) connected to the RT terminal (pin 5).
Internal current value: ILIM
Detection current value: IOCP
RLIM: Overcurrent detection resistor
RON: Main-side FET ON resistor
VIN: Input voltage
VO: DC/DC converter output voltage
fOSC: Oscillation frequency
L: Coil inductance
To reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal
(pin 6) to the "L" level to lower the VREF terminal (pin 8) voltage to 1.7 V (Min) or less. It can also be reset by
setting both of the CTL1 terminal (pin 9) and CTL2 terminal (pin 10) to the "L" level.
<Overcurrent detection circuit>
ILIM (µA) := 5546
RT (k)
IOCP (A) := ILIM(A) × RLIM()
RON () (VIN(V) VO(V)) × VO(V)
2 × VIN(V) × fOSC(Hz) × L(H)
+
11
12
23
28
18
CSCP
Current
Protection
Logic
CTL
CTL1
CTL2
118 µA
10 µA
VREF
UVLO
S
Latch
Latch2
R
PWRGOOD
ILIM1
(ILIM2)
VS1
(VS2)
VIN
M1
25
MB39A106
20
2. Setting Time Constant for Timer-Latch Short-Circuit Protection Circuit
Each channel uses t he short-circuit detection compar ator (SCP Comp.) to alw a ys compar e the error am plifier’s
output level to the reference voltage.
While the DC/DC converter load cond itions a re stable on both channels, the short-circuit detection co mparator
keeps its output at the “H” level and the CSCP terminal (pin 11) remains at the “L” level.
If a load condition changes rapidly due to a short-circuit of the load, causing the output voltage to drop , the short-
circuit detection comparator chan ges i ts o utpu t to t he “ L” level. This causes th e external short-circuit protection
capacitor Cscp connected to the CSCP terminal to be charged at 10 µA.
Short-circuit detection time (tSCP)
tSCP (s) := 0.070 × CSCP (µF)
When capacitor Cscp is charg ed to the threshold voltage (VTH := 0.70 V), the protection circuit sets th e latch and
tur ns o ff the extern al FET (setti ng the de ad time to 100%) . At this time, the latch inp ut is closed . As the re sult,
the CSCP terminal is held at the “Llevel and the PWRGOOD terminal is set to “L” level. The protection circuit
closes both channels even when a short-circuit is detected on only either.
To reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal
(pin 6) to the “L” level to lower the VREF terminal (pin 8) voltage to 1. 7 V (Min ) or less. It can also be r eset by
setting both of the CTL1 terminal (pin 9) and CTL2 terminal (pin 10) to th e “L” level.
<Timer-lat c h sh o rt- circuit protec tion circuit>
+
+
+
11
12
1
15
VO
R1
R2
(INE2)
INE1
2
14
(FB2)
FB1
CSCP
Error
Amp
SCP
Comp.
CTL
CTL1
CTL2
3.1 V
1.23 V
10 µA
VREF
UVLO
S
Latch
Latch2
R
PWRGOOD
MB39A106
21
3. Setting Overvoltage Detection by the Timer-Latch Overvo ltage Protection Circuit
An ov erv oltage output from the DC/ DC conv erter can be detected by connecting e xternal resistors from the DC/
DC conv erter output to the n oninv erted input terminal (-INE1 terminal (pin 1) and -I NE2 terminal (pin 15)) of the
overvoltage co mparators (OVP Comp. 1 and OVP Comp. 2).
When the DC/DC converter output voltage exceeds the ov ervoltage detection level, the output of the overvoltage
comparator (OVP Comp. 1 and OVP Comp. 2) becomes the “H” level and the overvoltage protection circuit
actuates the ti mer circuit to start charging the e xternal capacitor Cscp connected to the CSCP terminal (pin 11).
If the ov erv oltage remains applied bey ond setting time, the circuit sets the latch to turn off the FET on the main
side of each chann el while setting the PWRGOOD terminal (pin 12) to the “L” le ve l. The protection circuit closes
both channels even when an overvoltage is detected on only either.
Over voltage detection voltage : VOVP
VOVP (V) := 1.38 × (R1 () + R2 () ) / R2 () := 1.12 × VO
To reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal
(pin 6) to the "L" level to lower the VREF terminal (pin 8) voltage to 1.7 V (Min) or less. It can also be reset by
setting both of the CTL1 terminal (pin 9) and CTL2 terminal (pin 10) to the "L" level.
<Timer-latch overvoltage protection circuit>
+
+
11
12
1
15
V
O
R1
R2
(INE2)
INE1
CSCP
Error
Amp
OVP
Comp.
CTL
CTL1
CTL2
1.38 V
10 µA
VREF
UVLO
S
Latch
Latch2
R
PWRGOOD
1.23 V
MB39A106
22
TREATMENT OF UNUSED ILIM TERMINALS
When the overcurrent protection circuit is not used, the ILIM1 terminal (pin 25) and ILIM2 terminal (pin 23) should
be shorted to the SGND terminal.
<Operation Without Using the ILIM Terminals>
PROCESSING WITHOUT USING THE CSCP TERMINAL
When the timer-la tch short-circuit protectio n circuit is not used, the CSCP terminal (pin 11) should be shor ted
to SGND using the shortest possible conne ction.
<Operation Without Us ing the CSCP Terminal>
TREATMENT OF UNUSED PWRGOOD TERMINALS
When the PWRGOOD terminal is not used, the PWRGOOD terminal (pin 12) should be shorted or open to the
SGND terminal.
<Operation Without Using the PWRGOOD Terminals>
SGND
ILIM2
ILIM1
23
25
7
SGND
CSCP
11
7
SGND
PWRGOOD PWRGOOD
"Open"
12
7
12
MB39A106
23
OUTPUT STATES DURING PR OTECTION CIRCUIT OPERATION
The table belo w lists the output states with each protection circuit actuated.
RESETTING THE LATCH OF EACH PROTECTION CIRCUIT
When the overvoltage, overcurrent, or short-circuit protection circuit detects each abnormality, it sets the latch
to fix the output at the "L" level. The PWRGOOD terminal (pin 12) is fixed at the "L" level upon abnormality
detection by each protection circuit.
To reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal
(pin 6) to the "L" level to lower the VREF terminal (pin 8) voltage to 1.7 V (Min) or less. It can also be reset by
setting both of the CTL1 terminal (pin 9) and CTL2 terminal (pin 10) to the "L" level.
Output terminal
Protection ci rc u it CH1 CH2 PWRGOOD
OUT1-1 OUT2-1 OUT1-2 OUT2-2
Overcurrent protection circuit CH1 L L L L L
CH2 L L L L L
Overvoltage protection circuit CH1 L H L H L
CH2 L H L H L
Short-circuit protection CH1 L L L L L
CH2 L L L L L
Under voltage lockout protecti on circuit L L L L L
MB39A106
24
NOTE ON IC’S INTERNAL POWER CONSUMPTION
The oscillation frequency of an IC and the total gate charge of FETs largely affects the internal dissipation of
the IC.
Pay attention to the following point with respect to the internal power consumption of the IC when applications
are used.
IB (mean current) is obtained from the following equation, assuming Qg1 and Qg2 as the total gate charges
applied to the gate capacitors (Ciss1, Ciss2, Crss1, Crss2) of external FETs Q1 and Q2.
Current per ch an ne l
As the current consumption b y the IC, e xcluding IB, is a bout 15 mA, the po wer consumption is obta ined from the
following equation :
Power consumption : Pc
Pc (W) = 0.015 × VCC (V) + 2 × VCC (V) IB (A) VB (V) IB (A)
Refer to “Power Consumption vs. Input Voltage” on the next page as a reference and use the above method of
obtaining the power consumption to design your application of the IC taking account of the “Power Dissipation
vs. Ambient Temperature” characteristic in the TYPICAL CHARAC TERISTICS.
IB (A) = I1 + I2
:= Ibias1 × t1 + Qg1 + Ibias2 × t2 + Qg2(Ibias1 = Ibias2 := 3 mA)
tt t t
Drive
1-1
Drive
2-1
24
22
30
29
A
28
27
26
L1 VO1
VIN VCC
6 V IBVB
CB1
VS1
PGND1
OUT1-1
OUT2-1
CVB
I1
I2
Crss1 Crss2
Ciss1
Ciss2
Q1
Q2
t
t2
t1
t
VOUT1-1
VOUT2-1
I1
I2
Bias current
Ibias1 := 3 mA
Bias current
Ibias2 := 3 mA
MB39A106
25
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Qg1 = Qg2 = 70 nC
Qg1 = Qg2 = 50 nC
Qg1 = Qg2 = 30 nC
Qg1 = Qg2 = 20 nC
Qg1 = Qg2 = 10 nC
Ta = +25 °C
fOSC = 300 kHz
SW1 = OFF
SW2 = OFF
f
OSC
= 300 kHz
f
OSC
= 500 kHz
f
OSC
= 200 kHz
f
OSC
= 100 kHz
f
OSC
= 10 kHz
Ta = +25 °C
Qg1 = Qg2 = 20 nC
SW1 = OFF
SW2 = OFF
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0 5 6 7 8 9 1011121314151617181920
Power consumption PC (W)
Input voltage VIN (V)
P o wer Consumpt ion vs. Input Voltage (Qg Para meter)
Power consumption PC (W)
Input voltage VIN (V)
Power Consump tion vs. Input Voltage (f OSC Parameter)
MB39A106
26
I/O EQUIVALENT CIRCUIT
24
8
7
+
46.6 k
24.6 k
VREF
VCC
SGND
1.23 V
67 k
104 k
SGND
6
CTL 100 k
2 k
SGND
CTLX
VREF
(3.5 V)
400
SGND
CSX
VREF
(3.5 V)
2 k
SGND
CSCP
VREF
(3.5 V)
11
+
5
1.40 V
RT
VREF
(3.5 V)
SGND
VCC
ILIMX
SGND
VSX 12 PWRGOOD
VREF
(3.5 V)
SGND
FBX
CSX
1.23 V
VCC
VREF
(3.5 V)
-INEX
SGND
CBX
VB
SGND
OUT1-X
VSX
100 k
35 k
22
PGNDX
VB
GND
OUT2-X
100 k
35 k
<Reference voltage block>
< Soft-start block>
< Overcurrent protection circuit block (CH1, CH2) >
< Error amplifier block (CH1, CH2) >< Output block main side>
< Control block>< Channel control block>
< Short-circuit protection
circuit block>< Triangular wave oscillator
block (RT) >
< Protection st atus output circuit block>
< Output block synchronous rectification side (CH1, CH2) >
X : Each channel No.
ESD
Protection
Element
ESD
Protection
Element
ESD
Protection
Element
MB39A106
27
APPLICATION EXAMPLE
R13
430
R10
10 kR9
13 k
C10
0.022
µF
C11
0.1 µF
R12
6.2 k
A
R16
120
R15
10 kR14
13 k
C12
0.022
µF
C13
0.1 µF
C14
0.01 µF
R17
3.3 k
B
AC/DC
Converter
(12 V)
V
IN
C16
0.1 µF
C9
4.7 µF
C3 0.1 µF
+
+C5
0.1 µF
82
µF
C25 C18
150
µF
C4
L1 V
O
1
(2 V/10 A)
22
µH
Q1
R1
1.3 k
0.1
µF
C6 0.1 µF
+
+C8
0.1 µF
82
µF
C26 C17
150
µF
C7
L2 V
O
2
(5 V/5 A)
22
µH
Q2
R5
1.3 k
0.1
µF
C15
0.1 µF
R8
47 k
R4
100 k
B
A
Open : CH1 ON
L : CH1 OFF
VTH = 1.4 V
CTL1
FB1
INE1
CS1
CB1
OUT1-1
VS1
OUT2-1
PGND1
ILIM1
VB
Open : CH2 ON
L : CH2 OFF
VTH = 1.4 V
CTL2
FB2
INE2
CS2
CB2
OUT1-2
VS2
OUT2-2
PGND2
ILIM2
CSCP
SGNDVREFRT
PWRGOOD
Protection
control
signal
NC
NC
CTL
VCC
+
+
VREF
Buff
100
k
6 k
Error
Amp1
1.23 V
1.38 V
118 µA
+
+PWM
Comp.1
+
+
9
1
3
Drv
1-1
Drv
2-1
230
29
28
27
26
25
Dead Time
Modulation 1
Current
Protection
Logic
22
VB Reg.
+
+
VREF
Buff
100
k
6 k
1.23 V
1.38 V
118 µA
3 µA
3 µA
+
+
+
+
10
15
13
Drv
1-2
Drv
2-2
14 16
17
18
19
20
23
Dead Time
Modulation 2
Current
Protection
Logic
CTL2 = H
Max Duty 81%
Dtr ± 6%
+
+
SCP Comp.
3.1 V
11
12
4
21
8
5
bias 1.23 V VCC
VREF VR1 Power
ON/OFF
CTL
CTL
CTL1
CTL2
CTL
CTL1
CTL2
10 µA
VREF
UVLO OSC
45 pF 3.5 V
S
Latch
Latch2
R
SQ
R
Latch1
3.0 V
CT1
1.8 V
3.0 V
CT2
1.8 V
OVP
Comp.1
Error
Amp2
OVP
Comp.2
PWM
Comp.2
7
6
Max Duty 81%
Dtr ± 6%
24 6 V
CH1
CH2
CTL1 = H
H: UVLO
release
L priority
L priority
L priority
L priority
H priority
H: at OVP
H: at OVP
H: at OVP
H: at OCP
H: at SCP
H: at OCP
H: at OCP
L: at protection
operation
to Error amp reference
H : ON (Power/ON)
L : OFF (Standby mode)
VTH = 1.4 V
MB39A106
28
PARTS LIST
Note : IR : International Rectifier Corp.
TDK : TDK Corp oration
SANYO : SANYO Electric Co., Ltd.
ssm : SUSUMU Electronics Corp.
Dual FETKY is a trademark of International Rectifier Corp.
OS-CON is a trademark of SANYO Electric Co., Ltd.
COMPONENT ITEM SPECIFICATION VENDOR PARTS NO.
Q1, Q2 Dual FETKYTM
Main sides:
VDS = 30 V, Qg = 9.9 nC (Max)
Synchronou s sides:
VDS = 30 V, Qg = 20.7 nC (Max)
SBD: VF = 0.52 V (Max)
at IF = 1 A
IR IRF7901D1
L1, L2 Coil 22 µH 3.5 A, 31.6 mTDK SLF12565T-
220M3R5
C3, C6
C4
C5, C8
C7
C9
C10
C11, C13
C12
C14
C15, C16
C17, C18
C25, C26
Ceramics Condenser
OS-CONTM
Ceramics Condenser
OS-CONTM
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
OS-CONTM
0.1 µF
150 µF
0.1 µF
150 µF
4.7 µF
0.022 µF
0.1 µF
0.022 µF
0.01 µF
0.1 µF
0.1 µF
82 µF
50 V
6.3 V
50 V
6.3 V
10 V
50 V
50 V
50 V
50 V
50 V
50 V
16 V
TDK
SANYO
TDK
SANYO
TDK
TDK
TDK
TDK
TDK
TDK
TDK
SANYO
C1608JB1H104K
6SVP150M
C1608JB1H104K
6SVP150M
C3216JB1A475M
C1608JB1H223K
C1608JB1H104K
C1608JB1H223K
C1608JB1H103K
C1608JB1H104K
C1608JB1H104K
16SVP82M
R1, R5
R4
R8
R9
R10
R12
R13
R14
R15
R16
R17
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
1.3
100 k
47 k
13 k
10 k
6.2 k
430
13 k
10 k
120
3.3 k
0.5 %
0.5 %
0.5 %
0.5 %
0.5 %
0.5 %
0.5 %
0.5 %
0.5 %
0.5 %
0.5 %
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
RR0816P132D
RR0816P104D
RR0816P473D
RR0816P133D
RR0816P103D
RR0816P622D
RR0816P434D
RR0816P133D
RR0816P103D
RR0816P124D
RR0816P332D
MB39A106
29
SELECTION OF COMPONENTS
• N-ch MOS FET
The N-ch MOS FET for switching use should be rated for at least 20% more than the maximum input voltage.
To minimize continuity loss, use a FET with low RDS(ON) between the dr ain and source. For h igh input v oltage and
high frequency operation, on/off-cycle switching loss will be higher so that power dissipation must be considered.
In this application, the IR IRF7901D1 is used. Continuity loss, on/off switching loss, and total loss are determined
by the f ollo wing formulas . The selection m ust ensure that peak dr ain current do es not e xceed r ated v alues , and
also must be in accordance with overcurrent detection levels.
Continuity loss : PC
On-cycle switching loss : PS (ON)
Off-cycle switching loss : PS (OFF)
Total loss : PT
PT = PC + PS (ON) + PS (OFF)
Example: Using the IR IRF7901D1
CH1 Main side
Input voltage VIN (Max) = 15 V, output voltage VO = 3.3 V, drain current ID = 3 A, Oscillation frequency
fOSC = 300 kHz, L = 22 µH, drain-source on resistance RDS (ON) := 33 m, tr = 13.8 ns, tf = 8 ns.
Drain current (Max) : ID (Max)
Drain current (Min) : ID (Min)
PC = ID2 × RDS (ON) × Duty
PS (ON) = VD (Max) × ID × tr × fOSC
6
PS (OFF) = VD (Max) × ID (Max) × tf × fOSC
6
ID (Max) =IO + VIN (Max) VOton
2L
=3 + 153.3 × 1 × 0.22
2 × 22 × 106300 × 103
:=3.20 (A)
ID (Min) =IOVIN (Max) VOton
2L
=3153.3 × 1 × 0.22
2 × 22 × 106300 × 103
:=2.80 (A)
MB39A106
30
CH1 (Synchronous rectifica tion side)
Input voltage VIN (Max) = 15 V, output voltage VO = 3.3 V, drain current ID = 3 A, oscillation frequency
fOSC = 300 kHz, L = 22 µH, drain-source on resistance RDS (ON) := 28 m, tr = 16.4 ns, tf = 5. 2 ns.
Drain current (Max) : ID (Max)
Drain current (Min) : ID (Min)
PC1 = ID2 × RDS (ON) × Duty (ON)
= 32 × 0.033 × 0.22
:= 0.065 W
PS1 (ON) = VD (Max) × ID × tr × fOSC
6
= 15 × 3 × 13.8 × 109 × 300 × 103
6
:= 0.031 W
PS1 (OFF) = VD (Max) × ID (Max) × tf × fOSC
6
= 15 × 3.2 × 8 × 109 × 300 × 103
6
:= 0.019 W
PT1 = PC1 + PS1 (ON) + PS1 (OFF)
:= 0.065 + 0.031 + 0.019
:= 0.115 W
ID (Max) =IO + VOtoff
2L
=3 + 3.3 × 1 × (10.22)
2 × 22 × 106300 × 10 3
:=3.20 (A)
ID (Min) =IOVOtoff
2L
=33.3 × 1 × (10.22)
2 × 22 × 106300 × 103
:= 2.80 (A)
MB39A106
31
The above power dissipation figures for the I RF7901D1 are satisfied with ample margin at 2W (Ta = +100 °C) .
PC2 = ID2 × RDS (ON) × Duty (OFF)
= 3
2 × 0.028 × (10.22)
:= 0.197 W
PS2 (ON) = VD (Max) × ID × tr × fOSC
6
= 15 × 3 × 16.4 × 109 × 300 × 103
6
:= 0.037 W
PS2 (OFF) = VD (Max) × ID (Max) × tf × fOSC
6
= 15 × 3.2 × 5.2 × 109 × 300 × 103
6
:= 0.012 W
PT2 = PC2 + PS2 (ON) + PS2 (OFF)
:= 0.197 + 0.037 + 0.012
:= 0.246 W
PT = PT1 + PT2
:= 0.115 + 0.246
:= 0.361 W
MB39A106
32
CH2 (Main side)
Input voltage VIN (Max) = 15 V, output voltage VO = 5 V, drain current ID = 3 A, Oscillation frequency fOSC = 300
kHz, L = 22 µH, drain-source on resistance RDS (ON) := 33 m, tr = 13.8 ns, tf = 8 ns.
Drain current (Max) : ID (Max)
Drain current (Min) : ID (Min)
ID (Max) =IO + VIN (Max) VOton
2L
=3 + 155 × 1 × 0.33
2 × 22 × 106300 × 103
:=3.25 (A)
ID (Min) = IO+VIN (Max) VOton
2L
= 3155 × 1 × 0.33
2 × 22 × 106300 × 103
:= 2.75 (A)
PC1 = ID2 × RDS (ON) × Duty (ON)
= 3
2 × 0.033 × 0.33
:= 0.098 W
PS1 (ON) = VD (Max) × ID × tr × fOSC
6
= 15 × 3 × 13.8 × 109 × 300 × 103
6
:= 0.031 W
PS1 (OFF) = VD (Max) × ID (Max) × tf × fOSC
6
= 15 × 3.25 × 8 × 109 × 300 × 103
6
:= 0.020 W
PT1 = PC1 + PS1 (ON) + PS1 (OFF)
:= 0. 09 8 + 0.031 + 0.020
:= 0.149 W
MB39A106
33
CH2 (Synchronous rectifica tion side)
Input voltage VIN (Max) = 15 V, output voltage VO = 5 V, drain current ID = 3 A, Oscillation frequency fOSC = 300
kHz, L = 22 µH, drain-source on resistance RDS (ON) := 28 m, tr = 16.4 ns, tf = 5.2 ns.
Drain current (Max) : ID (Max)
The above power dissipation figures for the I RF7901D1 are satisfied with ample margin at 2W (Ta = +100 °C) .
ID (Max) =IO + VOtoff
2L
=3 + 5 × 1 × (10.33)
2 × 22 × 106300 × 103
:=3.25 (A)
ID (Min) =IOVOtoff
2L
=35 × 1 × (10.33)
2 × 22 × 106300 × 103
:= 2.75 (A)
PC2 = ID2 × RDS (ON) × Duty (OFF)
= 3
2 × 0.028 × (10.33)
:= 0.169 W
PS2 (ON) = VD (Max) × ID × tr × fOSC
6
= 15 × 3 × 16.4 × 109 × 300 × 103
6
:= 0.037 W
PS2 (OFF) = VD (Max) × ID (Max) × tf × fOSC
6
= 15 × 3.25 × 5.2 × 109 × 300 × 103
6
:= 0.013 W
PT2 = PC2 + PS2 (ON) + PS2 (OFF)
:= 0.169 + 0.037 + 0.013
:= 0.219 W
PT = PT1 + PT2 (OFF)
:= 0.149 + 0.219
:= 0.368 W
MB39A106
34
• Inductors
In selecting inductors, it is of course essential not to apply more current than the rated capacity of the inductor ,
but also to note that the lower limit fo r ripple current is a critical point that if reached will cause discontinuous
operat ion and a considerable drop in efficiency. This can be prevented by choosing a higher inductance value,
which will enab le contin uous oper ation under light loads . Note that if the inductance value is too high, ho w e v er,
direct current resistance (DCR) is increased and this will also reduce efficiency. The inductance must be set at
the point where efficiency is greatest.
Note also that th e DC superimposition chara cteristics become wor se as the load cur rent value approaches the
rated current value of the inductor , so that the inductance value is r educed and ripple current increases, causing
loss of efficiency. The selection of rated current value and inductance value will var y depending on where the
point of peak efficiency lies with respect to loa d current.
Inductance values are determined by the following formulas.
The L v alue f or all load current condition is set so t hat the peak to peak v alue of the ripple current is 1/2 the load
current or less.
Inductance value : L
Example:
CH1
CH2
Inductance values derived from the above formulas are values that provide sufficient margin for continuous
operation at maximum load current, but at which continuous operation is not possible at light loads. It is therefore
necessary to determine the load level at which continuous operation becomes possible. In this application, the
TDK SLF12565T-220M3R5 is used. At 22 µH, the load current value under continuous operating conditions is
determined by the following formula.
Load current value under continuous operating conditions : I O
Example : Using the SLF12565T-220M3R5
22 µH (allowable tolerance ±20%) , rated current = 3.5 A
L 2 (VINVO) ton
IO
L 2 (VIN (Max) VO) ton
IO
2 × (153.3) × 1 × 0.22
3 300 × 103
5.7 µH
L 2 (VIN (Max) VO) ton
IO
2 × (155) × 1 × 0.33
3300 × 103
7.3 µH
IO VOtoff
2L
MB39A106
35
CH1
CH2
To determine whether the current through the inductor is within rated values, it is necessary to deter mine the
peak value of the ripple current as well as the peak-to-peak values of the ripple current that affect the output
ripple volta ge. The peak value and peak-to-peak v a lue of the ripple curr en t can be d et ermined by t he following
formulas.
Peak v alue : IL
Peak-to-peak value : IL
Example: Using the S LF 1 25 65 T-220M3R5
22 µH (allowable tolerance ±20%) , rated current = 3.5 A
Peak v alue
CH1
CH2
IO VOtoff
2L
3.3 × 1 × (10.22)
2 × 22 × 106300 × 103
195 mA
IO VOtoff
2L
5 × 1 × (10.33)
2 × 22 × 106300 × 103
254 mA
IL IO+VIN VOton
2L
IL = VIN VOton
L
IL IO+VIN (Max) VOton
2L
3 +153.3 × 1 × 0.22
2 × 22 × 106300 × 103
3.20 A
IL IO+VIN (Max) VOton
2L
3 +155 × 1 × 0.33
2 × 22 × 106300 × 103
3.25 A
MB39A106
36
Peak-to-peak value:
CH1
CH2
• Smoothing Capacitor
The smoothing capacitor is an indispensable element for reducing ripple voltage in output. In selecting a smooth-
ing capacitor it is essential to consider equivalent series resistanc e (ESR) an d allowable ripple curre nt. Hig he r
ESR means higher ripple voltage, so that to reduce rip p le voltage it is necessary to select a capacitor with low
ESR. How ever, the use of a ca pacitor with lo w ESR can have substantial effects on loop phase characteristics ,
and therefore requires attention to system stability. Care should also be taken to use a capacity with sufficient
margin for allowable ripple current. This application uses the 6SVP150M (OS-CONTM : SANYO) . The ESR,
capacitance value, and ripple current can be calculated from the following formulas.
Equivalent Series Resistance : ESR
Capacitance value : CL
Ripple current : ICLrms
Example: Using the 6SVP150M
Rated voltage = 6.3 V, ESR = 35 m, maximum allowable ripple current = 2.35 Arms
Equivalent series resistance
CH1
IL = VIN (Min) VOton
L
= 153.3 × 1 × 0.22
22 × 106300 × 103
:= 0.39 A
IL = VIN (Max) VOton
L
= 155 × 1 × 0.33
22 × 106300 × 103
:= 0.5 A
ESR VO 1
IL2πfCL
CL IL
2πf (VO IL × ESR)
ICLrms (VIN VO) ton
23L
ESR VO 1
IL2πfCL
0.033 1
0.39 2π × 300 × 103 × 150 × 106
81.1 m
MB39A106
37
CH2
Capacitance value
CH1
CH2
Ripple curren t
CH1
CH2
ESR VO 1
IL2πfCL
0.05 1
0.5 2π × 300 × 103 × 150 × 106
96.5 m
CL IL
2πf (VO IL × ES R)
0.39
2π × 300 × 103 × (0.033 0.39 × 0.035)
10.7
µF
CL IL
2πf (VO IL × ESR)
0.5
2π × 300 × 103 × (0.05 0.5 × 0.035)
8.2
µF
ICLrms (VIN (Max) VO) ton
23L
(15 3.3) × 0.22
23L × 22 × 106 × 3 00 × 103
112.6 mArms
ICLrms (VIN (Max) VO) ton
23L
(15 5) × 0.33
23L × 22 × 106 × 300 × 103
114.3 mArms
MB39A106
38
REFERENCE DATA
(Continued)
VIN = 8.5 V
VIN = 10 V
VIN = 12 V
100
90
80
70
60
50
40
30
0.01 0.10 1.00 10.00
Conversion efficiency η (%)
Load current IL (A)
Conversion Efficiency vs. Load Current (CH1)
Conversion efficiency η (%)
Load current IL (A)
Conversion Efficiency vs. Load Current (CH2)
VIN = 8.5 V
VIN = 10 V
VIN = 12 V
100
90
80
70
60
50
40
30
0.01 0.10 1.00 10.00
Ta = + 25 °C
3.3 V output
CTL = 5 V
CTL1 = Open
CTL2 = “L” level
Ta = + 25 °C
5 V output
CTL = 5 V
CTL1 = “L” level
CTL2 = Open
MB39A106
39
(Continued)
012345678910
VS1 (V)
12
10
8
6
4
2
0
t (µs)
0 100 200 300 400 500
VS1 (V)
(ns) 0 100 300 400 500
VS1 (V)
(ns)
tD1 90 ns tD2 150 ns
2
1
0
2
1
0
200
Switching Waveform (CH1)
Ta = + 25 °C
3.3 V output
VIN = 12 V
CTL = 5 V
CTL1 = Open
CTL2 =Llevel
VO1 = 3 A
Expansion Expansion
MB39A106
40
(Continued)
012345678910
V
S2
(V)
12
10
8
6
4
2
0
t (µs)
0 100 200 300 400 500
V
S2
(V)
(ns) 0 100 200 300 400 500
V
S2
(V)
(ns)
t
D1
90 ns
t
D1
160 ns
2
1
0
2
1
0
Switching Waveform (CH2)
Ta = + 25 °C
5 V output
VIN = 12 V
CTL = 5 V
CTL1 = “L”level
CTL2 = Open
VO2 = 3 A
Expansion Expansion
MB39A106
41
(Continued)
ts 36 ms
V
O
1
V
CTL
V
O
1 (V)
V
CTL
(V)
0 102030405060708090100
(ms)
0
5
0
4
2
V
O
2
V
CTL
V
O
2 (V)
V
CTL
(V)
0 102030405060708090100
(ms)
ts 36 ms
6
4
2
0
5
0
Ta = + 25 °C
VIN = 12 V
CTL1 = Open
CTL2 = “L”level
VO1 = 1.2
Soft-start Operating Waveform (CH1)
Soft-start Op er at ing Wave fo rm (CH2)
Ta = + 25 °C
VIN = 12 V
CTL1 = “L”level
CTL2 = Open
VO2 = 1.67
MB39A106
42
NOTES ON USE
Tak e account of common impedance when designing the earth line on a printed wiring board.
Take measures against static electricity.
- For semiconductors, use antistatic or conductive containers.
- When storing or carrying a printed circuit board af ter chip mounting, put it in a conductive bag or container.
- The work table, tools, and measuring instruments must be grounded.
- The worker must put on a grounding device containing 250 k to 1 M resistors in series.
Do not apply a negative voltage.
- Applying a negative voltage o f 0.3 V or less to an LSI may generate a parasiti c transistor, resulting in
malfunction.
PRECAUTIONS ON HANDLING THIS PRODUCT
This product has obtained US patents for patent numbers of 6, 147,477.
ORDERING IN FORMATION
EV BOARD ORDERING INFORMATION
RoHS COMPLIANCE INFORMATION OF LEAD (Pb) FREE VERSION
The LSI products of Fujitsu Microelectronics with “E1” are compliant with RoHS Directive, and has observed the
standard of lead, cadmium, mercury, Hexavalent chromium, polybrominated biphenyls (PBB) , and polybromi-
nated diphenyl ethers (PBDE) .
The product that conforms to this standard is added “E1” at the end of the part number.
MARKING FORMAT (LEAD FREE VERSION)
Part number Package Remarks
MB39A106PFT-❏❏❏E1 30-pin plastic TSSOP
(FPT-30P-M04) Lead Free version
EV board part No. EV board version No. Remarks
MB39A106EVB Board Rev. 2.0 TSSOP-30P
INDEX
MXXX
E1
B39A106
XXXX
Lead Free version
MB39A106
43
LABELING SAMPLE (LEAD FREE VERSION)
2006/03/01
ASSEMBLED IN JAPAN
G
QC PASS
(3N) 1MB123456P-789-GE1
1000
(3N)2 1561190005 107210
1,000
PCS
0605 - Z01A
1000
1/1
1561190005
MB123456P - 789 - GE1
MB123456P - 789 - GE1
MB123456P - 789 - GE1
Pb
Lead Free version
Lead-free mark
JEITA logo JEDEC logo
MB39A106
44
MB39A106PFT-❏❏❏E1
RECOMMENDED CONDITIONS OF MOISTURE SENSITIVITY LEVEL
[Temperature Profile for FJ Standard IR Reflow]
(1) IR (infrared reflow)
(2) Manual soldering (partial heating method)
Conditions : Temperature 400 °C Max
Times : 5 s max/pin
Item Condition
Mounting Method IR (infrared reflow) , Manual soldering (partial heating method)
Mounting times 2 times
Storage period
Before opening Please use it within two years after
Manufacture.
From opening to the 2nd
reflow Less than 8 days
When the storage period after
opening was exceeded Please processes within 8 days
after baking (125 °C, 24H)
Storage conditions 5 °C to 30 °C, 70%RH or less (the lowest possible humidity)
260 °C
(e)
(d')
(d)
255 °C
170 °C
190 °C
RT (b)
(a)
(c)
~
Note : Temperature : the top of the package body
(a) Tempera ture Increase gradien t : Average 1 °C/s to 4 °C/s
(b) Preliminary heating : Temperature 170 °C to 190 °C, 60 s to 180 s
(c) Temperat ure Incr ease grad ient : Average 1 °C/s to 4 °C/s
(d) Actual heating : Temperature 260 °C Max; 255 °C or more, 10 s or less
(d’) : Temperature 230 °C or more, 40 s or less
or
Temperature 225 °C or more, 60 s or less
or
Temperature 220 °C or more, 80 s or less
(e) Cooling : Natural cooling or forced cooling
H rank : 260 °C Max
MB39A106
45
PACKAGE DIMENSION
30-pin plastic TSSOP Lead pitch 0.50 mm
Package width
×
package length
4.40 × 7.80 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 1.10 mm MAX
30-pin plastic TSSOP
(FPT-30P-M04)
(FPT-30P-M04)
C
2001 FUJITSU LIMITED F30007SC-1-1
7.80±0.10(.307±.004)
0.50(.020) 0.20±0.03
(.008±.001)
.173–.004
+.008
–0.10
+0.20
4.40 6.40±0.10
(.252±.004)
0.10(.004)
7.00(.276) 0.3865(.0152)
0.3865(.0152)
0.90±0.05
(.035±.002)
"A"
0~8°
0.60±0.10
(.024±.004)
0.25(.010)
0.10±0.05
(.004±.002)
1.10(.043)
MAX
Details of "A" part
0.127±0.03
(.005±.001)
INDEX
0.10(.004)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB39A106
46
MEMO
MB39A106
47
MEMO
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0722, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3387
http://jp.fujitsu.com/fml/en/
For further information please contact:
North and South America
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen,
Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://www.fmk.fujitsu.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD.
151 Lorong Chuan, #05-08 New Tech Park,
Singapore 556741
Tel: +65-6281-0770 Fax: +65-6281-0220
http://www.fujitsu.com/sg/services/micro/semiconductor/
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm.3102, Bund Center, No.222 Yan An Road(E),
Shanghai 200002, China
Tel: +86-21-6335-1560 Fax: +86-21-6335-1605
http://cn.fujitsu.com/fmc/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road
Tsimshatsui, Kowloon
Hong Kong
Tel: +852-2377-0226 Fax: +852-2376-3269
http://cn.fujitsu.com/fmc/tw
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The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporat-
ing the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS
or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or
other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual
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limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
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The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
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