ICE5QRxxxxAx Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO12 Package Product Highlights Integrated 700 V/800 V avalanche rugged CoolMOSTM Novel Quasi-Resonant operation and proprietary implementation for low EMI Enhanced Active Burst Mode with selectable entry and exit standby power Active Burst Mode to reach the lowest standby power <100 mW PG-DIP-7 PG-DSO-12 Fast startup achieved with cascode configuration Digital frequency reduction for better overall system efficiency Robust line protection with input OVP and brownout Comprehensive protection Pb-free lead plating, halogen free mold compound, RoHS compliant Features Applications Integrated 700 V/800 V avalanche rugged CoolMOSTM Minimum switching frequency difference between low & high Auxiliary power supply for Home Appliances/white Goods, TV, line for higher efficiency & better EMI Enhanced Active Burst Mode with selectable entry and exit standby power Active Burst Mode to reach the lowest standby power <100 mW Fast startup achieved with cascode configuration Digital frequency reduction up to 10 zero crossings Built-in digital soft start Cycle-by-cycle peak current limitation Maximum on/off time limitation to avoid audible noise during start up and power down Robust line protection with input OVP and brownout Auto restart mode protection for VCC Over Voltage, VCC Under Voltage, Over load/Open Loop, Output Over Voltage, Over Temperature and CS (Current Sense) short to GND Limited charging current for VCC short to GND Pb-free lead plating, halogen free mold compound, RoHS PC & Server Blu-ray player, Set-top box & LCD/LED Monitor Description The Quasi-Resonant CoolSETTM- (ICE5QRxxxxAx) is the 5th generation of Quasi-Resonant integrated power IC optimized for off-line switch power supply in cascode configuration. It is housed in single package with 2 separate chips; one is controller chip and other is HV MOSFET chips. The IC can achieve lower EMI and higher efficiency with improved digital frequency reduction through the proprietary novel Quasi-Resonant operation. The enhanced Active Burst Mode enables flexibility in standby power range selection. The product has a wide operation range (10 ~ 25.5 V) of IC power supply and lower power consumption. The numerous protection functions including the robust line protection (both input OVP and brownout) to support the protections of the power supply system in failure situations. All of these make the CoolSETTM (ICE5QRxxxxAx) series an outstanding integrated power device in Quasi-Resonant flyback converter in the market. compliant Figure 1 Typical application Data Sheet www.infineon.com Please read the Important Notice and Warnings at the end of this document Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package Output Power of 5th generation Quasi-Resonant CoolSETTM Table 1 Output Power of 5th generation Quasi-Resonant CoolSETTM Type Package Marking VDS RDSon1 220VAC 20%2 85-300 VAC2 ICE5QR4770AZ PG-DIP-7 5QR4770AZ 700 V 4.73 27 W 15 W ICE5QR4780AZ PG-DIP-7 5QR4780AZ 800 V 4.13 28 W 15 W ICE5QR2270AZ PG-DIP-7 5QR2270AZ 700 V 2.13 41 W 22 W ICE5QR2280AZ PG-DIP-7 5QR2280AZ 800 V 2.13 41 W 22 W ICE5QR1070AZ PG-DIP-7 5QR1070AZ 700 V 1.15 58 W 32 W ICE5QR0680AZ PG-DIP-7 5QR0680AZ 800 V 0.71 74 W 41 W ICE5QR4770AG PG-DSO-12 5QR4770AG 700 V 4.73 27 W 15 W ICE5QR1680AG PG-DSO-12 5QR1680AG 800 V 1.53 50 W 27 W ICE5QR0680AG PG-DSO-12 5QR0680AG 800 V 0.71 77 W 42 W Typ. at TJ =25C (inclusive of low side MOSFET) Calculated maximum output power rating in an open frame design at Ta=50C, TJ=125C (integrated high voltage MOSFET) and using minimum drain pin copper area in a 2 oz copper single sided PCB. The output power figure is for selection purpose only. The actual power can vary depending on particular designs. Please contact to a technical expert from Infineon for more information. Data Sheet 2 Revision 2.0 2017-07-04 1 2 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package Table of Contents Product Highlights ......................................................................................................... 1 Features ....................................................................................................................... 1 Applications .................................................................................................................. 1 Description ................................................................................................................... 1 Output Power of 5th generation Quasi-Resonant CoolSETTM .................................................................. 2 1 Pin Configuration and Functionality ................................................................................ 5 2 Representative Block Diagram ........................................................................................ 6 3 3.1 3.2 3.3 3.3.1 3.3.1.1 3.3.1.2 3.3.1.3 3.3.2 3.3.2.1 3.3.3 3.3.4 3.4 3.5 3.5.1 3.5.2 3.5.3 3.6 Functional Description ................................................................................................... 7 VCC Pre-Charging and Typical VCC Voltage during Start-up ..................................................................... 7 Soft-start .................................................................................................................................................. 8 Normal Operation ................................................................................................................................... 8 Digital Frequency Reduction ............................................................................................................. 8 Minimum ZC Count Determination .............................................................................................. 8 Up/down counter .......................................................................................................................... 9 Zero crossing (ZC counter) ......................................................................................................... 10 Ringing suppression time ................................................................................................................ 10 Switch on determination ............................................................................................................ 10 Switch off determination ................................................................................................................. 11 Modulated gate drive ....................................................................................................................... 11 Current limitation .................................................................................................................................. 11 Active Burst Mode with selectable power level .................................................................................... 12 Entering Active Burst Mode Operation ............................................................................................ 13 During Active Burst Mode Operation ............................................................................................... 13 Leaving Active Burst Mode Operation ............................................................................................. 13 Protection Functions ............................................................................................................................. 15 4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16 4.17 Electrical Characteristics ............................................................................................... 18 Absolute Maximum Ratings .................................................................................................................. 18 Operating Range.................................................................................................................................... 20 Operating Conditions ............................................................................................................................ 20 Internal Voltage Reference.................................................................................................................... 21 PWM Section .......................................................................................................................................... 21 Current Sense ........................................................................................................................................ 21 Soft Start ................................................................................................................................................ 22 Digital Zero Crossing ............................................................................................................................. 22 Active Burst Mode.................................................................................................................................. 23 Line Over Voltage Protection ................................................................................................................ 23 Brownout Protection............................................................................................................................. 23 VCC Over Voltage Protection .................................................................................................................. 24 Over Load Protection ............................................................................................................................ 24 Output Over Voltage Protection ........................................................................................................... 24 Thermal Protection ............................................................................................................................... 24 CS Short to GND Protection .................................................................................................................. 25 CoolMOSTM Section ................................................................................................................................ 26 5 CoolMOSTM Performance Characteristics .......................................................................... 28 6 Output Power Curve...................................................................................................... 42 Data Sheet 3 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package 7 Outline Dimension ........................................................................................................ 51 8 Marking ....................................................................................................................... 53 Revision History ........................................................................................................... 54 Data Sheet 4 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package 1 Pin Configuration and Functionality NC NC DRAIN DRAIN 11 10 9 8 7 1 2 3 4 5 6 CS ZCD DRAIN DRAIN PG-DSO-12 VCC 12 VIN 2 GND 1 5 FB 7 DRAIN VCC 8 3 4 CS ZCD FB VIN PG-DIP-7 GND The pin configuration is shown in Figure 2 and the functions are described in Table 2. Figure 2 Pin Configuration Table 2 Pin Definitions and Functions Pin Symbol DIP-7 DSO-12 1 1 FB 2 2 VIN 3 3 CS 4 4 ZCD 5 5, 6, 7, 8 DRAIN 7 11 VCC 8 12 GND - 9, 10 NC Data Sheet Function Feedback & Burst entry/exit control FB pin combines the functions of feedback control, selectable burst entry/exit control and overload/open loop protection. Input Line OVP & Brownout VIN pin is connected to the bus via resistor divider (see Figure 1) to sense the line voltage. This pin combines the functions of input Line OVP, Brownout and minimum ZC count setting between low and high line. Current Sense The CS pin is connected to the shunt resistor for the primary current sensing externally and to the PWM signal generator block for switch-off determination (together with the feedback voltage) internally. Moreover, CS pin short to ground protection is sensed by this pin. Zero Crossing Detection ZCD pin combines the functions of start up, zero crossing detection and output over voltage protection. During the start up, it is used to provide a voltage level to the gate of power switch CoolMOSTM to charge VCC capacitor. Drain The DRAIN pin is connected to the drain of the integrated CoolMOSTM. VCC(Positive Voltage Supply) The VCC pin is the positive voltage supply to the IC. The operating range is between VVCC_OFF and VVCC_OVP. Ground The GND pin is the common ground of the CoolSETTM. Not connected. 5 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package 2 Representative Block Diagram ZCD VCC LOVP VVIN_LOVP 250 s Blanking time C7a VIN Brown In / Out VVIN_BO S Q Input OVP Mode 250 s Blanking time C16a S Q VVIN_BI C16b Undervoltage Lockout ZC counter Voltage Reference 16V & 10V Internal Bias Protection VVCC_OVP C12 50us 1 Soft-start 1 Counter PZCD_OVP_B Ringing Suppression VZCD_RS & G9 TOffMax VREF VFB_OLP/ VFB_LB D3 Protect C1 C12 tFB_OLP_B 1 & G5 G4 & G6 G3 Gate Drive S G8 C5 VFB_R Burst Mode detect 1 Q R TOnMax Gate Drive fSB OSC C3 en Gate Driver VFB_HLC VCS_N VCS_BL1 C4 FB 25k VFB_LHC C13 Regulation Burst Mode Level Select C15 VFB_EBL1 VFB_EBL2 C9 tFB_BEB VPWM V1 Active Burst Mode 2pF C20 VFB_BOn C10 PWM Comparator GPWM VCS_BL2 VCS_FB Peak Current Limit Leading Edge Blanking tCS_LEB 10k 1pF CS D2 PWM OP Current Mode VFB_BOff C11 Active Burst Block Figure 3 R G2 Autorestart C6 RFB Autorestart Protect S Q PWM Control Counter tCOUNT Q R G7 tVIN_REF CoolMOSTM S Up/down counter VZCD_OVP DRAIN RZCD G1 VVIN_REF Autorestart Protect Tj < Tjcon_OTP-TjHYS_OTP Comparator C8 OTP Mode Q Power Management Zero Crossing D1 S R Autorestart Protect VZCD_CT C2 50 s Blanking time Tj > Tjcon_OTP* Brown Out Mode R R Autorestart Protect clk Thermal Protection Delay tCS_STG_SAM GND C17 VCS_STG Current Limiting/ Current Sense short to Gnd Protection Representative Block Diagram Note: Junction temperature of the controller chip is sensed for over temperature protection. The CoolMOSTM is a separated chip from the controller chip in the same package. Please refer to the design guide and/or consult a technical expert from Infineon for the proper thermal design. Data Sheet 6 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package 3 Functional Description 3.1 VCC Pre-Charging and Typical VCC Voltage during Start-up As shown in Figure 1, once the line input voltage is applied, a rectified voltage appears across the capacitor CBUS. The pull up resistor RSTARTUP provides a current to charge the Ciss (input capacitance) of CoolMOSTM and gradually generate one voltage level. If the voltage over Ciss is high enough, CoolMOSTM on and VCC capacitor will be charged through primary inductance of transformer LP, CoolMOSTM and internal diode D3 with two steps constant current source IVCC_ Charge11 and IVCC_ Charge31. A very small constant current source (IVCC_Charge1) is charged to the VCC capacitor till VCC reach VCC_SCP to protect the controller from VCC pin short to ground during the start up. After this, the second step constant current source (IVCC_Charge3) is provided to charge the VCC capacitor further, until the VCC voltage exceeds the turned-on threshold VVCC_ON. As shown in the time phase I in Figure 4, the VCC voltage increase almost linearly with two steps. VVCC I (VVCC_ON )16V (VVCC_OFF) 10V tA II III tB (VVCC_SCP) 1.1V IVCC t (IVCC_Normal ) 0.9mA (IVCC_Charge1) -0.2mA t 0 t1 t2 IVCC_Charge2/3) -3/-3.2mA -IVCC Figure 4 VCC voltage and current at start up The time taking for the VCC pre-charging can then be approximately calculated as: _ (_ - _ ) 1 = A + B = + _1 _3 (1) When the VCC voltage exceeds the VCC turned on threshold VVCC_ON at time t1, the IC begins to operate with soft start. Due to power consumption of the IC and the fact that there is still no energy from the auxiliary winding to charge the VCC capacitor before the output voltage is built up, the VCC voltage drops (Phase II). Once the output voltage is high enough, the VCC capacitor receives the energy from the auxiliary winding from the time t2 onward and delivering the IVCC_ Normal2 to the CoolSETTM. The VCC then will reach a constant value depending on output load. IVCC_ Charge1/2/3 is charging current from the controller to VCC capacitor during start up IVCC_ Normal is supply current from VCC capacitor or auxiliary winding to the CoolSETTM during normal operation Data Sheet 7 1 2 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package 3.2 Soft-start As shown in Figure 5, at the time ton, the IC begins to operate with a soft-start. By this soft-start the switching stresses for the MOSFET, diode and transformer are minimized. The soft-start implemented in ICE5QRxxxxAx is a digital time-based function. The preset soft-start time is tSS (12 ms) with 4 steps. If not limited by other functions, the peak voltage on CS pin will increase step by step from 0.3 V to 1 V finally. During the first 3 ms of soft start, the ringing suppression time is set to 25 s to avoid irregular switching due to switch off oscillation noise. Vcs (V) VCS_Peak 0.75 0.60 0.45 0.30 ton 3 6 9 Figure 5 Maximum current sense voltage during soft start 3.3 Normal Operation 12 Time(ms) During normal operation, the ICE5QRxxxxAx works with a digital signal processing circuit composing an up/down counter, a zero-crossing counter (ZC counter) and a comparator, and an analog circuit composing a current measurement unit and a comparator. The switch-on and -off time points are each determined by the digital circuit and the analog circuit, respectively. The input information of the zero-crossing signal and the value of the up/down counter are needed to determine the switch-on while the feedback signal VFB and the current sensing signal VCS are necessary for the switch-off determination. Details about the full operation of the CoolSETTM in normal operation are illustrated in the following paragraphs. 3.3.1 Digital Frequency Reduction As mentioned above, the digital signal processing circuit consists of an up/down counter, a ZC counter and a comparator. These three parts are key to implement digital frequency reduction with decreasing load. In addition, a ringing suppression time controller is implemented to avoid mis-triggering by the high frequency oscillation when the output voltage is very low under conditions such as soft start period or output short circuit. Functionality of these parts is described as in the following. 3.3.1.1 Minimum ZC Count Determination To reduce the switching frequency difference between low and high line, minimum ZC count determination is implemented. Minimum ZC count is set to 1 if VIN less than VVIN_REF which represents for low line. For high line, minimum ZC count is set to 3 after VIN higher than VVIN_REF. There is also a hysteresis VVIN_REF with certain blanking time tVIN_REF for stable AC line selection between low and high line. Data Sheet 8 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package 3.3.1.2 Up/down counter The up/down counter stores the number of the zero crossing where the main power switch is switched on after demagnetization of the transformer. This value is fixed according to the feedback voltage, VFB, which contains information about the output power. Indeed, in a typical peak current mode control, a high output power results in a high feedback voltage, and a low output power leads to a low regulation voltage. Hence, according to VFB, the value in the up/down counter is changed to vary the power MOSFET off-time according to the output power. In the following, the variation of the up/down counter value according to the feedback voltage is explained. The feedback voltage VFB is internally compared with three threshold voltages VFB_LHC, VFB_HLC and VFB_R at each clock period of 48 ms. The up/down counter counts then upward, keep unchanged or count downward, as shown in Table 3. Operation of up/down counter Table 3 VFB up/down counter action Always lower than VFB_LHC Count upwards till n=8/101 Once higher than VF_LHC, but always lower than VFB_HLC Stop counting, no value changing Once higher than VFB_HLC, but always lower than VFB_R Count downwards till n=1/32 Once higher than VFB_R Set up/down counter to n=1/32 The number of zero crossing is limited and therefore, the counter varies among 1 to 8 (for low line) 3 to 10 (for high line) and any attempt beyond this range is ignored. When VFB exceeds VFB_R voltage, the up/down counter is reset to 1 (low line) and 3 (high line) in order to allow the system to react rapidly to a sudden load increase. The up/down counter value is also reset to 1 (low line) and 3 (high line) at the start-up time, to ensure an efficient maximum load start up. Figure 6 shows some examples on how up/down counter is changed according to the feedback voltage over time. The use of two different thresholds VFB_LHC and VFB_HLC to count upward or downward is to prevent frequency jittering when the feedback voltage is close to the threshold point. T=48ms clock t VFB,R1 VFB,R3 VFB,HLC VFB,HLC VFB,LHC VFB,LHC Figure 6 n+3 n+2 n+1 n n+1 n+2 n+3 n+2 n+1 n 3 Case 1 5 6 7 8 8 8 7 6 5 1 Case 1 6 7 8 9 9 9 8 7 6 3 Case 2 2 3 4 5 5 5 4 3 2 1 Case 2 4 5 6 7 7 7 6 5 4 3 Case 3 8 8 8 8 8 8 7 6 5 1 Case 3 10 10 10 10 10 10 9 8 7 3 low line Up/down counter operation n=8 (for low line) and n=10 (for high line) n=1 (for low line) and n=3 (for high line) Data Sheet n n+3 t n+2 Up/down counter 1 n n+3 t n+1 Up/down counter t VFB n+3 VFB T=48ms n+3 clock High line 1 2 9 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package 3.3.1.3 Zero crossing (ZC counter) In the system, the voltage from the auxiliary winding is applied to the ZCD pin through a RC network, which provides a time delay to the voltage from the auxiliary winding. Internally this pin is connected to a clamping network, a zero-crossing detector, an output overvoltage detector and a ringing suppression time controller. During on-state of the power switch a negative voltage applies to the ZCD pin. Through the internal clamping network, the voltage at the pin is clamped to certain level. The ZC counter has a minimum value of 1 (for low line) or 3 (for high line) and maximum value of 8 (for low line) or 10 (for high line). After the internal high voltage CoolMOSTM is turned off, every time when the falling voltage ramp of on SOURCE pin crosses the VZCD_CT threshold, a zero crossing is detected and ZC counter will increase by 1. It is reset every time after the DRIVER output is changed to high. The voltage VZCD is also used for the output over voltage protection. Once the voltage at this pin is higher than the threshold VZCD_OVP during off time of the main switch for 10 consecutive pulses, the IC enters output over voltage protection mode. To achieve the switch on at voltage valley, the voltage from the auxiliary winding is fed to a time delay network (the RC network consists of RZC and CZC as shown in Figure 1) before it is applied to the zero-crossing detector through the ZCD pin. The needed time delay to the main oscillation signal t should be approximately one fourth of the oscillation period, TOSC (by transformer primary inductor and drain-source capacitor) minus the propagation delay from the detected zero-crossing to the switch-on of the main switch tdelay, theoretically: (2) t = - 4 This time delay should be matched by adjusting the time constant of the RC network which is calculated as: (3) td = . + 3.3.2 Ringing suppression time After CoolMOSTM is turned off, there will be some oscillation on VDS, which will also appear on VZCD. To avoid mistriggering by such oscillations to turn on the CoolMOSTM, a ringing suppression timer is implemented. This suppression time is depended on the voltage VZCD. If the voltage VZCD is lower than the threshold VZCD_RS, a longer preset time tZCD_RS2 is applied. However, if the voltage VZCD is higher than the threshold, a shorter time tZCD_RS1 is set. 3.3.2.1 Switch on determination After the gate drive goes to low, it cannot be changed to high during ring suppression time. After ring suppression time, the gate drive can be turned on when the ZC counter value is higher or equal to up/down counter value. However, it is also possible that the oscillation between primary inductor and drain-source capacitor damps very fast and IC cannot detect enough zero crossings and ZC counter value will not be high enough to turn on the gate drive. In this case, a maximum off time is implemented. After gate drive has been remained off for the period of TOffMax, the gate drive will be turned on again regardless of the counter values and VZCD. This function can effectively prevent the switching frequency from going lower than 20 kHz. Otherwise it will cause audible noise during start up. Data Sheet 10 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package 3.3.3 Switch off determination In the converter system, the primary current is sensed by an external shunt resistor, which is connected between the internal low side MOSFET and the common ground. The sensed voltage across the shunt resistor VCS is applied to an internal current measurement unit, and its output voltage V1 is compared with the regulation voltage VFB. Once the voltage V1 exceeds the voltage VFB, the output flip-flop is reset. As a result, the main power switch is switched off. The relationship between the V1 and the VCS is described by (see Figure 3): (4) 1 = + To avoid mis-triggering caused by the voltage spike across the shunt resistor at the turn on of the main power switch, a leading edge blanking time, tLEB, is applied to the output of the comparator. In other words, once the gate drive is turned on, the minimum on time of the gate drive is the leading edge blanking time. In addition, there is a maximum on time, tOnMax, limitation implemented in the IC. Once the gate drive has been in high state longer than the maximum on time, it will be turned off to prevent the switching frequency from going too low because of long on time. 3.3.4 Modulated gate drive The drive-stage is optimized for EMI consideration. The switch on speed is slowed down before it reaches the CoolMOSTM turn on threshold. That is a slope control of the rising edge at the output of driver (see Figure 7). Thus the leading switch spike during turn on is minimized. VGATE (V) VGATE_HIGH typ. t = 117ns 5V t (ns) Figure 7 Gate rising waveform 3.4 Current limitation There is a cycle by cycle current limitation realized by the current limit comparator to provide over-current detection. The source current of the CoolMOSTM is sensed via a sense resistor RCS. By means of RCS the source current is transformed to a sense voltage VCS which is fed into the pin CS. If the voltage VCS exceeds an internal voltage limit, adjusted according to the Line voltage, the comparator immediately turns off the gate drive. To prevent the Current Limitation process from distortions caused by leading edge spikes, a Leading Edge Blanking time (tLEB) is integrated in the current sensing path. When the main bus voltage increases, the switch on time becomes shorter and therefore the operating frequency is also increased. As a result, for a constant primary current limit, the maximum possible output power is increased which is beyond the converter design limit. To avoid such a situation, both the internal peak current limit circuit (VCS) and the ZC count varies with the bus voltage according to Figure 8. Data Sheet 11 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package VCS (V) VCS_N, 1 0.9 Starting ZC = 1 0.83 Starting ZC = 3 1.29 VVIN_REF Figure 8 Variation of the VCS limit voltage according to the VIN voltage 3.5 Active Burst Mode with selectable power level VVIN (V) At light load condition, the IC enters Active Burst Mode operation to minimize the power consumption. Details about Active Burst Mode operation are explained in the following paragraphs. The burst mode entry level can be selected by changing the different resistor RSel at FB pin. There are 2 levels to be selected with different resistor which are targeted for low range of active burst mode power (Level 1) and high range of active burst mode power (Level 2). The following table shows the control logic for the entry and exit level with the FB voltage. Operation of the up/down counter Table 4 Level VFB VCS Entry level Exit level VFB_EBLX VFB_LB 1 VFB > VREF_B VCS_BL1 = 0.31 V 0.90 V 2.75 V 2 VFB < VREF_B VCS_BL2 = 0.35 V 1.05 V 2.75 V During IC first startup, the internal RefGOOD signal is logic low when VCC < 4 V. It will reset the Burst Mode level Detection latch. When the Burst Mode Level Detection latch is low and IC is in OFF state, the FB resistor is isolated from the FB pin and a current source Isel is turned on instead. From Vcc=4 V to Vcc on threshold, the FB pin will start to charge to a voltage level associated with RSel resistor. When Vcc reaches Vcc on threshold, the FB voltage is sensed. The burst mode thresholds are then chosen according to the FB voltage level. The Burst Mode Level Detection latch is then set to high. Once the detection latch is set high, any change of the FB level will not change the threshold level. When Vcc reaches Vcc on threshold, a timer of 2 s is started. After the 2 s timer ends, the current source is turned off while the FB resistor is connected to FB pin (see Figure 9). Data Sheet 12 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package Vdd Isel S2 UVLO 2s delay R RFB Ref good S1 FB Burst mode detection latch VCS_BLx VFB _E BL x Selection Logic Compare logic VREF_B RSel S Control unit Figure 9 Burst mode detect and adjust 3.5.1 Entering Active Burst Mode Operation For determination of entering Active Burst Mode operation, three conditions apply: the feedback voltage is lower than the threshold of VFB_EBLX the up/down counter is 8 for low line and 10 for high line and a certain blanking time tFB_BEB (20 ms). Once all of these conditions are fulfilled, the Active Burst Mode flip-flop is set and the controller enters Active Burst Mode operation. This multi-condition determination for entering Active Burst Mode operation prevents mis-triggering of entering Active Burst Mode operation, so that the controller enters Active Burst Mode operation only when the output power is really low during the preset blanking time. 3.5.2 During Active Burst Mode Operation After entering the Active Burst Mode the feedback voltage rises as VO starts to decrease due to the inactive PWM section. One comparator observes the feedback signal if the voltage level VFB_BOn is exceeded. In that case the internal circuit is again activated by the internal bias to start with switching. Turn-on of the power MOSFET is triggered by ZC counter with a fixed value of 8 ZC for low line and 10 ZC for high line. Turn-off is resulted if the voltage across the shunt resistor at CS pin hits the threshold VCS_BLX. If the output load is still low, the feedback signal decreases as the PWM section is operating. When feedback signal reaches the low threshold VFB_BOff , the internal bias is reset again and the PWM section is disabled until next time regulation signal increases beyond the VFB_BOn threshold. In Active Burst Mode, the feedback signal is changing like a saw tooth between VFB_BOff and VFB_BOn (see Figure 10). 3.5.3 Leaving Active Burst Mode Operation The feedback voltage immediately increases if there is a high load jump. This is observed by a comparator. As the current limit is VCS_BLX (31% or 35%) during Active Burst Mode, a certain load is needed so that feedback voltage can exceed VFB_LB. After leaving active burst mode, maximum current VCS_N (100%) can now be provided to stabilize output voltage. In addition, the up/down counter will be set to 1 (low line) or 3 (high line) immediately after leaving Active Burst Mode. This is helpful to decrease the output voltage undershoot. Data Sheet 13 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package VFB VFB_LB VFB_BOn VFB_BOff Entering Active Burst Mode Leaving Active Burst Mode VFB_EBx VCS VCS_N Time to 8th/10th ZC and Blanking time (tFB_BEB) t Current limit level during Active Burst Mode VCS_BLx VVCC t VVCC_OFF VO t Max. Ripple < 1% t Figure 10 Data Sheet Signals in Active Burst Mode 14 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package 3.6 Protection Functions The ICE5QRxxxxAx provides numerous protection functions which considerably improve the power supply system robustness, safety and reliability. The following table summarizes these protection functions. There are 3 different kinds of protection mode; non switch auto restart, auto restart and odd skip auto restart. The details can refer to the Figure 11, Figure 12 and Figure 13. Table 5 Protection functions Protection Functions Normal Mode Burst Mode Protection Mode Line Over Voltage Burst ON Burst OFF Non switch Auto Restart Brownout Non switch Auto Restart VCC Over Voltage NA1 VCC Under Voltage Over Load NA1 NA1 Odd skip Auto Restart Output Over Voltage NA1 Odd skip Auto Restart Over Temperature CS Short to GND NA1 Odd skip Auto Restart Auto Restart Non switch Auto Restart Odd skip Auto Restart The AC Line Over Voltage Protection is detected by sensing bus capacitor voltage through VIN pin via 2 potential divider resistors, Rl1 and Rl2 (see Figure 1). Once VVIN voltage is higher than the line over voltage threshold VVIN_LOVP, the controller enters Line Over Voltage Protection and it releases the protection mode after VVIN is lower than VVIN_LOVP. The Brownout protection is observed by VIN pin similar to line over voltage Protection method with a different voltage threshold level. When VVIN voltage is lower than the brownout threshold (VVIN_BO), the controller enters Brownout Protection and it releases the protection mode after VVIN higher than brownin threshold (VVIN_BI). During operation, the VCC voltage is continuously monitored. In case of a VCC Under Voltage or Over Voltage, the IC is reset and the main power switch is then kept off. After the VCC voltage falls below the threshold VVCC_OFF, the new start up sequence is activated. The VCC capacitor is then charged up. Once the voltage exceeds the threshold VVCC_ON, the IC begins to operate with a new soft-start. In case of open control loop or output Over Load, the feedback voltage will be pulled up and exceed VFB_OLP. After a blanking time of tFB_OLP_B, the IC enters auto restart mode. The blanking time here enables the converter to provide a peak power in case the increase in VFB is due to a sudden load increase. During off-time of the power MOSFET, the voltage at the ZCD pin is monitored for Output Over Voltage detection. If the voltage is higher than the preset threshold VZCD_OVP for 10 consecutive pulses, the IC enters Output Over Voltage Protection. If the junction temperature of controller chip exceeds Tjcon_OTP, the IC enters into Over Temperature protection (OTP) auto restart mode. The controller implements with a 40 C hysteresis. In another word, the controller/IC can only resume from OTP if its junction temperature drops 40 C from OTP trigger point. Please be noted that the separated CoolMOSTM chip may have different temperature (mostly higher) from the controller chip. If the voltage at the current sense pin is shorted and lower than the preset threshold VCS_STG with certain blanking time tCS_STG_B for 3 consecutive pulses during on-time of the power MOSFET, the IC enters CS Short to GND Protection. Not Applicable Data Sheet 1 15 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package There is also a maximum on time limitation implemented inside the ICE5QRxxxxAx. Once the gate voltage is high and longer than tOnMax, the switch is turned off immediately. Fault detected Fault released Start up and detect at every charging cycle VVCC Switching start at the following restartt cycle VCC_ON VCC_OFF VCS t No switching t Figure 11 Non switch Auto Restart Mode Fault detected Fault released Start up and detect at every charging cycle VVCC Switching start at the t cycle following restart VCC_ON VCC_OFF VCS t t Figure 12 Data Sheet Auto Restart Mode 16 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package Fault detected Fault released Start up and detect at every even charging cycle VVCC No detect No detect Switching start at the following event restart cycle VCC_ON VCC_OFF VCS t t Figure 13 Data Sheet Odd skip Auto Restart Mode 17 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package 4 Electrical Characteristics Attention: All voltages are measured with respect to ground (Pin 8 for DIP-7 and Pin12 for DSO-12). The voltage levels are valid if other ratings are not violated. 4.1 Absolute Maximum Ratings Attention: Stresses above the maximum values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. System design needs to ensure not to exceed the maximum limit. Table 6 Absolute Maximum Ratings Parameter Symbol Limit Values Min. Max. Unit Note / Test Condition Drain Source Voltage ICE5QRxx70Ax VDS 700 - V Tj = 25 C Drain Source Voltage ICE5QRxx80Ax VDS 800 - V Tj = 25 C Pulse drain current ICE5QR4770AZ1 ICE5QR4780AZ1 ICE5QR2270AZ2 ICE5QR2280AZ2 ICE5QR1070AZ2 ICE5QR0680AZ2 ICE5QR4770AG1 ICE5QR1680AG2 ICE5QR0680AG2 ID_Pulse A TC = 25 C Avalanche energy, repetitive ICE5QR4770AZ ICE5QR4780AZ ICE5QR2270AZ ICE5QR2280AZ ICE5QR1070AZ ICE5QR0680AZ ICE5QR4770AG ICE5QR1680AG ICE5QR0680AG EAR Pulse width tP limited by Tj,Max Pulse width tP=20 s and limited by Tj,Max Data Sheet - 2.2 2.6 5.8 5.8 5.8 5.8 2.2 5.8 5.8 mJ - 0.02 0.02 0.07 0.05 0.06 0.22 0.02 0.07 0.22 ID=0.14 A, VDD=50 V ID=0.2 A, VDD=50 V ID=0.4 A, VDD=50 V ID=0.4 A, VDD=50 V ID=0.38 A, VDD=50 V ID=1.8 A, VDD=50 V ID=0.14 A, VDD=50 V ID=0.6 A, VDD=50 V ID=1.8 A, VDD=50 V 1 2 18 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package Avalanche current, repetitive ICE5QR4770AZ ICE5QR4780AZ ICE5QR2270AZ ICE5QR2280AZ ICE5QR1070AZ ICE5QR0680AZ ICE5QR4770AG ICE5QR1680AG ICE5QR0680AG IAR VCC Supply Voltage A - 0.14 0.2 0.4 0.4 0.82 1.8 0.14 0.6 1.8 VCC -0.3 27.0 V FB Voltage VFB -0.3 3.6 V ZCD Voltage VZCD -0.3 27 V CS Voltage VCS -0.3 3.6 V VIN Voltage VIN -0.3 3.6 V -10.0 10.0 mA Maximum DC current on any pin except DRAIN & CS pins ESD robustness HBM VESD_HBM - 2000 V ESD robustness CDM VESD_CDM - 500 V According to EIA/JESD22 Junction temperature range TJ -40 150 C Controller & CoolMOS Storage Temperature TSTORE -55 150 C Thermal Resistance (JunctionAmbient) ICE5QR4770AZ ICE5QR4780AZ ICE5QR2270AZ ICE5QR2280AZ ICE5QR1070AZ ICE5QR0680AZ ICE5QR4770AG ICE5QR1680AG ICE5QR0680AG RthJA Data Sheet K/W - 106 107 103 104 100 100 104 95 94 19 Setup according to the JESD51 standard and using minimum drain pin copper area in a 2 oz copper single sided PCB Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package 4.2 Operating Range Note : Within the operating range the IC operates as described in the functional description. Table 7 Operating Range Parameter Symbol VCC Supply Voltage VVCC Limit Values Unit Min. Max. VVCC_OFF VVCC_OVP Junction Temperature of controller TjCon_op -40 TjCon_OTP C Junction Temperature of CoolMOS TjCoolMOS_op -40 150 C 4.3 Remark Max value limited due to OTP of controller chip Operating Conditions Note: The electrical characteristics involve the spread of values within the specified supply voltage and junction temperature range TJ from - 40 C to 125 C. Typical values represent the median values, which are related to 25C. If not otherwise stated, a supply voltage of VCC = 18 V is assumed. Table 8 Operating Conditions Parameter Symbol Limit Values Unit Note / Test Condition Min. Typ. Max. IVCC_Charge1 -0.35 -0.2 0.09 mA VVCC=0V, RStartUp=50M and VDRAIN=90V IVCC_Charge2 - -3.2 - mA VVCC=3V, RStartUp=50M and VDRAIN=90V IVCC_Charge3 -5 -3 -1 mA VVCC=15V, RStartUp=50M and VDRAIN=90V Current Consumption, Startup Current IVCC_Startup - 0.19 - mA Current Consumption, Normal IVCC_Normal - 0.9 - mA Current Consumption, Auto Restart IVCC_AR - 320 - A Current Consumption, Burst Mode IVCC_Burst Mode - 0.5 - mA VCC Turn-on Threshold Voltage VVCC_ON 15.3 16 16.5 V VCC Turn-off Threshold Voltage VVCC_OFF 9.5 10 10.5 V VCC Short Circuit Protection VVCC_SCP - 1.1 1.9 V VCC Turn-off blanking tVCC_OFF_B - 50 - s VCC Charge Current Data Sheet 20 VVCC=15V IFB=0A (No gate switching) VFB=1.8V Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package 4.4 Internal Voltage Reference Internal Voltage Reference Table 9 Parameter Internal Reference Voltage 4.5 Symbol Limit Values VREF Min. 3.2 Symbol Limit Values Typ. 3.3 Unit Max. 3.39 V PWM Section Parameter Unit Min. Typ. Max. Feedback Pull-Up Resistor RFB 11 15 20 k PWM-OP Gain GPWM 1.95 2.05 2.15 - Offset for Voltage Ramp VPWM 0.42 0.5 0.58 V Maximum on time in normal operation tOnMax 20 35 60 s Maximum off time in normal operation tOffMax 24 42.5 71 s Symbol Limit Values Peak current limitation in normal operation VCS_N Min. 0.94 Typ. 1.00 Max. 1.06 V Leading Edge Blanking time tCS_LEB 118 220 462 ns Peak Current Limitation in Active Burst Mode - Level 1 VCS_BL1 0.26 0.31 0.36 V Peak Current Limitation in Active Burst Mode - Level 2 VCS_BL2 0.3 0.35 0.4 V Table 11 Note / Test Condition Current Sense Current Sense Parameter Data Sheet Measured at pin FB IFB=0 PWM Section Table 10 4.6 Note / Test Condition 21 Unit Note / Test Condition Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package 4.7 Soft Start Soft Start Table 12 Parameter Symbol Soft-Start time Soft-start time step Internal regulation voltage at first step Internal regulation voltage step at soft start 4.8 Limit Values Unit Note / Test Condition Min. Typ. Max. tSS tSS_S1 8.5 - 12 ms 3 - VSS11 - 0.30 - V CS peak voltage VSS_S1 - 0.15 - V CS peak voltage ms Digital Zero Crossing Table 13 Digital Zero Crossing Parameter Symbol Limit Values Unit Min. Typ. Max. Note / Test Condition Zero crossing threshold voltage Zero crossing Ringing suppression threshold Minimum ringing suppression time VZCD_CT VZCD_RS 60 - 100 0.45 150 - mV V tZCD_RS1 1.5 2.5 4.1 s VZCD > VZCD,RS Maximum ringing suppression time tZCD_RS2 - 25.00 - s VZCD < VZCD,RS Threshold to reset Up/Down Counter Threshold for downward counting VFB_R - 2.80 - V VFB_HLC - 2.05 - V Threshold for upward counting VFB_LHC - 1.55 - V Counter Time tCOUNT - 48 - ms ZCD resistance RZCD 2.5 3.0 3.5 k VIN voltage threshold for line selection Blanking time for VIN voltage threshold for line selection VVIN_REF 1.48 1.52 1.58 V tVIN_REF - 16.00 - ms The parameter is not subjected to production test - verified by design/characterization Data Sheet 22 Internal resistor at ZCD pin 1 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package 4.9 Table 14 Active Burst Mode Active Burst Mode Parameter Symbol Limit Values Unit Min. Typ. Max. Charging current to select burst mode Isel 2.1 3 3.9 A Burst mode selection reference voltage VREF_B 2.65 2.75 2.85 V Feedback voltage for entering Active Burst Mode for level 1 VFB_EBL1 0.86 0.90 0.94 V Feedback voltage for entering Active Burst Mode for level 2 VFB_EBL2 1.0 1.05 1.1 V Blanking time for entering Active Burst Mode Feedback voltage for leaving Active Burst Mode Feedback voltage for burst-on tFB_BEB - 20 - ms VFB_LB 2.65 2.75 2.85 V VFB_BOn 2.3 2.40 2.5 V Feedback voltage for burst-off VFB_BOff 1.9 2.00 2.1 V 4.10 Table 15 Line Over Voltage Protection Line OVP Parameter Line Over Voltage threshold VVIN_LOVP Limit Values Min. Typ. 2.8 2.9 Line Over Voltage Blanking tVIN_LOVP_B - 4.11 Table 16 Symbol 250 Unit Max. 3.0 V - s Note / Test Condition Brownout Protection Brownout Protection Parameter Symbol Limit Values Unit Min. Typ. Max. BrownIn threshold BrownIn Blanking VVIN_BI tVIN_BI_B 0.63 - 0.66 250 0.69 - V s BrownOut threshold VVIN_BO 0.40 tVIN_BO_B 0.43 - V BrownOut Blanking 0.37 - Data Sheet Note / Test Condition 250 23 Note / Test Condition s Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package 4.12 Table 17 VCC Over Voltage Protection Vcc Over Voltage Protection Parameter Symbol Limit Values VCC Over Voltage threshold VVCC_OVP Min. 24 Typ. 25.50 Max. 27 V VCC Over Voltage blanking tVCC_OVP_B - 50.00 - s 4.13 Table 18 Unit Over Load Protection Overload Protection Parameter Symbol Limit Values Unit Min. Typ. Max. Over Load Detection threshold for OLP protection at FB pin VFB_OLP 2.65 2.75 2.85 V Over Load Protection Blanking Time tFB_OLP_B - 30 - ms 4.14 Table 19 Output OVP Symbol Limit Values Unit Min. Typ. Max. Output Over Voltage threshold VZCD_OVP 1.9 2.0 2.1 V Output Over Voltage Blanking Pulse PZCD_OVP_B - 10 - pulse Table 20 Note / Test Condition Output Over Voltage Protection Parameter 4.15 Note / Test Condition Note / Test Condition Consecutive Pulse Thermal Protection Thermal Protection Parameter Symbol Limit Values Unit Min. Typ. Max. Over temperature protection1 Tjcon_OTP 129 140 150 C Over temperature Hysteresis Over temperature Blanking Time TjHYS_OTP tjcon_OTP_B - 40 50 - C s The parameter is not subjected to production test - verified by design/characterization Data Sheet 24 Note / Test Condition Junction temperature of the controller chip (not the CoolMOSTM chip) 1 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package 4.16 Table 21 CS Short to GND Protection CS Short to GND Protection Parameter CS Short to Gnd Protection CS Short to Gnd Consecutive Trigger CS Short to Gnd Sample period Data Sheet Symbol Limit Values Unit Min. Typ. Max. VCS_STG PCS_STG 0.06 - 0.10 3 0.15 - V cycle tCS_STG_SAM 2.3 5 - s 25 Note / Test Condition Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package 4.17 CoolMOSTM Section Table 22 ICE5QRxxxxAx Parameter Symbol Drain Source Breakdown Voltage ICE5QRxx70Ax ICE5QRxx80Ax Drain Source On-Resistance (inclusive of low side MOSFET) V(BR)DSS Limit Values Min. Typ. Unit Max. V 700 800 - Note / Test Condition Tj = 25C - RDSon ICE5QR4770AZ - 4.73 8.73 5.18 - Tj = 25C Tj=125C1, ID =0.4A ICE5QR4780AZ - 4.13 8.69 4.85 - Tj = 25C Tj=125C1, ID =0.4A ICE5QR2270AZ - 2.13 4.31 2.33 - Tj = 25C Tj=125C1, ID =1A ICE5QR2280AZ - 2.13 4.31 2.35 - Tj = 25C Tj=125C1, ID =1A ICE5QR1070AZ - 1.15 1.85 1.25 Tj = 25C Tj=125C1, ID =1.1A ICE5QR0680AZ - 0.71 1.27 0.80 - Tj = 25C Tj=125C1, ID =2A ICE5QR4770AG - 4.73 8.73 5.18 - Tj = 25C Tj=125C1, ID =0.4A ICE5QR1680AG - 1.53 3.01 1.75 - Tj = 25C Tj=125C1, ID =1.4A ICE5QR0680AG - 0.71 1.27 0.80 - Tj = 25C Tj=125C1, ID =2A Effective output capacitance, energy related1 Co(er) pF ICE5QR4770AZ - 3.4 - VGS=0V,VDS=0~480V ICE5QR4780AZ - 3 - VGS=0V,VDS=0~500V ICE5QR2270AZ - 10 - VGS=0V,VDS=0~480V ICE5QR2280AZ - 7 - VGS=0V,VDS=0~500V ICE5QR1070AZ - 13 - VGS=0V,VDS=0~400V ICE5QR0680AZ - 24 - VGS=0V,VDS=0~500V ICE5QR4770AG - 3.4 - VGS=0V,VDS=0~480V ICE5QR1680AG - 8 - VGS=0V,VDS=0~500V The parameter is not subjected to production test - verified by design/characterization Data Sheet 26 1 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package ICE5QR0680AG - 24 - VGS=0V,VDS=0~500V Rise Time1 trise - 30 - ns Fall Time2 tfall - 30 - ns Measured in a Typical Flyback Converter Application Data Sheet 1 27 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package 5 CoolMOSTM Performance Characteristics Figure 14 Safe Operating Area (SOA) curve for ICE5QR4770AZ Figure 15 Safe Operating Area (SOA) curve for ICE5QR4780AZ Data Sheet 28 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package Figure 16 Safe Operating Area (SOA) curve for ICE5QR2270AZ Figure 17 Safe Operating Area (SOA) curve for ICE5QR2280AZ Data Sheet 29 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package Figure 18 Safe Operating Area (SOA) curve for ICE5QR1070AZ Figure 19 Safe Operating Area (SOA) curve for ICE5QR0680AZ Data Sheet 30 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package Figure 20 Safe Operating Area (SOA) curve for ICE5QR4770AG Figure 21 Safe Operating Area (SOA) curve for ICE5QR1680AG Data Sheet 31 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package Figure 22 Safe Operating Area (SOA) curve for ICE5QR0680AG Figure 23 Power dissipation of ICE5QR4770AZ, DIP-7 package; Ptot=f(Ta), (Maximum ratings as given in section 4.1 must not be exceeded) Data Sheet 32 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package Figure 24 Power dissipation of ICE5QR4780AZ, DIP-7 package; Ptot=f(Ta), (Maximum ratings as given in section 4.1 must not be exceeded) Figure 25 Power dissipation of ICE5QR2270AZ, DIP-7 package; Ptot=f(Ta), (Maximum ratings as given in section 4.1 must not be exceeded) Data Sheet 33 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package Figure 26 Power dissipation of ICE5QR2280AZ, DIP-7 package; Ptot=f(Ta), (Maximum ratings as given in section 4.1 must not be exceeded) Figure 27 Power dissipation of ICE5QR1070AZ, DIP-7 package; Ptot=f(Ta), (Maximum ratings as given in section 4.1 must not be exceeded) Data Sheet 34 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package Figure 28 Power dissipation of ICE5QR0680AZ, DIP-7 package; Ptot=f(Ta), (Maximum ratings as given in section 4.1 must not be exceeded) Figure 29 Power dissipation of ICE5QR4770AG, DSO-12 package; Ptot=f(Ta), (Maximum ratings as given in section 4.1 must not be exceeded) Data Sheet 35 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package Figure 30 Power dissipation of ICE5QR1680AG, DSO-12 package; Ptot=f(Ta), (Maximum ratings as given in section 4.1 must not be exceeded) Figure 31 Power dissipation of ICE5QR0680AG, DSO-12 package; Ptot=f(Ta), (Maximum ratings as given in section 4.1 must not be exceeded) Data Sheet 36 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package 780 760 VBR(DSS) [V] 740 720 700 680 660 640 620 -75 -50 -25 0 25 50 75 100 125 150 175 TJ [C] Figure 32 Drain-source breakdown voltage ICE5QRxx70Ax; VBR(DSS)=f(TJ), ID=1 mA Figure 33 Drain-source breakdown voltage ICE5QRxx80Ax; VBR(DSS)=f(TJ), ID=1 mA Data Sheet 37 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package Figure 34 Typical CoolMOSTM capacitances of ICE5QR4770Ax (C=f(VDS);VGS=0 V; f=1 MHz) Figure 35 Typical CoolMOSTM capacitances of ICE5QR4780AZ (C=f(VDS);VGS=0 V; f=250 kHz) Data Sheet 38 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package Figure 36 Typical CoolMOSTM capacitances of ICE5QR2270AZ (C=f(VDS);VGS=0 V; f=1 MHz) Figure 37 Typical CoolMOSTM capacitances of ICE5QR2280AZ (C=f(VDS);VGS=0 V; f=250 kHz) Data Sheet 39 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package Figure 38 Typical CoolMOSTM capacitances of ICE5QR1070AZ (C=f(VDS);VGS=0 V; f=250 kHz) Figure 39 Typical CoolMOSTM capacitances of ICE5QR0680Ax (C=f(VDS);VGS=0 V; f=250 kHz) Data Sheet 40 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package Figure 40 Data Sheet Typical CoolMOSTM capacitances of ICE5QR1680AG(C=f(VDS);VGS=0 V; f=250 kHz) 41 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package 6 Output Power Curve The calculated output power curves giving the typical output power versus ambient temperature are shown below. The curves are derived based on a typical discontinuous mode flyback in an open frame design at Ta=50C, TJ=125C (integrated high voltage MOSFET), using minimum drain pin copper area in a 2 oz copper single sided PCB and steady state operation only (no design margins for abnormal operation modes are included). The output power figure is for selection purpose only. The actual power can vary depending on particular designs. In a power supply system, appropriate thermal design margins must be applied to make sure that the maximum ratings given in section 4.1are respected at all times. Figure 41 Output power curve of ICE5QR4770AZ, VIN=85~300 VAC; POut=f(Ta) Figure 42 Output power curve of ICE5QR4770AZ, VIN=220 VAC; POut=f(Ta) Data Sheet 42 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package Figure 43 Output power curve of ICE5QR4780AZ, VIN=85~300 VAC; POut=f(Ta) Figure 44 Output power curve of ICE5QR4780AZ, VIN=220 VAC; POut=f(Ta) Data Sheet 43 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package Figure 45 Output power curve of ICE5QR2270AZ, VIN=85~300 VAC; POut=f(Ta) Figure 46 Output power curve of ICE5QR2270AZ, VIN=220 VAC; POut=f(Ta) Data Sheet 44 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package Figure 47 Output power curve of ICE5QR2280AZ, VIN=85~300 VAC; POut=f(Ta) Figure 48 Output power curve of ICE5QR2280AZ, VIN=220 VAC; POut=f(Ta) Data Sheet 45 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package Figure 49 Output power curve of ICE5QR1070AZ, VIN=85~300 VAC; POut=f(Ta) Figure 50 Output power curve of ICE5QR1070AZ, VIN=220 VAC; POut=f(Ta) Data Sheet 46 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package Figure 51 Output power curve of ICE5QR0680AZ, VIN=85~300 VAC; POut=f(Ta) Figure 52 Output power curve of ICE5QR0680AZ, VIN=220 VAC; POut=f(Ta) Data Sheet 47 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package Figure 53 Output power curve of ICE5QR4770AG, VIN=85~300 VAC; POut=f(Ta) Figure 54 Output power curve of ICE5QR4770AG, VIN=220 VAC; POut=f(Ta) Data Sheet 48 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package Figure 55 Output power curve of ICE5QR1680AG, VIN=85~300 VAC; POut=f(Ta) Figure 56 Output power curve of ICE5QR1680AG, VIN=220 VAC; POut=f(Ta) Data Sheet 49 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package Figure 57 Output power curve of ICE5QR0680AG, VIN=85~300 VAC; POut=f(Ta) Figure 58 Output power curve of ICE5QR0680AG, VIN=220 VAC; POut=f(Ta) Data Sheet 50 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package 7 Outline Dimension Figure 59 PG-DIP-7 Data Sheet 51 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package Figure 60 Data Sheet PG-DSO-12 52 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package 8 Marking Figure 61 Marking of DIP-7 Figure 62 Marking of DSO-12 Data Sheet 53 Revision 2.0 2017-07-04 Quasi-Resonant 700 V/800 V CoolSETTM - in DIP-7 and DSO-12 Package Revision History Major changes since the last revision Page or Reference 2, 18,19, 26~46 37 Data Sheet Description of change Addition of ICE5QR1070AZ Update of 700V CoolSETTM Drain-source breakdown voltage as shown in Figure 32 reference to errata sheet #10157AERRA 54 Revision 2.0 2017-07-04 Trademarks of Infineon Technologies AG AURIXTM, C166TM, CanPAKTM, CIPOSTM, CoolGaNTM, CoolMOSTM, CoolSETTM, CoolSiCTM, CORECONTROLTM, CROSSAVETM, DAVETM, DI-POLTM, DrBladeTM, EasyPIMTM, EconoBRIDGETM, EconoDUALTM, EconoPACKTM, EconoPIMTM, EiceDRIVERTM, eupecTM, FCOSTM, HITFETTM, HybridPACKTM, InfineonTM, ISOFACETM, IsoPACKTM, i-WaferTM, MIPAQTM, ModSTACKTM, my-dTM, NovalithICTM, OmniTuneTM, OPTIGATM, OptiMOSTM, ORIGATM, POWERCODETM, PRIMARIONTM, PrimePACKTM, PrimeSTACKTM, PROFETTM, PRO-SILTM, RASICTM, REAL3TM, ReverSaveTM, SatRICTM, SIEGETTM, SIPMOSTM, SmartLEWISTM, SOLID FLASHTM, SPOCTM, TEMPFETTM, thinQ!TM, TRENCHSTOPTM, TriCoreTM. Trademarks updated August 2015 Other Trademarks All referenced product or service names and trademarks are the property of their respective owners. Edition 2017-07-04 Published by Infineon Technologies AG 81726 Munchen, Germany ifx1owners. (c) 2017 Infineon Technologies AG. All Rights Reserved. Do you have a question about this document? Email: erratum@infineon.com Document reference IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie") . With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. 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