Ww WHITE MICROELECTRONICS WE512K8, WE25GK8, WE128K8-XCX 512Kx8 CMOS EEPROM, WE512K8-XCX, SMD 5962-93091 512Kx8 BIT CMOS EEPROM MODULE FIG. 1 FEATURES PIN COREG URATION W@ Read Access Times of 150nS, 200nS, 250nS, 300nS | @ JEDEC Standard 32 Pin, Hermetic Ceramic DIP (Package 301} Atai|1 32] v,. ; : mele a KE @ Full Military and Industrial Temperature Ranges A1s(]3 30[7] a17 @ MIL-STD-883 Compliant Devices Available aie Aas M@ Write Endurance 10,000 Cycles as[|6 a7{ a8 M@ Data Retention at 25C, 10 Years A5(|7 26[ a9 . Astle ostlatt @ low Power CMOS Operation: Aatl9 24 OE 3mA Standby Typical/100mA Operating Maximum ar ares B Automatic Page Write Operation aotli2 21} ] vor Internal Address and Data Latches for voo[]13 201] vos 512 Bytes, 1 to 128 Bytes/Row, Four Pages host i. eA vos @ Page Write Cycle Time 10mS Max. v,,] 16 17] vo3 M@ Data Polling for End of Write Detection @ Hardware and Software Data Protection @ TTL Compatible Inputs and Outputs PIN DESCRIPTION Ao-18 Address inputs WOo- 7 Data Input/Output cs Chip Select OE Output Enable WE Write Enable Voc +5.0V Power Vss Ground BLOCK DIAGRAM A0-16 100-74 of | Pot i : | WE oe 4 if " ti oth ty 12eK x8; nse !128K x8 j 128K x 8 | 4 | 4 | a | lo AN? . cecoser | A118 ~ 4 cs August 1995 5-1 White Microelectronics * Phoenix, AZ * (602) 437-1520 eaInANnW wANnUs12 PRSJTNGOW WOudj3 Fl [4 WHITE MICROELECTRONICS WE512K8, WE256K8, WE128K8-XCX 256Kx8 CMOS EEPROM, WE256K8-XCX, SMD 5962-93155 FIG.2 PIN CONFIGURATION TOP VIEW nelfi1 2] dV, Al6| [2 31[ | WE A15| 1/3 30[_] A17 Al2: 14 2g JA14 A7( }5 26, ]Ai3 A6[ |6 27| JA8 As[ |7 26(_JA9 A4! la 25, [AN A3(]a 24| | OE A2[ | 10 23[ | At0 A1| |it 22| |cs AgT) 12 21, ] 07 oo | }13 20] | vos wort )14 19f | vOs vO? [7] 15 18| | O04 Vf }16 171 | vos PIN DESCRIPTION Ag-17 Address inputs \/00-7 Data Input/Output cs Chip Select OE Output Enable WE Write Enable Vcc +5.0V Power Vss Ground BLOCK DIAGRAM Ao14 (00-74 | | Sao WE OE 1 ' ae + Y 1 | 2 8 | deK xB 32K KB " t t | ! A15 oo | A16 Decoder AIT | cs t 256Kx8 BIT CMOS EEPROM MODULE FEATURES Read Access Times of 150nS, 200nS JEDEC Standard 32 Pin, Hermetic Ceramic DIP (Package 301) Full Military and Industrial Temperature Ranges MIL-STD-883 Compliant Devices Available Write Endurance 10,000 Cycles Data Retention at 25C, 10 Years Low Power CMOS Operation: 2mA Standby Typical/90mA Operating Maximum Automatic Page Write Operation Internal Address and Data Latches for 512 Bytes, 1 to 64 Bytes/Row, Eight Pages Page Write Cycle Time 10mS Max. Data Polling for End of Write Detection Hardware and Software Data Protection TTL Compatible Inputs and Qutputs White Microelectronics * Phoenix, AZ * (602) 437-1520 5-2Wi WHITE MICROELECTRONICS WE512K8, WE256K8, WE128KB-XCX 128Kx8 CMOS EEPROM, WE128K8-XCX, SMD 5962-93154 FIG. 3 PIN CONFIGURATION TOP VIEW NCU} 4 321 1V,., Ai6[ |2 31[] WE A15[ 13 30, ] NC Al2[]4 29[ | A14 A7[]5 281) A13 A6(]6 27| 1 A8 A5(]7 26/ | A9 A4[ | 8 ast Att A3(]9 24[ 1 OF A2(] 10 23[] A10 Avi) 14 22[]cs AO| ] 12 21[ ] vor yoo []13 20[7] vO6 worl )14 19f 1 vos vO2 (.] 15 18] jvo4 v,.L] 16 17| J 03 PIN DESCRIPTION Ao-16 Address Inputs (00-7 Data Input/Output cs Chip Select OE Output Enable WE Write Enable Vcc +5.0V Power Vss Ground BLOCK DIAGRAM Ao-14 (00-74 : . cogh gly WE OE ' YY | | 1, | i" tt. sex xe | | 32K x8 32K x8 32K x8 i | 4 4 4 | bod! Als .| Ate | Decoder | cs t 128Kx8 BIT CMOS EEPROM MODULE FEATURES M@ Read Access Times of 150nS, 200nS @ JEDEC Standard 32 Pin, Hermetic Ceramic DIP {Package 300) @ Full Military and Industrial Temperature Ranges @ MIL-STD-883 Compliant Devices Available @ Write Endurance 10,000 Cycles W@ Data Retention at 25C, 10 Years Low Power CMOS Operation: 1mA Standby Typical/70mA Operating @ Automatic Page Write Operation Interna! Address and Data Latches for 256 Bytes, 1 to 64 Bytes/Row, Four Pages M@ Page Write Cycle Time 10mS Max. @ Data Polling for End of Write Detection M@ Hardware and Software Data Protection @ TTL Compatible Inputs and Outputs 5-3 White Microelectronics * Phoenix, AZ * (602) 437-1520 en1nanw woydaala FeSJINGOW WO0"dd4 en 74 WHITE MICROELECTRONICS WES512K8, WE256K8, WE128K8-XCX ABSOLUTE MAXIMUM RATINGS TRUTH TABLE Parameter Symbal Unit Cs OE WE Mode Data 1/0 Operating Temperature Ta -55 to +125 C H x x Standby High Z Storage Temperature Ts16 -65 to +150 L L H Read Data Out Signal Voltage Any Pin Vo 0.6 to + 6.25 V : 4 L Write ; a In Voltage on OF and AQ 06104135 V H x Out Disable High 2/Data Out - X xX H Write Thermal Resistance uc 28 CW x r X Inhibit junction to case Ani! Lead Temperature +300 C (soldering -10 secs) CAPACITANCE NOTE: (Ta = OV, f = MHz) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional Parameter Sym Condition 512Kx8 256Kx6|128Kx8 Unit operatian of the device at these or any other conditions above those indicated in Max Max | Max the operational sections of this specHieation 1s not implied Exposure to Input Capacitance | Cin [Vin = OV. t= 1MHz] 30 80 45 pf absolute Maximum rating condifians far extended periods may affect device relability Qutput Capacitance} Cour | Vio = OV. f= 1MH2} 30 80 60 pF RECOMMENDED OPERATING CONDITIONS This parameter is guaranteed by design but not tested. Parameler Symbol Min Max Unit Supply Valtage Vec 45 5.5 v Input High Voltage Vin 2.0 Vec + 0.3 Vv Input Low Voltage Vii -0.3 +0.8 V Operating Temp. (Mil.) Ta -55 +125 Cc Operating Temp. (Ind.) Ta -40 +85 DC CHARACTERISTICS (Vcc = 5.0V, Vss = OV, TA = -55C to +125C) Parameter Symbol Conditions 512K x8 256K x B 128K x8 Unit Min | Typ | Max | Min | Typ | Max |Min | Typ | Max Input Leakage Current li Vcc = 5.5, Vin = GND to Voc 10 10 10 pA Output Leakage Current ho CS = Vin, OE = Vin, Vour = GND to Vec 10 10 10 | A Dynamic Supply Current fee CS = Vit, OE = Vin, f = SMHz, Veco = 5.5 80 | 100 60 | 90 50 70 | mA Standby Current Isa CS = Vin, OF = Vin, f = 5MHz, Veco = 55 3 8 2| 6 1 4 | mA Output Low Voltage Vou lo. = 2.1mA, Vcc = 4.5V 0.45 0.45 0.45] V Output High Voltage Vou lox = -400pA, Vcc = 4.5V 2.4 2.4 24 Vv NOTE: OC test conditions: Vii = Vec -0.3V, Vii = 0.3V FIG. 4 AC TEST CONDITIONS AC TEST CIRCUIT J 44 Parameter Typ Unit wine? or Current Source -~ | input Pulse Levels Vi=O0,Vin= 3.0] V | Input Rise and Fall 5 ns a a input and Output Reference Leve! 15 Vv but : S Vy 15M Output Timing Reference Level 15 Vv Coy = 50 pt & ve (Bipolar Supply) NOTES: | Se Vz 1s programmable from -2V to +7V ie aa lac & hus programmable from 0 to 16mA Tester Impedance Z: = 75 Q Vi ts typically the midpoint of Vint and Vii a low It & Ioware adjusted to simulate a typical resistive load circuit Current Source ATE tester includes pq capacitance White Microelectronics * Phoenix, AZ * (602) 437-1520 5-4"A WHITE MICROELECTRONICS WE512K8, WE256K8, WE128K8-XCX Figure 5 shows Read cycle waveforms. A read cycle begins with selection address, chip select and output enable. Chip select is accomplished by placing the CS line law. Output enable is done by placing the OE line !ow. The memory places the selected data byte on |/Oo through |/07 after the access time. The output of the memory is placed in a high impedance state shortly after either the OE line or CS line is returned to a high level. FIG. 5 READ WAVEFORMS ADDRESS es1NANA ANnUial FRE : 7 L Berey be delayed up lo tacs_ OUTPUT _HiGH2 __ f VALID ? a tot after the falling edge of CS without impact on tor or by tarc- tor after an address change without impact on tact AC READ CHARACTERISTICS (SEE FIGURE 5) FOR WE512K8-XCX (Vcc = 5.0V, Vss= OV, Ta= -55C to +125C) Parameter Symbol -150 -200 -250 -300 Unit Min Max Min Max Min Max Min | Max Read Cycle Time tac 150 200 250 300 ns Address Access Time tacc 150 200 250 300 ns Chip Select Access Time tacs 150 200 250 300 ns Output Hold from Address Change, OE or CS ton 0 0 0 0 nS Output Enable to Output Valid toe 85 85 100 125 ns Chip Select or Output Enable to High Z Output tor 70 70 70 70 ns FOR WE256K8-XCX AND WE128K8-XCX Parameter Symbol 150 -200 Unit Min Max Min Max Read Cycle Time trc 150 200 ns Address Access Time tacc 150 200 ns Chip Select Access Time tacs 150 200 ns Output Hold fram Address Change, OE or CS tox 10 10 ng Qutput Enable to Output Vatid tor 85 100 ns Chip Select or Output Enable to High Z Output {oF 70 70 ns 5-5 White Microelectronics Phoenix, AZ * (602) 437-1520STINGOW WOYd34 en Cd WHITE MICROELECTRONICS WE512K8, WE256K8, WE128K8-XCX WRITE Write operations are initiated when both CS and WE are low and OF is high. The EEPROM devices support both a CS and WE controlled write cycle. The address is jatched by the falling edge of either CS or WE, whichever occurs last. The data is latched internally by the rising edge of either CS or WE, whichever occurs first. A byte write operation will automatically continue to completion. WRITE CYCLE TIMING Figures 6 and 7 show the write cycle timing relationships. A write cycle begins with address application, write enable and chip select. Chip select is accomplished by placing the CS line low. Write enable consists of setting the WE line low. The write cycle begins when the last of either CS or WE goes low The WE tine transition from high to low also initiates an internal 150uSec delay timer to permit page mode operation. Each subsequent WE transition from high to low that occurs before the completion of the 150uSec time out will restart the timer from zero. The operation of the timer is the same as a retriggerable one-shot. AC WRITE CHARACTERISTICS (VCC = 5.0V, VSS = OV, TA= -55C to +125C) Parameter Symbol 512K x 8 256K x 8 128K x 8 Unit Min Max Min Max Min Max Write Cycle Time, TYP = 6mS twe 10 10 10 ms Address Set-up Time tas 10 30 30 ns Write Pulse Width (WE or CS) twe 150 150 150 ns Chip Select Set-up Time tcs 0 0 0 | ons Address Hold Time (1) tAH 125 50 50 ns Data Hold Time tDH 10 0 0 ns Chip Select Hold Time tcH 0 0 0 ns Data Set-up Time tos 100 100 100 ns Output Enable Set-up Time toes 10 30 30 ns Output Enable Hold Time TOEH 10 0 0 ns Write Pulse Width High tweH 50 50 50 ns NOTES: _ 1. Avs and Ata must remain vatid through WE and CS low pulse, for 512K x8 Ars, Ati, and Ais must remain valid through WT and CS low pulse, for 256K x 8 Ais and A-s must remain valid through WE and CS low pulse, fot 12BK x 8 White Microelectronics * Phoenix, AZ (602) 437-1520 5-6WHITE MICROELECTRONICS (A WE512K8, WE256K8, WE128K8-XCX FIG. 6 WRITE WAVEFORMS WE CONTROLLED DATA IN NOTE: 1. Decoded Address Lines must be valid for the duration of the write FIG. 7 WRITE WAVEFORMS CS CONTROLLED NOTE: 1. Decoded Address Lines must be valid for the duration of the write + two-> __ yo Y a J h, htt ogg toeH ADDRESS (1) St K xX csHT* | a tas) tan ~ \ WE1-4 Ds. CS1-4 DATAIN - White Microelectronics * Phoenix, AZ * (602) 437-1520 eq1ndnWw WodaSTINGOW WOYd34 i 4 WHITE MICROELECTRONICS WE512K8, WE256K Aas PAS) DATA POLLING Operation with data polling permits a faster method of writing to the EEPROM. The actual time to complete the memory programming cycle is faster than the guaranteed maximum. The EEPROM features a method to determine when the internal programming cycle is completed. After a write cycle is initiated, the EEPROM will respond to read cycles to provide the microprocessor with the status of the programming cycle The status consists of the last data byte written being returned with data bit 1/07 complemented during the programming cycle, and I/Q7 true after completion Data polling allows a simple bit test operation to determine the status of the EEPROM. During the internal programming cycle, a read of the fast byte written will produce the complement of the data on 1/07. For example, if the data written consisted of |/07 = HIGH, then the data read back would consist of I/07 = LOW. A polled byte write sequence would consist of the following steps 1. write byte to EEPROM . store last byte and last address written 2 3. release a time slice to other tasks 4. read byte from EEPROM - last address 5. compare !/Q7 to stored value a) If different, write cycle is not completed, go to step 3. b) If same, write cycle is completed, go to step 1 or step 3. DATA POLLING AC CHARACTERISTICS (Vcc = 5.0V, Vss = DV, Ta= -55C to +125C} ADDRESS OUTPUT. ADDRESS VALID Parameter Symbol 12Kx8 256Kx8 128Kx8 Unit Min Max Min Max Min Max Data Hotd Time tox 10 0 0 ns Output Enable Haid Time toEH 10 0 0 ns Output Enable To Output Delay toe 100 100 100 ns Write Recovery Time twR 0 0 0 ns FIG. 8 DATA POLLING WAVEFORMS - a White Microelectronics * Phoenix, AZ * (602) 437-1520 5-8(74 WHITE MICROELECTRONICS WES512K8, WE256K8, WE128K8-XCX PAGE WRITE OPERATION PAGE MODE CHARACTERISTICS (Vcc = 5.0V, Vss= OV, Ta= -55C to +125C) These devices have a page write operation that allows one to 64 bytes of data (one to 128 bytes for the WE512K8) to be Parameter Symbol | Min | Max | Unit written into the device and then simultaneously written during Write Cycle Time, TYP = 6mS twe 10 | ms the internal programming period. Successive bytes may be Data Set-up Time tos | 100 nS loaded in the same manner after the first data byte has been - loaded. An interna! timer begins a time out operation at each Data Hold Time "0H 10 ns write cycle. If another write cycle is completed within 150us or Write Pulse Width twe__| 150 ns less, a new time out period begins. Each write cycle restarts Byte Load Cycle Time tac 150 |_uS the delay period. The write cycles can be continued as long as Write Pulse Width High tweH_ | 50 ns the interval is less than the time out period The usual procedure is to increment the least significant Device Block Address Page Address address lines from Ao through As (Ao through As for the WE512K8) at each write cycle. In this manner a page of up to WEST 2KB-XCX Avis ArAts 64 bytes (128 bytes for the WE512K8} can be loaded into the WE256K8-XCX AtsAt7 Ag-Ars EEPROM in a burst mode before beginning the relatively long WE128KB-XCX Ars-At6 As-Ais interval programming cycle. After the 150s time out is completed, the EEPROM begins an internal write cycle. During this cycle the entire page of bytes will be written at the same time. The internal programming cycle is the same regardless of the number of bytes accessed. The page address must be the same for each byte load and_ must be valid during each high to low transition of WE (or C5). The block address also must be the same for each byte load and must remain valid throughout the WE (or CS} low pulse. The page and block address lines are summarized below: FIG. 9 PAGE WRITE WAVEFORMS 5E tos ADDRESS (1) Ld VALID ADDRESS VALID DATA DATA pyreo |X BYTES NOTE: 1. Decoded Address Lines must be valid for the duration of the write : 5-9 White Microelectronics * Phoenix, AZ * (602) 437-1520 eq1NNOOW woyvdaiai FESJTNGOW WOYd33 "4 WHITE MICROELECTRONICS WE512K8, WE256K8, WE128K8-XCX FIG. 10 SOFTWARE BLOCK DATA PROTECTION ENABLE ALGORITHM LOAD DATAAA | (1) TO ADDRESS 5555 t LOAD DATA 55 TO ADDRESS 2AAA ! LOAD DATA AO TO ADDRESS 5555 T WRITES ENABLED LOAD DATA XX (2) TO ANY ADORESS LOAD LAST BYTE | (2) TO LAST ADDRESS NOTES: 1 Data Format: Orn (Hex): Address Format: Ara An (Hex) Ar and Ata control selection of one of four blocks in the 512Kx8 Ais, Avi, and Avs control selection of one of 8 pages in the 256Kx8 Aas and Atk control one of the four blocks in the 12BKx8 2. Write Protect state will be activated at end of write even if no other data Is loaded 3 Write Protect state will be deactivated at end of write period even if no other data is loaded 4. 1 {to 128 bytes of data at each of 4 blocks may be loaded in the 517Kx8 1 to 64 bytes of data at each of 8 blocks may be loaded in the 256Kx8 and 1 to 64 bytes on 4 blocks in the 128Kx8 White Microelectronics * Phoenix, AZ * (802) 437-1520 5-104 WHITE MICROELECTRONICS WE512K8, WE256K8, WE128K8-XCX FIG. 11 SOFTWARE BLOCK DATA PROTECTION DISABLE ALGORITHM NOTES: LOAD DATA AA TO ADDRESS 5555 I LOAD DATA 55 T ADDRESS 2AAA I LOAD DATA 80 TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 I LOAD DATA 55 TO ADDRESS 2AAA I LOAD DATA 20 TO ADDRESS 5555 I LOAD DATA XX TO ANY ADDRESS" LOAD LAST BYTE TO LAST ADDRESS 1 Data Format: 1/0v-0 (Hex); Addeess Format. Art -An (Hex) Ai: and Ais control setection of one of four blocks in the 512Kx8 Ais, Ati, and Avs control selection of one af 8 pages in the 756Kx8 Ais and Ais control one of the four blocks i the 128Kx8 2, White Protect state will be activated at end of write even if no other data ts loaded 3) Write Protect state will be deactivated at end of write period even if no other data is loaded 4. 1 to 128 bytes of dala at each of 4 blacks may be loaded in the SV2Kx8. 1 10 64 bytes of data at each of 8 blocks may be loaded in the 256Kx8 and 7 to 64 bytes on 4 blacks in the 128Kx8 SOFTWARE DATA PROTECTION A software write protection feature may be enabled or disabled by the user. When shipped by White Microelectronics, the devices have the feature disabled. Write access to the device is unrestricted To enable software write protection, the user writes three access code bytes te three special internal locations. Once write protection has been enabled, each write to the EEPROM must use the same three byte write sequence to permit writing The write protection feature can be disabled by a six byte write sequence of specific data to specific locations. Power transitions will not reset the software write protection. Each 32K byte block (128K bytes for the WE512K8} of EEPROM has independent write protection. One or more blocks may be enabled and the rest disabled in any combination. The software write protection guards against inadvertent writes during power transitions or unauthorized modification using a PROM programmer. The block selection is controlled by the upper most address lines (A17 through Aig for the WE512K8, At5 through A17 for the WE256K8, or Ais and A16 for the WE128K8). HARDWARE DATA PROTECTION Several methods of hardware data protection have been implemented in the White Microelectronics EEPROM. These are included to improve reliability during normal operations. a) Vcc power on delay As Vcc climbs past 3.8V typical the device will wait 5mSec typical before allowing write cycles. b} Vcc sense While below 3.8V typical write cycles are inhibited. c) Write inhibiting Holding OE low and either CS or WE high inhibits write cycles. d) Noise filter Pulses of <15nS (typ) on WE or CS will not initiate a write cycle. White Microelectronics * Phoenix, AZ * (602) 437-1520 ea1nadnaiuiuanus3s PeSJTNGOIW INOdd3S Ei 4 WHITE MICROELECTRONICS WE512K8, WE256K8, WE128K8-XC ORDERING INFORMATION WE XXXK8-X CX L PROCESSING: Q-= MIL-STD-883 Compliant M= Military Screened -55C to +125C | = Industrial -40C to +85C C = Commercial O0'C to +70C PACKAGE: C = Ceramic DIP (Package 300 for 128Kx8 Package 301 for 256Kx8 and 512Kx8) ACCESS TIME In nS ORGANIZATION, 512Kx8, 256Kx8 or 128KxB8 EEPROM WHITE MICROELECTRONICS SMD REFERENCE De = pe pee a 218 Tm Pa al: 512K x 8 EEPROM 150nS 32 pin DIP WE512K8-150CQ 512K x 8 EEPROM 300nS 32 pin DIP WE512K8-300CQ 512K x 8 EEPROM 250nS 32 pin DIP WE512K8-250CQ 512K x 8 EEPROM 200nS 32 pin DIP WE512K8-200CQ 256K x 8 EEPROM 200nS 32 pin DIP WE256K8-200CQ 256K x 8 EEPROM 150nS 32 pin DIP WE256K8-150CQ 128K x 8 EEPROM 200nS 32 pin DIP WE128K8-200CQ 128K x 8 EEPROM 150nS 32 pin DIP WE128K8-150CQ 5962-93091 01HXX 5962-93091 O2HXX 5962-93091 O3HXX 5962-93091 04HXX 5962-93155 O1HXX 5962-93155 02HXX 5962-93154 O1HXX 5962-93154 O2HXX White Microelectronics Phoenix, AZ (602) 437-1520