5 A, Low VIN, Low Noise, CMOS Linear Regulator ADP1765 Data Sheet TYPICAL APPLICATION CIRCUITS APPLICATIONS Regulation to noise sensitive applications such as radio frequency (RF) transceivers, analog-to-digital converter (ADC) and digital-to-analog converter (DAC) circuits, phase-locked loops (PLLs), voltage controlled oscillators (VCOs) and clocking integrated circuits Field-programmable gate array (FPGA) and digital signal processor (DSP) supplies Medical and healthcare Industrial and instrumentation GENERAL DESCRIPTION The ADP1765 is a low noise, low dropout (LDO) linear regulator. It is designed to operate from a single input supply with an input voltage as low as 1.10 V without the requirement of an external bias supply to increase efficiency and provide up to 5 A of output current (IOUT). The low 59 mV typical dropout voltage at a 5 A load allows the ADP1765 to operate with a small headroom while maintaining regulation and providing better efficiency. The ADP1765 is optimized for stable operation with small 22 F ceramic output capacitors. The ADP1765 delivers optimal transient performance with minimal printed circuit board (PCB) area. Rev. A ADP1765 VIN = 1.8V CIN 22F PG RPULL-UP 100k VIN VOUT COUT 22F SENSE ON EN PG SS CSS 10nF VOUT = 1.5V OFF VADJ VREG REFCAP CREG 1F CREF 1F GND Figure 1. Fixed Output Operation ADP1765 VIN = 1.8V CIN 22F PG RPULL-UP 100k VIN VOUT COUT 22F SENSE ON EN PG SS CSS 10nF VOUT = 1.5V OFF VADJ REFCAP VREG CREG 1F GND CREF 1F RADJ 10k 13933-002 5 A maximum output current Low input voltage supply range VIN = 1.10 V to 1.98 V, no external bias supply required Fixed output voltage range (VOUT_FIXED): 0.55 V to 1.5 V Adjustable output voltage range (VOUT_ADJ): 0.5 V to 1.5 V Ultralow noise: 2 V rms, 100 Hz to 100 kHz Noise spectral density: 5 nV/Hz at 10 kHz; 4 nV/Hz at 100 kHz Low dropout voltage: 59 mV typical at 5 A load Operating supply current: 5 mA typical at no load 1.5% fixed output voltage accuracy over line, load, and temperature Excellent power supply rejection ratio (PSRR) performance 61 dB typical at 10 kHz at 5 A load 43 dB typical at 100 kHz at 5 A load Excellent load/line transient response Soft start to reduce inrush current Optimized for small 22 F ceramic capacitors Current-limit and thermal overload protection Power-good indicator Precision enable 16-lead, 3 mm x 3 mm LFCSP package 13933-001 FEATURES Figure 2. Adjustable Output Operation The ADP1765 is available in fixed output voltages ranging from 0.55 V to 1.5 V. The output voltage (VOUT) of the adjustable output model can be set from 0.5 V to 1.5 V through an external resistor connected between VADJ and ground. The ADP1765 has an externally programmable soft start time by connecting a capacitor to the SS pin. Short-circuit and thermal overload protection circuits prevent damage in adverse conditions. The ADP1765 is available in a small, 16-lead LFCSP package for the smallest footprint solution to meet a variety of applications. Table 1. Related Devices Model ADP1761 ADP1762 ADP1763 ADP1740/ ADP1741 ADP1752/ ADP1753 ADP1754/ ADP1755 Input Voltage 1.10 V to 1.98 V 1.10 V to 1.98 V 1.10 V to 1.98 V 1.6 V to 3.6 V 1.6 V to 3.6 V 1.6 V to 3.6 V Maximum Current 1A 2A 3A 2A 0.8 A 1.2 A Fixed/ Adjustable Fixed/ adjustable Fixed/ adjustable Fixed/ adjustable Fixed/ adjustable Fixed/ adjustable Fixed/ adjustable Package 16-lead LFCSP 16-lead LFCSP 16-lead LFCSP 16-lead LFCSP 16-lead LFCSP 16-lead LFCSP Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. 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ADP1765 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Soft Start Function ..................................................................... 13 Applications ....................................................................................... 1 Adjustable Output Voltage ........................................................ 14 General Description ......................................................................... 1 Enable Feature ............................................................................ 14 Typical Application Circuits............................................................ 1 Power-Good (PG) Feature ........................................................ 14 Revision History ............................................................................... 2 Applications Information .............................................................. 15 Specifications..................................................................................... 3 Capacitor Selection .................................................................... 15 Input and Output Capacitor: Recommended Specifications........ 4 Undervoltage Lockout ............................................................... 16 Absolute Maximum Ratings............................................................ 5 Current-Limit and Thermal Overload Protection ................. 16 Thermal Data ................................................................................ 5 Thermal Resistance/Parameter................................................... 5 Paralleling ADP1765 Devices for High Current Applications ................................................................................ 16 ESD Caution .................................................................................. 5 Thermal Considerations............................................................ 17 Pin Configuration and Function Descriptions ............................. 6 PCB Layout Considerations ...................................................... 19 Typical Performance Characteristics ............................................. 7 Outline Dimensions ....................................................................... 20 Theory of Operation ...................................................................... 13 Ordering Guide .......................................................................... 20 REVISION HISTORY 6/2017--Rev. 0 to Rev. A Changed Thermal Resistance Section to Thermal Resistance/Parameter Section ......................................................... 5 Changes to Thermal Data Section and Table 5 ............................ 5 Changes to Typical Performance Characteristics Section ........... 7 Changes to Thermal Considerations Section, Table 7, Figure 50 through Figure 52, and Figure 50 Caption through Figure 52 Caption ............................................................................................. 17 Changes to Figure 53 through Figure 55, and Figure 53 Caption through Figure 55 Caption ............................................................ 18 1/2017--Revision 0: Initial Version Rev. A | Page 2 of 20 Data Sheet ADP1765 SPECIFICATIONS VIN = VOUT + 0.2 V or VIN = 1.1 V, whichever is greater, IOUT = 100 mA, CIN = 22 F, COUT = 22 F, CREF = 1 F, CREG = 1 F, TA = 25C, minimum and maximum limits at TJ = -40C to +125C, unless otherwise noted. Table 2. Parameter INPUT VOLTAGE SUPPLY RANGE OPERATING SUPPLY CURRENT Symbol VIN IGND SHUTDOWN CURRENT IGND_SD NOISE 1 Output Noise Noise Spectral Density POWER SUPPLY REJECTION RATIO1 OUTNOISE OUTNSD PSRR OUTPUT VOLTAGE RANGE Fixed Adjustable FIXED OUTPUT VOLTAGE ACCURACY VOUT_FIXED VOUT_ADJ VOUT ADJUSTABLE PIN CURRENT IADJ ADJUSTABLE OUTPUT VOLTAGE GAIN FACTOR AD REGULATION Line VOUT/VIN Load 2 DROPOUT VOLTAGE 3 VOUT/IOUT VDROPOUT START-UP TIME1, 4 SOFT START CURRENT CURRENT-LIMIT THRESHOLD1, 5 tSTARTUP IREF ILIMIT Test Conditions/Comments TJ = -40C to +125C IOUT = 0 A IOUT = 100 mA IOUT = 5 A EN = GND TJ = -40C to +85C TJ = 85C to 125C Min 1.10 5 5 12 4 VIN = VOUT + 0.2 V or VIN = 1.1 V, whichever is greater, to 1.98 V IOUT = 100 mA to 5 A IOUT = 4 A, VOUT = 1.2 V IOUT = 5 A, VOUT = 1.2 V CSS = 10 nF, VOUT = 1 V 1.1 V VIN 1.98 V Rev. A | Page 3 of 20 Max 1.98 17 18 25 200 900 10 Hz to 100 kHz, VIN = 1.1 V, VOUT = 0.9 V 100 Hz to 100 kHz, VIN = 1.1 V, VOUT = 0.9 V 10 Hz to 100 kHz, VIN = 1.5 V, VOUT = 1.3 V 100 Hz to 100 kHz, VIN = 1.5 V, VOUT = 1.3 V 10 Hz to 100 kHz, VIN = 1.7 V, VOUT = 1.5 V 100 Hz to 100 kHz, VIN = 1.7 V, VOUT = 1.5 V VOUT = 0.55 V to 1.5 V, IOUT = 100 mA At 10 kHz At 100 kHz IOUT = 5 A, modulated VIN 10 kHz, VOUT = 1.3 V, VIN = 1.7 V 100 kHz, VOUT = 1.3 V, VIN = 1.7 V 1 MHz, VOUT = 1.3 V, VIN = 1.7 V 10 kHz, VOUT = 0.9 V, VIN = 1.3 V 100 kHz, VOUT = 0.9 V, VIN = 1.3 V 1 MHz, VOUT = 0.9 V, VIN = 1.3 V TJ = 25C IOUT = 100 mA, TJ = 25C 100 mA < IOUT < 5 A, TJ = 0C to 85C 100 mA < IOUT < 5 A, TJ = 0C to 125C TJ = 25C, VADJ = 0.5 V VIN = VOUT + 0.2 V or VIN = 1.1 V, whichever is greater to 1.98 V VADJ = 0.5 V; VIN = VOUT+ 0.2 V or VIN = 1.1 V, whichever is greater, to 1.98 V TJ = 25C TJ = -40C to +125C Typ 0.55 0.5 -0.75 -1.3 -1.5 49.5 49.0 Unit V mA mA mA A A A 3 2 3 2 3 2 V rms V rms V rms V rms V rms V rms 5 4 nV/Hz nV/Hz 61 43 33 57 43 33 dB dB dB dB dB dB 50.0 50.0 1.5 1.5 +0.75 +1.3 +1.5 50.7 51.2 V V % % % A A 2.99 2.96 3.02 -0.10 +0.10 %/V 0.3 75 95 %/A mV mV ms A A 8 7.0 0.12 47 59 1 10 8.0 12 8.5 ADP1765 Parameter THERMAL SHUTDOWN1 Threshold Hysteresis POWER-GOOD (PG) OUTPUT Output Voltage Threshold Falling Rising Output Voltage Low Leakage Current Delay PRECISION EN INPUT Logic Input Voltage High Low Input Logic Hysteresis Input Leakage Current Input Delay Time UNDERVOLTAGE LOCKOUT Input Voltage Rising Falling Hysteresis Data Sheet Symbol Test Conditions/Comments TSSD TSSD_HYS TJ rising 152 16 C C PGFALL PGRISE PGLOW IPG_LKG PGDELAY 1.1 V VIN 1.98 V 1.1 V VIN 1.98 V 1.1 V VIN 1.98 V, IPG 1 mA 1.1 V VIN 1.98 V ENRISING to PGRISING 1.1 V VIN 1.98 V -6.2 -3.5 % % V A ms ENHIGH ENLOW ENHYS IEN_LKG tEN_DLY UVLO UVLORISE UVLOFALL UVLOHYS Min 0.01 0.75 0.60 0.55 VEN = VIN or GND From EN rising from 0 V to VIN to 0.1 x VOUT TJ = -40C to +125C TJ = -40C to +125C Typ 0.85 0.65 0.60 50 0.01 100 1.00 0.93 70 Max 0.3 1 0.69 0.65 1 1.06 Unit V V mV A s V V mV Guaranteed by characterization but not production tested. Based on an endpoint calculation using 100 mA and 5 A loads. Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage, which applies only for output voltages above 1.1 V. 4 Start-up time is the time from the rising edge of VEN to VOUT being at 90% of its nominal value. 5 Current-limit threshold is the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 1.0 V, or 0.9 V. 1 2 3 INPUT AND OUTPUT CAPACITOR: RECOMMENDED SPECIFICATIONS Table 3. Parameter CAPACITANCE 1 Input Output Regulator Reference CAPACITOR EQUIVALENT SERIES RESISTANCE (ESR) CIN, COUT CREG CREF 1 Symbol CIN COUT CREG CREF RESR Test Conditions/Comments TA = -40C to +125C Min Typ 14.5 14.5 0.7 0.07 22 22 1 1 Max Unit F F F F TA = -40C to +125C 0.2 0.5 2 The minimum input and output capacitance must be >14.5 F over the full range of the operating conditions. Consider the full range of the operating conditions in the application during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended. Y5V and Z5U capacitors are not recommended for use with any LDO. Rev. A | Page 4 of 20 Data Sheet ADP1765 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter VIN to GND EN to GND VOUT to GND SENSE to GND VREG to GND REFCAP to GND VADJ to GND SS to GND PG to GND Storage Temperature Range Operating Temperature Range Operating Junction Temperature Lead Temperature (Soldering, 10 sec) Rating -0.3 V to +2.16 V -0.3 V to +3.96 V -0.3 V to VIN -0.3 V to VIN -0.3 V to VIN -0.3 V to VIN -0.3 V to VIN -0.3 V to VIN -0.3 V to +3.96 V -65C to +150C -40C to +125C 125C 300C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL DATA Absolute maximum ratings apply individually only, not in combination. The ADP1765 can be damaged when the junction temperature limits are exceeded. The use of appropriate thermal management techniques is recommended to ensure that the maximum junction temperature does not exceed the limits shown in Table 4. characterization parameters are not the same as thermal resistances. JB measures the component power flowing through multiple thermal paths rather than a single path as in thermal resistance, JB. Therefore, JB thermal paths include convection from the top of the package as well as radiation from the package, factors that make JB more useful in real-world applications. THERMAL RESISTANCE/PARAMETER Values shown in Table 5 are calculated in compliance with JEDEC standards for thermal reporting. JA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. JC is the junction to case thermal resistance. JB is the junction to board thermal resistance. JB is the junction to board thermal characterization parameter. JT is the junction to top thermal characterization parameter. In applications where high maximum power dissipation exists, close attention to thermal board design is required. Thermal resistance/parameter values may vary, depending on the PCB material, layout, and environmental conditions. Table 5. Thermal Resistance/Parameter Package Type CP-16-48 1 JA 40.65 JC 7.47 JB 17.38 JB 12.9 JT 0.85 Unit C/W Thermal resistance/parameter simulated values are based on a JEDEC 2S2P thermal test board for JT, JB, JA and JB and a JEDEC 1S0P thermal test board for JC with four thermal vias. See JEDEC JESD51-12. 1 ESD CAUTION Use the following equation to calculate the junction temperature (TJ) from the board temperature (TBOARD) or package top temperature (TTOP) TJ = TBOARD + (PD x JB) TJ = TTOP + (PD x JT) JB is the junction to board thermal characterization parameter and JT is the junction to top thermal characterization parameter with units of C/W. JB of the package is based on modeling and calculation using a 4-layer board. JESD51-12, Guidelines for Reporting and Using Electronic Package Thermal Information, states that thermal Rev. A | Page 5 of 20 ADP1765 Data Sheet 13 SENSE 14 SS 16 EN 15 PG PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VIN 1 VIN 3 12 VOUT ADP1765 TOP VIEW (Not to Scale) 10 VOUT GND 7 VOUT VADJ 8 VREG 6 9 REFCAP 5 VIN 4 11 VOUT NOTES 1. THE EXPOSED PAD IS ELECTRICALLY CONNECTED TO GND. IT IS RECOMMENDED THAT THIS PAD BE CONNECTED TO A GROUND PLANE ON THE PCB. THE EXPOSED PAD IS ON THE BOTTOM OF THE PACKAGE. 13933-003 VIN 2 Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 to 4 Mnemonic VIN 5 REFCAP 6 VREG 7 8 GND VADJ 9 to 12 VOUT 13 SENSE 14 15 SS PG 16 EN EP Description Regulator Input Supply. Bypass VIN to GND with a 22 F or greater capacitor. Note that all four VIN pins must be connected to the source supply. Reference Filter Capacitor. Connect a 1 F capacitor from the REFCAP pin to ground. Do not connect a load from this pin to ground. Regulated Input Supply to LDO Amplifier. Bypass VREG to GND with a 1 F or greater capacitor. Do not connect a load from this pin to ground. Ground. Adjustable Voltage Pin for the Adjustable Output Option. Connect a 10 k external resistor between the VADJ pin and ground to set the output voltage to 1.5 V. For the fixed output option, leave this pin floating. Regulated Output Voltage. Bypass VOUT to GND with a 22 F or greater capacitor. Note that all four VOUT pins must be connected to the load. Sense Input. The SENSE pin measures the actual output voltage at the load and feeds it to the error amplifier. Connect SENSE as close to the load as possible to minimize the effect of IR drop between VOUT and the load. Soft Start Pin. A capacitor connected to this pin determines the soft start time. Power-Good Output. This open-drain output requires an external pull-up resistor. If the device is in shutdown mode, current-limit mode, or thermal shutdown mode, or if the VOUT voltage falls below 90% of the nominal output voltage, the PG pin immediately transitions to low. Enable Input. Drive the EN pin high to turn on the regulator. Drive the EN pin low to turn off the regulator. For automatic startup, connect the EN pin to the VIN pin. Exposed Pad. The exposed pad is electrically connected to GND. It is recommended that this pad be connected to a ground plane on the PCB. The exposed pad is on the bottom of the package. Rev. A | Page 6 of 20 Data Sheet ADP1765 TYPICAL PERFORMANCE CHARACTERISTICS VIN = VOUT + 0.2 V or VIN = 1.1 V, whichever is greater, VOUT = 1.3 V, IOUT = 100 mA, TA = 25C, unless otherwise noted. 24 1.312 ILOAD ILOAD ILOAD ILOAD ILOAD ILOAD 1.310 1.308 1.306 = 0.1A = 1.0A = 2.0A = 3.0A = 4.0A = 5.0A 22 20 18 16 IGND (mA) 1.302 1.300 14 12 10 8 1.298 ILOAD = 0.1A ILOAD = 1.0A ILOAD = 2.0A ILOAD = 3.0A ILOAD = 4.0A ILOAD = 5.0A 6 1.296 4 1.294 2 -20 0 20 40 60 80 100 120 140 TEMPERATURE (C) 13933-004 1.292 -40 0 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (C) Figure 4. Output Voltage (VOUT) vs. Temperature, VOUT = 1.3 V 13933-007 VOUT (V) 1.304 Figure 7. Ground Current (IGND) vs. Temperature, VOUT = 1.3 V 1.304 24 22 1.303 20 1.302 18 16 IGND (mA) VOUT (V) 1.301 1.300 1.299 14 12 10 8 1.298 6 1.297 4 10 0 0.1 10 Figure 8. Ground Current (IGND) vs. Load Current (ILOAD), VOUT = 1.3 V Figure 5. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = 1.3 V 24 1.306 ILOAD ILOAD ILOAD ILOAD ILOAD ILOAD 1.305 1.304 1.303 = 0.1A = 1.0A = 2.0A = 3.0A = 4.0A = 5.0A 22 20 18 ILOAD = 0.1A ILOAD = 1.0A ILOAD = 2.0A ILOAD = 3.0A ILOAD = 4.0A ILOAD = 5.0A 16 IGND (mA) 1.302 1.301 1.300 14 12 10 8 1.299 6 1.298 4 1.297 2 1.58 1.66 1.74 1.82 1.90 1.98 VIN (V) 0 1.5 1.6 1.7 1.8 1.9 2.0 VIN (V) Figure 9. Ground Current (IGND) vs. Input Voltage (VIN), VOUT = 1.3 V Figure 6. Output Voltage (VOUT) vs. Input Voltage (VIN), VOUT = 1.3 V Rev. A | Page 7 of 20 13933-009 1.296 1.50 13933-006 VOUT (V) 1 LOAD CURRENT (A) 13933-008 1 LOAD CURRENT (A) 13933-005 2 1.296 0.1 ADP1765 Data Sheet 0.906 24 0.904 22 20 0.902 18 16 IGND (mA) 0.898 0.896 0.894 0.888 -20 0 20 40 60 80 100 120 2 140 0 -40 60 80 100 120 140 22 18 0.900 16 IGND (mA) 0.899 0.898 0.897 0.896 0.895 14 12 10 8 0.894 6 0.893 4 0.892 1 10 LOAD CURRENT (A) 0 0.1 13933-011 0.890 0.1 1 10 LOAD CURRENT (A) Figure 11. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = 0.9 V 13933-014 2 0.891 Figure 14. Ground Current (IGND) vs. Load Current (ILOAD), VOUT = 0.9 V 0.904 24 ILOAD = 0.1A ILOAD = 1.0A ILOAD = 2.0A ILOAD = 3.0A ILOAD = 4.0A ILOAD = 5.0A 22 20 18 ILOAD = 0.1A ILOAD = 1.0A ILOAD = 2.0A ILOAD = 3.0A ILOAD = 4.0A ILOAD = 5.0A 16 IGND (mA) 0.899 0.898 0.897 0.896 0.895 14 12 10 8 0.894 6 0.893 4 0.892 2 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 VIN (V) 13933-012 0.891 Figure 12. Output Voltage (VOUT) vs. Input Voltage (VIN), VOUT = 0.9 V 0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 VIN (V) Figure 15. Ground Current (IGND) vs. Input Voltage (VIN), VOUT = 0.9 V Rev. A | Page 8 of 20 13933-015 VOUT (V) 40 20 0.901 VOUT (V) 20 24 0.902 0.890 1.1 0 Figure 13. Ground Current (IGND) vs. Temperature, VOUT = 0.9 V 0.903 0.900 -20 TEMPERATURE (C) 0.904 0.901 ILOAD = 0.1A ILOAD = 1.0A ILOAD = 2.0A ILOAD = 3.0A ILOAD = 4.0A ILOAD = 5.0A 4 Figure 10. Output Voltage (VOUT) vs. Temperature, VOUT = 0.9 V 0.902 10 6 TEMPERATURE (C) 0.903 12 13933-013 ILOAD = 0.1A ILOAD = 1.0A ILOAD = 2.0A ILOAD = 3.0A ILOAD = 4.0A ILOAD = 5.0A 0.890 0.886 -40 14 8 0.892 13933-010 VOUT (V) 0.900 Data Sheet ADP1765 24 1000 100 VIN = 1.10V VIN = 1.30V VIN = 1.50V VIN = 1.70V VIN = 1.90V VIN = 1.98V ILOAD = 0.1A ILOAD = 1.0A ILOAD = 2.0A ILOAD = 3.0A ILOAD = 4.0A ILOAD = 5.0A 22 20 18 14 IGND (mA) IGND_SD (A) 16 10 1 12 10 8 6 0.1 4 13933-016 0 1.1 TEMPERATURE (C) 1.2 1.3 1.5 1.4 VIN (V) 13933-019 2 0.01 Figure 19. Ground Current (IGND) vs. Input Voltage (VIN) in Dropout, VOUT = 1.3 V Figure 16. Shutdown Current (IGND_SD) vs. Temperature at Various Input Voltages (VIN), VOUT = 0.9 V 0.10 T 0.09 SLEW RATE = 5A/s 0.08 IOUT VDROPOUT (V) 0.07 3 0.06 0.05 VOUT 0.04 1 0.03 0.02 1 10 LOAD CURRENT (A) Figure 17. Dropout Voltage (VDROPOUT) vs. Load Current (ILOAD), VOUT = 1.3 V B W B W CH1 50mV CH3 2A 5GSPS 4.00s CH3 1M POINTS T 11.04000s 2.44A 13933-020 0 0.1 13933-017 0.01 Figure 20. Load Transient Response, COUT = 22 F, VIN = 1.8 V, VOUT = 1.3 V 1.32 T 1.31 SLEW RATE = 5A/s 1.30 1.29 IOUT 3 1.27 1.26 VOUT 1.25 1 1.24 1.22 1.21 1.20 1.25 1.30 1.35 1.40 1.45 = 0.1A = 1.0A = 2.0A = 3.0A = 4.0A = 5.0A 1.50 VIN (V) Figure 18. Output Voltage (VOUT) vs. Input Voltage (VIN) in Dropout, VOUT = 1.3 V CH1 50mV CH3 2A B W B W 5GSPS 4.00s CH3 1M POINTS T 11.36000s 2.44A 13933-021 ILOAD ILOAD ILOAD ILOAD ILOAD ILOAD 1.23 13933-018 VOUT (V) 1.28 Figure 21. Load Transient Response, COUT = 47 F, VIN = 1.8 V, VOUT = 1.3 V Rev. A | Page 9 of 20 ADP1765 Data Sheet T T SLEW RATE = 4.5A/s VIN IOUT 3 VOUT 1 2 VOUT CH3 5GSPSs 4.00s 1M POINTS T 11.24000s 2.48A CH1 2mV CH2 500mV B W B W CH2 5GSPS 4.00s 1M POINTS T 9.020000s 1.53V 13933-025 B W B W CH1 50mV CH3 2A 13933-022 1 Figure 25. Line Transient Response, Load Current = 5 A, VIN = 1.3 V to 1.7 V Step, VOUT = 0.9 V Figure 22. Load Transient Response, COUT = 22 F, VIN = 1.4 V, VOUT = 0.9 V 4.0 T 10Hz TO 100kHz 100Hz TO 100kHz 3.5 OUTPUT NOISE (V rms) SLEW RATE = 4.5A/s IOUT 3 VOUT 1 3.0 2.5 2.0 1.5 1.0 B W B W 5GSPS 4.00s CH3 1M POINTS T 11.32000s 2.48A 0 0.1 1 10 LOAD CURRENT (A) Figure 23. Load Transient Response, COUT = 47 F, VIN = 1.4 V, VOUT = 0.9 V 13933-026 CH1 50mV CH3 2A 13933-023 0.5 Figure 26. Output Noise vs. Load Current (ILOAD) 4.0 T 10Hz TO 100kHz 100Hz TO 100kHz 3.5 OUTPUT NOISE (V rms) VIN 2 VOUT 1 3.0 2.5 2.0 1.5 1.0 B W 5GSPS B W 1M POINTS 4.00s CH2 T 9.020000s 1.86V 0 0.5 0.7 0.9 1.1 1.3 OUTPUT VOLTAGE (V) Figure 24. Line Transient Response, Load Current = 5 A, VIN = 1.6 V to 1.98 V Step, VOUT = 1.3 V Figure 27. Output Noise vs. Output Voltage (VOUT) Rev. A | Page 10 of 20 1.5 13933-027 CH1 2mV CH2 500mV 13933-024 0.5 Data Sheet ADP1765 1k 1k 100 10 1 0.1 0.1 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) ILOAD = 0.1A ILOAD = 1.0A ILOAD = 3.0A ILOAD = 4.0A ILOAD = 5.0A 100 10 1 0.1 10 10k 100k 1M 10M Figure 31. Noise Spectral Density vs. Frequency at Various Load Current (IOUT), 10 Hz to 10 MHz -10 1k VOUT = 0.5V VOUT = 0.9V VOUT = 1.3V VOUT = 1.5V -20 -30 100 PSRR (dB) -40 10 -50 -60 -70 -80 VIN = 1.5V VIN = 1.6V VIN = 1.7V VIN = 1.8V VIN = 1.9V -90 -100 100 1k 10k 100k 1M 10M FREQUENCY (Hz) -110 1 10 100 1k 10k 100k 10M Figure 32. Power Supply Rejection Ratio (PSRR) vs. Frequency at Various Input Voltages (VIN), VOUT = 1.3 V, Load = 5 A Figure 29. Noise Spectral Density vs. Frequency at Various Output Voltages (VOUT), 10 Hz to 10 MHz -10 100k ILOAD ILOAD ILOAD ILOAD ILOAD 10k = 0.1A = 1.0A = 3.0A = 4.0A = 5.0A -20 -30 -40 PSRR (dB) 1k 100 10 -50 -60 -70 -80 ILOAD = 0.1A ILOAD = 1.0A ILOAD = 2.0A ILOAD = 3.0A ILOAD = 4.0A ILOAD = 5.0A -90 1 1 10 100 1k 10k 100k FREQUENCY (Hz) 1M 13933-030 -100 0.1 0.1 1M FREQUENCY (Hz) -110 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 33. Power Supply Rejection Ratio (PSRR) vs. Frequency at Various Loads (ILOAD), VOUT = 1.3 V, VIN = 1.7 V Figure 30. Noise Spectral Density vs. Frequency at Various Load Current (IOUT), 0.1 Hz to 1 MHz Rev. A | Page 11 of 20 13933-033 0.1 10 13933-032 1 13933-029 NOISE SPECTRAL DENSITY (nV/Hz) 1k FREQUENCY (Hz) Figure 28. Noise Spectral Density vs. Frequency at Various Output Voltages (VOUT), 0.1 Hz to 1 MHz NOISE SPECTRAL DENSITY (nV/Hz) 100 13933-031 10k NOISE SPECTRAL DENSITY (nV/Hz) VOUT = 0.5V VOUT = 0.9V VOUT = 1.3V VOUT = 1.5V 13933-028 NOISE SPECTRAL DENSITY (nV/Hz) 100k Data Sheet -10 0 -20 -10 -30 -20 -40 -30 -50 -40 -60 -70 -60 -70 -80 VIN = 1.1V VIN = 1.2V VIN = 1.3V VIN = 1.4V VIN = 1.5V -90 -110 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) -100 0.2 Figure 34. Power Supply Rejection Ratio (PSRR) vs. Frequency at Various Input Voltages (VIN), VOUT = 0.9 V, Load = 5 A -30 -20 -40 -30 -50 -40 PSRR (dB) 0 -10 -60 -70 -100 10 100 1k 10k 100k 1M 0.6 -50 -60 -80 -90 -110 1 0.5 -70 = 0.1A = 1.0A = 2.0A = 3.0A = 4.0A = 5.0A 10M FREQUENCY (Hz) Figure 35. Power Supply Rejection Ratio (PSRR) vs. Frequency at Various Loads (ILOAD), VOUT = 0.9 V, VIN = 1.3 V 13933-035 ILOAD ILOAD ILOAD ILOAD ILOAD ILOAD 0.4 Figure 36. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage at Various Frequencies, VOUT = 0.9 V, Load = 5 A -20 -90 0.3 HEADROOM (V) -10 -80 FREQUENCY = 10Hz FREQUENCY = 100Hz FREQUENCY = 1kHz FREQUENCY = 10kHz FREQUENCY = 100kHz FREQUENCY = 1MHz FREQUENCY = 10MHz -100 0.2 FREQUENCY = FREQUENCY = FREQUENCY = FREQUENCY = 0.3 10Hz 100Hz 1kHz 10kHz FREQUENCY = 100kHz FREQUENCY = 1MHz FREQUENCY = 10MHz 0.4 HEADROOM (V) 0.5 0.6 13933-037 -100 -80 13933-034 -90 PSRR (dB) -50 13933-036 PSRR (dB) PSRR (dB) ADP1765 Figure 37. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage at Various Frequencies, VOUT = 1.3 V, Load = 5 A Rev. A | Page 12 of 20 Data Sheet ADP1765 THEORY OF OPERATION The ADP1765 is a low dropout (LDO), low noise linear regulator that uses an advanced proprietary architecture to achieve high efficiency regulation. It also provides high PSRR and excellent line and load transient response using a small 22 F ceramic output capacitor. The device operates from a 1.10 V to 1.98 V input rail to provide up to 5 A of output current. The supply current in shutdown mode is less than 4 A. ADP1765 tSTARTUP_ADJ = tDELAY + VADJ x (CSS/ISS) PG REFERENCE, BIAS GND SENSE For applications that require a controlled startup, the ADP1765 provides a programmable soft start function. The programmable soft start is useful for reducing inrush current upon startup and for providing voltage sequencing. To implement soft start, connect a small ceramic capacitor from SS to GND. At startup, a 10 A current source charges this capacitor. The voltage at SS limits the ADP1765 start-up output voltage, providing a smooth ramp up to the nominal output voltage. To calculate the start-up time for the fixed output (tSTARTUP_FIXED) and adjustable (tSTARTUP_ADJ) output, use the following equations: tSTARTUP_FIXED = tDELAY + VREF x (CSS/ISS) (1) SS BLOCK SS REFCAP Figure 38. Functional Block Diagram, Fixed Output where: tDELAY is a fixed delay of 100 s. VREF is a 0.5 V internal reference for the fixed output model option. CSS is the soft start capacitance from SS to GND. ISS is the current sourced from SS (10 A). VADJ is the voltage at the VADJ pin, equal to RADJ x IADJ. ADP1765 VOUT VIN VREG INTERNAL BIAS SUPPLY SHORT-CIRCUIT, THERMAL PROTECTION SENSE VOUT (V) IADJ EN VADJ 3x PG SS BLOCK SS REFCAP 13933-039 GND The ADP1765 is available in output voltages ranging from 0.55 V to 1.5 V for a fixed output. Contact your local Analog Devices, Inc., sales representative for other fixed voltage options. The adjustable output option can be set from 0.5 V to 1.5 V. The ADP1765 uses the EN pin to enable and disable the VOUT pin under normal 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -1.0 EN CSS = 0nF CSS = 10nF CSS = 22nF -0.5 0 0.5 1.0 1.5 2.0 2.5 TIME (ms) Figure 40. Fixed VOUT Ramp-Up with External Soft Start Capacitor (VOUT, EN) vs. Time VOUT (V) Figure 39. Functional Block Diagram, Adjustable Output Internally, the ADP1765 consists of a reference, an error amplifier, and a pass device. The output current is delivered via the pass device, which is controlled by the error amplifier, forming a negative feedback system that ideally drives the feedback voltage to equal the reference voltage. If the feedback voltage is lower than the reference voltage, the negative feedback drives more current, increasing the output voltage. If the feedback voltage is higher than the reference voltage, the negative feedback drives less current, decreasing the output voltage. (2) 13933-040 EN SHORT-CIRCUIT, THERMAL PROTECTION 13933-038 VREG VOUT INTERNAL BIAS SUPPLY SOFT START FUNCTION 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -1.0 EN VOUT VOUT VOUT VOUT VOUT VOUT -0.5 0 0.5 1.0 TIME (ms) = = = = = = 1.5 0.5V; 0.5V; 0.5V; 1.5V; 1.5V; 1.5V; CSS CSS CSS CSS CSS CSS 2.0 = = = = = = 0nF 10nF 22nF 0nF 10nF 22nF 2.5 13933-041 VIN operating conditions. When EN is high, VOUT turns on. When EN is low, VOUT turns off. For automatic startup, tie EN to VIN. Figure 41. Adjustable VOUT Ramp-Up with External Soft Start Capacitor (VOUT, EN) vs. Time Rev. A | Page 13 of 20 ADP1765 Data Sheet ADJUSTABLE OUTPUT VOLTAGE POWER-GOOD (PG) FEATURE The output voltage of the ADP1765 can be set over a 0.5 V to 1.5 V range. Connect a resistor (RADJ) from the VADJ pin to ground to set the output voltage. To calculate the output voltage (VOUT), use the following equation: The ADP1765 provides a power-good pin (PG) to indicate the status of the output. This open-drain output requires an external pull-up resistor that can be connected to VIN or VOUT. If the device is in shutdown mode, current-limit mode, or thermal shutdown, or if it falls below 90% of the nominal output voltage, PG immediately transitions low. During soft start, the rising threshold of the power-good signal is 96.5% of the nominal output voltage. VOUT = AD x (RADJ x IADJ) (3) where: AD is the gain factor with a typical value of 2.99 between the VADJ pin and VOUT pin. IADJ is the 50 A constant current out of the VADJ pin. ENABLE FEATURE The ADP1765 uses the EN pin to enable and disable the VOUT pins under normal operating conditions. As shown in Figure 42, when a rising voltage on EN crosses the active threshold, VOUT turns on. When a falling voltage on EN crosses the inactive threshold, VOUT turns off. T The open-drain output is held low when the ADP1765 has sufficient input voltage to turn on the internal PG transistor. An optional soft start delay can be detected. The PG transistor is terminated via a pull-up resistor to VIN or VOUT. Power-good accuracy is 93.8% of the nominal regulator output voltage when this voltage is rising, with a 96.5% trip point when this voltage is falling. Regulator input voltage brownouts or glitches trigger a power no good if VOUT falls below 93.8%. A normal power-down triggers a power good when VOUT is at 96.5%. VOUT T EN EN 1 VOUT 2 1 100kSPS 10.00ms CH1 10k POINTS T 121.9200ms 1.21V PG Figure 42. Typical EN Pin Operation 2 As shown in Figure 43, the EN pin has built in hysteresis. This hysteresis prevents on/off oscillations that can occur due to noise on the EN pin as it passes through the threshold points. 1.4 CH1 1V CH3 1V 5.00MSPS 200s CH2 10k POINTS T CH2 1V -70.00000s 1.30V 13933-044 CH1 200mV CH2 200mV 13933-042 3 Figure 44. Typical PG Voltage Behavior vs. VOUT, VIN Rising (VOUT = 1.3 V) 1.3 T 1.2 EN 1.1 1.0 1 0.8 VOUT 0.7 0.6 0.5 3 PG 0.4 TA = +125C TA = +85C TA = +25C TA = 0C TA = -40C 0.2 0.1 0 0.59 0.60 0.61 0.62 0.63 2 0.64 0.65 0.66 EN THRESHOLD (V) Figure 43. Output Voltage (VOUT) vs. EN Threshold, VOUT = 1.3 V CH1 1V BW CH2 1V BW CH3 1V BW 200s 500MSPS 1M POINTS T CH2 700mV -5.20000s 13933-045 0.3 13933-043 VOUT (V) 0.9 Figure 45. Typical PG Voltage Behavior vs. VOUT, VIN Falling (VOUT = 1.3 V) Rev. A | Page 14 of 20 Data Sheet ADP1765 APPLICATIONS INFORMATION CAPACITOR SELECTION Input and Output Capacitor Properties Output Capacitor Use any good quality ceramic capacitors with the ADP1765 as long as they meet the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are recommended. Y5V and Z5U dielectrics are not recommended, due to their poor temperature and dc bias characteristics. The ADP1765 is designed for operation with small, space-saving ceramic capacitors, but it can function with most commonly used capacitors as long as care is taken with the effective series resistance (ESR) value. The ESR of the output capacitor affects the stability of the LDO control loop. A minimum of 22 F capacitance with an ESR of 50 m or less is recommended to ensure the stability of the ADP1765. Transient response to changes in load current is also affected by output capacitance. Using a larger value of output capacitance improves the transient response of the ADP1765 to large changes in load current. Figure 46 and Figure 47 show the transient responses for output capacitance values of 22 F and 47 F, respectively. T SLEW RATE = 5A/s IOUT 3 Figure 48 shows the capacitance vs. dc bias voltage characteristics of a C2012X5R1A226K125AB, 0805 case, 22 F, 10 V, X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. In general, a capacitor in a larger package or with a higher voltage rating exhibits improved stability. The temperature variation of the X5R dielectric is about 15% over the -55C to +85C temperature range and is not a function of package size or voltage rating. 25 VOUT 5GSPS 4.00s CH3 1M POINTS T 11.04000s 2.44A 13933-046 B W B W CH1 50mV CH3 2A CAPACITANCE, NOMINAL (F) 1 Figure 46. Output Transient Response, COUT = 22 F, VOUT = 1.3 V 20 15 10 5 SLEW RATE = 5A/s 0 0 2 4 6 8 DC BIAS VOLTAGE (V) IOUT 3 10 13933-048 T Figure 48. Capacitance vs. DC Bias Voltage Use Equation 4 to determine the worst-case capacitance, accounting for capacitor variation over temperature, component tolerance, and voltage. VOUT 1 CEFF = COUT x (1 - TEMPCO) x (1 - TOL) B W B W 5GSPS 4.00s CH3 1M POINTS T 11.36000s 2.44A where: CEFF is the effective capacitance at the operating voltage. COUT is the output capacitor. TEMPCO is the worst case capacitor temperature coefficient. TOL is the worst case component tolerance. 13933-047 CH1 50mV CH3 2A (4) Figure 47. Output Transient Response, COUT = 47 F, VOUT = 1.3 V Input Bypass Capacitor Connecting a 22 F capacitor from the VIN pin to the GND pin to the ground plane reduces the circuit sensitivity to the PCB layout, especially when long input traces or high source impedances are encountered. If an output capacitance greater than 22 F is required, it is recommended to increase the input capacitor to match it. In this example, the worst case temperature coefficient (TEMPCO) over -55C to +125C is assumed to be 15% for an X5R dielectric. The tolerance of the capacitor (TOL) is assumed to be 10%, and COUT = 19.48 F at 1.0 V, as shown in Figure 48. Substituting these values in Equation 4 yields Rev. A | Page 15 of 20 CEFF = 19.48 F x (1 - 0.15) x (1 - 0.1) = 14.9 F ADP1765 Data Sheet output and reducing the output current to zero. As the junction temperature cools and drops below 136C, the output turns on and conducts 8.0 A into the short, again causing the junction temperature to rise above 152C. This thermal oscillation between 136C and 152C causes a current oscillation between 8.0 A and 0 A that continues as long as the short remains at the output. Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage. To guarantee the performance of the ADP1765, it is imperative to evaluate the effects of dc bias, temperature, and tolerances on the behavior of the capacitors for each application. Current-limit and thermal overload protections are intended to protect the device against accidental overload conditions. For reliable operation, device power dissipation must be externally limited so that junction temperatures do not exceed 125C. UNDERVOLTAGE LOCKOUT The ADP1765 has an internal undervoltage lockout (UVLO) circuit that disables all inputs and the output when the input voltage is less than approximately 1.06 V. The UVLO ensures that the ADP1765 inputs and output behave in a predictable manner during power-up. PARALLELING ADP1765 DEVICES FOR HIGH CURRENT APPLICATIONS In applications where high output current is required while maintaining low noise and high PSRR performance, connect two ADP1765 devices in parallel to handle loads up to 9 A. CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION The ADP1765 is protected against damage due to excessive power dissipation by current-limit and thermal overload protection circuits. The ADP1765 is designed to reach the current limit when the output load reaches 8.0 A (typical). When the output load exceeds 8.0 A, the output voltage is reduced to maintain a constant current limit. When paralleling theADP1765, the two outputs must be of the same voltage setting to maintain good current sharing between the two LDOs. To improve current sharing accuracy, add identical ballast resistors (RBALLAST) at the output of each regulator, as shown in Figure 49. Note that large ballast resistors improve current sharing accuracy, but degrade the load regulation performance and increase the losses along the power line. Therefore, it is best to keep the ballast resistors at a minimum. In addition, tie the VADJ, SS, and REFCAP pins of the LDO regulators together to minimize error between the two outputs. Thermal overload protection is included that limits the junction temperature to a maximum of 152C (typical). Under extreme conditions (that is, high ambient temperature and power dissipation) when the junction temperature begins to rise above 152C, the output turns off, reducing the output current to zero. When the junction temperature drops below 136C (typical), the output turns on again, and the output current is restored to its nominal value. Use Equation 5 to calculate the output of the two paralleled ADP1765 LDOs. VOUT = 2 xAD x (RADJ x IADJ) Consider the case where a hard short from VOUT to ground occurs. At first, the ADP1765 reaches the current limit so that only 8.0 A is conducted into the short. If self-heating of the junction becomes great enough to cause its temperature to rise above 152C, thermal shutdown activates, turning off the where: AD is the gain factor with a typical value of 2.99 between the VADJ pin and VOUT pin. IADJ is the 50 A constant current out of the VADJ pin. ADP1765 VIN = 1.5V CIN 22F VIN RBALLAST = 5m VOUT SENSE RPULLUP 100k VOUT = 1.2V/9A COUT 22F ENABLE EN PG SS CSS 1nF VADJ VREG CREG 1F CREF 1F GND ADP1765 CIN 22F RADJ 4.02k REFCAP VIN RBALLAST = 5m VOUT COUT 22F SENSE EN PG SS VADJ REFCAP GND CREF 1F 13933-049 VREG CREG 1F Figure 49. Two ADP1765 Devices Connected in Parallel to Achieve Higher Current Output Rev. A | Page 16 of 20 (5) Data Sheet ADP1765 To guarantee reliable operation, the junction temperature of the ADP1765 must not exceed 125C. To ensure that the junction temperature stays below this maximum value, the user must be aware of the parameters that contribute to junction temperature changes. These parameters include board temperature, power dissipation in the power device, and thermal characterization parameter between the junction and board (JB). The JB parameter is dependent on the package assembly compounds and the PCB copper area. Table 7 shows the typical JB values for the 16-lead LFCSP package for various PCB copper areas. Table 7. Typical non-JEDEC JB Values JB (C/W) at 2W 71.05 18.9 13.45 13.15 TJ MAX 120 40 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VIN - VOUT (V) Figure 50. 1000 mm2 of PCB Copper, TB = 25C 140 TJ MAX 120 0.1A 1.0A 2.0A 3.0A 4.0A 5.0A 100 80 60 40 (6) 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VIN - VOUT (V) 13933-051 20 Figure 51. 500 mm2 of PCB Copper, TB = 25C 140 TJ MAX (7) Power dissipation due to ground current is quite small and can be ignored. Therefore, the junction temperature equation simplifies to (8) 120 JUNCTION TEMPERATURE (C) where: VIN and VOUT are the input and output voltages, respectively. ILOAD is the load current. IGND is the ground current. TJ = TB + (((VIN - VOUT) x ILOAD) x JB) 60 0 where: TB is the board temperature. PD is the power dissipation in the die, given by PD = ((VIN - VOUT) x ILOAD) + (VIN x IGND) 80 20 Calculate the junction temperatures of the ADP1765 by TJ = TB + (PD x JB) 0.1A 1.0A 2.0A 3.0A 4.0A 5.0A 100 0.1A 1.0A 2.0A 3.0A 4.0A 5.0A 100 80 60 40 20 0 0 0.2 0.4 0.6 0.8 1.0 1.2 VIN - VOUT (V) Figure 52. 100 mm2 of PCB Copper, TB= 25C Rev. A | Page 17 of 20 1.4 13933-052 PCB Copper Area (mm2) 25 100 500 1000 140 13933-050 When the junction temperature exceeds 152C, the regulator enters thermal shutdown. The regulator recovers only after the junction temperature decreases below 136C to prevent any permanent damage. Therefore, thermal analysis for the chosen application is important to guarantee reliable performance over all conditions. The junction temperature of the die is the sum of the board temperature and the temperature rise of the package due to the power dissipation, as shown in Equation 6. Figure 50 to Figure 55 show the junction temperature calculations for the different board temperatures, power dissipation, and areas of the PCB copper. JUNCTION TEMPERATURE (C) In applications with a low input-to-output voltage differential, the ADP1765 does not dissipate much heat. However, in applications with high ambient temperature and/or high input voltage, the heat dissipated in the package may become large enough to cause the junction temperature of the die to exceed the maximum junction temperature of 125C. As shown in Equation 8, for a given board temperature, inputto-output voltage differential and continuous load current, a minimum copper area requirement exists for the PCB to ensure that the junction temperature does not rise above 125C. JUNCTION TEMPERATURE (C) THERMAL CONSIDERATIONS ADP1765 Data Sheet 140 140 TJ MAX TJ MAX 120 JUNCTION TEMPERATURE (C) 0.1A 1.0A 2.0A 3.0A 4.0A 5.0A 100 80 60 40 0.1A 1.0A 2.0A 3.0A 4.0A 5.0A 100 80 60 40 20 20 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VIN - VOUT (V) 0 13933-053 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VIN - VOUT (V) Figure 53. 1000 mm2 of PCB Copper, TB = 50C 13933-055 JUNCTION TEMPERATURE (C) 120 Figure 55. 100 mm2 of PCB Copper, TB = 50C 140 TJ MAX 0.1A 1.0A 2.0A 3.0A 4.0A 5.0A 100 80 TADP1765 = 115.3C 60 40 TB = 93.3C 0 0 0.2 0.4 0.6 0.8 1.0 1.2 VIN - VOUT (V) Figure 54. 500 mm2 of PCB Copper, TB = 50C 1.4 13933-056 20 13933-054 JUNCTION TEMPERATURE (C) 120 Figure 56. Thermal Image of the ADP1765 Evaluation Board at ILOAD = 5 A, VIN = 1.5 V, VOUT = 1.3 V, TB = 93.3C Figure 56 shows a thermal image of the ADP1765 evaluation board operating at a 5 A current load. The total power dissipation on the ADP1765 is 933 mW, which makes the temperature on the surface of the device higher by 22C than the temperature of the evaluation board. Rev. A | Page 18 of 20 Data Sheet ADP1765 PCB LAYOUT CONSIDERATIONS 13933-058 Place the input capacitor as close as possible to the VIN and GND pins. Place the output capacitor as close as possible to the VOUT and GND pins. Place the soft start capacitor (CSS) as close as possible to the SS pin. Place the reference capacitor (CREF) and regulator capacitor (CREG) as close as possible to the REFCAP pin and VREG pin, respectively. Connect the load as close as possible to the VOUT and SENSE pins. 13933-057 Figure 58. Typical Board Layout, Top Side 13933-059 Figure 57. Evaluation Board Figure 59. Typical Board Layout, Bottom Side Rev. A | Page 19 of 20 ADP1765 Data Sheet OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 3.10 3.00 SQ 2.90 0.50 BSC 13 PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 16 1 12 1.80 1.70 SQ 1.60 EXPOSED PAD 9 *0.40 TOP VIEW 0.80 0.75 0.70 4 5 8 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF PKG-005014 SEATING PLANE 0.20 MIN BOTTOM VIEW 0.35 0.30 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. *COMPLIANT TO JEDEC STANDARDS MO-220-WEED-4 WITH EXCEPTION TO LEAD LENGHT. 10-04-2016-A PIN 1 INDICATOR 0.28 0.23 0.18 Figure 60. 16-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm x 3 mm Body and 0.75 mm Package Height (CP-16-48) Dimensions shown in millimeters ORDERING GUIDE Model 1, 2 ADP1765ACPZ0.85-R7 ADP1765ACPZ-0.9-R7 ADP1765ACPZ0.95-R7 ADP1765ACPZ-1.0-R7 ADP1765ACPZ-1.1-R7 ADP1765ACPZ-1.2-R7 ADP1765ACPZ1.25-R7 ADP1765ACPZ-1.3-R7 ADP1765ACPZ-1.5-R7 ADP1765ACPZ-R7 ADP1765-1.0-EVALZ ADP1765-ADJ-EVALZ 1 2 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Output Voltage (V) 0.85 0.9 0.95 1.0 1.1 1.2 1.25 1.3 1.5 Adjustable 1.0 1.0 Package Description 16-Lead LFCSP 16-Lead LFCSP 16-Lead LFCSP 16-Lead LFCSP 16-Lead LFCSP 16-Lead LFCSP 16-Lead LFCSP 16-Lead LFCSP 16-Lead LFCSP 16-Lead LFCSP Evaluation Board (Fixed) Evaluation Board (Adjustable) Package Option CP-16-48 CP-16-48 CP-16-48 CP-16-48 CP-16-48 CP-16-48 CP-16-48 CP-16-48 CP-16-48 CP-16-48 Branding LUA LUB LUM LUD LUE LUF LUR LUG LUJ LUK Z = RoHS Compliant Part. For additional voltage options, contact a local Analog Devices sales or distribution representative. Additional voltage options are available by special order and include the following: 0.55 V, 0.6 V, 0.65 V, 0.7 V, 0.75 V, 0.8 V, 1.05 V, 1.15 V, 1.35 V, 1.4 V, and 1.45 V. (c)2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D13933-0-6/17(A) Rev. A | Page 20 of 20