5 A, Low VIN, Low Noise,
CMOS Linear Regulator
Data Sheet
ADP1765
Rev. A Document Feedback
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FEATURES
5 A maximum output current
Low input voltage supply range
VIN = 1.10 V to 1.98 V, no external bias supply required
Fixed output voltage range (VOUT_FIXED): 0.55 V to 1.5 V
Adjustable output voltage range (VOUT_ADJ): 0.5 V to 1.5 V
Ultralow noise: 2 µV rms, 100 Hz to 100 kHz
Noise spectral density: 5 nV/√Hz at 10 kHz; 4 nV/√Hz at 100 kHz
Low dropout voltage: 59 mV typical at 5 A load
Operating supply current: 5 mA typical at no load
±1.5% fixed output voltage accuracy over line, load, and
temperature
Excellent power supply rejection ratio (PSRR) performance
61 dB typical at 10 kHz at 5 A load
43 dB typical at 100 kHz at 5 A load
Excellent load/line transient response
Soft start to reduce inrush current
Optimized for small 22 µF ceramic capacitors
Current-limit and thermal overload protection
Power-good indicator
Precision enable
16-lead, 3 mm × 3 mm LFCSP package
APPLICATIONS
Regulation to noise sensitive applications such as radio
frequency (RF) transceivers, analog-to-digital converter
(ADC) and digital-to-analog converter (DAC) circuits,
phase-locked loops (PLLs), voltage controlled oscillators
(VCOs) and clocking integrated circuits
Field-programmable gate array (FPGA) and digital signal
processor (DSP) supplies
Medical and healthcare
Industrial and instrumentation
GENERAL DESCRIPTION
The ADP1765 is a low noise, low dropout (LDO) linear
regulator. It is designed to operate from a single input supply
with an input voltage as low as 1.10 V without the requirement
of an external bias supply to increase efficiency and provide up
to 5 A of output current (IOUT).
The low 59 mV typical dropout voltage at a 5 A load allows the
ADP1765 to operate with a small headroom while maintaining
regulation and providing better efficiency.
The ADP1765 is optimized for stable operation with small 22 µF
ceramic output capacitors. The ADP1765 delivers optimal transient
performance with minimal printed circuit board (PCB) area.
TYPICAL APPLICATION CIRCUITS
VIN
EN
SS
VREG
VOUT
SENSE
C
OUT
22µF
PG
R
PULL-UP
100kΩ PG
VADJ
GNDREFCAP
C
IN
22µF
ON
OFF
V
OUT
= 1.5V
ADP1765
V
IN
= 1.8V
C
REG
1µF C
REF
1µF
C
SS
10nF
13933-001
Figure 1. Fixed Output Operation
VIN
EN
SS
VREG
VOUT
SENSE
PG
R
PULL-UP
100kΩ PG
VADJ
GND
REFCAP
C
REG
1µF C
REF
1µF
R
ADJ
10kΩ
C
SS
10nF
ON
OFF
V
OUT
= 1.5V
ADP1765
V
IN
= 1.8V
C
OUT
22µF
C
IN
22µF
13933-002
Figure 2. Adjustable Output Operation
The ADP1765 is available in fixed output voltages ranging from
0.55 V to 1.5 V. The output voltage (VOUT) of the adjustable
output model can be set from 0.5 V to 1.5 V through an
external resistor connected between VADJ and ground.
The ADP1765 has an externally programmable soft start time by
connecting a capacitor to the SS pin. Short-circuit and thermal
overload protection circuits prevent damage in adverse conditions.
The ADP1765 is available in a small, 16-lead LFCSP package for
the smallest footprint solution to meet a variety of applications.
Table 1. Related Devices
Model
Input
Voltage
Maximum
Current
Fixed/
Adjustable Package
ADP1761 1.10 V to
1.98 V
1 A Fixed/
adjustable
16-lead
LFCSP
ADP1762 1.10 V to
1.98 V
2 A Fixed/
adjustable
16-lead
LFCSP
ADP1763 1.10 V to
1.98 V
3 A Fixed/
adjustable
16-lead
LFCSP
ADP1740/
ADP1741
1.6 V to
3.6 V
2 A Fixed/
adjustable
16-lead
LFCSP
ADP1752/
ADP1753
1.6 V to
3.6 V
0.8 A Fixed/
adjustable
16-lead
LFCSP
ADP1754/
ADP1755
1.6 V to
3.6 V
1.2 A Fixed/
adjustable
16-lead
LFCSP
ADP1765* PRODUCT PAGE QUICK LINKS
Last Content Update: 10/03/2017
COMPARABLE PARTS
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EVALUATION KITS
•ADP1764/ADP1765 Evaluation Board
DOCUMENTATION
Data Sheet
•ADP1765: 5 A, Low VIN, Low Noise, CMOS Linear
Regulator Data Sheet
User Guides
•UG-1072: Evaluating the ADP1764 and ADP1765 Low VIN,
Low Noise, CMOS Linear Regulators
TOOLS AND SIMULATIONS
•ADI Linear Regulator Design Tool and Parametric Search
• ADIsimPower™ Voltage Regulator Design Tool
DESIGN RESOURCES
•ADP1765 Material Declaration
•PCN-PDN Information
•Quality And Reliability
•Symbols and Footprints
DISCUSSIONS
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ADP1765 Data Sheet
Rev. A | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Typical Application Circuits ............................................................ 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Input and Output Capacitor: Recommended Specifications ........ 4
Absolute Maximum Ratings ............................................................ 5
Thermal Data ................................................................................ 5
Thermal Resistance/Parameter ................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 13
Soft Start Function ..................................................................... 13
Adjustable Output Voltage ........................................................ 14
Enable Feature ............................................................................ 14
Power-Good (PG) Feature ........................................................ 14
Applications Information .............................................................. 15
Capacitor Selection .................................................................... 15
Undervoltage Lockout ............................................................... 16
Current-Limit and Thermal Overload Protection ................. 16
Paralleling ADP1765 Devices for High Current
Applications ................................................................................ 16
Thermal Considerations ............................................................ 17
PCB Layout Considerations ...................................................... 19
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 20
REVISION HISTORY
6/2017—Rev. 0 to Re v. A
Changed Thermal Resistance Section to Thermal
Resistance/Parameter Section ......................................................... 5
Changes to Thermal Data Section and Table 5 ............................ 5
Changes to Typical Performance Characteristics Section ........... 7
Changes to Thermal Considerations Section, Table 7, Figure 50
through Figure 52, and Figure 50 Caption through Figure 52
Caption ............................................................................................. 17
Changes to Figure 53 through Figure 55, and Figure 53 Caption
through Figure 55 Caption ............................................................ 18
1/2017—Revision 0: Initial Version
Data Sheet ADP1765
Rev. A | Page 3 of 20
SPECIFICATIONS
VIN = VOUT + 0.2 V or VIN = 1.1 V, whichever is greater, IOUT = 100 mA, CIN = 22 µF, COUT = 22 µF, CREF = 1 µF, CREG = 1 µF, TA = 25°C,
minimum and maximum limits at TJ = −40°C to +125°C, unless otherwise noted.
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT VOLTAGE SUPPLY RANGE
IN
T
J
= −40°C to +125°C
1.10
1.98
V
OPERATING SUPPLY CURRENT IGND IOUT = 0 µA 5 17 mA
IOUT = 100 mA 5 18 mA
I
OUT
= 5 A
12
25
mA
SHUTDOWN CURRENT IGND_SD EN = GND 4 µA
TJ = −40°C to +85°C 200 µA
TJ = 85°C to 125°C 900 µA
NOISE1
Output Noise
NOISE
10 Hz to 100 kHz, V
IN
= 1.1 V, V
OUT
= 0.9 V
3
µV rms
100 Hz to 100 kHz, VIN = 1.1 V, VOUT = 0.9 V 2 µV rms
10 Hz to 100 kHz, VIN = 1.5 V, VOUT = 1.3 V 3 µV rms
100 Hz to 100 kHz, VIN = 1.5 V, VOUT = 1.3 V 2 µV rms
10 Hz to 100 kHz, VIN = 1.7 V, VOUT = 1.5 V 3 µV rms
100 Hz to 100 kHz, VIN = 1.7 V, VOUT = 1.5 V 2 µV rms
Noise Spectral Density
NSD
V
OUT
= 0.55 V to 1.5 V, I
OUT
= 100 mA
At 10 kHz 5 nV/√Hz
At 100 kHz 4 nV/√Hz
POWER SUPPLY REJECTION RATIO1 PSRR IOUT = 5 A, modulated VIN
10 kHz, VOUT = 1.3 V, VIN = 1.7 V 61 dB
100 kHz, VOUT = 1.3 V, VIN = 1.7 V 43 dB
1 MHz, VOUT = 1.3 V, VIN = 1.7 V 33 dB
10 kHz, VOUT = 0.9 V, VIN = 1.3 V 57 dB
100 kHz, V
OUT
= 0.9 V, V
IN
= 1.3 V
43
dB
1 MHz, VOUT = 0.9 V, VIN = 1.3 V 33 dB
OUTPUT VOLTAGE RANGE TJ = 25°C
Fixed
OUT_FIXED
0.55
1.5
V
Adjustable VOUT_ADJ 0.5 1.5 V
FIXED OUTPUT VOLTAGE ACCURACY VOUT IOUT = 100 mA, TJ = 25°C −0.75 +0.75 %
100 mA < I
OUT
< 5 A, T
J
= 0°C to 85°C
−1.3
+1.3
%
100 mA < IOUT < 5 A, TJ = 0°C to 125°C −1.5 +1.5 %
ADJUSTABLE PIN CURRENT IADJ TJ = 25°C, VADJ = 0.5 V 49.5 50.0 50.7 µA
VIN = VOUT + 0.2 V or VIN = 1.1 V, whichever
is greater to 1.98 V
49.0 50.0 51.2 µA
ADJUSTABLE OUTPUT VOLTAGE GAIN FACTOR AD VADJ = 0.5 V; VIN = VOUT+ 0.2 V or VIN = 1.1 V,
whichever is greater, to 1.98 V
TJ = 25°C 2.99
TJ = −40°C to +125°C 2.96 3.02
REGULATION
Line ∆VOUT/∆VIN VIN = VOUT + 0.2 V or VIN = 1.1 V, whichever
is greater, to 1.98 V
−0.10 +0.10 %/V
Load2 ∆VOUT/∆IOUT IOUT = 100 mA to 5 A 0.12 0.3 %/A
DROPOUT VOLTAGE3 VDROPOUT IOUT = 4 A, VOUT = 1.2 V 47 75 mV
IOUT = 5 A, VOUT = 1.2 V 59 95 mV
START-UP TIME1, 4 tSTARTUP CSS = 10 nF, VOUT = 1 V 1 ms
SOFT START CURRENT IREF 1.1 V ≤ VIN ≤ 1.98 V 8 10 12 µA
CURRENT-LIMIT THRESHOLD1, 5 ILIMIT 7.0 8.0 8.5 A
ADP1765 Data Sheet
Rev. A | Page 4 of 20
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
THERMAL SHUTDOWN1
Threshold TSSD TJ rising 152 °C
Hysteresis TSSD_HYS 16 °C
POWER-GOOD (PG) OUTPUT
Output Voltage Threshold
Falling PGFALL 1.1 V ≤ VIN ≤ 1.98 V −6.2 %
Rising PGRISE 1.1 V ≤ VIN ≤ 1.98 V −3.5 %
Output Voltage Low
LOW
1.1 V ≤ V
IN
≤ 1.98 V, I
PG
≤ 1 mA
0.3
V
Leakage Current IPG_LKG 1.1 V ≤ VIN ≤ 1.98 V 0.01 1 µA
Delay PGDELAY ENRISING to PGRISING 0.75 ms
PRECISION EN INPUT
1.1 V ≤ V
IN
≤ 1.98 V
Logic Input Voltage
High ENHIGH 0.60 0.65 0.69 V
Low ENLOW 0.55 0.60 0.65 V
Input Logic Hysteresis ENHYS 50 mV
Input Leakage Current IEN_LKG VEN = VIN or GND 0.01 1 µA
Input Delay Time tEN_DLY From EN rising from 0 V to VIN to 0.1 × VOUT 100 µs
UNDERVOLTAGE LOCKOUT UVLO
Input Voltage
Rising UVLORISE TJ = −40°C to +125°C 1.00 1.06 V
Falling UVLOFALL TJ = −40°C to +125°C 0.85 0.93 V
Hysteresis UVLOHYS 70 mV
1 Guaranteed by characterization but not production tested.
2 Based on an endpoint calculation using 100 mA and 5 A loads.
3 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage, which applies only for output
voltages above 1.1 V.
4 Start-up time is the time from the rising edge of VEN to VOUT being at 90% of its nominal value.
5 Current-limit threshold is the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V output voltage
is defined as the current that causes the output voltage to drop to 90% of 1.0 V, or 0.9 V.
INPUT AND OUTPUT CAPACITOR: RECOMMENDED SPECIFICATIONS
Table 3.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
CAPACITANCE1 TA = −40°C to +125°C
Input CIN 14.5 22 µF
Output COUT 14.5 22 µF
Regulator CREG 0.7 1 µF
Reference CREF 0.07 1 µF
CAPACITOR EQUIVALENT SERIES RESISTANCE (ESR) RESR TA = −40°C to +125°C
CIN, COUT 0.2 Ω
C
REG
0.5
Ω
CREF 2 Ω
1 The minimum input and output capacitance must be >14.5 µF over the full range of the operating conditions. Consider the full range of the operating conditions in
the application during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended. Y5V and Z5U
capacitors are not recommended for use with any LDO.
Data Sheet ADP1765
Rev. A | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
VIN to GND −0.3 V to +2.16 V
EN to GND
−0.3 V to +3.96 V
VOUT to GND −0.3 V to VIN
SENSE to GND −0.3 V to VIN
VREG to GND −0.3 V to VIN
REFCAP to GND −0.3 V to VIN
VADJ to GND −0.3 V to VIN
SS to GND
−0.3 V to V
IN
PG to GND −0.3 V to +3.96 V
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Operating Junction Temperature 125°C
Lead Temperature (Soldering, 10 sec) 300°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP1765 can be damaged when the junction
temperature limits are exceeded. The use of appropriate thermal
management techniques is recommended to ensure that the
maximum junction temperature does not exceed the limits shown
in Table 4.
Use the following equation to calculate the junction temperature
(TJ) from the board temperature (TBOARD) or package top
temperature (TTOP)
TJ = TBOARD + (PD × ΨJB)
TJ = TTOP + (PD × ΨJT)
ΨJB is the junction to board thermal characterization parameter
and ΨJT is the junction to top thermal characterization
parameter with units of °C/W.
ΨJB of the package is based on modeling and calculation using a
4-layer board. JESD51-12, Guidelines for Reporting and Using
Electronic Package Thermal Information, states that thermal
characterization parameters are not the same as thermal
resistances. ΨJB measures the component power flowing
through multiple thermal paths rather than a single path as in
thermal resistance, θJB. Therefore, ΨJB thermal paths include
convection from the top of the package as well as radiation from
the package, factors that make ΨJB more useful in real-world
applications.
THERMAL RESISTANCE/PARAMETER
Values shown in Table 5 are calculated in compliance with
JEDEC standards for thermal reporting. θJA is the natural
convection junction to ambient thermal resistance measured in a
one cubic foot sealed enclosure. θJC is the junction to case thermal
resistance. θJB is the junction to board thermal resistance. ΨJB is
the junction to board thermal characterization parameter. ΨJT is
the junction to top thermal characterization parameter.
In applications where high maximum power dissipation exists,
close attention to thermal board design is required. Thermal
resistance/parameter values may vary, depending on the PCB
material, layout, and environmental conditions.
Table 5. Thermal Resistance/Parameter
Package
Type θJA θJC θJB ΨJB ΨJT Unit
CP-16-48
1
40.65
7.47
17.38
12.9
0.85
°C/W
1 Thermal resistance/parameter simulated values are based on a JEDEC 2S2P
thermal test board for ΨJT, ΨJB, θJA and θJB and a JEDEC 1S0P thermal test board
for θJC with four thermal vias. See JEDEC JESD51-12.
ESD CAUTION
ADP1765 Data Sheet
Rev. A | Page 6 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
VIN
VIN
VIN
VIN
VOUT
NOTES
1. THE EXPOSED PAD IS ELECTRICALLY
CONNECTED TO GND. IT IS RECOMMENDED
THAT THIS PAD BE CONNECTED TO A GROUND
PLANE ON THE PCB. THE EXPOSED PAD IS
ON THE BOTTOM OF THE PACKAGE.
SENSE
SS
PG
EN
VOUT
VOUT
VOUT
REFCAP
VREG
GND
VADJ
ADP1765
TOP VIEW
(Not to Scale)
13933-003
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 to 4 VIN Regulator Input Supply. Bypass VIN to GND with a 22 μF or greater capacitor. Note that all four VIN pins must be
connected to the source supply.
5 REFCAP
Reference Filter Capacitor. Connect a 1 μF capacitor from the REFCAP pin to ground. Do not connect a load from
this pin to ground.
6 VREG
Regulated Input Supply to LDO Amplifier. Bypass VREG to GND with a 1 μF or greater capacitor. Do not connect a
load from this pin to ground.
7 GND Ground.
8 VADJ
Adjustable Voltage Pin for the Adjustable Output Option. Connect a 10 kΩ external resistor between the VADJ pin
and ground to set the output voltage to 1.5 V. For the fixed output option, leave this pin floating.
9 to 12 VOUT Regulated Output Voltage. Bypass VOUT to GND with a 22 μF or greater capacitor. Note that all four VOUT pins
must be connected to the load.
13 SENSE
Sense Input. The SENSE pin measures the actual output voltage at the load and feeds it to the error amplifier.
Connect SENSE as close to the load as possible to minimize the effect of IR drop between VOUT and the load.
14 SS Soft Start Pin. A capacitor connected to this pin determines the soft start time.
15 PG Power-Good Output. This open-drain output requires an external pull-up resistor. If the device is in shutdown
mode, current-limit mode, or thermal shutdown mode, or if the VOUT voltage falls below 90% of the nominal
output voltage, the PG pin immediately transitions to low.
16 EN Enable Input. Drive the EN pin high to turn on the regulator. Drive the EN pin low to turn off the regulator. For
automatic startup, connect the EN pin to the VIN pin.
EP Exposed Pad. The exposed pad is electrically connected to GND. It is recommended that this pad be connected to
a ground plane on the PCB. The exposed pad is on the bottom of the package.
Data Sheet ADP1765
Rev. A | Page 7 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = VOUT + 0.2 V or VIN = 1.1 V, whichever is greater, VOUT = 1.3 V, I OUT = 100 mA, TA = 25°C, unless otherwise noted.
–40 –20 020 40 60 80 100 140120
V
OUT
(V)
TEMPERATURE (°C)
1.292
1.294
1.296
1.298
1.300
1.302
1.304
1.306
1.308
1.310
1.312 I
LOAD
= 0.1A
I
LOAD
= 1.0A
I
LOAD
= 2.0A
I
LOAD
= 3.0A
I
LOAD
= 4.0A
I
LOAD
= 5.0A
13933-004
Figure 4. Output Voltage (VOUT) vs. Temperature, VOUT = 1.3 V
0.1 110
VOUT (V)
LO AD CURRE NT (A)
1.296
1.297
1.298
1.299
1.300
1.301
1.302
1.303
1.304
13933-005
Figure 5. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = 1.3 V
V
OUT
(V)
V
IN
(V)
I
LOAD
= 0.1A
I
LOAD
= 1.0A
I
LOAD
= 2.0A
I
LOAD
= 3.0A
I
LOAD
= 4.0A
I
LOAD
= 5.0A
1.296
1.297
1.298
1.299
1.300
1.301
1.302
1.303
1.304
1.305
1.306
1.50 1.58 1.66 1.74 1.82 1.90 1.98
13933-006
Figure 6. Output Voltage (VOUT) vs. Input Voltage (VIN), VOUT = 1.3 V
–40 –20 020 40 60 80 100 140120
I
GND
(mA)
TEMPERATURE (°C)
I
LOAD
= 0.1A
I
LOAD
= 1.0A
I
LOAD
= 2.0A
I
LOAD
= 3.0A
I
LOAD
= 4.0A
I
LOAD
= 5.0A
0
2
4
6
8
10
12
14
16
18
20
22
24
13933-007
Figure 7. Ground Current (IGND) vs. Temperature, VOUT = 1.3 V
0.1 110
I
GND
(mA)
LOAD CURRENT ( A)
0
2
4
6
8
10
12
14
16
18
20
22
24
13933-008
Figure 8. Ground Current (IGND) vs. Load Current (ILOAD), VOUT = 1.3 V
1.5 1.6 1.7 1.8 1.9 2.0
IGND (mA)
VIN (V)
ILOAD = 0.1A
ILOAD = 1.0A
ILOAD = 2.0A
ILOAD = 3.0A
ILOAD = 4.0A
ILOAD = 5.0A
0
2
4
6
8
10
12
14
16
18
20
22
24
13933-009
Figure 9. Ground Current (IGND) vs. Input Voltage (VIN), VOUT = 1.3 V
ADP1765 Data Sheet
Rev. A | Page 8 of 20
–40 –20 020 40 60 80 100 140120
V
OUT
(V)
TEMPERATURE (°C)
I
LOAD
= 0.1A
I
LOAD
= 1.0A
I
LOAD
= 2.0A
I
LOAD
= 3.0A
I
LOAD
= 4.0A
I
LOAD
= 5.0A
0.886
0.888
0.890
0.892
0.894
0.896
0.898
0.900
0.902
0.904
0.906
13933-010
Figure 10. Output Voltage (VOUT) vs. Temperature, VOUT = 0.9 V
0.1 110
V
OUT
(V)
LOAD CURRENT ( A)
0.890
0.891
0.892
0.893
0.894
0.895
0.896
0.897
0.898
0.899
0.900
0.901
0.902
0.903
0.904
13933-011
Figure 11. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = 0.9 V
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0
V
OUT
(V)
V
IN
(V)
I
LOAD
= 0.1A
I
LOAD
= 1.0A
I
LOAD
= 2.0A
I
LOAD
= 3.0A
I
LOAD
= 4.0A
I
LOAD
= 5.0A
0.890
0.891
0.892
0.893
0.894
0.895
0.896
0.897
0.898
0.899
0.900
0.901
0.902
0.903
0.904
13933-012
Figure 12. Output Voltage (VOUT) vs. Input Voltage (VIN), VOUT = 0.9 V
–40 –20 020 40 60 80 100 140120
I
GND
(mA)
TEMPERATURE (°C)
I
LOAD
= 0.1A
I
LOAD
= 1.0A
I
LOAD
= 2.0A
I
LOAD
= 3.0A
I
LOAD
= 4.0A
I
LOAD
= 5.0A
0
2
4
6
8
10
12
14
16
18
20
22
24
13933-013
Figure 13. Ground Current (IGND) vs. Temperature, VOUT = 0.9 V
0.1 110
I
GND
(mA)
LOAD CURRENT ( A)
0
2
4
6
8
10
12
14
16
18
20
22
24
13933-014
Figure 14. Ground Current (IGND) vs. Load Current (ILOAD), VOUT = 0.9 V
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0
IGND (mA)
VIN (V)
ILOAD = 0.1A
ILOAD = 1.0A
ILOAD = 2.0A
ILOAD = 3.0A
ILOAD = 4.0A
ILOAD = 5.0A
0
2
4
6
8
10
12
14
16
18
20
22
24
13933-015
Figure 15. Ground Current (IGND) vs. Input Voltage (VIN), VOUT = 0.9 V
Data Sheet ADP1765
Rev. A | Page 9 of 20
I
GND_SD
(µA)
TEMPERATURE (°C)
0.01
0.1
1
10
100
1000 V
IN
= 1.10V
V
IN
= 1.30V
V
IN
= 1.50V
V
IN
= 1.70V
V
IN
= 1.90V
V
IN
= 1.98V
13933-016
Figure 16. Shutdown Current (IGND_SD) vs. Temperature at
Various Input Voltages (VIN), VOUT = 0.9 V
0.1 110
V
DROPOUT
(V)
LOAD CURRENT ( A)
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
13933-017
Figure 17. Dropout Voltage (VDROPOUT) vs. Load Current (ILOAD), VOUT = 1.3 V
1.25 1.35 1.40 1.451.30 1.50
V
OUT
(V)
V
IN
(V)
1.20
1.21
1.22
1.23
1.24
1.25
1.26
1.27
1.28
1.29
1.30
1.31
1.32
I
LOAD
= 0.1A
I
LOAD
= 1.0A
I
LOAD
= 2.0A
I
LOAD
= 3.0A
I
LOAD
= 4.0A
I
LOAD
= 5.0A
13933-018
Figure 18. Output Voltage (VOUT) vs. Input Voltage (VIN) in Dropout,
VOUT = 1.3 V
1.1 1.2 1.3 1.4 1.5
I
GND
(mA)
V
IN
(V)
I
LOAD
= 0.1A
I
LOAD
= 1.0A
I
LOAD
= 2.0A
I
LOAD
= 3.0A
I
LOAD
= 4.0A
I
LOAD
= 5.0A
0
2
4
6
8
10
12
14
16
18
20
22
24
13933-019
Figure 19. Ground Current (IGND) vs. Input Voltage (VIN) in Dropout,
VOUT = 1.3 V
3
1
T
CH1 50mV
CH3 2A 4.00µs5GSPS
1M POINTS CH3 2.44A
T 11.04000µ s
I
OUT
V
OUT
SLE W RAT E = 5A/µs
BW
BW
13933-020
Figure 20. Load Transient Response, COUT = 22 µF, VIN = 1.8 V, VOUT = 1.3 V
3
1
T
CH1 50mV
CH3 2A 4.00µs5GSPS
1M POINTS CH3 2.44A
T 11.36000µ s
I
OUT
V
OUT
SLEW RAT E = 5A/µs
BW
BW
13933-021
Figure 21. Load Transient Response, COUT = 47 µF, VIN = 1.8 V, VOUT = 1.3 V
ADP1765 Data Sheet
Rev. A | Page 10 of 20
3
1
T
CH1 50mV
CH3 2A 4.00µs5GSPSs
1M POINTS CH3 2.48A
T 11.24000µ s
BW
BW
I
OUT
V
OUT
SLEW RAT E = 4.5A/µs
13933-022
Figure 22. Load Transient Response, COUT = 22 µF, VIN = 1.4 V, VOUT = 0.9 V
3
1
T
CH1 50mV
CH3 2A 4.00µs5GSPS
1M POINTS CH3 2.48A
T 11.32000µ s
BW
BW
I
OUT
V
OUT
SLEW RAT E = 4.5A/µs
13933-023
Figure 23. Load Transient Response, COUT = 47 µF, VIN = 1.4 V, VOUT = 0.9 V
1
2
T
CH1 2mV
CH2 500mV 4.00µs5GSPS
1M POINTS CH2 1.86V
T 9.020000µ s
BW
BW
V
IN
V
OUT
13933-024
Figure 24. Line Transient Response, Load Current = 5 A,
VIN = 1.6 V to 1.98 V Step, VOUT = 1.3 V
1
2
T
CH1 2mV
CH2 500mV 4.00µs
5GSPS
1M POINTS CH2 1.53V
T 9.020000µ s
BW
BW
V
IN
V
OUT
13933-025
Figure 25. Line Transient Response, Load Current = 5 A,
VIN = 1.3 V to 1.7 V Step, VOUT = 0.9 V
0.1 110
OUT P UT NO ISE ( µV rms)
LOAD CURRENT ( A)
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0 10Hz TO 100kHz
100Hz T O 100kHz
13933-026
Figure 26. Output Noise vs. Load Current (ILOAD)
0.5 0.7 0.9 1.1 1.3 1.5
OUT P UT NO ISE ( µV rms)
OUTPUT VOLTAGE (V)
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0 10Hz TO 100kHz
100Hz T O 100kHz
13933-027
Figure 27. Output Noise vs. Output Voltage (VOUT)
Data Sheet ADP1765
Rev. A | Page 11 of 20
FREQUENCY (Hz)
V
OUT
= 0.5V
V
OUT
= 0.9V
V
OUT
= 1.3V
V
OUT
= 1.5V
0.1 1 10 100 1k 10k 100k 1M
100k
0.1
NOISE SPECTRAL DENSITY (nV/
√
Hz)
1
10
100
1k
10k
13933-028
Figure 28. Noise Spectral Density vs. Frequency
at Various Output Voltages (VOUT), 0.1 Hz to 1 MHz
FREQUENCY (Hz)
VOUT = 0.5V
VOUT = 0.9V
VOUT = 1.3V
VOUT = 1.5V
0.1
1
10
100
1k
10 100 1k 10k 100k 10M1M
NOISE SPECTRAL DENSITY (nV/
√
Hz)
13933-029
Figure 29. Noise Spectral Density vs. Frequency
at Various Output Voltages (VOUT), 10 Hz to 10 MHz
FREQUENCY (Hz)
0.1 1 10 100 1k 10k 100k 1M
I
LOAD
= 0.1A
I
LOAD
= 1.0A
I
LOAD
= 3.0A
I
LOAD
= 4.0A
I
LOAD
= 5.0A
100k
0.1
NOISE SPECTRAL DENSITY (nV/
√
Hz)
1
10
100
1k
10k
13933-030
Figure 30. Noise Spectral Density vs. Frequency
at Various Load Current (IOUT), 0.1 Hz to 1 MHz
NOISE SPECTRAL DENSITY (nV/√Hz)
FREQUENCY (Hz)
0.1
1
10
100
1k
10 100 1k 10k 100k 10M1M
I
LOAD
= 0.1A
I
LOAD
= 1.0A
I
LOAD
= 3.0A
I
LOAD
= 4.0A
I
LOAD
= 5.0A
13933-031
Figure 31. Noise Spectral Density vs. Frequency
at Various Load Current (IOUT), 10 Hz to 10 MHz
PSRR (dB)
FREQUENCY (Hz)
1 10 100 1k 10k 100k 10M1M
VIN = 1.5V
VIN = 1.6V
VIN = 1.7V
VIN = 1.8V
VIN = 1.9V
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–
10
13933-032
Figure 32. Power Supply Rejection Ratio (PSRR) vs. Frequency at
Various Input Voltages (VIN), VOUT = 1.3 V, Load = 5 A
PSRR (dB)
FREQUENCY (Hz)
1 10 100 1k 10k 100k 10M1M
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–
10
I
LOAD
= 0.1A
I
LOAD
= 1.0A
I
LOAD
= 2.0A
I
LOAD
= 3.0A
I
LOAD
= 4.0A
I
LOAD
= 5.0A
13933-033
Figure 33. Power Supply Rejection Ratio (PSRR) vs. Frequency at
Various Loads (ILOAD), VOUT = 1.3 V, VIN = 1.7 V
ADP1765 Data Sheet
Rev. A | Page 12 of 20
PSRR (dB)
FREQUENCY ( Hz )
110 100 1k 10k 100k 10M
1M
V
IN
= 1.1V
V
IN
= 1.2V
V
IN = 1.3V
VIN = 1.4V
VIN = 1.5V
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
13933-034
Figure 34. Power Supply Rejection Ratio (PSRR) vs. Frequency at
Various Input Voltages (VIN), VOUT = 0.9 V, Load = 5 A
PSRR (dB)
FREQUENCY ( Hz )
110 100 1k 10k 100k 10M1M
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
I
LOAD
= 0.1A
I
LOAD
= 1.0A
I
LOAD
= 2.0A
I
LOAD
= 3.0A
I
LOAD
= 4.0A
I
LOAD
= 5.0A
13933-035
Figure 35. Power Supply Rejection Ratio (PSRR) vs. Frequency at
Various Loads (ILOAD), VOUT = 0.9 V, VIN = 1.3 V
0.2 0.3 0.4 0.5 0.6
PSRR (dB)
HEADROOM ( V )
FREQUENCY = 10Hz
FREQUENCY = 100Hz
FREQUENCY = 1kHz
FREQUENCY = 10kHz
FREQUENCY = 100kHz
FREQUENCY = 1M Hz
FREQUENCY = 10M Hz
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
13933-036
Figure 36. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage at
Various Frequencies, VOUT = 0.9 V, Load = 5 A
0.2 0.3 0.4 0.5 0.6
PSRR (dB)
HEADROOM ( V )
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
13933-037
FREQ UENCY = 10 Hz
FREQ UENCY = 10 0 Hz
FREQ UENCY = 1k Hz
FREQ UENCY = 10 k Hz
FREQ UENCY = 10 0 kHz
FREQ UENCY = 1MHz
FREQ UENCY = 10 MHz
Figure 37. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage at
Various Frequencies, VOUT = 1.3 V, Load = 5 A
Data Sheet ADP1765
Rev. A | Page 13 of 20
THEORY OF OPERATION
The ADP1765 is a low dropout (LDO), low noise linear regulator
that uses an advanced proprietary architecture to achieve high
efficiency regulation. It also provides high PSRR and excellent line
and load transient response using a small 22 F ceramic output
capacitor. The device operates from a 1.10 V to 1.98 V input rail
to provide up to 5 A of output current. The supply current in
shutdown mode is less than 4 μA.
SS BLOCK
REFCAP
SS
PG
SHORT-CIRCUIT,
THERMAL
PROTECTION
INTERNAL
BIAS SUPPLY
ADP1765
VIN
VREG
EN
GND
REFERENCE,
BIAS
VOUT
SENSE
13933-038
Figure 38. Functional Block Diagram, Fixed Output
SS BLOCK
SHORT-CIRCUIT,
THERMAL
PROTECTION
INTERNAL
BIAS SUPPLY
3×
REFCAP
SS
PG
VIN
V
REG
V
ADJ
I
ADJ
EN
GND
VOUT
SENSE
ADP1765
13933-039
Figure 39. Functional Block Diagram, Adjustable Output
Internally, the ADP1765 consists of a reference, an error amplifier,
and a pass device. The output current is delivered via the pass
device, which is controlled by the error amplifier, forming a
negative feedback system that ideally drives the feedback voltage
to equal the reference voltage. If the feedback voltage is lower
than the reference voltage, the negative feedback drives more
current, increasing the output voltage. If the feedback voltage is
higher than the reference voltage, the negative feedback drives
less current, decreasing the output voltage.
The ADP1765 is available in output voltages ranging from 0.55 V
to 1.5 V for a fixed output. Contact your local Analog Devices, Inc.,
sales representative for other fixed voltage options. The adjustable
output option can be set from 0.5 V to 1.5 V. The ADP1765 uses
the EN pin to enable and disable the VOUT pin under normal
operating conditions. When EN is high, VOUT turns on. When
EN is low, VOUT turns off. For automatic startup, tie EN to VIN.
SOFT START FUNCTION
For applications that require a controlled startup, the ADP1765
provides a programmable soft start function. The programmable
soft start is useful for reducing inrush current upon startup and
for providing voltage sequencing. To implement soft start, connect
a small ceramic capacitor from SS to GND. At startup, a 10 μA
current source charges this capacitor. The voltage at SS limits
the ADP1765 start-up output voltage, providing a smooth ramp up
to the nominal output voltage. To calculate the start-up time for
the fixed output (tSTARTUP_FIXED) and adjustable (tSTARTUP_ADJ) output,
use the following equations:
tSTARTUP_FIXED = tDELAY + VREF × (CSS/ISS) (1)
tSTARTUP_ADJ = tDELAY + VADJ × (CSS/ISS) (2)
where:
tDELAY is a fixed delay of 100 μs.
VREF is a 0.5 V internal reference for the fixed output model option.
CSS is the soft start capacitance from SS to GND.
ISS is the current sourced from SS (10 μA).
VADJ is the voltage at the VADJ pin, equal to RADJ × IADJ.
1.6
0
0.1
V
OUT
(V)
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
–1.0 2.5
TIME (ms)
–0.5 0 0.5 1.0 1.5 2.0
EN
C
SS
= 0nF
C
SS
= 10nF
C
SS
= 22nF
13933-040
Figure 40. Fixed VOUT Ramp-Up with External Soft Start Capacitor (VOUT, EN) vs. Time
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.1
0.2
0
–1.0 –0.5 0 0.5 1.51.0 2.0 2.5
V
OUT
(V)
TIME (ms)
EN
VOUT = 0.5V; CSS = 0nF
VOUT = 0.5V; CSS = 10nF
VOUT = 0.5V; CSS = 22nF
VOUT = 1.5V; CSS = 0nF
VOUT = 1.5V; CSS = 10nF
VOUT = 1.5V; CSS = 22nF
13933-041
Figure 41. Adjustable VOUT Ramp-Up with External Soft Start Capacitor
(VOUT, EN) vs. Time
ADP1765 Data Sheet
Rev. A | Page 14 of 20
ADJUSTABLE OUTPUT VOLTAGE
The output voltage of the ADP1765 can be set over a 0.5 V to
1.5 V range. Connect a resistor (RADJ) from the VADJ pin to
ground to set the output voltage. To calculate the output voltage
(VOUT), use the following equation:
VOUT = AD × (RADJ × IADJ) (3)
where:
AD is the gain factor with a typical value of 2.99 between the
VADJ pin and VOUT pin.
IADJ is the 50 μA constant current out of the VADJ pin.
ENABLE FEATURE
The ADP1765 uses the EN pin to enable and disable the VOUT pins
under normal operating conditions. As shown in Figure 42, when a
rising voltage on EN crosses the active threshold, VOUT turns on.
When a falling voltage on EN crosses the inactive threshold,
VOUT turns off.
CH1 200mV
CH2 200mV
10.00ms100kSPS
10k POINTS
CH1 1.21V
T 121.9200ms
2
1
T
13933-042
EN
VOUT
Figure 42. Typical EN Pin Operation
As shown in Figure 43, the EN pin has built in hysteresis. This
hysteresis prevents on/off oscillations that can occur due to noise
on the EN pin as it passes through the threshold points.
0.59 0.60 0.62 0.640.61 0.63 0.65 0.66
VOUT (V)
EN THRESHOLD (V)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
TA = +125°C
TA = +85°C
TA = +25°C
TA = 0°C
TA = –40°C
13933-043
Figure 43. Output Voltage (VOUT) vs. EN Threshold, VOUT = 1.3 V
POWER-GOOD (PG) FEATURE
The ADP1765 provides a power-good pin (PG) to indicate the
status of the output. This open-drain output requires an external
pull-up resistor that can be connected to VIN or VOUT. If the
device is in shutdown mode, current-limit mode, or thermal
shutdown, or if it falls below 90% of the nominal output voltage,
PG immediately transitions low. During soft start, the rising
threshold of the power-good signal is 96.5% of the nominal
output voltage.
The open-drain output is held low when the ADP1765 has
sufficient input voltage to turn on the internal PG transistor. An
optional soft start delay can be detected. The PG transistor is
terminated via a pull-up resistor to VIN or VOUT.
Power-good accuracy is 93.8% of the nominal regulator output
voltage when this voltage is rising, with a 96.5% trip point when
this voltage is falling.
Regulator input voltage brownouts or glitches trigger a power
no good if VOUT falls below 93.8%.
A normal power-down triggers a power good when VOUT is at
96.5%.
CH1 1V
CH2 1V
CH3 1V 200µs5.00MSPS
10k POINTS
CH2 1.30V
T –70.00000µs
2
3
1
T
EN
PG
V
OUT
13933-044
Figure 44. Typical PG Voltage Behavior vs. VOUT, VIN Rising (VOUT = 1.3 V)
CH1 1V
BW
CH2 1V
BW
CH3 1V
BW
200µs
500MSPS
1M POINTS
CH2 700mV
T –5.20000µs
2
3
1
T
EN
PG
V
OUT
13933-045
Figure 45. Typical PG Voltage Behavior vs. VOUT, VIN Falling (VOUT = 1.3 V)
Data Sheet ADP1765
Rev. A | Page 15 of 20
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Output Capacitor
The ADP1765 is designed for operation with small, space-saving
ceramic capacitors, but it can function with most commonly used
capacitors as long as care is taken with the effective series
resistance (ESR) value. The ESR of the output capacitor affects
the stability of the LDO control loop. A minimum of 22 µF
capacitance with an ESR of 50 mΩ or less is recommended to
ensure the stability of the ADP1765. Transient response to changes
in load current is also affected by output capacitance. Using a larger
value of output capacitance improves the transient response of the
ADP1765 to large changes in load current. Figure 46 and Figure 47
show the transient responses for output capacitance values of 22 µF
and 47 µF, respectively.
3
1
T
CH1 50mV
CH3 2A 4.00µs5GSPS
1M POINTS CH3 2.44A
T 11.04000µ s
I
OUT
V
OUT
SLEW RAT E = 5A/µs
BW
BW
13933-046
Figure 46. Output Transient Response, COUT = 22 µF, VOUT = 1.3 V
3
1
T
CH1 50mV
CH3 2A 4.00µs5GSPS
1M POINTS CH3 2.44A
T 11.36000µ s
I
OUT
V
OUT
SLE W RAT E = 5A/µs
BW
BW
13933-047
Figure 47. Output Transient Response, COUT = 47 µF, VOUT = 1.3 V
Input Bypass Capacitor
Connecting a 22 µF capacitor from the VIN pin to the GND pin
to the ground plane reduces the circuit sensitivity to the PCB
layout, especially when long input traces or high source imped-
ances are encountered. If an output capacitance greater than
22 µF is required, it is recommended to increase the input
capacitor to match it.
Input and Output Capacitor Properties
Use any good quality ceramic capacitors with the ADP1765 as
long as they meet the minimum capacitance and maximum ESR
requirements. Ceramic capacitors are manufactured with a variety
of dielectrics, each with different behavior over temperature and
applied voltage. Capacitors must have a dielectric adequate to
ensure the minimum capacitance over the necessary temperature
range and dc bias conditions. X5R or X7R dielectrics with a
voltage rating of 6.3 V or 10 V are recommended. Y5V and Z5U
dielectrics are not recommended, due to their poor temperature
and dc bias characteristics.
Figure 48 shows the capacitance vs. dc bias voltage characteristics
of a C2012X5R1A226K125AB, 0805 case, 22 µF, 10 V, X5R
capacitor. The voltage stability of a capacitor is strongly influenced
by the capacitor size and voltage rating. In general, a capacitor
in a larger package or with a higher voltage rating exhibits
improved stability. The temperature variation of the X5R
dielectric is about ±15% over the −55°C to +85°C temperature
range and is not a function of package size or voltage rating.
25
0
5
10
15
20
0 2 4 6 8 10
CAPACITANCE, NOM INAL ( µ F)
DC BIAS V OL TAGE ( V )
13933-048
Figure 48. Capacitance vs. DC Bias Voltage
Use Equation 4 to determine the worst-case capacitance,
accounting for capacitor variation over temperature, component
tolerance, and voltage.
CEFF = COUT × (1 − TEMPCO) × (1 − TOL) (4)
where:
CEFF is the effective capacitance at the operating voltage.
COUT is the output capacitor.
TEMPCO is the worst case capacitor temperature coefficient.
TOL is the worst case component tolerance.
In this example, the worst case temperature coefficient
(TEMPCO) over −55°C to +125°C is assumed to be 15% for an
X5R dielectric. The tolerance of the capacitor (TOL) is assumed
to be 10%, and COUT = 19.48 µF at 1.0 V, as shown in Figure 48.
Substituting these values in Equation 4 yields
CEFF = 19.48 μF × (1 − 0.15) × (1 − 0.1) = 14.9 μF
ADP1765 Data Sheet
Rev. A | Page 16 of 20
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over temperature
and tolerance at the chosen output voltage.
To guarantee the performance of the ADP1765, it is imperative
to evaluate the effects of dc bias, temperature, and tolerances on
the behavior of the capacitors for each application.
UNDERVOLTAGE LOCKOUT
The ADP1765 has an internal undervoltage lockout (UVLO)
circuit that disables all inputs and the output when the input
voltage is less than approximately 1.06 V. The UVLO ensures that
the ADP1765 inputs and output behave in a predictable manner
during power-up.
CURRENT-LIMIT AND THERMAL OVERLOAD
PROTECTION
The ADP1765 is protected against damage due to excessive power
dissipation by current-limit and thermal overload protection
circuits. The ADP1765 is designed to reach the current limit
when the output load reaches 8.0 A (typical). When the output
load exceeds 8.0 A, the output voltage is reduced to maintain a
constant current limit.
Thermal overload protection is included that limits the junction
temperature to a maximum of 152°C (typical). Under extreme
conditions (that is, high ambient temperature and power dissipa-
tion) when the junction temperature begins to rise above 152°C,
the output turns off, reducing the output current to zero. When the
junction temperature drops below 136°C (typical), the output turns
on again, and the output current is restored to its nominal value.
Consider the case where a hard short from VOUT to ground
occurs. At first, the ADP1765 reaches the current limit so that
only 8.0 A is conducted into the short. If self-heating of the
junction becomes great enough to cause its temperature to rise
above 152°C, thermal shutdown activates, turning off the
output and reducing the output current to zero. As the junction
temperature cools and drops below 136°C, the output turns on
and conducts 8.0 A into the short, again causing the junction
temperature to rise above 152°C. This thermal oscillation between
136°C and 152°C causes a current oscillation between 8.0 A and
0 A that continues as long as the short remains at the output.
Current-limit and thermal overload protections are intended to
protect the device against accidental overload conditions. For
reliable operation, device power dissipation must be externally
limited so that junction temperatures do not exceed 125°C.
PARALLELING ADP1765 DEVICES FOR HIGH
CURRENT APPLICATIONS
In applications where high output current is required while
maintaining low noise and high PSRR performance, connect two
ADP1765 devices in parallel to handle loads up to 9 A.
When paralleling theADP1765, the two outputs must be of the
same voltage setting to maintain good current sharing between
the two LDOs. To improve current sharing accuracy, add identical
ballast resistors (RBALLAST) at the output of each regulator, as shown
in Figure 49. Note that large ballast resistors improve current
sharing accuracy, but degrade the load regulation performance
and increase the losses along the power line. Therefore, it is best
to keep the ballast resistors at a minimum. In addition, tie the
VADJ, SS, and REFCAP pins of the LDO regulators together to
minimize error between the two outputs.
Use Equation 5 to calculate the output of the two paralleled
ADP1765 LDOs.
VOUT = 2 ×AD × (RADJ × IADJ) (5)
where:
AD is the gain factor with a typical value of 2.99 between the
VADJ pin and VOUT pin.
IADJ is the 50 µA constant current out of the VADJ pin.
VIN
EN ENABLE
SS
VREG
VOUT
SENSE
C
OUT
22µF
PG
VADJ
GNDREFCAP
C
IN
22µF
R
PULLUP
100kΩ
R
BALLAST
= 5mΩ
R
BALLAST
= 5mΩ
V
OUT
= 1.2V /9A
ADP1765
V
IN
= 1.5V
VIN
EN
SS
VREG
VOUT
SENSE
C
OUT
22µF
PG
VADJ
GNDREFCAP
C
IN
22µF
ADP1765
C
REG
1µF C
REF
1µF
R
ADJ
4.02kΩ
C
SS
1nF
C
REG
1µF C
REF
1µF
13933-049
Figure 49. Two ADP1765 Devices Connected in Parallel to Achieve Higher Current Output
Data Sheet ADP1765
Rev. A | Page 17 of 20
THERMAL CONSIDERATIONS
In applications with a low input-to-output voltage differential,
the ADP1765 does not dissipate much heat. However, in
applications with high ambient temperature and/or high input
voltage, the heat dissipated in the package may become large
enough to cause the junction temperature of the die to exceed
the maximum junction temperature of 125°C.
When the junction temperature exceeds 152°C, the regulator
enters thermal shutdown. The regulator recovers only after the
junction temperature decreases below 136°C to prevent any
permanent damage. Therefore, thermal analysis for the chosen
application is important to guarantee reliable performance over
all conditions. The junction temperature of the die is the sum of
the board temperature and the temperature rise of the package
due to the power dissipation, as shown in Equation 6.
To guarantee reliable operation, the junction temperature of the
ADP1765 must not exceed 125°C. To ensure that the junction
temperature stays below this maximum value, the user must be
aware of the parameters that contribute to junction temperature
changes. These parameters include board temperature, power
dissipation in the power device, and thermal characterization
parameter between the junction and board (ΨJB). The ΨJB
parameter is dependent on the package assembly compounds and
the PCB copper area. Table 7 shows the typical ΨJB values for the
16-lead LFCSP package for various PCB copper areas.
Table 7. Typical non-JEDEC ΨJB Values
PCB Copper Area (mm2) ΨJB (°C/W) at 2W
25 71.05
100 18.9
500 13.45
1000 13.15
Calculate the junction temperatures of the ADP1765 by
TJ = TB + (PD × ΨJB) (6)
where:
TB is the board temperature.
PD is the power dissipation in the die, given by
PD = ((VIN − VOUT) × ILOAD) + (VIN × IGND) (7)
where:
VIN and VOUT are the input and output voltages, respectively.
ILOAD is the load current.
IGND is the ground current.
Power dissipation due to ground current is quite small and can
be ignored. Therefore, the junction temperature equation
simplifies to
TJ = TB + (((VIN − VOUT) × ILOAD) × ΨJB) (8)
As shown in Equation 8, for a given board temperature, input-
to-output voltage differential and continuous load current, a
minimum copper area requirement exists for the PCB to ensure
that the junction temperature does not rise above 125°C.
Figure 50 to Figure 55 show the junction temperature calculations
for the different board temperatures, power dissipation, and
areas of the PCB copper.
00.2 0.6 1.00.4 0.8 1.2 1.4
JUNCTI ON T E M P E RATURE (°C)
VIN – VOUT (V)
0
20
40
60
80
100
120
140
0.1A
1.0A
2.0A
3.0A
4.0A
5.0A
TJ MAX
13933-050
Figure 50. 1000 mm2 of PCB Copper, TB = 25°C
00.2 0.6 1.00.4 0.8 1.2 1.4
JUNCTI ON T E M P E RATURE (°C)
VIN – VOUT (V)
0
20
40
60
80
100
120
140
13933-051
TJ MAX
0.1A
1.0A
2.0A
3.0A
4.0A
5.0A
Figure 51. 500 mm2 of PCB Copper, TB = 25°C
00.2 0.6 1.00.4 0.8 1.2 1.4
JUNCTI ON T E M P E RATURE (°C)
VIN – VOUT (V)
0
20
40
60
80
100
120
140
13933-052
TJ MAX
0.1A
1.0A
2.0A
3.0A
4.0A
5.0A
Figure 52. 100 mm2 of PCB Copper, TB= 25°C
ADP1765 Data Sheet
Rev. A | Page 18 of 20
00.2 0.6 1.00.4 0.8 1.2 1.4
JUNCTI ON T E M P E RATURE (°C)
VIN – VOUT (V)
0
20
40
60
80
100
120
140
13933-053
TJ MAX
0.1A
1.0A
2.0A
3.0A
4.0A
5.0A
Figure 53. 1000 mm2 of PCB Copper, TB = 50°C
00.2 0.6 1.00.4 0.8 1.2 1.4
JUNCTI ON T E M P E RATURE (°C)
VIN – VOUT (V)
0
20
40
60
80
100
120
140
13933-054
TJ MAX
0.1A
1.0A
2.0A
3.0A
4.0A
5.0A
Figure 54. 500 mm2 of PCB Copper, TB = 50°C
00.2 0.6 1.00.4 0.8 1.2 1.4
JUNCTI ON T E M P E RATURE (°C)
VIN – VOUT (V)
0
20
40
60
80
100
120
140
13933-055
TJ MAX
0.1A
1.0A
2.0A
3.0A
4.0A
5.0A
Figure 55. 100 mm2 of PCB Copper, TB = 50°C
13933-056
T
B
= 93.3°C
T
ADP1765
= 115.3°C
Figure 56. Thermal Image of the ADP1765 Evaluation Board at ILOAD = 5 A,
VIN = 1.5 V, VOUT = 1.3 V, TB = 93.3°C
Figure 56 shows a thermal image of the ADP1765 evaluation
board operating at a 5 A current load. The total power dissipation
on the ADP1765 is 933 mW, which makes the temperature on
the surface of the device higher by 22°C than the temperature of
the evaluation board.
Data Sheet ADP1765
Rev. A | Page 19 of 20
PCB LAYOUT CONSIDERATIONS
Place the input capacitor as close as possible to the VIN and
GND pins. Place the output capacitor as close as possible to the
VOUT and GND pins. Place the soft start capacitor (CSS) as
close as possible to the SS pin. Place the reference capacitor
(CREF) and regulator capacitor (CREG) as close as possible to the
REFCAP pin and VREG pin, respectively. Connect the load as
close as possible to the VOUT and SENSE pins.
13933-057
Figure 57. Evaluation Board
13933-058
Figure 58. Typical Board Layout, Top Side
13933-059
Figure 59. Typical Board Layout, Bottom Side
ADP1765 Data Sheet
Rev. A | Page 20 of 20
OUTLINE DIMENSIONS
3.10
3.00 S Q
2.90
0.28
0.23
0.18
1.80
1.70 S Q
1.60
1
0.50
BSC
BOTTOM VIEWTOP VIEW
16
5
8
9
1213
4
*0.40
0.35
0.30
0.05 M AX
0.02 NOM
0.203 RE F
0.20 M IN
COPLANARITY
0.08
PI N 1
INDICATOR
0.80
0.75
0.70
FOR PRO P E R CONNECT IO N OF
THE EXPOSED PAD, REFER TO
THE P I N CONF IGURATI ON AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
10-04-2016-A
PKG-005014
*COM P LIANT TO JEDE C S TANDARDS MO-220-WEED-4
WITH EXCEPTION TO LEAD LENGHT.
EXPOSED
PAD
PIN 1
INDIC ATOR AREA OPT IONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
SEATING
PLANE
Figure 60. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2 Temperature Range Output Voltage (V) Package Description Package Option Branding
ADP1765ACPZ0.85-R7 −40°C to +125°C 0.85 16-Lead LFCSP CP-16-48 LUA
ADP1765ACPZ-0.9-R7 −40°C to +125°C 0.9 16-Lead LFCSP CP-16-48 LUB
ADP1765ACPZ0.95-R7 −40°C to +125°C 0.95 16-Lead LFCSP CP-16-48 LUM
ADP1765ACPZ-1.0-R7 −40°C to +125°C 1.0 16-Lead LFCSP CP-16-48 LUD
ADP1765ACPZ-1.1-R7 −40°C to +125°C 1.1 16-Lead LFCSP CP-16-48 LUE
ADP1765ACPZ-1.2-R7 −40°C to +125°C 1.2 16-Lead LFCSP CP-16-48 LUF
ADP1765ACPZ1.25-R7 −40°C to +125°C 1.25 16-Lead LFCSP CP-16-48 LUR
ADP1765ACPZ-1.3-R7 −40°C to +125°C 1.3 16-Lead LFCSP CP-16-48 LUG
ADP1765ACPZ-1.5-R7 −40°C to +125°C 1.5 16-Lead LFCSP CP-16-48 LUJ
ADP1765ACPZ-R7 −40°C to +125°C Adjustable 16-Lead LFCSP CP-16-48 LUK
ADP1765-1.0-EVALZ
1.0
Evaluation Board (Fixed)
ADP1765-ADJ-EVALZ 1.0 Evaluation Board (Adjustable)
1 Z = RoHS Compliant Part.
2 For additional voltage options, contact a local Analog Devices sales or distribution representative. Additional voltage options are available by special order and
include the following: 0.55 V, 0.6 V, 0.65 V, 0.7 V, 0.75 V, 0.8 V, 1.05 V, 1.15 V, 1.35 V, 1.4 V, and 1.45 V.
©2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13933-0-6/17(A)