Si823x Data Sheet
0.5 and 4.0 Amp ISOdrivers (2.5 and 5 kVRMS)
The Si823x isolated driver family combines two independent, isolated drivers into a sin-
gle package. The Si8230/1/3/4 are high-side/low-side drivers, while the Si8232/5/7/8 are
dual drivers. Versions with peak output currents of 0.5 A (Si8230/1/2/7) and 4.0 A
(Si8233/4/5/8) are available. All drivers operate with a maximum supply voltage of 24 V.
The Si823x drivers utilize Silicon Labs' proprietary silicon isolation technology, which
provides up to 5 kVRMS withstand voltage per UL1577 and fast 45 ns propagation times.
Driver outputs can be grounded to the same or separate grounds or connected to a pos-
itive or negative voltage. The TTL level compatible inputs with >400 mV hysteresis are
available in individual control input (Si8230/2/3/5/7/8) or PWM input (Si8231/4) configu-
rations. High integration, low propagation delay, small installed size, flexibility, and cost-
effectiveness make the Si823x family ideal for a wide range of isolated MOSFET/IGBT
gate drive applications.
Automotive Grade is available for certain part numbers. These products are built using
automotive-specific flows at all steps in the manufacturing process to ensure the robust-
ness and low defectivity required for automotive applications.
KEY FEATURES
Two completely isolated drivers in one
package
Up to 5 kVRMS input-to-output isolation
Up to 1500 VDC peak driver-to-driver
differential voltage
HS/LS and dual driver versions
Up to 8 MHz switching frequency
0.5 A peak output (Si8230/1/2/7)
4.0 A peak output (Si8233/4/5/8)
High electromagnetic immunity
RoHS-compliant packages:
SOIC-14/16 wide body
SOIC-16 narrow body
LGA-14
QFN-14 (pin to pin compatible with
LGA-14 packages)
AEC-Q100 qualification
Automotive-grade OPNs available
AIAG compliant PPAP documentation
support
IMDS and CAMDS listing support
Industrial Applications
Power delivery systems
Motor control systems
Isolated dc-dc power supplies
Lighting control systems
Plasma displays
Solar and industrial inverters
Safety Regulatory Approvals
UL 1577 recognized
Up to 5000 VRMS for 1 minute
CSA component notice 5A approval
IEC 60950-1, 62368-1, 60601-1 (re-
inforced insulation)
VDE certification conformity
VDE 0884-10
EN60950-1 (reinforced insulation)
CQC certification approval
GB4943.1
Automotive Applications
On-board chargers
Battery management systems
Charging stations
Traction inverters
Hybrid Electric Vehicles
Battery Electric Vehicles
silabs.com | Building a more connected world. Rev. 2.13
1. Ordering Guide
Table 1.1. Si823x Ordering Guide 1, 2, 3
Ordering Part
Number (OPN) Inputs Configuration Peak
Current
UVLO
Voltage
Isolation
Rating Temp Range Package Type
Legacy
Ordering
Part Number
(OPN)
2.5 kV Only
Wide Body (WB) Package Options
Si8230BB-D-IS VIA, VIB High Side/
Low Side
0.5 A 8 V
2.5 kVrms –40 to +125 °C SOIC-16
Wide Body
Si8230-A-IS
Si8231BB-D-IS PWM High Side/
Low Side Si8231-A-IS
Si8232BB-D-IS VIA,VIB Dual Driver Si8232-A-IS
Si8234CB-D-IS PWM High Side/
Low Side
4.0 A
10 V N/A
Si8233BB-D-IS VIA,VIB High Side/
Low Side
8 V
Si8233-B-IS
Si8234BB-D-IS PWM High Side/
Low Side Si8234-B-IS
Si8235BB-D-IS VIA,VIB Dual Driver Si8235-B-IS
Si8230AB-D-IS VIA, VIB High Side/
Low Side 0.5 A 5 V
2.5 kVrms –40 to +125 °C SOIC-16
Wide Body
N/A
Si8231AB-D-IS PWM N/A
Si8232AB-D-IS VIA,VIB Dual Driver N/A
Si8233AB-D-IS VIA,VIB High Side/
Low Side 4.0 A 5 V
N/A
Si8234AB-D-IS PWM N/A
Si8235AB-D-IS VIA,VIB Dual Driver N/A
Narrow Body (NB) Package Options
Si8230BB-D-IS1 VIA,VIB High Side/
Low Side
0.5 A 8 V
2.5 kVrms –40 to +125 °C SOIC-16
Narrow Body N/A
Si8231BB-D-IS1 PWM High Side/
Low Side
Si8232BB-D-IS1 VIA,VIB Dual Driver
Si8233BB-D-IS1 VIA,VIB High Side/
Low Side
4.0 A 8 V
Si8234BB-D-IS1 PWM High Side/
Low Side
Si8235BB-D-IS1 VIA,VIB Dual Driver
Si8235BA-D-IS1 VIA,VIB Dual Driver 1.0 kVrms
Si823x Data Sheet
Ordering Guide
silabs.com | Building a more connected world. Rev. 2.13 | 2
Ordering Part
Number (OPN) Inputs Configuration Peak
Current
UVLO
Voltage
Isolation
Rating Temp Range Package Type
Legacy
Ordering
Part Number
(OPN)
2.5 kV Only
Si8230AB-D-IS1 VIA,VIB High Side/
Low Side 0.5 A 5 V
2.5 kVrms –40 to +125 °C SOIC-16
Narrow Body
N/A
Si8231AB-D-IS1 PWM N/A
Si8232AB-D-IS1 VIA,VIB Dual Driver N/A
Si8233AB-D-IS1 VIA,VIB High Side/
Low Side 4.0 A 5 V
N/A
Si8234AB-D-IS1 PWM N/A
Si8235AB-D-IS1 VIA,VIB Dual Driver N/A
LGA Package Options
Si8233CB-D-IM
VIA,VIB
High Side/
Low Side
4.0 A
10 V
2.5 kVrms –40 to +125 °C LGA-14 5x5
mm
N/A
Si8233BB-D-IM 8 V Si8233-B-IM
Si8233AB-D-IM 5 V N/A
Si8234BB-D-IM PWM 8 V Si8234-B-IM
Si8234AB-D-IM 5 V N/A
Si8235BB-D-IM VIA,VIB Dual Driver 8 V Si8235-B-IM
Si8235AB-D-IM 5 V N/A
QFN Package Options
SI8233AB-D-IM1 VIA,VIB
High Side/
Low Side
4.0 A
5 V
2.5 kVrms –40 to +125 °C QFN-14
N/A
SI8233BB-D-IM1 8 V N/A
SI8234AB-D-IM1 PWM 5 V N/A
SI8234BB-D-IM1 8 V N/A
SI8235AB-D-IM1 VIA,VIB Dual Driver 5 V N/A
SI8235BB-D-IM1 8 V N/A
5 kV Ordering Options
Si8230BD-D-IS VIA, VIB High Side/
Low Side
0.5 A
8 V 5.0 kVrms –40 to +125 °C SOIC-16
Wide Body N/A
Si8231BD-D-IS PWM High Side/
Low Side
Si8232BD-D-IS VIA, VIB Dual Driver
Si8233BD-D-IS VIA, VIB High Side/
Low Side
4.0 A
Si8234BD-D-IS PWM High Side/
Low Side
Si8235BD-D-IS VIA, VIB Dual Driver
Si823x Data Sheet
Ordering Guide
silabs.com | Building a more connected world. Rev. 2.13 | 3
Ordering Part
Number (OPN) Inputs Configuration Peak
Current
UVLO
Voltage
Isolation
Rating Temp Range Package Type
Legacy
Ordering
Part Number
(OPN)
2.5 kV Only
Si8230AD-D-IS VIA, VIB High Side/
Low Side 0.5 A 5 V
5.0 kVrms –40 to +125 °C
SOIC-16
Wide Body
N/A
Si8231AD-D-IS PWM N/A
Si8232AD-D-IS VIA, VIB Dual Driver N/A
Si8233AD-D-IS VIA, VIB High Side/
Low Side 4.0 A 5 V
N/A
Si8234AD-D-IS PWM N/A
Si8235AD-D-IS VIA, VIB Dual Driver N/A
SI8230AD-D-IS3 VIA, VIB High Side/
Low Side
0.5 A SOIC-14 Wide
Body with
increased
creepage
N/A
SI8230BD-D-IS3 VIA, VIB 8 V N/A
SI8233AD-D-IS3 VIA, VIB 4.0 A 5 V N/A
SI8233BD-D-IS3 VIA, VIB 8 V N/A
SI8235AD-D-IS3 VIA, VIB Dual Driver 5 V N/A
SI8235BD-D-IS3 VIA, VIB 8 V N/A
3 V VDDI Ordering Options
Si8237AB-D-IS1 VIA, VIB Dual Driver 0.5 A 5 V
2.5 kVrms
–40 to +125 °C
SOIC-16
Narrow Body
N/A
Si8237BB-D-IS1 VIA, VIB Dual Driver 8 V
Si8238AB-D-IS1 VIA, VIB Dual Driver 4.0 A 5 V
Si8238BB-D-IS1 VIA, VIB Dual Driver 8 V
Si8237AD-D-IS VIA, VIB Dual Driver 0.5 A 5 V
5.0 kVrms
SOIC-16
Wide Body
Si8237BD-D-IS VIA, VIB Dual Driver 8 V
Si8238AD-D-IS VIA, VIB Dual Driver
4.0 A
5 V
Si8238BD-D-IS VIA, VIB Dual Driver 8 V
SI8238AD-D-IS3 VIA, VIB Dual Driver 5 V SOIC-14 Wide
Body with
increased
creepage
SI8238BD-D-IS3 VIA, VIB Dual Driver 8 V
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifica-
tions and peak solder temperatures.
2. “Si” and “SI” are used interchangeably.
3. An "R" at the end of the part number denotes tape and reel packaging option.
Si823x Data Sheet
Ordering Guide
silabs.com | Building a more connected world. Rev. 2.13 | 4
Automotive Grade OPNs
Automotive-grade devices are built using automotive-specific flows at all steps in the manufacturing process to ensure robustness and
low defectivity. These devices are supported with AIAG-compliant Production Part Approval Process (PPAP) documentation, and fea-
ture International Material Data System (IMDS) and China Automotive Material Data System (CAMDS) listing. Qualifications are compli-
ant with AEC-Q100, and a zero-defect methodology is maintained throughout definition, design, evaluation, qualification, and mass pro-
duction steps.
Table 1.2. Ordering Guide for Automotive Grade OPNs1, 2, 4, 5
Ordering Part Num-
ber (OPN) Inputs Configuration Peak Cur-
rent
UVLO
Voltage
Isolation
Rating Temp Range Package Type
Wide Body (WB) Package Options
Si8233BB-AS VIA, VIB High Side/Low Side 4.0 A 8 V 2.5 kVrms –40 to +125 °C SOIC-16 Wide
Body
Narrow Body (NB) Package Options
Si8230BB-AS1 VIA, VIB High Side/Low Side 0.5 A 8 V 2.5 kVrms –40 to +125 °C SOIC-16 Narrow
Body
Si8233BB-AS1 VIA, VIB High Side/Low Side 4.0 A 8 V 2.5 kVrms –40 to +125 °C SOIC-16 Narrow
Body
Si8235BB-AS1 VIA, VIB High Side/Low Side 4.0 A 8 V 2.5 kVrms –40 to +125 °C SOIC-16 Narrow
Body
Si8233AB-AS1 VIA, VIB High Side/Low Side 4.0 A 5 V 2.5 kVrms –40 to +125 °C SOIC-16 Narrow
Body
LGA Package Option
Si8233BB-AM VIA, VIB High Side/Low Side 4.0 A 8 V 2.5 kVrms –40 to +125 °C LGA-14
5x5 mm
Si8234BB-AM PWM High Side/Low Side 4.0 A 8 V 2.5 kVrms –40 to +125 °C LGA-14
5x5 mm
Si8235BB-AM VIA, VIB Dual Driver 4.0 A 8 V 2.5 kVrms –40 to +125 °C LGA-14
5x5 mm
5 kV Ordering Options
Si8233BD-AS VIA, VIB High Side/Low Side 4.0 A 8 V 5.0 kVrms –40 to +125 °C SOIC-16 Wide
Body
Si8235BD-AS VIA, VIB Dual Driver 4.0 A 8 V 5.0 kVrms –40 to +125 °C SOIC-16 Wide
Body
Si8235BD-AS3 VIA, VIB Dual Driver 4.0 A 8 V 5.0 kVrms –40 to +125 °C SOIC-14 Wide
Body with in-
creased creepage
3 V VDDI Ordering Options
Si8237BB-AS1 VIA, VIB Dual Driver 0.5 A 8 V 2.5 kVrms –40 to +125 °C SOIC-16 Narrow
Body
Si8238BB-AS1 VIA, VIB Dual Driver 4.0 A 8 V 2.5 kVrms –40 to +125 °C SOIC-16 Narrow
Body
Si8238BD-AS VIA, VIB Dual Driver 4.0 A 8 V 5.0 kVrms –40 to +125 °C SOIC-16 Wide
Body
Si823x Data Sheet
Ordering Guide
silabs.com | Building a more connected world. Rev. 2.13 | 5
Ordering Part Num-
ber (OPN) Inputs Configuration Peak Cur-
rent
UVLO
Voltage
Isolation
Rating Temp Range Package Type
Note:
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifica-
tions.
2. “Si” and “SI” are used interchangeably.
3. An "R" at the end of the part number denotes tape and reel packaging option.
4. Automotive-Grade devices (with an "–A" suffix) are identical in construction materials, topside marking, and electrical parameters
to their Industrial-Grade (with a "–I" suffix) version counterparts. Automotive-Grade products are produced utilizing full automotive
process flows and additional statistical process controls throughout the manufacturing flow. The Automotive-Grade part number is
included on shipping labels.
5. Additional Ordering Part Numbers may be available in Automotive-Grade. Please contact your local Silicon Labs sales represen-
tative for further information.
6. In Section 8. Top Markings, the Manufacturing Code represented by either “RTTTTT” or “TTTTTT” contains as its first character a
letter in the range N through Z to indicate Automotive-Grade.”
Si823x Data Sheet
Ordering Guide
silabs.com | Building a more connected world. Rev. 2.13 | 6
Table of Contents
1. Ordering Guide ..............................2
2. System Overview ..............................9
2.1 Top Level Block Diagrams ..........................9
2.2 Functional Description ...........................11
2.3 Typical Operating Characteristics (0.5 Amp) ....................12
2.4 Typical Operating Characteristics (4.0 Amp) ....................15
2.5 Family Overview and Logic Operation During Startup .................17
2.5.1 Products ..............................17
2.5.2 Device Behavior ............................18
2.6 Power Supply Connections ..........................19
2.7 Power Dissipation Considerations .......................19
2.8 Layout Considerations ...........................21
2.9 Undervoltage Lockout Operation ........................21
2.9.1 Device Startup ............................21
2.9.2 Undervoltage Lockout ..........................22
2.9.3 Undervoltage Lockout (UVLO) .......................22
2.9.4 Control Inputs .............................22
2.9.5 Disable Input .............................22
2.10 Programmable Dead Time and Overlap Protection .................23
3. Electrical Specifications ..........................25
3.1 Test Circuits ...............................28
4. Applications............................... 34
4.1 High-Side/Low-Side Driver ..........................34
4.2 Dual Driver ...............................35
5. Pin Descriptions .............................36
6. Package Outlines .............................42
6.1 Package Outline: 16-Pin Wide Body SOIC.....................42
6.2 Package Outline: 14-Pin Wide Body SOIC.....................44
6.3 Package Outline: 16-Pin Narrow Body SOIC ....................46
6.4 Package Outline: 14 LD LGA (5 x 5 mm) .....................47
6.5 Package Outline: 14 LD QFN .........................48
7. Land Patterns ..............................49
7.1 Land Pattern: 16-Pin Wide Body SOIC ......................49
7.2 Land Pattern: 14-Pin Wide Body SOIC ......................50
7.3 Land Pattern: 16-Pin Narrow Body SOIC .....................51
7.4 Land Pattern: 14 LD LGA/QFN ........................52
silabs.com | Building a more connected world. Rev. 2.13 | 7
8. Top Markings ..............................53
8.1 Si823x Top Marking (14/16-Pin Wide Body SOIC) ..................53
8.2 Si823x Top Marking (16-Pin Narrow Body SOIC) ..................54
8.3 Si823x Top Marking (14 LD LGA/QFN) ......................55
9. Revision History .............................56
silabs.com | Building a more connected world. Rev. 2.13 | 8
2. System Overview
2.1 Top Level Block Diagrams
Si8230/3
UVLO
UVLO
GNDI
VIB
VDDI
VIA VDDA
VOA
GNDA
VOB
VDDI
VDDI
I S O L A TI ON
VDDI
VDDB
GNDB
DISABLE
I S O L A TI O N
UVLO
DT CONTROL &
OVERLAP
PROTECTION
DT
Figure 2.1. Si8230/3 Two-Input High-Side/Low-Side Isolated Drivers
Si823x Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 2.13 | 9
Si8231/4
UVLO
UVLO
GNDI
VDDI
PWM VDDA
VOA
GNDA
VOB
VDDI
VDDI
I S O L A TI ON
VDDI
VDDB
GNDB
DISABLE
I S O L A TI O N
UVLO
DT CONTROL
&
OVERLAP
PROTECTION
DT
LPWM
LPWM
Figure 2.2. Si8231/4 Single-Input High-Side/Low-Side Isolated Drivers
Si8232/5/7/8
UVLO
VDDA
VOA
GNDA
VOB
VDDI
I S O L A TI ON
VDDI
VDDB
GNDB
UVLO
VIA
I S O L A TI O N
UVLO
GNDI
VIB
VDDI
VDDI
DISABLE
Figure 2.3. Si8232/5/7/8 Dual Isolated Drivers
Si823x Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 2.13 | 10
2.2 Functional Description
The operation of an Si823x channel is analogous to that of an optocoupler and gate driver, except an RF carrier is modulated instead of
light. This simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A
simplified block diagram for a single Si823x channel is shown in the figure below.
RF OSCILLATOR
MODULATOR DEMODULATOR
AB
Semiconductor-
Based Isolation
Barrier
Transmitter Receiver
Dead
time
control 0.5 to 4 A
peak
Gnd
VDD
Driver
Figure 2.4. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the
Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that
decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying
scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to
magnetic fields. See the figure below for more details.
Input Signal
Output Signal
Modulation Signal
Figure 2.5. Modulation Scheme
Si823x Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 2.13 | 11
2.3 Typical Operating Characteristics (0.5 Amp)
The typical performance characteristics depicted in Figure 2.6 Rise/Fall Time vs. Supply Voltage on page 12 through Figure
2.15 Output Source Current vs. Temperature on page 13 are for information purposes only. Refer to Table 3.1 Electrical Characteris-
tics1 on page 25 for actual specification limits.
0
2
4
6
8
10
9 12 15 18 21 24
Rise/Fall Time (ns)
VDDA Supply (V)
25
°C
CL= 100 pF
Tfall
Trise
Figure 2.6. Rise/Fall Time vs. Supply Voltage
10
15
20
25
30
9 12 15 18 21 24
Propagation Delay (ns)
VDDA Supply (V)
H-L
L-H
25
°C
CL= 100 pF
Figure 2.7. Propagation Delay vs. Supply Voltage
0
5
10
15
20
25
30
35
40
0.0 0.5 1.0 1.5 2.0
Rise/Fall Time (ns)
Load (nF)
VDD=12 V
, 25
°C
Tfall
Trise
Figure 2.8. Rise/Fall Time vs. Load
10
15
20
25
30
35
40
45
50
0.0 0.5 1.0 1.5 2.0
Propagation Delay (ns)
Load (nF)
VDD=12 V, 25
°C
H-L
L- H
Figure 2.9. Propagation Delay vs. Load
Si823x Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 2.13 | 12
10
15
20
25
30
-45 -20 5 30 55 80 105 130
Propagation Delay (ns)
Temperature (°C)
VDD=12 V, Load = 200 pF
L-H
H-L
Figure 2.10. Propagation Delay vs. Temperature
1
2
3
4
5
-45 -20 5 30 55 80 105 130
VDDA = 15 V,
f = 250 kHz, CL = 0 pF
Duty Cycle = 50%
2 Channels Switching
Temperature (° C)
Supply Current (mA)
Figure 2.11. Supply Current vs. Temperature
0
0.5
1
1.5
2
2.5
3
3.5
9 14 19 24
VDDA Supply Current (mA)
VDDA Supply Voltage (V)
Duty Cycle = 50%
CL= 0 pF
1 Channel Switching
1 MHz
500 kHz
100 kHz
50 kHz
Figure 2.12. Supply Current vs. Supply Voltage
0
1
2
3
4
5
6
7
9 14 19 24
VDDA Supply Current (mA)
VDDA Supply Voltage (V)
Duty Cycle = 50%
CL= 100 pF
1 Channel Switching
1 MHz
500 kHz
100 kHz
50 kHz
Figure 2.13. Supply Current vs. Supply Voltage
250
300
350
400
450
500
9 14 19 24
Source Current (mA)
Supply Voltage (V)
Vout=VDD-5 V
Figure 2.14. Output Source Current vs. Supply Voltage
250
275
300
325
350
375
400
425
-45 -20 5 30 55 80 105 130
Source Current (mA)
Temperature (°C)
VDD=12 V, Vout=VDD -5 V
Figure 2.15. Output Source Current vs. Temperature
Si823x Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 2.13 | 13
500
625
750
875
1000
1125
9 14 19 24
Sink Current (mA)
Supply Voltage (V)
Vout=5 V
Figure 2.16. Output Sink Current vs. Supply Voltage
500
600
700
800
900
-45 -20 5 30 55 80 105 130
Sink Current (mA)
Temperature (°C)
VDD=12 V, Vout=5 V
Figure 2.17. Output Sink Current vs. Temperature
Si823x Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 2.13 | 14
2.4 Typical Operating Characteristics (4.0 Amp)
The typical performance characteristics depicted in Figure 2.18 Rise/Fall Time vs. Supply Voltage on page 15 through Figure
2.27 Output Source Current vs. Temperature on page 16 are for information purposes only. Refer to Table 3.1 Electrical Characteris-
tics1 on page 25 for actual specification limits.
0
2
4
6
8
10
9 12 15 18 21 24
Rise/Fall Time (ns)
VDDA Supply (V)
25°C
CL= 100 pF
Tfall
Trise
Figure 2.18. Rise/Fall Time vs. Supply Voltage
10
15
20
25
30
9 12 15 18 21 24
Propagation Delay (ns)
VDDA Supply (V)
H -L
L- H
25°C
CL= 100 pF
Figure 2.19. Propagation Delay vs. Supply Voltage
0
10
20
30
40
0 2 4 6 8 10
Rise/Fall Time (ns)
Load (nF)
VDD=12V
, 25°C
Tfall
Trise
Figure 2.20. Rise/Fall Time vs. Load
10
20
30
40
50
0246810
Propagation Delay (ns)
Load (nF)
VDD=12V,
25°C
H-L
L-H
Figure 2.21. Propagation Delay vs. Load
Si823x Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 2.13 | 15
10
15
20
25
30
-45 -20 5 30 55 80 105 130
Propagation Delay (ns)
Temperature ( ° C)
VDD=12V,
Load = 200pF
H-L
L-H
Figure 2.22. Propagation Delay vs. Temperature
0
2
4
6
8
10
-45 -20 5 30 55 80 105 130
Supply Current (mA)
Temperature ( °C)
VDDA = 15V,
f = 250kHz,CL= 0 pF
Duty Cycle = 50%
2 Channels Switching
Figure 2.23. Supply Current vs. Temperature
0
2
4
6
8
10
12
14
9 12 15 18 21 24
VDDA Supply Current (mA)
VDDA Supply Voltage (V)
Duty Cycle = 50%
CL= 0 pF
1 Channel Switching
1MHz
500kHz
100kHz
50 kHz
Figure 2.24. Supply Current vs. Supply Voltage
0
2
4
6
8
10
12
14
9 12 15 18 21 24
VDDA Supply Current (mA)
VDDA Supply Voltage (V)
Duty Cycle = 50%
CL= 100 pF
1 Channel Switching 1MHz
500kHz
100kHz
50 kHz
Figure 2.25. Supply Current vs. Supply Voltage
2
2.25
2.5
2.75
3
3.25
3.5
3.75
4
9 12 15 18 21 24
Source Current (A)
Supply Voltage (V)
Vout=VDD -5V
Figure 2.26. Output Source Current vs. Supply Voltage
2
2.25
2.5
2.75
3
3.25
3.5
-45 -20 5 30 55 80 105 130
Source Current (A)
Temperature ( °C)
VDD=12V,
Vout=VDD -5V
Figure 2.27. Output Source Current vs. Temperature
Si823x Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 2.13 | 16
4
5
6
7
8
9
9 12 15 18 21 24
Sink Current (A)
Supply Voltage (V)
Vout=5V
Figure 2.28. Output Sink Current vs. Supply Voltage
4
4.25
4.5
4.75
5
5.25
5.5
5.75
6
6.25
6.5
6.75
7
-45 -20 5 30 55 80 105 130
Sink Current (A)
Temperature (°C)
VDD=12V,
Vout=5V
Figure 2.29. Output Sink Current vs. Temperature
2.5 Family Overview and Logic Operation During Startup
The Si823x family of isolated drivers consists of high-side, low-side, and dual driver configurations.
2.5.1 Products
The table below shows the configuration and functional overview for each product in this family.
Table 2.1. Si823x Family Overview
Part Number Configuration Overlap Protection Programmable
Dead Time
Inputs Peak Output Cur-
rent (A)
Si8230 High-Side/Low-Side VIA, VIB 0.5
Si8231 High-Side/Low-Side PWM 0.5
Si8232/7 Dual Driver VIA, VIB 0.5
Si8233 High-Side/Low-Side VIA, VIB 4.0
Si8234 High-Side/Low-Side PWM 4.0
Si8235/8 Dual Driver VIA, VIB 4.0
Si823x Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 2.13 | 17
2.5.2 Device Behavior
The table below consists of truth tables for the Si8230/3, Si8231/4, and Si8232/5/7/8 families.
Table 2.2. Si823x Family Truth Table1
Si8230/3 (High-Side/Low-Side) Truth Table
Inputs VDDI State Disable Output Notes
VIA VIB VOA VOB
L L Powered L L L Output transition occurs after internal dead time expires.
L H Powered L L H Output transition occurs after internal dead time expires.
H L Powered L H L Output transition occurs after internal dead time expires.
H H Powered L L L Invalid state. Output transition occurs after internal dead
time expires.
X2X2Unpowered X L L Output returns to input state within 7 µs of VDDI power re-
storation.
X X Powered H L L Device is disabled.
Si8231/4 (PWM Input High-Side/Low-Side) Truth Table
PWM Input VDDI State Disable Output Notes
VOA VOB
H Powered L H L Output transition occurs after internal dead time expires.
L Powered L L H Output transition occurs after internal dead time expires.
X2Unpowered X L L Output returns to input state within 7 µs of VDDI power re-
storation.
X Powered H L L Device is disabled.
Si8232/5/7/8 (Dual Driver) Truth Table
Inputs VDDI State Disable Output Notes
VIA VIB VOA VOB
L L Powered L L L Output transition occurs immediately
(no internal dead time).
L H Powered L L H Output transition occurs immediately
(no internal dead time).
H L Powered L H L Output transition occurs immediately
(no internal dead time).
H H Powered L H H Output transition occurs immediately
(no internal dead time).
X2X2Unpowered X L L Output returns to input state within 7 µs of VDDI power re-
storation.
X X Powered H L L Device is disabled.
Notes:
1. This truth table assumes VDDA and VDDB are powered. If VDDA and VDDB are below UVLO, see 2.9 Undervoltage
Lockout Operation for more information.
2. Note that an input can power the input die through an internal diode if its source has adequate current.
Si823x Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 2.13 | 18
2.6 Power Supply Connections
Isolation requirements mandate individual supplies for VDDI, VDDA, and VDDB. The decoupling caps for these supplies must be
placed as close to the VDD and GND pins of the Si823x as possible. The optimum values for these capacitors depend on load current
and the distance between the chip and the regulator that powers it. Low effective series resistance (ESR) capacitors, such as Tantalum,
are recommended.
2.7 Power Dissipation Considerations
Proper system design must assure that the Si823x operates within safe thermal limits across the entire load range.The Si823x total
power dissipation is the sum of the power dissipated by bias supply current, internal parasitic switching losses, and power dissipated by
the series gate resistor and load. Equation 1 shows total Si823x power dissipation.
PD=
(
VDDI
)(
IDDI
)
+ 2
(
IDD2
)(
VDD2
)
+
(
f
)(
QG
)(
VDD2
)
RP
RP+ RG+
(
f
)(
QG
)(
VDD2
)
RN
RN+ RG+ 2fCintVDD22
where:
PD is the total Si823x device power dissipation (W)
IDDI is the input-side maximum bias current (3 mA)
IDD2 is the driver die maximum bias current (2.5 mA)
Cint is the internal parasitic capacitance (75 pF for the 0.5 A driver and 370 pF for the 4.0 A driver)
VDDI is the input-side VDD supply voltage (2.7 to 5.5 V)
VDD2 is the driver-side supply voltage (10 to 24 V)
f is the switching frequency (Hz)
QG is the gate charge of the FET being driven
RG is the external gate resistor
RP is the RDS(ON) of the driver pull-up switch: (Rp = 15 Ω for the 0.5 A driver; Rp = 2.7 Ω for the 4.0 A driver)
RN is the RDS(ON) of the driver pull-down switch: (Rn = 5 Ω for the 0.5 A driver and 1 Ω for the 4.0 A driver)
Equation 1
Power dissipation example for 0.5 A driver using Equation 1 with the following givens:
VDD1 = 5.0 V
VDD2 = 12 V
f = 350 kHz
RG = 22 Ω
QG = 25 nC
Pd= 0.015 + 0.060 +
(
350 × 103
)(
25 × 10-9
)
(
12
)(
5
5 + 22
)
+
(
350 × 103
)(
25 × 10-9
)
(12)
(
15
15 + 22
)
+2
(
350 × 103
)(
75 × 1012
)
(144) = 145 mW
Si823x Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 2.13 | 19
From which the driver junction temperature is calculated using Equation 2, where:
Pd is the total Si823x device power dissipation (W)
θja is the thermal resistance from junction to air (105 °C/W in this example)
TA is the ambient temperature
Tj=Pd×Θja×TA= (0.145)(105) + 20 = 35.2 ° C
The maximum power dissipation allowable for the Si823x is a function of the package thermal resistance, ambient temperature, and
maximum allowable junction temperature, as shown in Equation 2:
PDmax Tjmax TA
Θja
where:
PDmax = Maximum Si823x power dissipation (W)
Tjmax = Si823x maximum junction temperature (150 °C)
TA = Ambient temperature (20 °C)
Θja = Si823x junction-to-air thermal resistance (105 °C/W)
Equation 2
Substituting values for PDmax Tjmax, TA, and θja into Equation 2 results in a maximum allowable total power dissipation of 1.29 W. Maxi-
mum allowable load is found by substituting this limit and the appropriate data sheet values from Table 3.1 Electrical Characteristics1
on page 25 into Equation 1 and simplifying. The result is Equation 3 (0.5 A driver) and Equation 4 (4.0 A driver), both of which as-
sume VDDI = 5 V and VDDA = VDDB = 18 V.
QG(MAX) =0.164
f3.05 × 109
Equation 3
QG(MAX) =0.634
f5.81 × 109
Equation 4
Equation 3 and Equation 4 are graphed in the figure below, where the points along the load line represent the package dissipation-
limited value of CL for the corresponding switching frequency.
Si823x Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 2.13 | 20
2.8 Layout Considerations
It is most important to minimize ringing in the drive path and noise on the Si823x VDD lines. Care must be taken to minimize parasitic
inductance in these paths by locating the Si823x as close to the device it is driving as possible. In addition, the VDD supply and ground
trace paths must be kept short. For this reason, the use of power and ground planes is highly recommended. A split ground plane sys-
tem having separate ground and VDD planes for power devices and small signal components provides the best overall noise perform-
ance.
2.9 Undervoltage Lockout Operation
Device behavior during start-up, normal operation and shutdown is shown in Figure 2.30 Device Behavior during Normal Operation and
Shutdown on page 22, where UVLO+ and UVLO- are the positive-going and negative-going thresholds respectively. Note that outputs
VOA and VOB default low when input side power supply (VDDI) is not present.
2.9.1 Device Startup
Outputs VOA and VOB are held low during power-up until VDD is above the UVLO threshold for time period tSTART. Following this,
the outputs follow the states of inputs VIA and VIB.
Si823x Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 2.13 | 21
2.9.2 Undervoltage Lockout
Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when VDD is below its
specified operating circuits range. The input (control) side, Driver A and Driver B, each have their own undervoltage lockout monitors.
The Si823x input side enters UVLO when VDDI < VDDIUV–, and exits UVLO when VDDI > VDDIUV+. The driver outputs, VOA and VOB,
remain low when the input side of the Si823x is in UVLO and their respective VDD supply (VDDA, VDDB) is within tolerance. Each
driver output can enter or exit UVLO independently. For example, VOA unconditionally enters UVLO when VDDA falls below VDDAUV–
and exits UVLO when VDDA rises above VDDAUV+.
VIA
VOA
DISABLE
VDDI
UVLO-
VDDA
tSTART tSTART tSTART tSD tRESTART tPHL tPLH
UVLO+
UVLO-
UVLO+
tSD
VDDHYS
VDDHYS
Figure 2.30. Device Behavior during Normal Operation and Shutdown
2.9.3 Undervoltage Lockout (UVLO)
The UVLO circuit unconditionally drives VO low when VDD is below the lockout threshold. Upon power up, the Si823x is maintained in
UVLO until VDD rises above VDDUV+. During power down, the Si823x enters UVLO when VDD falls below the UVLO threshold plus
hysteresis (i.e., VDD < VDDUV+ – VDDHYS).
2.9.4 Control Inputs
VIA, VIB, and PWM inputs are high-true, TTL level-compatible logic inputs. A logic high signal on VIA or VIB causes the corresponding
output to go high. For PWM input versions (Si8231/4), VOA is high and VOB is low when the PWM input is high, and VOA is low and
VOB is high when the PWM input is low.
2.9.5 Disable Input
When brought high, the DISABLE input unconditionally drives VOA and VOB low regardless of the states of VIA and VIB. Device opera-
tion terminates within tSD after DISABLE =VIH and resumes within tRESTART after DISABLE = VIL. The DISABLE input has no effect if
VDDI is below its UVLO level (i.e., VOA, VOB remain low).
Si823x Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 2.13 | 22
2.10 Programmable Dead Time and Overlap Protection
All high-side/low-side drivers (Si8230/1/3/4) include programmable overlap protection to prevent outputs VOA and VOB from being high
at the same time. These devices also include programmable dead time, which adds a user-programmable delay between transitions of
VOA and VOB. When enabled, dead time is present on all transitions, even after overlap recovery. The amount of dead time delay (DT)
is programmed by a single resistor (RDT) connected from the DT input to ground per Equation 5. Note that the dead time pin can be
tied to VDDI or left floating to provide a nominal dead time at approximately 400 ps.
DT ≈ 10 × RDT
where:
DT = dead time (ns) and
RDT = dead time programing resistor (kΩ)
Equation 5
The device driving VIA and VIB should provide a minimum dead time of TDD to avoid activating overlap protection. Input/output timing
waveforms for the two-input drivers are shown in Figure 2.31 Input / Output Waveforms for High-Side / Low-Side Two-Input Drivers on
page 23, and dead time waveforms are shown in Figure 2.32 Dead Time Waveforms for High-Side / Low-Side Two-input Drivers on
page 24.
Figure 2.31. Input / Output Waveforms for High-Side / Low-Side Two-Input Drivers
Si823x Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 2.13 | 23
VIA/
PWM
VIB
VOA
VOB
DT
DT
10%
10%
90%
90%
50%
VOB
A. Typical Dead Time Operation
VIA/
PWM
VOA
VOB
DT
DT
VIB
DT DT
OVERLAP OVERLAP
B. Dead Time Operation During Overlap
Figure 2.32. Dead Time Waveforms for High-Side / Low-Side Two-input Drivers
Si823x Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 2.13 | 24
3. Electrical Specifications
Table 3.1. Electrical Characteristics1
2.7 V < VDDI < 5.5 V, VDDA = VDDB = 12 V or 15 V, TA = –40 to +125 °C, Typical specs at 25 °C, TJ = -40 to +150 °C
Parameter Symbol Test Condition Min Typ Max Unit
DC Specifications
Input-side Power Supply
Voltage
VDDI Si8230/1/2/3/4/5
Si8237/8
4.5
2.7
5.5
5.5
V
Driver Supply Voltage VDDA, VDDB Voltage between VDDA and
GNDA, and VDDB and GNDB
(See 1. Ordering Guide)
6.5 24 V
Input Supply Quiescent
Current
IDDI(Q) Si8230/2/3/5/7/8 2 3 mA
Si8231/4 3.5 5 mA
Output Supply Quiescent
Current
IDDA(Q), IDDB(Q) Current per channel 3.0 mA
Input Supply Active Current IDDI Input freq = 500 kHz, no load 3.5 mA
Output Supply Active Current IDDA
IDDB
Current per channel with
Input freq = 500 kHz, no load
6 mA
Input Pin Leakage Current IVIA, IVIB, IPWM –10 +10 µA dc
Input Pin Leakage Current
(Si8230/1/2/3/4/5)
IDISABLE –10 +10 µA dc
Input Pin Leakage Current
(Si8237/8)
-1000 +1000
Logic High Input Threshold VIH 2.0 V
Logic Low Input Threshold VIL 0.8 V
Input Hysteresis VIHYST Si8230/1/2/3/4/5/7/8 400 450 mV
Logic High Output Voltage VOAH, VOBH IOA, IOB = –1 mA (VDDA /
VDDB)
— 0.04
V
Logic Low Output Voltage VOAL, VOBL IOA, IOB = 1 mA 0.04 V
Output Short-Circuit Pulsed
Sink Current
IOA(SCL), IOB(SCL) Si8230/1/2/7, Figure 3.1 IOL
Sink Current Test Circuit on
page 28
0.5 A
Si8233/4/5/8, Figure 3.1 IOL
Sink Current Test Circuit on
page 28
4.0 A
Output Short-Circuit Pulsed
Source Current
IOA(SCH),
IOB(SCH)
Si8230/1/2/7, Figure 3.2 IOH
Source Current Test Circuit on
page 28
0.25 A
Si8233/4/5/8, Figure 3.2 IOH
Source Current Test Circuit on
page 28
2.0 A
Si823x Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 2.13 | 25
Parameter Symbol Test Condition Min Typ Max Unit
Output Sink Resistance RON(SINK) Si8230/1/2/7 5.0 Ω
Si8233/4/5/8 1.0 Ω
Output Source Resistance RON(SOURCE) Si8230/1/2/7 15 Ω
Si8233/4/5/8 2.7 Ω
VDDI Undervoltage Threshold VDDIUV+ VDDI rising (Si8230/1/2/3/4/5) 3.60 4.0 4.45 V
VDDI Undervoltage Threshold VDDIUV– VDDI falling
(Si8230/1/2/3/4/5)
3.30 3.70 4.15 V
VDDI Lockout Hysteresis VDDIHYS (Si8230/1/2/3/4/5) 250 mV
VDDI Undervoltage Threshold VDDIUV+ VDDI rising (Si8237/8) 2.15 2.3 2.5 V
VDDI Undervoltage Threshold VDDIUV– VDDI falling (Si8237/8) 2.10 2.22 2.40 V
VDDI Lockout Hysteresis VDDIHYS (Si8237/8) 75 mV
VDDA, VDDB Undervoltage
Threshold
VDDAUV+, VDDBUV+ VDDA, VDDB rising
5 V Threshold 5.20 5.80 6.30 V
8 V Threshold 7.50 8.60 9.40 V
10 V Threshold 9.60 11.1 12.2 V
12.5 V Threshold 12.4 13.8 14.8 V
VDDA, VDDB Undervoltage
Threshold
VDDAUV–, VDDBUV– VDDA, VDDB falling
5 V Threshold 4.90 5.52 6.0 V
8 V Threshold 7.20 8.10 8.70 V
10 V Threshold 9.40 10.1 10.9 V
12.5 V Threshold 11.6 12.8 13.8 V
VDDA, VDDB
Lockout Hysteresis
VDDAHYS,
VDDBHYS
UVLO voltage = 5 V 280 mV
VDDA, VDDB
Lockout Hysteresis
VDDAHYS,
VDDBHYS
UVLO voltage = 8 V 600 mV
VDDA, VDDB
Lockout Hysteresis
VDDAHYS,
VDDBHYS
UVLO voltage = 10 V or 12.5 V 1000 mV
AC Specifications
Minimum Pulse Width 10 ns
Propagation Delay tPHL, tPLH CL = 200 pF 30 45 ns
Pulse Width Distortion
|tPLH - tPHL|
PWD 5.60 ns
Minimum Overlap Time2TDD DT = VDDI, No-Connect 0.4 ns
Si823x Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 2.13 | 26
Parameter Symbol Test Condition Min Typ Max Unit
Programmed Dead Time3DT Figure 2.32 Dead Time Wave-
forms for High-Side / Low-Side
Two-input Drivers on page 24,
RDT = 100 k
730 900 1170 ns
Figure 2.32 Dead Time Wave-
forms for High-Side / Low-Side
Two-input Drivers on page 24,
RDT = 6 k
55 70 75 ns
Output Rise and Fall Time tR,tFCL = 200 pF (Si8230/1/2/7) 20 ns
CL = 200 pF (Si8233/4/5/8) 12 ns
Shutdown Time from
Disable True
tSD 60 ns
Restart Time from
Disable False
tRESTART 60 ns
Device Start-up Time tSTART Time from VDD_ = VDD_UV+ to
VOA, VOB = VIA, VIB
40 µs
Common Mode
Transient Immunity
CMTI VIA, VIB, PWM = VDDI or 0 V
VCM = 1500 V
(see Figure 3.3 Common Mode
Transient Immunity Test Circuit
on page 29)
20 45 kV/µs
Notes:
1. VDDA = VDDB = 12 V for 5, 8, and 10 V UVLO devices; VDDA = VDDB = 15 V for 12.5 V UVLO devices.
2. TDD is the minimum overlap time without triggering overlap protection (Si8230/1/3/4 only).
3. The largest RDT resistor that can be used is 220 kΩ.
Si823x Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 2.13 | 27
3.1 Test Circuits
Figures Figure 3.1 IOL Sink Current Test Circuit on page 28, Figure 3.2 IOH Source Current Test Circuit on page 28, and Figure
3.3 Common Mode Transient Immunity Test Circuit on page 29 depict sink current, source current, and common-mode transient im-
munity test circuits, respectively.
INPUT
1 µF 100 µF
10
RSNS
0.1
Si823x
1 µF
CER
10 µF
EL
VDDA = VDDB = 15 V
IN OUT
VSS
VDD
SCHOTTKY
50 ns
200 ns
Measure
INPUT WAVEFORM
GND
VDDI
VDDI
8 V +
_
Figure 3.1. IOL Sink Current Test Circuit
INPUT
1 µF 100 µF
10
RSNS
0.1
Si823x
1 µF
CER
10 µF
EL
VDDA = VDDB = 15 V
IN OUT
VSS
VDD
50 ns
200 ns
Measure
INPUT WAVEFORM
GND
VDDI
SCHOTTKY
VDDI
5.5 V +
_
Figure 3.2. IOH Source Current Test Circuit
Si823x Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 2.13 | 28
Oscilloscope
5V
Isolated
Supply
VDDA
VOA
GNDA
12 V
Supply
High Voltage
Surge Generator
Vcm Surge
Output
100k
High Voltage
Differential
Probe
VDDB
VOB
GNDB
DT
GNDI
VDDI
INPUT
DISABLE
Input Signal
Switch
Input
Output
Isolated
Ground
Si823x
Figure 3.3. Common Mode Transient Immunity Test Circuit
Table 3.2. Regulatory Information1
CSA
The Si823x is certified under CSA Component Acceptance Notice 5A. For more details, see Master Contract Number 232873.
60950-1, 62368-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
60601-1: Up to 250 VRMS working voltage and 2 MOPP (Means of Patient Protection).
VDE
The Si823x is certified according to VDE 0884-10 and EN 60950-1. For more details, see certificates 40018443, 40030763.
0884-10: Up to 891 Vpeak for basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
UL
The Si823x is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 VRMS isolation voltage for basic protection.
CQC
The Si823x is certified under GB4943.1-2011. For more details, see certificates CQC13001096106, CQC13001096108, and CQC
17001178087.
Rated up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
Si823x Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 2.13 | 29
Note:
1. Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec. Regulatory Certifi-
cations apply to 3.75 kVRMS rated devices which are production tested to 4.5 kVRMS for 1 sec. Regulatory Certifications apply to
5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec.
For more information, see 1. Ordering Guide.
Table 3.3. Insulation and Safety-Related Specifications
Parameter Symbol Test Condition Value Unit
WBSOIC-14/16
5 kVRMS
WBSOIC-14/16
NBSOIC-16
2.5 kVRMS
14 LD LGA
/QFN
2.5 kVRMS
Nominal External Air
Gap
(Clearance)1
CLR 8.0 8.0/4.01 3.5 mm
Nominal External Track-
ing (Creepage)1
CPG 8.0 8.0/4.01 3.5 mm
Minimum Internal Gap
(Internal Clearance)
DTI 0.014 0.014 0.014 mm
Tracking Resistance CTI or PTI IEC60112 600 600 600 V
Erosion Depth ED 0.019/0.122 0.019/0.122 0.021 mm
Resistance
(Input-Output)2
RIO 1012 1012 1012 Ω
Capacitance
(Input-Output)2
CIO f = 1 ΜΗz 1.4 1.4 1.4 pF
Input Capacitance3CI4.0 4.0 4.0 pF
Notes:
1. The values in this table correspond to the nominal creepage and clearance values as detailed in 6.1 Package Outline: 16-Pin
Wide Body SOIC, 6.2 Package Outline: 14-Pin Wide Body SOIC, 6.3 Package Outline: 16-Pin Narrow Body SOIC, 6.4 Package
Outline: 14 LD LGA (5 x 5 mm), 6.5 Package Outline: 14 LD QFN. VDE certifies the clearance and creepage limits as 4.7 mm
minimum for the NB SOIC and 8.5 mm minimum for the WB SOIC package. UL does not impose a clearance and creepage mini-
mum for component level certifications. CSA certifies the clearance and creepage of the WB SOIC package with designation
"IS3" as 8 mm minimum. CSA certifies the clearance and creepage limits as 3.9 mm minimum for the NB SOIC and 7.6 mm mini-
mum for the WB SOIC package with package designation "IS" as listed in the data sheet.
2. To determine resistance and capacitance, the Si823x is converted into a 2-terminal device. Pins 1–8 (1–7, 14 LD LGA/QFN) are
shorted together to form the first terminal and pins 9–16 (8–14, 14 LD LGA/QFN) are shorted together to form the second termi-
nal. The parameters are then measured between these two terminals.
3. Measured from input pin to ground.
Si823x Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 2.13 | 30
Table 3.4. IEC 60664-1 Ratings
Parameter Test Condition Specification
WB SOIC-14/16 NB SOIC-16 14 LD
LGA/QFN
Basic Isolation Group Material Group I I I
Installation Classification Rated Mains Voltages < 150 VRMS I-IV I-IV I-IV
Rated Mains Voltages < 300 VRMS I-IV I-III I-III
Rated Mains Voltages < 400 VRMS I-III I-II I-II
Rated Mains Voltages < 600 VRMS I-III I-II I-II
Table 3.5. VDE 0884-10 Insulation Characteristics1
Parameter Symbol Test Condition
Characteristic
Unit
WB
SOIC-14/16
NB SOIC-16
14 LD LGA/QFN
Maximum Working Insula-
tion Voltage VIORM 891 560 V peak
Input to Output Test Volt-
age VPR
Method b1
(VIORM x 1.875 = VPR,
100%
Production Test, tm = 1
sec,
Partial Discharge < 5 pC)
1671 1050 V peak
Transient Overvoltage VIOTM t = 60 s 6000 4000 V peak
Surge Voltage VIOSM
Tested per IEC 60065 with
surge voltage of 1.2 µs/50
µs
Si823xxB/C/D tested with
4000 V 3077 3077 V peak
Pollution Degree (DIN VDE
0110, Table 1) 2 2
Insulation Resistance at
TS, VIO = 500 V RS>109>109Ω
*Note:
1. Maintenance of the safety data is ensured by protective circuits. The Si823x provides a climate classification of 40/125/21.
Si823x Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 2.13 | 31
Table 3.6. VDE 0884-10 Safety Limiting Values1
Parameter Symbol Test
Condition
WB SOIC-14/16 NB SOIC-16 14 LD
LGA/QFN
Unit
Case
Temperature
TS150 150 150 °C
Safety Input Current ΙSθJA = 100 °C/W (WB SO-
IC-14/16),
105 °C/W (NB SOIC-16,
14 LD LGA/QFN)
VDDI = 5.5 V,
VDDA = VDDB = 24 V,
TJ = 150 °C, TA = 25 °C
50 50 50 mA
Device Power Dissipa-
tion2
PD1.2 1.2 1.2 W
Notes:
1. Maximum value allowed in the event of a failure. Refer to the thermal derating curve in Figures Figure 3.4 WB SOIC, NB SOIC,
14 LD LGA/QFN Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per VDE 0884-10 on
page 32.
2. The Si82xx is tested with VDDI = 5.5 V, VDDA = VDDB = 24 V, TJ = 150 ºC, CL = 100 pF, input 2 MHz 50% duty cycle square wave.
Table 3.7. Thermal Characteristics
Parameter Symbol WB
SOIC-14/16
NB
SOIC-16
14 LD LGA/QFN Unit
IC Junction-to-Air
Thermal Resistance
θJA 100 105 105 °C/W
0 20015010050
60
40
20
0
Case Temperature (ºC)
Safety-Limiting Current (mA)
VDDI = 5.5 V
VDDA, VDDB = 24 V
10
30
50
Figure 3.4. WB SOIC, NB SOIC, 14 LD LGA/QFN Thermal Derating Curve, Dependence of Safety Limiting Values with Case
Temperature per VDE 0884-10
Si823x Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 2.13 | 32
Table 3.8. Absolute Maximum Ratings1
Parameter Symbol Min Max Unit
Storage Temperature2TSTG –65 +150 °C
Ambient Temperature under Bias TA–40 +125 °C
Junction Temperature TJ +150 °C
Input-side Supply Voltage VDDI –0.6 6.0 V
Driver-side Supply Voltage VDDA, VDDB –0.6 30 V
Voltage on any Pin with respect to
Ground VIO –0.5 VDD + 0.5 V
Output voltage to GND, repeat
spike of –2 V for 200 ns, 200 kHz
VOA to GNDA,
VOB to GNDB –2 VDDA/B + 0.5 V
Peak Output Current (tPW = 10 µs,
duty cycle = 0.2%)
(0.5 Amp versions)
IOPK 0.5 A
Peak Output Current (tPW = 10 µs,
duty cycle = 0.2%)
(4.0 Amp versions)
IOPK 4.0 A
Lead Solder Temperature (10 s) 260 °C
Maximum Isolation (Input to Out-
put) (1 s)
WB SOIC
6500 VRMS
Maximum Isolation (Output to Out-
put) (1 s)
WB SOIC
2500 VRMS
Maximum Isolation (Input to Out-
put) (1 s)
NB SOIC
4500 VRMS
Maximum Isolation (Output to Out-
put) (1 s)
NB SOIC
2500 VRMS
Maximum Isolation (Input to Out-
put) (1 s)
14 LD LGA/QFN
3850 VRMS
Maximum Isolation (Output to Out-
put) (1 s)
14 LD LGA/QFN
650 VRMS
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to
the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for ex-
tended periods may affect device reliability.
2. VDE certifies storage temperature from –40 to 150 °C.
Si823x Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 2.13 | 33
4. Applications
The following examples illustrate typical circuit configurations using the Si823x.
4.1 High-Side/Low-Side Driver
The Figure A in the drawing below shows the Si8230/3 controlled using the VIA and VIB input signals, and Figure B shows the Si8231/4
controlled by a single PWM signal.
Si8230/3
CB
1500 V max
GNDI
VDDI
VIA
VDDA
VOA
GNDA
VOB
VDDI
DISABLE
VDD2
DT
RDT
CONTROLLER
VIB
C1
1 µF
OUT1
OUT2
I/O
Q1
Q2
D1
VDDB
C3
1µF
Si8231/4
CB
PWM
VDDA
VOA
GNDA
VOB
DISABLE
DT
RDT
CONTROLLER
PWMOUT
I/O
Q1
Q2
D1
A B
VDD2
C3
1µF
1500 V max
C2
0.1 µF
GNDI
VDDI
VDDI
C1
1 µF C2
0.1 µF
VDDB
GNDB
C4
0.1 µF
C5
10 µF
VDDB
GNDB
C4
0.1 µF
C5
10 µF
Figure 4.1. Si823x in Half-Bridge Application
For both cases, D1 and CB form a conventional bootstrap circuit that allows VOA to operate as a high-side driver for Q1, which has a
maximum drain voltage of 1500 V. The boot-strap start up time will depend on the CB cap chosen. See application note, “AN486: High-
Side Bootstrap Design Using Si823x ISODrivers in Power Delivery Systems”. VOB is connected as a conventional low-side driver, and,
in most cases, VDD2 is the same as VDDB. Note that the input side of the Si823x requires VDD in the range of 4.5 to 5.5 V (2.7 to 5.5
V for Si8237/8), while the VDDA and VDDB output side supplies must be between 6.5 and 24 V with respect to their respective
grounds. It is recommended that bypass capacitors of 0.1 and 1 µF value be used on the Si823x input side and that they be located as
close to the chip as possible. Moreover, it is recommended that 0.1 and 10 µF bypass capacitors, located as close to the chip as possi-
ble, be used on the Si823x output side to reduce high-frequency noise and maximize performance.
Si823x Data Sheet
Applications
silabs.com | Building a more connected world. Rev. 2.13 | 34
4.2 Dual Driver
The figure below shows the Si823x configured as a dual driver. Note that the drain voltages of Q1 and Q2 can be referenced to a com-
mon ground or to different grounds with as much as 1500 V dc between them.
Si8232/5/7/8
VIA VDDA
VOA
GNDA
VOB
VDDB
GNDB
DISABLE
CONTROLLER
VIB
PH1
PH2
I/O
Q1
Q2
VDDA
VDDB
GNDI
VDDI
VDDI
C1
1 µF
C2
0.1 µF
C5
0.1 µF
C6
10 µF
C3
0.1 µF
C4
10 µF
Figure 4.2. Si8232/5/7/8 in a Dual Driver Application
Because each output driver resides on its own die, the relative voltage polarities of VOA and VOB can reverse without damaging the
driver. That is, the voltage at VOA can be higher or lower than that of VOB by VDD without damaging the driver. Therefore, a dual
driver in a low-side high side/low side drive application can use either VOA or VOB as the high side driver. Similarly, a dual driver can
operate as a dual low-side or dual high-side driver and is unaffected by static or dynamic voltage polarity changes.
Si823x Data Sheet
Applications
silabs.com | Building a more connected world. Rev. 2.13 | 35
5. Pin Descriptions
VIA
VIB
VDDI
GNDI
DISABLE
DT
NC
VDDI
VDDA
VOA
GNDA
NC
NC
VDDB
VOB
GNDB
Si8230
Si8233
SOIC-16 (Wide)
VIA
VIB
VDDI
GNDI
DISABLE
DT
NC
VDDI
VDDA
VOA
GNDA
NC
NC
VDDB
VOB
GNDB
Si8230
Si8233
SOIC-16 (Narrow)
1
2
3
4
5
6
7
89
12
11
10
13
14
15
16 1
2
3
4
5
6
7
89
12
11
10
13
14
15
16
Table 5.1. Si8230/3 Two-Input HS/LS Isolated Driver (SOIC-16). WB SOIC-14 with IS3 package designation, has pins 12 & 13
missing
Pin Name Description
1 VIA Non-inverting logic input terminal for Driver A.
2 VIB Non-inverting logic input terminal for Driver B.
3 VDDI Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
4 GNDI Input-side ground terminal.
5 DISABLE Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It
is strongly recommended that this input be connected to external logic level to avoid er-
roneous operation due to capacitive noise coupling.
6 DT Dead time programming input. The value of the resistor connected from DT to ground
sets the dead time between output transitions of VOA and VOB. Defaults to 400 ps dead
time when connected to VDDI or left open (see 2.10 Programmable Dead Time and
Overlap Protection). If improved noise immunity is desired, a 10 nF capacitor may be
added in parallel to the dead time programming resistor (RDT).
7 NC No connection.
8 VDDI Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
9 GNDB Ground terminal for Driver B.
10 VOB Driver B output (low-side driver).
11 VDDB Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
12 NC No connection.
13 NC No connection.
14 GNDA Ground terminal for Driver A.
15 VOA Driver A output (high-side driver).
16 VDDA Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
Si823x Data Sheet
Pin Descriptions
silabs.com | Building a more connected world. Rev. 2.13 | 36
PWM
NC
VDDI
GNDI
DISABLE
DT
NC
VDDI
VDDA
VOA
GNDA
NC
NC
VDDB
VOB
GNDB
Si8231
Si8234
SOIC-16 (Wide)
PWM
NC
VDDI
GNDI
DISABLE
DT
NC
VDDI
VDDA
VOA
GNDA
NC
NC
VDDB
VOB
GNDB
Si8231
Si8234
SOIC-16 (Narrow)
1
2
3
4
5
6
7
89
12
11
10
13
14
15
16 1
2
3
4
5
6
7
89
12
11
10
13
14
15
16
Table 5.2. Si8231/4 PWM Input HS/LS Isolated Driver (SOIC-16). WB SOIC-14 with IS3 package designation, has pins 12 & 13
missing
Pin Name Description
1 PWM PWM input.
2 NC No connection.
3 VDDI Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
4 GNDI Input-side ground terminal.
5 DISABLE Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It
is strongly recommended that this input be connected to external logic level to avoid er-
roneous operation due to capacitive noise coupling.
6 DT Dead time programming input. The value of the resistor connected from DT to ground
sets the dead time between output transitions of VOA and VOB. Defaults to 400 ps dead
time when connected to VDDI or left open (see 2.10 Programmable Dead Time and
Overlap Protection). If improved noise immunity is desired, a 10 nF capacitor may be
added in parallel to the dead time programming resistor (RDT).
7 NC No connection.
8 VDDI Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
9 GNDB Ground terminal for Driver B.
10 VOB Driver B output (low-side driver).
11 VDDB Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
12 NC No connection.
13 NC No connection.
14 GNDA Ground terminal for Driver A.
15 VOA Driver A output (high-side driver).
16 VDDA Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
Si823x Data Sheet
Pin Descriptions
silabs.com | Building a more connected world. Rev. 2.13 | 37
VIA
NC
VDDI
GNDI
DISABLE
NC
VIB
VDDI
VDDA
VOA
GNDA
NC
NC
VDDB
VOB
GNDB
Si8232
Si8235
Si8237
Si8238
SOIC-16 (Wide)
VIA
VIB
VDDI
GNDI
DISABLE
NC
NC
VDDI
VDDA
VOA
GNDA
NC
NC
VDDB
VOB
GNDB
Si8232
Si8235
Si8237
Si8238
SOIC-16 (Narrow)
1
2
3
4
5
6
7
89
12
11
10
13
14
15
16 1
2
3
4
5
6
7
89
12
11
10
13
14
15
16
Table 5.3. Si8232/5/7/8 Dual Isolated Driver (SOIC-16). WB SOIC-14 with IS3 package designation, has pins 12 & 13 missing
Pin Name Description
1 VIA Non-inverting logic input terminal for Driver A.
2 VIB Non-inverting logic input terminal for Driver B.
3 VDDI Input-side power supply terminal; connect to a source of 4.5 to 5.5 V, (2.7 to 5.5 V for
Si8237/8).
4 GNDI Input-side ground terminal.
5 DISABLE Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It
is strongly recommended that this input be connected to external logic level to avoid er-
roneous operation due to capacitive noise coupling.
6 NC No connection.
7 NC No connection.
8 VDDI Input-side power supply terminal; connect to a source of 4.5 to 5.5 V, (2.7 to 5.5 V for
Si8237/8).
9 GNDB Ground terminal for Driver B.
10 VOB Driver B output.
11 VDDB Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
12 NC No connection.
13 NC No connection.
14 GNDA Ground terminal for Driver A.
15 VOA Driver A output.
16 VDDA Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
Si823x Data Sheet
Pin Descriptions
silabs.com | Building a more connected world. Rev. 2.13 | 38
LGA-14 and QFN-14 (5 x 5 mm)
GNDI
VIA
VIB
VDDI
DISABLE
DT
VDDI
VDDA
VOA
GNDA
NC
VDDB
VOB
GNDB
Si8233
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Table 5.4. Si8233 Two-Input HS/LS Isolated Driver (14 LD LGA and QFN)
Pin Name Description
GNDI 1 Input-side ground terminal.
VIA 2 Non-inverting logic input terminal for Driver A.
VIB 3 Non-inverting logic input terminal for Driver B.
VDDI 4 Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
DISABLE 5 Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It
is strongly recommended that this input be connected to external logic level to avoid er-
roneous operation due to capacitive noise coupling.
DT 6 Dead time programming input. The value of the resistor connected from DT to ground
sets the dead time between output transitions of VOA and VOB. Defaults to 400 ps dead
time when connected to VDDI or left open (see2.10 Programmable Dead Time and
Overlap Protection). If improved noise immunity is desired, a 10 nF capacitor may be
added in parallel to the dead time programming resistor (RDT).
VDDI 7 Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
GNDB 8 Ground terminal for Driver B.
VOB 9 Driver B output (low-side driver).
VDDB 10 Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
NC 11 No connection.
GNDA 12 Ground terminal for Driver A.
VOA 13 Driver A output (high-side driver).
VDDA 14 Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
Si823x Data Sheet
Pin Descriptions
silabs.com | Building a more connected world. Rev. 2.13 | 39
LGA-14 and QFN-14 (5 x 5 mm)
GNDI
PWM
NC
VDDI
DISABLE
DT
VDDI
VDDA
VOA
GNDA
NC
VDDB
VOB
GNDB
Si8234
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Table 5.5. Si8234 PWM Input HS/LS Isolated Driver (14 LD LGA and QFN)
Pin Name Description
GNDI 1 Input-side ground terminal.
PWM 2 PWM input.
NC 3 No connection.
VDDI 4 Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
DISABLE 5 Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It
is strongly recommended that this input be connected to external logic level to avoid er-
roneous operation due to capacitive noise coupling.
DT 6 Dead time programming input. The value of the resistor connected from DT to ground
sets the dead time between output transitions of VOA and VOB. Defaults to 400 ps dead
time when connected to VDDI or left open (see 2.10 Programmable Dead Time and
Overlap Protection). If improved noise immunity is desired, a 10 nF capacitor may be
added in parallel to the dead time programming resistor (RDT).
VDDI 7 Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
GNDB 8 Ground terminal for Driver B.
VOB 9 Driver B output (low-side driver).
VDDB 10 Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
NC 11 No connection.
GNDA 12 Ground terminal for Driver A.
VOA 13 Driver A output (high-side driver).
VDDA 14 Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
Si823x Data Sheet
Pin Descriptions
silabs.com | Building a more connected world. Rev. 2.13 | 40
LGA-14 and QFN-14 (5 x 5 mm)
GNDI
VIA
VIB
VDDI
DISABLE
NC
VDDI
VDDA
VOA
GNDA
NC
VDDB
VOB
GNDB
Si8235
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Table 5.6. Si8235 Dual Isolated Driver (14 LD LGA and QFN)
Pin Name Description
GNDI 1 Input-side ground terminal.
VIA 2 Non-inverting logic input terminal for Driver A.
VIB 3 Non-inverting logic input terminal for Driver B.
VDDI 4 Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
DISABLE 5 Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It
is strongly recommended that this input be connected to external logic level to avoid er-
roneous operation due to capacitive noise coupling.
NC 6 No connection.
VDDI 7 Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
GNDB 8 Ground terminal for Driver B.
VOB 9 Driver B output (low-side driver).
VDDB 10 Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
NC 11 No connection.
GNDA 12 Ground terminal for Driver A.
VOA 13 Driver A output (high-side driver).
VDDA 14 Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
Si823x Data Sheet
Pin Descriptions
silabs.com | Building a more connected world. Rev. 2.13 | 41
6. Package Outlines
6.1 Package Outline: 16-Pin Wide Body SOIC
Figure 6.1 16-Pin Wide Body SOIC on page 42 illustrates the package details for the Si823x in a 16-Pin Wide Body SOIC. Table
6.1 Package Diagram Dimensions on page 42 lists the values for the dimensions shown in the illustration.
Figure 6.1. 16-Pin Wide Body SOIC
Table 6.1. Package Diagram Dimensions
Dimension Min Max
A 2.65
A1 0.10 0.30
A2 2.05
b 0.31 0.51
c 0.20 0.33
D 10.30 BSC
E 10.30 BSC
E1 7.50 BSC
e 1.27 BSC
L 0.40 1.27
h 0.25 0.75
θ
Si823x Data Sheet
Package Outlines
silabs.com | Building a more connected world. Rev. 2.13 | 42
Dimension Min Max
ααα 0.10
bbb 0.33
ccc 0.10
ddd 0.25
eee 0.10
fff 0.20
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MS-013, Variation AA.
4. Recommended reflow profile per JEDEC J-STD-020 specification for small body, lead-free components.
Si823x Data Sheet
Package Outlines
silabs.com | Building a more connected world. Rev. 2.13 | 43
6.2 Package Outline: 14-Pin Wide Body SOIC
Figure 6.2 Si823x 14-pin WB SOIC Outline on page 44 illustrates the package details for the Si823x in a 14-Pin Wide Body SOIC.
Table 6.2 Package Diagram Dimensions on page 44 lists the values for the dimensions shown in the illustration.
Figure 6.2. Si823x 14-pin WB SOIC Outline
Table 6.2. Package Diagram Dimensions
Dimension MIN MAX
A 2.65
A1 0.10 0.30
A2 2.05
b 0.31 0.51
c 0.20 0.33
D 10.30 BSC
E 10.30 BSC
E1 7.50 BSC
e 1.27 BSC
L 0.40 1.27
h 0.25 0.75
Θ08
aaa 0.10
bbb 0.33
ccc 0.10
ddd 0.25
eee 0.10
fff 0.20
Si823x Data Sheet
Package Outlines
silabs.com | Building a more connected world. Rev. 2.13 | 44
Dimension MIN MAX
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MS-013, Variation AA.
4. Recommended reflow profile per JEDEC J-STD-020 specification for small body, lead-free components.
Si823x Data Sheet
Package Outlines
silabs.com | Building a more connected world. Rev. 2.13 | 45
6.3 Package Outline: 16-Pin Narrow Body SOIC
Figure 6.3 16-pin Small Outline Integrated Circuit (SOIC) Package on page 46 illustrates the package details for the Si823x in a 16-
pin narrow-body SOIC. Table 6.3 Package Diagram Dimensions on page 46 lists the values for the dimensions shown in the illustra-
tion.
Figure 6.3. 16-pin Small Outline Integrated Circuit (SOIC) Package
Table 6.3. Package Diagram Dimensions
Dimension Min Max Dimension Min Max
A 1.75 L 0.40 1.27
A1 0.10 0.25 L2 0.25 BSC
A2 1.25 h 0.25 0.50
b 0.31 0.51 θ
c 0.17 0.25 aaa 0.10
D 9.90 BSC bbb 0.20
E 6.00 BSC ccc 0.10
E1 3.90 BSC ddd 0.25
e 1.27 BSC
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
Si823x Data Sheet
Package Outlines
silabs.com | Building a more connected world. Rev. 2.13 | 46
6.4 Package Outline: 14 LD LGA (5 x 5 mm)
Figure 6.4 Si823x LGA Outline on page 47 illustrates the package details for the Si823x in an LGA outline. Table 6.4 Package Dia-
gram Dimensions on page 47 lists the values for the dimensions shown in the illustration.
Figure 6.4. Si823x LGA Outline
Table 6.4. Package Diagram Dimensions
Dimension MIN NOM MAX
A 0.74 0.84 0.94
b 0.25 0.30 0.35
D 5.00 BSC
D1 4.15 BSC
e 0.65 BSC
E 5.00 BSC
E1 3.90 BSC
L 0.70 0.75 0.80
L1 0.05 0.10 0.15
aaa 0.10
bbb 0.10
ccc 0.08
ddd 0.15
eee 0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
Si823x Data Sheet
Package Outlines
silabs.com | Building a more connected world. Rev. 2.13 | 47
6.5 Package Outline: 14 LD QFN
Figure 6.5 Si823x 14-pin LD QFN Outline on page 48 illustrates the package details for the Si823x in an QFN outline. Table
6.5 Package Diagram Dimensions on page 48 lists the values for the dimensions shown in the illustration.
Figure 6.5. Si823x 14-pin LD QFN Outline
Table 6.5. Package Diagram Dimensions
Dimension MIN NOM MAX
A 0.74 0.85 0.90
A1 0 0.025 0.05
b 0.25 0.30 0.35
D 5.00 BSC
e 0.65 BSC
E 5.00 BSC
E1 3.60 BSC
L 0.50 0.60 0.70
L13 0.10 BSC
ccc 0.08
ddd 0.10
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. L1 shall not be less than 0.01 mm.
Si823x Data Sheet
Package Outlines
silabs.com | Building a more connected world. Rev. 2.13 | 48
7. Land Patterns
7.1 Land Pattern: 16-Pin Wide Body SOIC
Figure 7.1 16-Pin SOIC Land Pattern on page 49 illustrates the recommended land pattern details for the Si823x in a 16-pin wide-
body SOIC. Table 7.1 16-Pin Wide Body SOIC Land Pattern Dimensions on page 49 lists the values for the dimensions shown in the
illustration.
Figure 7.1. 16-Pin SOIC Land Pattern
Table 7.1. 16-Pin Wide Body SOIC Land Pattern Dimensions
Dimension Feature (mm)
C1 Pad Column Spacing 9.40
E Pad Row Pitch 1.27
X1 Pad Width 0.60
Y1 Pad Length 1.90
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN for Density Level B (Median Land Protru-
sion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
Si823x Data Sheet
Land Patterns
silabs.com | Building a more connected world. Rev. 2.13 | 49
7.2 Land Pattern: 14-Pin Wide Body SOIC
Figure 7.2 14-Pin WB SOIC Land Pattern on page 50 illustrates the recommended land pattern details for the Si823x in a 14-pin Wide
Body SOIC. Table 7.2 14-Pin WB SOIC Land Pattern Dimensions on page 50 lists the values for the dimensions shown in the
illustration.
Figure 7.2. 14-Pin WB SOIC Land Pattern
Table 7.2. 14-Pin WB SOIC Land Pattern Dimensions
Dimension Feature (mm)
C1 Pad Column Spacing 9.70
E Pad Row Pitch 1.27
X1 Pad Width 0.60
Y1 Pad Length 1.60
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN for Density Level B (Median Land Protru-
sion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
Si823x Data Sheet
Land Patterns
silabs.com | Building a more connected world. Rev. 2.13 | 50
7.3 Land Pattern: 16-Pin Narrow Body SOIC
Figure 7.3 16-Pin Narrow Body SOIC PCB Land Pattern on page 51 illustrates the recommended land pattern details for the Si823x in
a 16-pin narrow-body SOIC. Table 7.3 16-Pin Narrow Body SOIC Land Pattern Dimensions on page 51 lists the values for the dimen-
sions shown in the illustration.
Figure 7.3. 16-Pin Narrow Body SOIC PCB Land Pattern
Table 7.3. 16-Pin Narrow Body SOIC Land Pattern Dimensions
Dimension Feature (mm)
C1 Pad Column Spacing 5.40
E Pad Row Pitch 1.27
X1 Pad Width 0.60
Y1 Pad Length 1.55
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
Si823x Data Sheet
Land Patterns
silabs.com | Building a more connected world. Rev. 2.13 | 51
7.4 Land Pattern: 14 LD LGA/QFN
Figure 7.4 14-Pin LGA/QFN Land Pattern on page 52 illustrates the recommended land pattern details for the Si823x in a 14-pin LGA/
QFN. Table 7.4 14-Pin LGA/QFN Land Pattern Dimensions on page 52 lists the values for the dimensions shown in the illustration.
Figure 7.4. 14-Pin LGA/QFN Land Pattern
Table 7.4. 14-Pin LGA/QFN Land Pattern Dimensions
Dimension (mm)
C1 4.20
E 0.65
X1 0.80
Y1 0.40
Notes:
General
1. All dimensions shown are in millimeters (mm).
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabri-
cation Allowance of 0.05 mm.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
Si823x Data Sheet
Land Patterns
silabs.com | Building a more connected world. Rev. 2.13 | 52
8. Top Markings
8.1 Si823x Top Marking (14/16-Pin Wide Body SOIC)
Table 8.1. Top Marking Explanation (14/16-Pin Wide Body SOIC)
Line 1 Marking: Base Part Number
Ordering Options
See Ordering Guide for more information.
Si823 = ISOdriver product series
Y = Peak output current
0, 1, 2, 7 = 0.5 A
3, 4, 5, 8 = 4.0 A
U = UVLO level
A = 5 V; B = 8 V; C = 10 V; D = 12.5 V
V = Isolation rating
B = 2.5 kV; C = 3.75 kV; D = 5.0 kV
Line 2 Marking: YY = Year
WW = Workweek
Assigned by the Assembly House. Corresponds to the year and
workweek of the mold date.
TTTTTT = Mfg Code Manufacturing Code from Assembly Purchase Order form.
Line 3 Marking: Circle = 1.5 mm Diameter
(Center Justified)
“e4” Pb-Free Symbol
Country of Origin
ISO Code Abbreviation
TW = Taiwan (as shown), TH = Thailand
Si823x Data Sheet
Top Markings
silabs.com | Building a more connected world. Rev. 2.13 | 53
8.2 Si823x Top Marking (16-Pin Narrow Body SOIC)
Line 1 Marking: Base Part Number
Ordering Options
See Ordering Guide for more information.
Si823 = ISOdriver product series
Y = Peak output current
0, 1, 2, 7 = 0.5 A
3, 4, 5, 8 = 4.0 A
U = UVLO level
A = 5 V; B = 8 V; C = 10 V; D = 12.5 V
V = Isolation rating
A = 1.0 kV; B = 2.5 kV; C = 3.75 kV
Line 2 Marking: YY = Year
WW = Workweek
Assigned by the Assembly House. Corresponds to the year and
workweek of the mold date.
TTTTTT = Mfg Code Manufacturing Code from Assembly Purchase Order form.
Si823x Data Sheet
Top Markings
silabs.com | Building a more connected world. Rev. 2.13 | 54
8.3 Si823x Top Marking (14 LD LGA/QFN)
Line 1 Marking: Base Part Number
Ordering Options
See Ordering Guide for more information.
Si823 = ISOdriver product series
Y = Peak output current
0, 1, 2 = 0.5 A
3, 4, 5 = 4.0 A
Line 2 Marking: Ordering options U = UVLO level
A = 5 V; B = 8 V; C = 10 V; D = 12.5 V
V = Isolation rating
A = 1.0 kV; B = 2.5 kV; C = 3.75 kV
I = –40 to +125 °C ambient temperature range
M = LGA package type
M1 = QFN package type
Line 3 Marking: TTTTTT Manufacturing Code from Assembly
Line 4 Marking: Circle = 1.5 mm diameter Pin 1 identifier
YYWW Manufacturing date code
Si823x Data Sheet
Top Markings
silabs.com | Building a more connected world. Rev. 2.13 | 55
9. Revision History
Revision 2.13
September, 2018
Added automotive grade OPNs in Table 1.2 Ordering Guide for Automotive Grade OPNs1, 2, 4, 5 on page 5.
Modified power equations in 2.7 Power Dissipation Considerations.
Corrected typo for IDISABLE in Table 3.1 Electrical Characteristics1 on page 25.
Reformatted Table 3.5 VDE 0884-10 Insulation Characteristics1 on page 31.
Added Absolute Max rating of –2V/200 ns on output pins in Table 3.8 Absolute Maximum Ratings1 on page 33.
Updated 7.2 Land Pattern: 14-Pin Wide Body SOIC.
Revision 2.12
May 2018
Updated the Ordering Guide for Automotive-Grade OPN options.
Revision 2.1.1
January 2018
Added new table to Ordering Guide for Automotive-Grade OPN options.
Revision 2.1
October 2017
Added IS3 and IM1 packaging options
Added IEC 62368-1 references throughout
Changed max propagation delay spec from 60 ns to 45 ns based on new test limits
Removed references to IEC 61010
Removed references to IEC 60747, replaced with references to VDE 0884-10
Revision 2.0
August 7, 2017
Revision 1.9
July 7, 2017
Updated 1. Ordering Guide to designate tape and reel packaging option.
Revision 1.8
May 17, 2016
Converted document from Framemaker to DITA.
Revision 1.7
Updated 3.1 Test Circuits
Added CQC certificate numbers.
Updated Table 3.3 Insulation and Safety-Related Specifications on page 30
Updated Erosion Depth.
Updated Table 3.5 VDE 0884-10 Insulation Characteristics1 on page 31
Updated VPR for WBSOIC-16.
Updated Table 3.8 Absolute Maximum Ratings1 on page 33
Removed Io and added Peak Output Current specifications.
Updated Equation 1.
Updated Figure 4.1 Si823x in Half-Bridge Application on page 34.
Updated Figure 4.2 Si8232/5/7/8 in a Dual Driver Application on page 35.
Updated Ordering Guide Table 1.1 Si823x Ordering Guide 1, 2, 3 on page 2
Si823x Data Sheet
Revision History
silabs.com | Building a more connected world. Rev. 2.13 | 56
Revision 1.6
Updated Table 1.1 Si823x Ordering Guide 1, 2, 3 on page 2, Ordering Part Numbers.
Added Revision D Ordering Part Numbers.
Removed all Ordering Part Numbers of previous revisions.
Revision 1.5
Updated Table 3.1 Electrical Characteristics1 on page 25, input and output supply current.
Added references to AEC-Q100 qualified throughout.
Changed all 60747-5-2 references to 60747-5-5.
Added references to CQC throughout.
Updated pin descriptions throughout.
Corrected dead time default to 400 ps from 1 ns.
Updated Table 1.1 Si823x Ordering Guide 1, 2, 3 on page 2, Ordering Part Numbers.
Removed moisture sensitivity level table notes.
Revision 1.4
Updated 1. Ordering Guide.
Updated "3 V VDDI Ordering Options".
Revision 1.3
Added Si8237/8 throughout.
Updated Table 3.1 Electrical Characteristics1 on page 25.
Updated Figure 3.1 IOL Sink Current Test Circuit on page 28.
UpdatedFigure 3.2 IOH Source Current Test Circuit on page 28.
Added Figure 3.3 Common Mode Transient Immunity Test Circuit on page 29.
Updated Si823x Family Truth Table to include notes 1 and 2.
Updated 2.10 Programmable Dead Time and Overlap Protection.
Removed references to Figures 26A and 26B.
Updated Table 1.1 Si823x Ordering Guide 1, 2, 3 on page 2.
Added Si8235-BA-C-IS1 ordering part number.
Added table note.
Revision 1.2
Updated 1. Ordering Guide.
Updated moisture sensitivity level (MSL) for all package types.
Updated Table 3.8 Absolute Maximum Ratings1 on page 33.
Added junction temperature spec.
Updated 3.1 Test Circuits with new notes.
Updated Figures Figure 2.16 Output Sink Current vs. Supply Voltage on page 14, Figure 2.14 Output Source Current vs. Supply
Voltage on page 13, Figure 2.17 Output Sink Current vs. Temperature on page 14, and Figure 2.15 Output Source Current vs. Tem-
perature on page 13 to reflect correct y-axis scaling.
Updated Figure 4.2 Si8232/5/7/8 in a Dual Driver Application on page 35.
Updated .
Updated 6.1 Package Outline: 16-Pin Wide Body SOIC.
Updated Table 6.1 Package Diagram Dimensions on page 42.
Change references to 1.5 kVRMS rated devices to 1.0 kVRMS throughout.
Updated 2.7 Power Dissipation Considerations.
Si823x Data Sheet
Revision History
silabs.com | Building a more connected world. Rev. 2.13 | 57
Revision 1.1
Updated .
Updated CMTI specification.
Updated Table 3.1 Electrical Characteristics1 on page 25.
Updated CMTI specification.
Updated Table 3.5 VDE 0884-10 Insulation Characteristics1 on page 31.
Updated 4.2 Dual Driver.
Updated 1. Ordering Guide.
Replaced pin descriptions on page 1 with chip graphics.
Revision 1.0
Updated Tables 3.1 Test Circuits, Table 3.3 Insulation and Safety-Related Specifications on page 30, Table 3.4 IEC 60664-1 Rat-
ings on page 31, and Table 3.5 VDE 0884-10 Insulation Characteristics1 on page 31.
Updated 1. Ordering Guide.
Added 5 V UVLO ordering options
Added Device Marking sections.
Revision 0.3
Moved Sections 2, 3, and 4 to after Section 5.
Updated Tables Table 5.4 Si8233 Two-Input HS/LS Isolated Driver (14 LD LGA and QFN) on page 39, Table 5.5 Si8234 PWM Input
HS/LS Isolated Driver (14 LD LGA and QFN) on page 40.
Removed Si8230, Si8231, and Si8232 from pinout and from title.
Updated and added Ordering Guide footnotes.
Updated UVLO specifications in Table 3.1 Electrical Characteristics1 on page 25.
Added PWD and Output Supply Active Current specifications in Table 3.1 Electrical Characteristics1 on page 25.
Updated and added typical operating condition graphs in 2.3 Typical Operating Characteristics (0.5 Amp) and 2.4 Typical Operating
Characteristics (4.0 Amp).
Revision 0.2
Updated all specs to reflect latest silicon revision.
Updated Table 3.1 Electrical Characteristics1 on page 25 to include new UVLO options.
Updated Table 3.8 Absolute Maximum Ratings1 on page 33 to reflect new maximum package isolation ratings
Added Figures 34, 35, and 36.
Updated Ordering Guide to reflect new package offerings.
Added "Undervoltage Lockout (UVLO)" section to describe UVLO operation.
Revision 0.11
Initial release.
Si823x Data Sheet
Revision History
silabs.com | Building a more connected world. Rev. 2.13 | 58
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SI8234BB-D-IS1R SI8232AB-D-ISR SI8236AA-D-IMR SI8237BB-D-IS1R SI8233BD-D-ISR SI8238AB-D-IS1R
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D-IS1R SI8231BB-D-ISR SI8230AB-D-IS1R SI8231AB-D-IS1 SI8235AD-D-ISR SI8231AD-D-ISR Si8232DB-D-IS